IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO.

1, JANUARY 2008

Guest Editorial Special Section on Congurable Computing Design I: High-Level Reconguration

ONFIGURABLE computing, also called recongurable or adaptive computing, is a fast growing area in digital design and computer engineering. The reason is that the traditional market of microelectronics is shifting from industrial to consumer application. The main driving forces have been mobile computing and automotive industry. In these application areas, the traditional approaches, based on microprocessors and/or application-specic integrated circuits (ASICs), do not work well. These applications need exible, high-performance devices with low power consumption. Microprocessors are too slow and energy hungry while ASICs are efcient but inexible. Thus, the new emerging applications and market demand new technology. Many companies and researchers believe that the answer will be congurable computing platform. Recent developments show that congurable computing can outperform traditional, microprocessor-based solutions 10100 times. In the early years, the recongurable computing platform was used in very dedicated and specic application areas: in specialized signal and image processing systems and for prototyping VLSIs for embedded systems. Today, the recongurable computing platform is used for a wide range of applications: from very dedicated embedded applications to supercomputing. The range of research problems and interests runs from purely hardware related designs to building multiprocessing systems on recongurable spaces of elementary processors; from ne-grain granularity and parallelism to coarse-grain parallelism. The new emerging areas of consumer microelectronics are mobile handheld appliances (handheld devices, multimedia, and communication systems); computer networking; mobile vehicular systems (automotive applications with embedded control systems, communication systems and multimedia); supercomputing applications and congurable multiprocessors. During the past years, the security related problems on congurable computing platform has gained particular interest. Thus, the congurable computing forms a new and complete eld in digital engineering, covering theory and applications, hardware, and software. This Special Section on Congurable Computing Design covers physical, purely hardware related designs level as well as abstract level: building exible and adaptable multiprocessing environments with operating systems, often heterogeneous systems containing ne-grain congurable components and recongurable multiprocessing environments (MPSoCs). We received 98 submissions from which 16 papers were selected for publishing. These papers are divided between two Special Section issues, both containing eight papers. Issue I,

Digital Object Identier 10.1109/TVLSI.2007.913685

High-Level Reconguration and issue II, Hardware Level Reconguration. The rst issue on High-Level Reconguration deals with arranging computational processes on a congurable hardware platform: with problems above electronics. Nevertheless, it is not organizing computations in a traditional, von Neumann computer; it is implementing algorithms and computational processes directly in hardware. Dealing with congurable computing systems design issues, the gap between hardware and software is rather small. Congurable computing introduces traditional software related topics, such as languages, operating systems, and integrates these with hardware related topics of digital design. While in general, there is a similarity in theoretical models and methods on the functional level, the actual methods involved are rather different and need more specic attention from researchers. The rst two papers present coarse-grained recongurable processor architectures, which can be considered as recongurable multiprocessors, or multiprocessor systems on chip (MPSoC). Both these architectures present heterogeneous systems. The rst paper, Towards Software Dened Radios using Coarse-Grained Recongurable Hardware, by G. K. Rauwerda et al., deals with implementing mobile wireless terminals on recongurable MONTIUM tile processor. Wireless terminals are adaptive multimode communication devices. The implementation of these devices requires exible and efcient hardware, which is provided by a heterogeneous recongurable architecture. The implementation of a WCDMA and an OFDM receiver in the same recongurable processor is discussed. In A Medium-Grain Recongurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance, M. J. Myjak and J. G. Delgado-Frias present medium-grain recongurable architecture that combines the advantages of both: negrain exibility of gate arrays and coarse-grain efciency of word-length computations. They analyze the implementation of several common benchmarks, ranging from oating-point arithmetic to a radix-4 fast Fourier transform. The next three papers deal with process management (or threads and tasks) in recongurable multiprocessor systems. These papers consider run-time process management strategies in heterogeneous system; present a new parallel programming model for recongurable computing; and energy efcient management of tasks in recongurable multiprocessing environment. All three papers can be classied as process management in congurable multiprocessing environment. The rst paper of this group, Run-Time Management of a MPSoC Containing FPGA Fabric Tiles, by V. L. Nollet et al., deals with a heterogeneous multiprocessor system on recongurable hardware platform for multimedia applications. In such

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 1, JANUARY 2008

systems, the run-time assignment of tasks onto the communication and computation resources of a recongurable multiprocessor becomes inevitable. This paper presents a run-time task assignment heuristic that provides fast and efcient task assignment in an MPSoC containing ne-grain recongurable hardware tiles. The paper, Achieving Programming Model Abstractions for Recongurable Computing, by D. Andrews et al., introduces a programming model for specifying parallel threads running on a recongurable computing platform of hybrid CPU/FPGA system. The thread model abstracts the components on either side of the CPU/FPGA boundary into a unied, custom, threaded, multiprocessor architecture platform. This approach enables the use of standard thread communication and synchronization operations across the software/hardware boundary. In the last paper of this group, A Cooperative Management Scheme for Power Efcient Implementations of Real-Time Operating Systems on Soft Processors, by J. Ou and V. K. Prasanna, the process management in a real-time operating system is considered. This paper addresses energy efciency in a system of FPGA-based congurable soft processors, which is achieved using congurability of soft processors and managing interrupts and tasks. The implementations of two popular real-time operating systems on a state-of-the-art FPGA device are presented. The next two papers consider parallel processing applications on a recongurable computing platform. Both deal with network ow or trafc: one in computer network and the other in metropolitan road trafc network. The last one is also an example of using congurable computing platform for speeding up traditional supercomputing applications in science and engineering.

In the paper Recongurable Architecture for Network Flow Analysis, S. Yusuf et al., deal with parallel processing in analyzing network trafc in increasingly high network data rates. The multiple network ows are analyzed and processed in parallel using FPGA-based recongurable computing platform. This architecture can support ows at multigigabit rate, which is faster than most software-based solutions where acceptable data rates are typically no more than 100 million bits/s. The paper A Case Study of Hardware/Software Partitioning of Trafc Simulation on the Cray XD1, by J. L Tripp et al., presents a case study of a simulation of metropolitan road trafc networks. The problem is mapped onto a recongurable supercomputer, the Cray XD1. Five different methods are presented for mapping the application onto the combined hardware/software system. The results show that key predictors of performance are not necessarily maximum parallelism, but must account for the fraction of the problem that runs on the recongurable logic and the amount data ow between software and hardware. The last paper of this Special Section brings us back to the hardware architecture. The Recongurable Instruction Cell Array, by S. Khawam et al., presents an instruction cell-based recongurable computing architecture for low-power applications. Top-down software driven approach is used for development such array. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power DSPs processors, but still maintaining their throughput performance. TOOMAS P. PLAKS, Guest Editor London South Bank University London, SEI 0AA U.K.

Toomas P. Plaks (M95) received the Ph.D. degree in computer engineering from Chalmers University of Technology, Gothenburg, Sweden, and the M.Eng. degree in computer engineering and information processing from Tallinn Technical University, Tallinn, Estonia. He is the Managing Director and the founder of a newly established company, Conhard Design Ltd., London, U.K., in the area of mobile computing applications and hardware. He is also a Visiting Fellow of the Reading University, Reading, U.K., and the London South Bank University, London, U.K. His research interests include the design of high-performance application-specic processors, massively parallel computer systems, and recongurable architectures in mobile computing and multimedia applications. His main interests focus on the theory and design of regular processor arrays and mapping algorithms onto space and time, i.e., into hardware. Also, his interests include computer networking, mobile computing, and web-based technologies. He has published over 70 scientic papers including a monograph on a synthesis of regular processor arrays. He is the founder and the Chairman of the International Conference on Engineering of Recongurable Systems and Algorithms (ERSA) in Las Vegas, NV, and the initiator of Mobile Computing Hardware Architecture (MOCHA) Symposium, HI. He is the Guest Editor of a series of special issues on designing dedicated processors on recongurable computing platform. Dr. Plaks is a member of the New York Academy of Sciences and the U.K. Chapter of the Association for Computing Machinery Special Interest Group on Design Automation (ACM SIGDA). His biography is included in the Marquis Whos Who in Science and Engineering.