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Assignment 2

The document contains 8 questions related to computer architecture concepts like addressing modes, memory hierarchies, and cache performance. Question 1 asks to show the effective addresses and register contents for various addressing mode instructions. Question 2 asks to write program segments to perform stack operations using different addressing modes. Question 3 asks to write a program to perform an operation on memory locations using different instruction classes. The remaining questions ask about memory interleaving, cache hit ratios, cache addressing schemes, and calculating average memory access time for a nested loop accessing an array.

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Nzan Nkap
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122 views

Assignment 2

The document contains 8 questions related to computer architecture concepts like addressing modes, memory hierarchies, and cache performance. Question 1 asks to show the effective addresses and register contents for various addressing mode instructions. Question 2 asks to write program segments to perform stack operations using different addressing modes. Question 3 asks to write a program to perform an operation on memory locations using different instruction classes. The remaining questions ask about memory interleaving, cache hit ratios, cache addressing schemes, and calculating average memory access time for a nested loop accessing an array.

Uploaded by

Nzan Nkap
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment 2

1. Consider a computer that has a number of registers such that the three reg- isters R0 = 1500, R1 =
4500, and R2 = 1000. Show the effective address of memory and the registers’ contents in each of
the following instructions (assume that all numbers are decimal).

(a) ADD (R0)+, R2


(b) SUBTRACT-(R1),R2
(c) MOVE 500(R0), R2
(d) LOAD #5000, R2
(e) STORE R0, 100(R2)

2. Assume that the top of the stack in a program is pointed to by the register SP. You are required to
write program segments to perform each of the following tasks (assume that only the following
addressing modes are available: indexed, autoincrement, and autodecrement).

(a) Pop the top three elements of the stack, add them, and push the result back onto the stack.
(b) Pop the top two elements of the stack, subtract them, and push the results back onto the
stack.
(c) Push five elements (one at a time) onto the stack.
(d) Remove the top five elements from the top of the stack.
(e) Copy the third element from the top of the stack into register R0.

3. You are required to write a program segment that can perform the operation C A þ B where each
of A and B represents a set of 100 memory locations each storing a value such that the set of
values represented by A are stored starting at memory location 1000 and those represented by B
are stored starting at memory location 2000. The results should be stored starting at memory
location 3000. The above operation is to be performed using each of the following instruction
classes.
(a) A machine with one-address instructions
(b) A machine with one-and-half instructions
(c) A machine with two-address instructions
(d) A machine with three-address instructions
(e) A machine with zero-address instructions

4. Write program segments that perform the operation C each of the instruction classes indicated in
Question 3 above. Assume that A, B, and C are memory addresses.

5. Determine the memory interleaving factor required to obtain an average access time of less that 60
ns given that the main memory has an access time of 100 ns and the cache has an access time of 20
ns. What is the average access time of the resulting system?
6. What is the average access time of a system having three levels of memory, a cache memory, a
semiconductor main memory, and a magnetic disk second- ary memory, if the access times of the
memories are 20 ns, 100 ns, and 1 ms, respectively. The cache hit ratio is 90% and the main memory
hit ratio is 95%.
7. A computer system has an MM consisting of 16 MB 32-bit words. It also has an 8 KB cache. Assume
that the computer uses a byte-addressable mechan- ism. Determine the number of bits in each field of
the address in each of the following organizations:
a. Direct mapping with block size of one word
b. Direct mapping with a block size of eight words
c. Associative mapping with a block size of eight words
d. Set-associative mapping with a set size of four block and a block size of one word.
8. Consider the execution of the following program segment on an 8x8 array A.

For i: = 0 to 7 do
SUM: = 0
For j: = 0 to 7 do
SUM: = SUM + A(i,j)
End for
AVE(i): = SUM/8
End for

Assume that the main memory is divided into eight interleaved memory blocks and that each
cache memory block consists of eight elements. Assume also that the cache memory access time
is 10 ns and that the memory access time is ten times the cache memory access time. Compute
the average access time per element of the array A.

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