A 19-bit Monolithic Charge-Balancing A/D

Converter
by
Tung Shen Chew
S.M., Massachusetts Institute of Technology, 2011
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY 2 2W3
February 2013 LK~.AflIES
© Massachusetts Institute of Technology 2013. All rights reserved.

A uthor ................................................
Department of Electrical Engine ring and Computer Science
I Q,
February 1,2013
Certified by........ .. .. . ....-. . ...... r . . . - .
Charles G. Sodini
LeBel Professor of Electrical Engineering
A;I)
// / Thesis Supervisor
./ A,

Certifiedby . .. C ert............. d...... ...........

Barry Harvey
Analog Fellow at Intersil Corporation
Thesis Supervisor

Accepted by............... ....................................

Dennis M. Freeman
Chairman, Masters of Engineering Thesis Committee
2
 A 19-bit Monolithic Charge-Balancing A/D Converter
by
Tung Shen Chew

Submitted to the Department of Electrical Engineering and Computer Science

on February 1, 2013, in partial fulfillment of the
requirements for the degree of
Master of Engineering in Electrical Engineering

Abstract
Existing high-resolution ADC topologies are expensive, complicated and vulnerable
to switch leakage at high temperature. This thesis introduces the Modified Lands-
burg ADC, a high-resolution converter optimized for minimum cost and die area.
Switch resistance cancellation, charge-injection compensation and auto-zero methods
are used to build a simple and robust ADC which will operate reliably across the mil-
itary temperature range. Implemented on a 0.25pm CMOS process, with a die area
of under 300mil2, the Modified Landsburg ADC achieves an ENOB of 15.6 bits and
an SNR of 95.8dB at 5 Samples/s while consuming <2mW. It enables the integration
of a high-resolution converter in smaller, cheaper systems.

Thesis Supervisor: Charles G. Sodini

Title: LeBel Professor of Electrical Engineering

Thesis Supervisor: Barry Harvey

Title: Analog Fellow at Intersil Corporation

3
4
Acknowledgments

This project is both an industry design and an academic thesis, and what follows is a
frail attempt to thank everyone at Intersil Corporation and MIT who were involved
in its existence. There are of course some whose names I have missed, whose support
and encouragement were both welcome and needed. You know who you are!
Thank you, George Landsburg, for coming up with the Landsburg topology in
the late 70's. I realize that you didn't call it that - I've taken. the liberty of naming
it after you. Few ideas develop in a vacuum, and I imagine you had some people to
thank for it too.
Thank you, Barry Harvey, for unearthing the Landsburg and letting me play with
it. I've learned much from you about the philosophy and engineering of circuits. You
are a teacher, colleague and inspiration.
Thank you, Josh Baylor & Steven Herbst, for mentoring me through my time at
Intersil and helping me grapple with the oddities of Cadence. You are smart fellows,
good thinkers and great friends. I expect big things from you in the future!
Thank you, Professor Charles Sodini, for agreeing to be my thesis supervisor and
putting up with my erratic writing schedule. What I lack in timeliness, I hope I make
up for with a job well done.
Thank you, Anne Hunter, for helping me navigate the tangled web of the thesis-
writing process. You are a kind, empathetic lady, and I hope your influence is felt in
Course VI from now until eternity.
And finally: Thanks, Mum & Dad, for giving me life and daring me to dream.
As time passes I become more and more like you. That's great, because you're both
awesome people.

5
6
Contents

1 Introduction 15

1.1 Project Motivation . . . . . . . . . . . . . . . . . 15

1.2 Organization of Thesis . . . . . . . . . . . . . . . 17

2 The Landsburg ADC 19

2.1 Limitations of the Dual-Slope and CT EA ADC . . . . . . . . . . . 19

2.1.1 The Dual-Slope ADC . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.2 The Continuous Time EA ADC . . . . . . . . . . . . . . . . . 22

2.2 Introducing the Landsburg ADC . . . . . . . . . . . . . . . . . . . . 25

2.2.1 Locking the Number of Switch Transitions . . . . . . . . . . . 25

2.2.2 Discerning One-Clock Charge Differences . . . . . . . . . . . 26

2.2.3 The Autozero Mechanism . . . . . . . . . . . . . . . . . . . . 28

2.2.4 Putting It All Together . . . . . . . . . . . . . . . . . . . . . . 33

3 System Design of the Modified Landsburg ADC 35

3.1 Smaller Capacitors, Higher Resolution . . . . . . . . . . . . 36

3.1.1 Upper Limits on Resolution & Clock Frequency . . . 36

3.1.2 A Discussion of m and n . . . . . . . . . . . . . . . 38

3.1.3 Choosing Ci, Resolution & Clock Frequency . . . . 40

3.2 Single-Supply Operation & Eliminating the Reference Buffer 41

3.2.1 Switch Resistance Compensation . . . . . . . . . . . 43

3.3 Pseudo-Differential Inputs & Auto-Zero . . . . . . . . . . . . 44

3.3.1 Issues With Switch Leakage Current . . . . . . . . . 48

7
 3.3.2 Mixed-Signal Feedback Loop . . . . . . . . . . . . . . . . . . 49
3.3.3 Two Measure States . . . . . . . . . . . . . . . . . . . . . . . 58

3.4 Regenerative, Latched Comparator . . . . . . . . . . . . . . . . . . . 61

3.5 Digital Logic Tweaks . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.5.1 Residue-State Truncation . . . . . . . . . . . . . . . . . . . . 62

3.5.2 Overrange & Underrange Detection . . . . . . . . . . . . . . . 64

4 Circuit Design of the Modified Landsburg ADC 65

4.1 Input Switch Network . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.1.1 Transmission Gate Design . . . . . . . . . . . . . . . . . . . . 67

4.1.2 3-Way Break-Before-Make Logic . . . . . . . . . . . . . . . . . 68

4.2 Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.2.1 Input Properties . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.2.2 Gain & Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . 71

4.2.3 Bandwidth & Slew Rate . . . . . . . . . . . . . . . . . . . . . 71

4.3 Up/Down Current Source . . . . . . . . . . . . . . . . . . . . . . . . 73

4.4 Integrating Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5 Latching Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5 Noise Analysis 83
5.1 Integrated Noise Sources . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.2 Non-integrated Noise Sources . . . . . . . . . . . . . . . . . . . . . . 87

5.3 Normalized Total Noise . . . . . . . . . . . . . . . . . . . . . . . . . 88

6 Conclusion & Future Work 91

6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8
List of Figures

2-1 The Dual-Slope ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2-2 Charge on dual-slope integration capacitor . . . . . . . . . . . . . . . 21

2-3 The CT EA ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2-4 Charge on CT EA ADC integration capacitor . . . . . . . . . . . . . 23

2-5 Landsburg ADC 16-clock switching sequences: low (upper) & high
(low er) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2-6 Landsburg ADC residual charge measurement . . . . . . . . . . . . . 27

2-7 Landsburg ADC block diagram . . . . . . . . . . . . . . . . . . . . . 28

2-8 Landsburg ADC when performing AZ1 . . . . . . . . . . . . . . . . . 30

2-9 Block diagram of AZ1 feedback loop, complete (upper) and simplified
(low er) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2-10 Ripple-rejection sampling of va . . . . . . . . . . . . . . . . . . . . . 32

2-11 Landsburg ADC when performing AZ2 . . . . . . . . . . . . . . . . . 33

3-1 Landsburg ADC 16-clock switching sequences: original (upper) & mod-

ified (low er) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3-2 Landsburg ADC single supply modifications, with reference buffer (a),

without reference buffer (b), with constant summing-node impedance

(c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. 41

3-3 Simplified diagram of switch resistance compensation . . . . . . . . . 43

3-4 Implementation of switch resistance compensation . . . . . . . . . . . 44

3-5 100 Monte Carlo simulations of reference current drift over tempera-

ture, with Vref = 1.25V . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9
3-6 Landsburg ADC with pseudo-differential inputs & modified up/down
current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3-7 Landsburg ADC with gm-cell replacing Razf, in AZ1 configuration . . 47

3-8 Block diagram of AZ1 feedback loop with gm-cell replacing Razf, com-
plete (upper) & simplified (lower) . . . . . . . . . . . . . . . . . . . . 47

3-9 Landsburg ADC with current-splitting auto-zero resistors . . . . . . . 50

3-10 Landsburg ADC with 8-bit auto-zero current DAC . . . . . . . . . . 51

3-11 Transient simulation of mixed-signal AZ1 for various values of vi"_:

Vaz (upper) & DAC input code (lower) . . . . . . . . . . . . . . . . . 52

3-12 Change in DAC current, Aidac, due to a sine-wave at comparator input 53

3-13 Block diagram of mixed-signal feedback loop, complete (upper) & sim-
plified (lower) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3-14 Logarithmic plot of analog auto-zero loop gain (dashed line), DAC loop
gain (dash-dotted line) & combined loop gain (solid line) . . . . . . . 56

3-15 Transient simulation of mixed-signal AZ1 for various values of vi,

showing DAC input code, with 20mV offset mismatch between com-
parator & gm-cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3-16 Landsburg ADC with latching comparator and without auto-zero loop 59

3-17 vi,- and vi,+ input ranges, with (a) & without (b) auto-zero feedback
loop .......... .................................... 60

3-18 Comparator latch timing, with decision being made on the 4th clocki
rising edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3-19 Lansdburg ADC residual charge measurement, original (dotted line) &
truncated (solid line) . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4-1 Final version of Modified Landsburg ADC with labelled blocks . . . . 65

4-2 Transmission Gate design: transistor-level (a) & symbol (b) . . . . . 67

4-3 Transmission gate resistance over -1.25V to 1.75V range . . . . . . . 68

4-4 Arrangement of transmission gates in input switch network . . . . . . 68

4-5 3-Way Break-Before-Make logic: gate control (a) & break-detection (b) 69

10
4-6 Break-before-make input transition from vin+ to vin . . . . . . . . .. 70

4-7 Input buffer slewing behavior during one instance of Measure State &

Residue State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4-8 Block-level diagram of up/down current source . . . . . . . . . . . . . 73

4-9 Schematic of biasing cell, vref buffer, dummy switch and v"f
2Rrei current

source in the up/down current source . . . . . . . . . . . . . . . . . . 74

4-10 Schematic of break-before-make logic (a) and switches (b) in the up/down

current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4-11 Schematic of integrating amplifier . . . . . . . . . . . . . . . . . . . . 76

4-12 Simulated nominal frequency response of integrating amplifier, with

Vdd 3V, vref

3 = 1.25V . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4-13 Simulated settling behavior of integrating amplifier with vdd = 3V,

vref = 1.25V: vint (upper) and joint (lower) . . . . . . . . . . . . . . 78
4-14 Schematic of latching comparator . . . . . . . . . . . . . . . . . . . . 78

4-15 Simulation of comparator response to t0.5mV overdrive, with Vdd =

3V Vref = 1.25V: latch signal (upper), comparator output (middle) &

differential input signal (lower) . . . . . . . . . . . . . . . . . . . . . 79

4-16 Simulation of comparator transition time, with Vdd = 3V Vref = 1.25V:

latch signal (upper) & comparator output (lower) . . . . . . . . . . . 80

4-17 Simulation of comparator RMS noise, integrated over frequency, with

Vdd = 3V Vref = 1.25V: across 50fF capacitor (left axis) & referenced
to comparator input (right axis) . . . . . . . . . . . . . . . . . . . . . 81

5-1 Block diagram of modified Landsburg ADC with noise sources . . . . 83

5-2 Log-log magnitude plot of vc (8) transfer function with 0. is integration

tim e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5-3 Log-log magnitude plot of total ADC noise power at comparator input,

n,conversio(f) over frequency . . . . . . . . . . . . . . . . . . . . . . . 89

5-4 Log-log magnitude plot of noise power of the 2re current source, ic 1 (f) 90

11
12
List of Tables

1.1 Commercially available high-resolution, low-bandwidth ADCs . . . . 16

1.2 Academic high-resolution, low-bandwidth ADCs . . . . . . . . . . . . 16

3.1 Target specifications for modified Landsburg ADC . . . . . . . . . . . 35

4.1 Power & Area Budget of Circuit Blocks in Landsburg ADC . . . . . . 66

4.2 Truth Table for Input Switch Network . . . . . . . . . . . . . . . . . 67

4.3 Simulated nominal specifications of integrating amplifier . . . . . . . 76

5.1 Integrator summing node currents induced by noise sources . . . . . . 85

13
14
Chapter 1

Introduction

1.1 Project Motivation

Analog-to-digital converters (ADCs) act as an essential interface between the con-

tinuous, analog signals of the real world and the discretized signals which can be
processed by digital electronics. Multiple ADC architectures remain popular over
time because each one represents a specific compromise between speed, power, reso-
lution and cost. Depending on the requirements of an application, some architectures
are more suitable than others.
Many applications exist which require high resolution (>16 bits) at near-DC band-
width (<10Hz), such as handheld multimeters and temperature gauges. Historically,
the architecture of choice for such applications has been the dual-slope ADC, which
has since fallen out of favor due to the semiconductor industry's trend towards low-
voltage, fully-integrated, single-supply circuits. This is incompatible with the dual-
slope architecture's need for a fairly high supply voltage and large external capac-
itors. Table 1.1 shows four high-resolution commercial ADCs released in the last
decade[1] [2] [3] [4], whereas Table 1.2 shows a few' recent academic high-resolution
designs[5] [6] [7]. The discrete-time sigma-delta (DT EA) architecture is clearly dom-
inant among high-resolution designs.

'Very few examples are available, as recent academic ADC research is much more focused on
high bandwidth than high resolution.

15
 Table 1.1: Commercially available high-resolution, low-bandwidth ADCs
Product ISL26132 LTC2482 MCP3425 CS5526
Manufacturer Intersil Linear Tech Microchip Cirrus Logic
Year 2011 2005 2007 2005
Architecture DT EA DT EA DT EA DT EA
Resolution (bits) 24 16 16 20
Sample Rate (Samples/s) 10-80 6.8 15 15
INL error (ppm of FSR) 3 at 25 C 2 at 25 0C 10 at 25 0C 7 at 25 0 C
10 over temp 20 over temp 15 over temp
Approximate SNDR (dB) 111 97.5 97.5 109
Supply Current 10mA 160piA 155pA 1.65mA

Table 1.2: Academic high-resolution, low-bandwidth ADCs

Author J. E. Johnston C. B. Wang V. Quiquemmpoix
Year 1999 2000 2006
Architecture DT EA DT EA DT EA
Resolution (bits) 24 20 22
Sample Rate (Samples/s) 7.5 25k 15
INL error (ppm of FSR) 0
3 at 25 C 0
12 at 25 C 4 at 25 0C
Approximate SNDR (dB) 110 98 108
Supply Current - 15mA 120pA

There are several reasons why the DT EA architecture works poorly at high-
resolution. High-resolution DT EA ADCs require large switching capacitors to re-
duce L sampling noise to sub-LSB levels and minimize charge injection nonlinearity

(caused by the unpredictable number of switching transitions). These large capaci-

tors must be driven by an input buffer. The large capacitors and input buffer raise
the cost of the ADC, which is further increased by the need for an anti-aliasing input
filter. Finally, linearity cannot be maintained at high temperature due to switch leak-
age. These fundamental limitations indicate a need for a different ADC architecture,
tailored specifically for this role.

This paper describes a charge-balancing ADC which achieves high-resolution, low-

bandwidth performance at minimal cost. It is based on an architecture introduced by
George Landsburg in 1977 [8] (hereafter referred to as the Landsburg architecture).
The proposed changes to the architecture have focused on leveraging the advantages of

16
modern silicon and meeting contemporary expectations of an ADC 2 . The Landsburg
has been modified to run at a much higher resolution 3 , run off of a single 3-5V supply
and require no external components. Full use is made of the speed and inexpensive
digital logic of the modern 0.25pim process.

1.2 Organization of Thesis

Chapter 1 introduces the central problem of the thesis.

Chapter 2 is a thorough description of the original Landsburg ADC. It is described
in terms of its similarity to the dual-slope and continuous-time EA topologies.
Chapter 3 outlines the proposed architectural changes to match the Landsburg
ADC with modern needs and manufacturing capabilities. In-depth analysis is done
on the advantages and trade-offs of each modification.
Chapter 4 describes the various analog subsystems in the ADC: the input switch
network & amplifier, up/down current source, integrating amplifier and latching com-
parator. This chapter details the function, specifications and transistor-level imple-
mentation of each of these blocks.
Chapter 5 details how noise sources inside the ADC affect its output.
Chapter 6 concludes the thesis and suggests a direction for future work.

2
To the extent of the author's knowledge, this is the first time this architecture has been used
since Landsburg's original work.
319 bits, as opposed to the original 12 bits.

17
18
Chapter 2

The Landsburg ADC

2.1 Limitations of the Dual-Slope and CT EA ADC

As little work has been done on the Landsburg ADC since its conception, this thesis
will include a full description of its operation. We will first review two common low-
bandwidth, high-resolution ADC topologies: the dual-slope ADC and the Continuous-
Time Sigma-Delta (CT EA) ADC. They both work on the following principle:

1. Charge is added to a capacitor in a quantity (Qi) controlled by the input voltage.

2. A measured quantity of charge (Q2) is drained from the capacitor until the
charge added in step 1 has been precisely removed.

3. Q1 + Q2 = 0, so by measuring Q2, we measure Q, and hence the input voltage.

2.1.1 The Dual-Slope ADC

Figure 2-1 illustrates the dual-slope ADC, which is composed of an integrator, a

comparator and an input switch, Si. As shown in Figure 2-2, the dual-slope ADC
executes steps 1 and 2 sequentially to perform a conversion. The integration ca-
pacitor's voltage is initially at the comparator's threshold. In step 1, the integrator
integrates a current proportional to the input voltage for a fixed amount of time (tup).
At the end of tup, an additional voltage (and charge) proportional to the input voltage

19
 C
Vint

Sin R
Vin
Vref 0-0-

+ Comp Vcomp

Figure 2-1: The Dual-Slope ADC

has been stored on the integration capacitor. Charge added in step 1:

= up
Q1 = iintup

In step 2, the integration capacitor is discharged at a fixed rate set by the reference
voltage. The comparator flips after an additional duration of td,,n, when the added
charge from step 1 has been fully removed in step 2. Charge added in step 2:

Q -Vref tdon
R
Q2 = iref tdown -

The more charge which has been added in step 1, the more time required to remove
that charge in step 2. This results in a measurement of vin:

Q1 +Q2= 0

tdown
Vin = Vref t up

For a clocked system, rewriting t. = ntleock:

ndown
Vin = -Vref no p

While the dual-slope is a simple topology capable of very high resolution, it has

20
 Step 1: input currentintegration Step 2: reference currentintegration
I
I ~II
?c
slope a Vin

slope a vn I

fixed down - slope

ttup tdownl

tdown2

Figure 2-2: Charge on dual-slope integration capacitor

21
several major disadvantages.
Firstly, the ADC's output is derived from the timing of a single, extremely precise
comparator decision, which places harsh requirements on the speed, accuracy and
noise performance of the comparator. This is because the ADC performs steps 1 and
2 sequentially, adding and then removing charge. At the end of step 1, substantial
charge - and high voltage - accumulates on the integrating capacitor. This is the
high tip of the triangle in Figure 2-2, which may be over 100V in precision designs.
This substantial instantaneous charge requires that the integration capacitor be an
expensive external component with a very low voltage coefficient, increasing the bill-
of-materials and circuit board area required to use the ADC.
The comparator requirements are relaxed if the integrator is allowing to swing over
a relatively large voltage, allowing for faster, more decisive comparator transitions.
Nevertheless, this requires a high supply voltage which is incompatible with modern,
low-voltage manufacturing processes. For these reasons, the dual-slope ADC has
fallen out of mainstream use.

2.1.2 The Continuous Time EA ADC

Rin C
Sin
Vi n Vi nt

Sud Rref
+Vref/2
-Vref/2 0-

Comp Vcomp

Figure 2-3: The CT EA ADC

The CT EA topology, illustrated in Figure 2-3, differs from the dual-slope by

performing steps 1 and 2 simultaneously. The ADC integrates a current proportional
to vi,, for a fixed number of clock cycles. At the beginning of every clock cycle, a

22
decision is made to move the up-down switch, Sud to either +Ivref or -Vref. Over
the duration of that clock cycle, this either adds or subtracts a charge AQ = Vreftclck

This decision is made to drive the integrated charge towards zero; if Qjnt < 0, charge
is added, and if Qine > 0, charge is subtracted. The resulting (simplified) charge
waveform is shown in Figure 2-4 for a total of 10 clock cycles. The top dotted line
shows the total charge added by the input voltage (Qi) and the bottom dotted line
shows the total charge added by successive integrations of ±kVref (Q2). The solid
line is the sum of these two charges.

Qc

Step 1: integrated charge from vi,

- -Q - - -- - -
1

tN

%' %

2
Step 2: known charge removed by±vTf1 % OF e

tclock

Figure 2-4: Charge on CT EA ADC integration capacitor

Assuming that charge is added for nad cycles and charge is subtracted for nsubtract
cycles, the total charge contributed by step 2 is:

Vreftdcock
Q2 = &ei (nadd - nsubtract)
2Rref

Hence we can find vin as a function of nadd and nsubtract:

Vintclock
Q1 ~ iintup (~~add+ nsubtract

Q1+Q2=0

23
 Rin nsubtract - nadd
Vin ~~ Vref
2Rref subtract + nadd

In the example in Figure 2-4, with nadd= 4 and nsubtract = 6:

Rin 6 - 4
Vin = re 2 f re 6 + 4

As long as < the negative feedback action will always limit the inte-
grated charge to within +(I| l +IIre, I)tcloc. In other words, by performing steps
1 and 2 simultaneously (adding and subtracting charge simultaneously) we manage
to drastically reduce the peak charge and voltage on the capacitor. This circumvents
several problems with the dual-slope ADC: a small, on-chip integrating capacitor can
be used and the ADC can be implemented on a low-voltage manufacturing process.
Demands on comparator performance are greatly reduced, as the ADC output is no
longer derived from a single, precise comparator decision. Instead it is a result of
many decisions, one every clock cycle, where the comparator is triggered off of a
much larger, faster waveform.

Nevertheless, the CT EA ADC has a source of nonlinearity which compromises

its use for high-resolution conversion. Every clock cycle, Sed is set to either +"Vref

or - Vref. During each transition between +Vref and -jVref, charge is injected
from Sud into the integrating capacitor. As the number of switch transitions is unpre-
dictable, this ill-defined number of charge injections appears as noise and nonlinearity
at the CT EA ADC's output[10]. High-resolution EA ADCs are still built in spite
of this effect, albeit with several engineering workarounds. These include the use
of bigger capacitors, higher integration currents and larger switches with carefully
balanced positive and negative charge injections. As these workarounds do not scale
well to a small, low-cost design, the following section will offer a method to lock the
number of switch transitions.

24
2.2 Introducing the Landsburg ADC

2.2.1 Locking the Number of Switch Transitions

This section describes a return-to-zero method which fixes the number of switch tran-
sitions to improve the linearity of the CT EA ADC. If the number of switch transitions
(and hence the quantity of charge injection) is constant for each measurement, this
charge injection results in input offset instead of nonlinearity and noise. This off-
set can then be removed using zero-offset calibration techniques, to be discussed in
Chapter 2.2.3.

VRref

tclock

Varef

+Vregf/2
t
-V,,,r12

tclock

Figure 2-5: Landsburg ADC 16-clock

2 switching
2 sequences: low (upper) &high (lower)

Previously, a decision was made to set Sud to +"Vref or -j1ore, at the start of

every clock cycle. Consider a system where this decision is made every 16 clock
cycles instead, and sets the +.Ivref or -jVref pattern for the next 16 cycles. In order
to force one +"Vref to -joref transition and one -"Vref to +'Vreyf transition, the
16-clock sequences in Figure 2-5 are used. The first cycle in each sequence is always
high and the last cycle in each sequence is always low, so one transition in each
direction must occur. As the charge from the first cycle cancels out the charge from
the last cycle, the high and low sequences add or subtract 14 cycles of charge from
the integrating capacitor. Hence, denoting the number of high and low sequences as

25
Nhigh and N1 ,, respectively, vi, can be found:

Q1 = iintup= Vintclock 16(Nhigh + Niow)

Rrn

Q2= Vreftdock 14(Nhigh - Nio,)

2Rref

Q1 + Q2 = 0

Rin 14(Nio, - Nhigh)

2Ref 16(Niow + Nhgoh)

Defining the total integration time, tintegration = tcdocknintegration = 1 6 tcockNintegration,

where Nintegration = nintegration = Nhigh + Nio,:

Rin 14(2Nio, - Nintegration)

Vin = Vref 2 Rref 1 6 Nintegration

While this system has improved linearity over the CT EA ADC, it requires a

much faster clock. If each 16-clock pattern represents one count, a clock with 16x

frequency will be needed, compared to a CT EA ADC of equal resolution.

What if we define a single-clock charge difference to be one count, and we add an

additional mechanism to measure single-clock charge differences? Then each 16-clock

pattern represents 14 counts, and we only need a clock with 6 x frequency, compared

to a CT EA ADC of equal resolution. The next section will explain how this is

implemented in the Landsburg architecture.

2.2.2 Discerning One-Clock Charge Differences

Defining dont as the digital output code:

dout = Ldout/14] + dout mod 14

where we have only been able to discern the [dont/1 4 ] term. The remainder, dout mod 14

comes from the residual charge on the integrating capacitor at the end of the conver-

sion, which should be in the range of ±142ef tdock. In order to measure this charge,

26
the Landsburg behaves like a 5-bit dual-slope converter. Figure 2-6 illustrates this
behavior for two example values of residual charge, Qresi and Qres2. In both cases,
after nint 16-cycle-sequence integration cycles, Sin is opened to halt any further cur-
rent from vin and preserve the residual charge on the integrating capacitor. Sud is
then set to -}Vref to integrate up for a fixed number of cycles (nw,). This ensures
that Q, > 0 before the final down-integration. Finally, as in the dual-slope ADC, the
integration capacitor is discharged at a fixed rate (by setting Sud to +-Vrej) until an
up-to-down comparator transition occurs. The number of clock cycles which elapse
before the comparator transition (ndmv) indicate how much residual charge remained.
The entire conversion can be summarized with the formula:

2 (in
U14(2Naw - Nintegration) + nIown - nup)
re R,.e \ 16 Nintegration

vin is disconnected,
saving residual

QC GC charge

Qresl-------------------------- -

Vnninn

n nt

nup ndown2

Figure 2-6: Landsburg ADC residual charge measurement

The up-integration is always performed before the down-integration to ensure that

the output is always measured on the up-to-down comparator transition. This elim-

inates the effects of comparator hysteresis. This up-integration must be performed

long enough to be certain that vint is above the comparator threshold before the

27
down-integration. Since the residual charge, Q.e on the integrating capacitor is in
the range of -14 to +14 clock cycles of charge, it can be assumed that vit will be
above the comparator threshold if you up-integrate for more than 14 clock cycles. In
other words, it is necessary for nu to be greater than 14. Similarly, ndow,,max must
be greater than (nup + 14) clock cycles to ensure that the up-to-down comparator
transition occurs.
The Landsburg ADC can be thought of as a split ADC. During the 'Measure
State', it acts as a first-order CT EA ADC with a fixed number of switch transitions
in order to find Ldout/14]. It then proceeds to the 'Residue State', where it behaves
like a dual-slope ADC to measure the remaining dut mod 14. One part of the system
remains to be explained: the autozero mechanism.

2.2.3 The Autozero Mechanism

Reference Sud
Buffer +Vref

Up/Down
Current
Source

Rref

'I
Sin Clint movint
Vin Rin

+ > Comparator Vcomp

Input Suffer
Integrating
Amplifier

Ca Saz

aaz + az
Auto-Zero Raz A
Current -
Source

Auto-Zero
Buffer

Figure 2-7: Landsburg ADC block diagram

28
 Figure 2-7 shows a block diagram of the Landsburg ADC. As in Figure 2-3, R,
6
supplies the Lu- current which is integrated over nintegration = 1 Nintegration clock
RVre

cycles. In order to add or subtract the Rref current, the up-down switch (Sad) is
Vref through
controlled to source a current of either 0 or Rref Rref. The current through
Raz is calibrated (by controlling the stored voltage on Caz) such that the combined
current into the integrating capacitor is Vi ± . This Raz current is nominally
- Vre but will adjust to provide additional current to null the effects of the main

offset sources in the circuit. These sources are as follows:

1. Integrating amplifier input offset voltage, Voffset,intamp

2. Integrating amplifier input bias current, ibias,intamp

3. Input buffer input offset voltage, Voffset,inamp

4. Auto-zero buffer input offset voltage, Voffset,AZamp

5. Reference buffer input offset voltage, Voffset,ref amp

6. Asymmetrical charge injection from up-down and down-up switching transitions

7. Comparator input offset voltage, Voffset,cwmp

The first six offset sources cause additional currents to flow into Cint. Sources 1-5
contribute additional currents of V!fsetmntamp
RinJlRref IIRaz, I bias,intamp, Voffset,inamp
Rin 7
Voffset,AZamp
Raz
and
Voffsetref amp respectively. The current from Source 6 is highly variable with switching
Rref

speeds and temperature. The first auto-zero mechanism (AZ1) uses a feedback loop
to store a precise voltage on Caz such that the current into Cit is *
Rin
t+vref,.
2Rref
The
second auto-zero mechanism (AZ2) ensures that Cint is charged to the comparator's

transition voltage at the beginning of each measurement. This is essential as the

comparator's transition voltage is Voffset,cmp above ground.

Figure 2-8 shows the ADC configuration during AZ1. Switches Sin and Sed are

both set to simulate the conditions of a zero input voltage: Si, grounds the input, and

Sud alternates between Vref and ground every 8 clock cycles. This creates a sequence
which repeats every 16 clock cycles, containing one down-to-up transition and one

up-to-down transition. As with a zero input signal, this waveform spends equal time

integrating up as it does integrating down. Sa, is closed to form a feedback loop

29
 Sud
Reference VreT
Buffer +
--
Up/Down
Current -
Source VSud r
V0,

Rref

* in
Vin _ sin Rin

+ Comparator Vcomp
Input Buffer
Integrating
Amnplifier
Saz
Caz

Auto-Zero Raz +
Current -
Source -az

Auto-Zero
Buffer

Figure 2-8: Landsburg ADC when performing AZ

which servos the integration current (i.e. the current into Cit) to - + 2± . With
the grounded input buffer, the integration current should be ± 2R,,f
ref

Consider the case where vaz = 0. With the switching waveform in Figure 2-5,
Vref (in other words,
the integration current will be 0 or Rref ref
2Rref
± r
2Rref
) as well as
the currents caused by offset sources 1-5. The feedback loop thus has to set vaz such
that iRz = -2 in addition to the currents from the offset sources. The resultant
integrating current is the desired t rf

The feedback loop dynamics are illustrated in Figure 2-9. There is a 2nd-order
low-pass filter response from the switching voltage, VS.d to the voltage stored on the
auto-zero capacitor, vz. This can be seen in the transfer function:

Vaz(S) _ Raz 1

Vsd(s) R,; ( 1+ sRazCaz + sRazCint(l + sRazfCaz))

VS.d is a square wave between 0 and Vref, of frequency 1 with a 50% duty cycle. It

is the superposition of a high-frequency, jVref square wave and an average voltage of

30
 Raz

1 LRref lint Vint ~ iRazf

s + -- +--+Vaz
ud Rre sCint Raz sCaz

int
,"LRre V int
V ~ R 0 - -s -+Vaz
sf Th ref sCint o + higazICaz

1
sCaz +
Raz

Figure 2-9: Block diagram of AZ1 feedback loop, complete (upper) and simplified
(lower)

The low-pass filter response filters out the high-frequency switching, allowing
} Vref.
the average voltage to be captured on the auto-zero capacitor. While the low loop
bandwidth is necessary to filter out the high-frequency switching, it mandates that
AZI must be run for a long period of time for vaz to converge to the full resolution of
the ADC. A timing technique is used to further reject the high-frequency switching:
due to the 2nd-order low-pass filtering, high frequencies will have a known phase-shift
of 1800. Hence the opening of Saz (to sample & store Vaz onto Caz) can be timed to

the exact moment when the ripple is at its midpoint, to minimize the amount of
ripple which is sampled. This is shown in Figure 2-10.

To show that this feedback loop causes the integrating current to converge to
± '
1 , consider the circuit in Figure 2-8. During AZI, the integrating current is the
sum of currents from the up/down current source, the auto-zero current source and
offset sources 1-5. Any low-frequency component of the integrating current will not
be filtered out by the low-pass nature of the feedback loop, and will cause a shift in

Vaz. As a result, the loop will servo va, until there is no longer any low-frequency
component in the integrating current, converging to just the high-frequency ± -Cf

31
 0

-02

-046

-0.6 -1

-0.8

V Ripple is at its Sz oeed to occv,,

Rwhen ipple is atits
nidpoin4 further
rejecing ripple

-1.2

-14
0 0 01 002 0,03 0,04 0,05 0.06
time(s)

Figure 2-10: Ripple-rejection sampling of Vaz

square wave. During the Measure State, Saz is opened and S, is connected to V .

This results in the integrating current becoming vin t ref, controlled by the position

of Sad.

It is necessary for this feedback loop to have low bandwidth in order to filter out

the high-frequency switching. As a result, it takes a long time (50ms in the original

design) for the loop to converge to the full resolution of the ADC.

The purpose of the second auto-zero mechanism, AZ2, is to compensate for the

comparator's input offset voltage (offset source 6). As the comparator's transition

voltage is the baseline for 'zero' charge stored on the integration capacitor, it is nec-

essary to set vint to the comparator's transition voltage at the beginning of conversion.

This is done with the circuit configured as in Figure 2-11. Due to the adjustment of

vaz in AZ1, the integration current is either ref

2Rref or - 2ref
vrf, depending on the position

of Sad. To move vint to the comparator's transition voltage, Sed is set to integrate
down if vpOM is high, and integrate up if vmOp is low. This creates the 'converge and

dither' pattern for vint which can be seen in Figure 2-11. As long as AZ2 is run long

enough for Vint to travel from the supply rails to the comparator transition voltage

32
 Sud C
Reference
Buffer +

Up/Down

sd Eu
Current -

- if lcomp
ref
Source
0if 17comp

Rref

I
VA Sin
Vin + Rin F nt 11 0Vint

+ Comparator Vcmp
Input Buffer
Integrating
Amplifier I

Caz Saz Vn

Jaz + Vty., converges to vff,,,,

Auto-Zero Raz
t
Current
Source

Auto- Zerr
Buffer

Figure 2-11: Landsburg ADC when performing AZ2

(Voffset,comp), Vint will end up dithering around the Voffset,comp by the end of AZ2. A
change in polarity at the comparator's input will effect a change in integration current
between - ref
2Rref and 2Rref
ref , and the time delay of this change, tdelay,AZ21o, affects the
closeness with which Vof fset,com, dithers around vit. Neglecting noise, the following
upper bound can be placed upon this dithering:

Voffset,comp - I
Vint dither < VreftdelayAZ21oot
2
Rref Cint

2.2.4 Putting It All Together

A single conversion using the Landsburg ADC thus involves the following sequential
steps:

1. AZ1, to set Vaz and cancel out offset sources 1-5.

2. AZ2, to set Vint to the comparator threshold and cancel out offset source 6.

33
 3. Measure State, to measure the output down to a 14 LSB resolution. (Chapter
2.2.1)
4. Residue State, to measure the mod 14 residue of the output and provide unit
clock resolution. (Chapter 2.2.2)

In the original Landsburg ADC described in [8], AZ1 was run for 50ms per con-
version, whereas the Measure State was run for 100ms to reject 50Hz and 60Hz noise.
AZ2 and the Residue State required a negligible duration of time. This gave the ADC
a sample rate of roughly 6.6 Samples/s at 12-bit resolution with a 30kHz clock.

34
Chapter 3

System Design of the Modified

Landsburg ADC

This chapter describes various architectural changes made to the Landsburg ADC to
meet modern standards of ADC performance. Each change moves the design towards
being a fully-monolithic, high-resolution, single-supply ADC with pseudo-differential
inputs, implemented on a .25pum CMOS process. The target specifications of this
design are in Table 3.1.

Table 3.1: Target specifications for modified Landsburg ADC

Sample Rate 5 Samples/s
Resolution 19 bits
Power Consumption approximately 1.5mW
Supply Voltage 3V - 5V
Reference Voltage 1.25V 0 3V supply, 2.5V @ 5V supply
Input Offset <1 LSB
Gain Error <0.01% over temp
INL <1 LSB (<0.0002%) Full-Scale
Operating Temperature -40 0 C - 125 0 C

35
3.1 Smaller Capacitors, Higher Resolution

The original Landsburg architecture has two large capacitors: the integrating capac-

itor and auto-zero capacitor, each of which are on the order of dozens of nanofarads

[9]. These capacitors must be shrunk to a few hundred picofarads at most, so that

they can be placed on-die. Consider the voltage change at the output of the integrator

as it integrates a constant current, I, for one clock cycle (the integrator has negative

gain):

Avint - tcdock
Cint

Reducing the capacitor size magnifies the voltage change. This is analogous to scaling

up the entire Vint waveform, which will clip (causing a loss of linearity) as it is limited

by the supply voltage rails. In order to reduce the capacitance while staying within

the limits of the power supply, our options are to reduce the current and the length

of each clock cycle (i.e. increase the clock frequency). There are other reasons for

increasing the clock frequency. As the Landsburg ADC is an oversampling converter,

its resolution increases linearly with clock frequency, so increasing clock frequency

while keeping the Measure State time constant will increase the resolution of the

converter.

3.1.1 Upper Limits on Resolution & Clock Frequency

What factors limit the clock frequency? Observe the main blocks of the Landsburg

ADC in Figure 2-7. Of these, the input buffer and auto-zero buffer are only required

to pass low-frequency signals. While the comparator's output must settle in less than

one clock cycle, a fast-settling, low-power comparator can be built using a regenerative

latching topology. The comparator's settling time is not the limiting factor on clock

frequency.

In general, the most demanding and power-hungry parts of a system are those

which require both high bandwidth and high precision. In the Landsburg ADC,
these parts are the integrating amplifier and reference buffer. Consider the 16-clock

return-to-zero sequences described in Chapter 2.2.1 and reproduced in the upper half

36
 Available SettlingTime
Available SettlingTime

0. 1 1 11
t
1 clock up, 15 clocks dawn L 15 clocks up, 1 clock down
tcla*k

Available SettlingTime
Available SettlingTime
I I
Vet
JffiWI t
t 0.
2 clocks up, 14 clocks down In- 14 clocksup, 2 clocks down
teack tclack

Figure 3-1: Landsburg ADC 16-clock switching sequences: original (upper) & modi-
fled (lower)

of Figure 3-1. The fastest transition which much be captured to full 19-bit accuracy
is the single high pulse in the low-sequence and the single low pulse in the high-
sequence. In other words, it is necessary for the integrating amplifier and reference
buffer to achieve >19-bit settling within a single clock cycle. The main constraint on
the maximum clock frequency (and maximum resolution) of the Landsburg ADC is
the full-resolution settling time of theses two components.

Fast, high-resolution settling requires the use of a high-bandwidth, high-gain,

dominant-pole amplifier. The limits of the manufacturing process will determine
the maximum achievable performance of this amplifier, which in turn defines the
maximum performance of the ADC. What can be done to extend the ADC's resolution
beyond this limit?

Consider the alternative set of 16-clock return-to-zero sequences in the lower half
of Figure 3-1. In the original set of sequences, every 16-clock sequence added or
subtracted 14 cycles of charge, as the first high pulse always negated the last low
pulse. In this new set, every 16-clock sequence adds or subtracts 12 cycles of charge,
as the first two high pulses always negate the last two low pulses. As described in
Chapter 2.2.2, the original Landsburg ADC's Measure State measures [dot/14J and
its Residue State measures dot mod 14. In this modified version, the Measure State
measures [dmt/12J and the Residue State measures dot mod 12. The overall gain

37
equation is now:

V Rin 12(2Nlo - Nintegration) + ndown - nup

Vi =Vref 2 re - 16Nintegration

As each 16-clock sequence now causes a change of 12 (instead of 14) cycles of charge,

12 = 116.7%
we would need a clock which is 1- the speed of an equal-resolution original

Landsburg ADC. However, the integrating amplifier and reference buffer now have

2 clock cycles to achieve >19-bit settling, and a correspondingly lower bandwidth.

While the required clock speed has increased by 16.7%, the required bandwidth for

these two circuit blocks has gone down to 11 = 58.3% of its original value. For a

given amplifier settling time, the ADC can now be run to a clock speed and resolution
which is 212 = 171.4% of its original limit.

We can generalize by saying that the return-to-zero sequences are m cycles long.

Within each m-clock sequence, the first n cycles are always high and the last n cycles

are always low. The original Landsburg then used m = 16 and n = 1, whereas the

modified Landsburg uses m = 16 and n = 2. In an ADC with R-bit resolution,

the integrating amplifier and reference buffer are required to settle to over R-bit

accuracy within ntdok time. Every m-clock sequence adds or subtracts (m - 2n)

cycles of charge. The range of possible outputs is 2 R-1 counts above and below

ground, requiring the Measure State to run for ( 2 R-12n2) clocks. The generalized

gain equation is then:

Vin = in (n - 2n)(2N 0 v - Nintegration) + ndown - nu)

vi=vr;2 Rref ( Nintegration

3.1.2 A Discussion of m and n

In order to optimi'ze our choice of m and n, we must consider their effect on the output

swing of the integrating amplifier. As previously established, it is essential that its

output does not clip in order to preserve linearity. Every m clock cycles, Snd is set such

that Vint moves towards the comparator threshold (Voffset,comp) during the following

m clock cycles.The largest possible voltage difference between vint and voffset,comp is

38
the furthest distance that vint can travel away from vo1 fset,comp during those m clock

cycles. The upper and lower bounds on this voltage difference correspond to the

minimum and maximum input current (iin), beyond which the ADC goes underrange

or overrange.

What is the minimum and maximum input current? After AZI calibration, we

know the integration current, iint = R,± 2Rref

Vf = iin + iu, where iud is the up/down
current. If the input current is within bounds, this means that the average up/down

current is of sufficient magnitude to overwhelm the input current and pull vint towards

the comparator threshold. The most extreme average up/down currents are achieved

if Sud performs just the 'high' sequence ((m - n) high pulses followed by n low pulses)
or just the 'low' sequence (n high pulses followed by (m - n) low pulses) for the

entire duration of the Measure State. Thus the two most extreme average up/down

currents are 2Rre-f

m-2n
m
and - 2Rref
'Vref
m
". It follows that the minimum and maximum

input currents are just within -Vref

2R,ef
m-2n
m
and Vref m-2n
2Rref m

Now we can finally calculate the maximum and minimum voltage difference be-

tween vint and Voffset,comp. As the integrator has negative gain, the maximum differ-

ence is when iin = Vref

- 2Rref m-2n
m
and Sud performs the 'low' sequence. vint starts just be-
low Vof1 f set,comp, travels downwards for n cycles (integrating a current of -vref m- 2n+

2Rf) and then travels upwards for (m - n) clock cycles (integrating a current of
V-4 m-2n - e ). Calculating [Vint - Voffset,comp]max'
2Rref m nrf

[Vint - Voffset,comp]max = tdock Vref n(- m -2n+ 1) + (n - n)(- - 1))

Cint 2Rref M

[Vint - Voffset,comp]max tdk 2 Vref 2 (in - 2n)

Cint Rref

Similarly, the minimum difference is when i Vref m-2n and Sud performs the

'high' sequence. vint starts just above Voffset,comp, travels downwards for (m - n)

cycles (integrating a current of Vrf m-2n + f,) and then travels upwards for n
2 ref m - 2 ref
clock cycles (integrating a current of e- m.n
2Rrei m 2Rrei
). The lowest voltage in this

sequence is after (in - n) cycles, just before Vin- begins travelling upwards. Calculating

39
Vint - Vof fset,compl min *

[Vint - Vof f set,comp] min - tdock Vref - 2 +

2
Cint Rref m - n)( M

2
[Vint - Vo ffset,comp]min = -tdock 2Vref (m - 2n +2n)

It can be seen that the magnitude of [vint - Voffset,comp]min is slightly greater than

[Vint - Voffset,comp]max. This asymmetry is because VS.d in Figure 3-1 always goes high
at the beginning of the sequence before going low, in other words, Vint starts moving

downwards before moving upwards. This asymmetry can be reversed by switching

the order of the m-clock sequences, by having the first n pulses always be low and

the last n pulses always be high.

With all these equations, how do we choose m and n? n can range from 1 to m.

While increasing n loosens the settling-time requirements for the integrating amplifier

and reference buffer, it also increases the number of clock cycles required to perform

a conversion, as does decreasing m. As 2n approaches m, the number of clock cycles

approaches infinity. One approach is to start with n = 1 and increase n if the

amplifier settling times are just too slow for the target speed & resolution. Increasing

m decreases the number of clock cycles per conversion (allowing the use of a slower

clock) but also increases the required size of Cint to keep the integrator output swing

from clipping. The eventual choice of m = 16 and n = 2 is a compromise between

these effects.

3.1.3 Choosing Cint, Resolution & Clock Frequency

With m = 16, n = 2 and a total Measure State time of 0.1s (to reject 50Hz and

60Hz), we can calculate a need for at least ( 2R-1 m 2 n) ~ 350000 clock cycles. With a

target resolution of 19 bits, this implies a clock frequency of >3.5MHz; 3.6MHz was

chosen for redundancy. Ref = 200kQ and Cint = 50pF were also chosen. With a

2.5V reference, this results in a 0.84V to -0.85V integrator output swing around the

comparator threshold. Using the smaller 1.25V reference, the range becomes 420mV

40
to -430mV. As described in Chapter 4.4, this fairly small voltage swing was chosen

as it was not possible to build an integrating amplifier with rail-to-rail outputs which

also met the gain, bandwidth and power requirements.

3.2 Single-Supply Operation & Eliminating the Ref-

erence Buffer

The original Landsburg design uses bipolar power supplies and a ground-referenced

voltage reference. The switching voltage (controlled by Sad) varies between 0 and v,ef

relative to the integrator's summing node, which is biased at ground. During AZI,

the negative gain of the VSd to vaz transfer function causes vaz to servo to a voltage

below the integrator's summing node.

From
Auto- Zero Buffer

Cint
Raz Vint

Rin

From
Input Buffer +-Comparator Vcomp
Integrating vref
Amplifier

) b) Rref2 Sud

Rref

Vref Vrel
Vref
BRkference RefereceSud
su r Vr:
Buffer Vrr Sud Sjud

Rref Rref

L -------------------------------- - ..-- ...-...--. -----------------------------

Figure 3-2: Landsburg ADC single supply modifications, with reference buffer (a),
without reference buffer (b), with constant summing-node impedance (c)

In order to adapt the Landsburg to single-supply operation, it is necessary to flip it

41
upside-down. As shown in Figure 3-2a, the integrator summing node and comparator

threshold are now biased at vref. As the amplifiers and comparator are powered from

ground to the positive rail (vdd), there is a voltage headroom of -Vref to (Vdd - Vref)
around the summing node. In this new configuration, the switching voltage now

varies between -VTef and 0 relative to the integrator summing node. Vaz then servos

to a voltage above the integrator summing node.

In this new configuration, the summing node is now (Vref + Volfset,intamp) above
ground, where Voffset,intamp is the input offset of the integrating amplifier. Assuming

that Voffset,intamp is small, Rref can simply be connected between the summing node

and ground to sink a (g + V"/" R-mP) reference current. A switch in series with
Ref allows this current to be turned on and off, as shown in Figure 3-2b. A double-

throw switch is used to connect Rref to a basic Vref buffer when the reference current

is not being sunk from the summing node. This ensures that Rref has consistent,
code-independent self-heating, so that code-dependent temperature (and resistance)

changes do not introduce non-linearity. The reference buffer is a fast-settling, high-

gain, rail-to-rail amplifier. Its removal significantly reduces the cost of the Landsburg

architecture.

In order to maintain consistent summing node impedance (and preserve linearity),

an additional reference resistor (Rref2) is added, as shown in Figure 3-2c. This resistor

is connected from Vref to the summing node when Rref is not connected. As this

resistor pulls very minimal current (Vfsetintamp), its matching to Ref is not critical.
In simulation, as much as 3% mismatch between Rref and Rref 2 did not produce a

measurable increase in INL. This 'ffset intamp current also cancels out the vffsetintamp
Rref2 Rref

term of the Rref reference current, removing the gain error caused by the integrating

amplifier's input offset.

This description is incomplete because it assumes that there is no voltage drop

across the switches. Taking switch resistance into account, the reference current

through Rref will be less than vref and no longer ratiometric with Rin, increasing

the ADC's gain drift over temperature. The next section describes a method to

compensate for finite, nonlinear switch resistance.

42
3.2.1 Switch Resistance Compensation

Cint

Vdd Vint
V+ +
-Vref/Rref Integrating
Amplifier

Dunmy
Sud Switch

Rref + Vref

Figure 3-3: Simplified diagram of switch resistance compensation

As illustrated in Figure 3-3, switch resistance compensation is performed by using

a dummy switch to replicated the voltage drop across Suad. The intended current
through Ref is Rf, so a rough approximation of this current is made (using a resistor
and current mirror, not shown) and sourced into the dummy switch. Denoting the
voltage across the switch as Vswitch, we can describe the voltage at the integrating
amplifier's positive input:

V+in,intamp = Vref + Vswitch,dummy

Assuming the amplifier's inputs are at the same voltage:

V-in,intamp = V+in,intamp = Vref + Vswitch,dummy

V-in,intamp ~ i Re, Rref + Vswitch,Sud Vref

V + Vswitch,dummy

The dummy switch and Sud are well-matched and in close thermal proximity. If
they are carrying almost the same current, then Vswitch,Sud Vswitch,dummy.
V This
implies that iRref Rref Vref, SO iV f~ Rref
ref and the switches are carrying almost

43
the same current. Figure 3-5 shows a temperature sweep over 100 Monte Carlo

simulations, comparing the current of the switch and resistor against just a resistor.

With a 1.25V reference, the ±3u worst-case deviation from purely resistive behavior is

0.38ppm/ 0 C, producing a gain error of 0.006% over the entire operating temperature.

The corresponding worst-case deviation using a 2.5V reference is 0.25ppm/ 0 C, or

0.004%. Both are within the <0.01% gain error target.

From
Auto-Zero Buffer

Cint
SVint
Ra
Rin Rzi

From
Input Buffer + Comparator Vcomp

Vdd Integrating Vref

V+ Amplifier
~Vref/Rref

Sud V-
Vref 4Rref2 Dummy
Sud Swih

JRr ef
Vref

Figure 3-4: Implementation of switch resistance compensation

3.3 Pseudo-Differential Inputs & Auto-Zero

Consider the auto-zero mechanism illustrated in Figure 2-9. By using an up/down

waveform with a 50% duty cycle during AZI, we are instructing the ADC to regard

the ground voltage at the input buffer (as set by Si,) as the zero-point of the measure-

ment, and store this information as a voltage across Caz. If we switch Sud between

differential input pins vi,- and vi,_ instead of vir, and ground, the ADC is able to

44
 6.25040u - -

6.2500u - -- -

6.250 -- -- - - --------- ~
6.24980u

6.24960u - ~
- -
-A....

6.24940u --------
-40.0 -20.0 0.00 20.0 40.0 60.0 80.0 100 120
Temp (C)

Figure 3-5: 100 Monte Carlo simulations of reference current drift over temperature,
with v,ef = 1.25V

measure a pseudo-differential' voltage vi, = (Vin+ - Vin_). In this configuration, AZ1

is essentially an analog Measure State which stores its measurement of vin_ using
C, as analog memory. The auto-zero mechanism is thus modified to provide pseudo-
differential inputs. Figure 3-6 illustrates the input buffer connected in this manner,
including the modifications from Chapter 3.2.
The next step is to replace Razf with a gm-cell, as shown in Figure 3-7. This
is done to relax the design requirements on the integrating amplifier, which already
needs high gain and fast settling behavior. If the integrating amplifier directly drives
Razf, it will also need a low-impedance output stage and significant output swing.
These two requirements go away if we replace Razf with a MOS-input, rail-to-rail
gm-cell. Figure 3-8 shows the updated AZ1 feedback loop dynamics. It can be shown
that this loop is stable (with phase margin > 450) if gmazfRaz > 1.
cint

'In a fully differential system, vin+ and vi,_ would be measured simultaneously. This ADC
is 'pseudo-differential' because vi,_ is measured during AZ1, followed by vin+ which is measured
during the Measure State.

45
 Auto-Zero
BufferI-

Auto-Zero Razf
Current
Source Raz
Caz
Saz
-az +

Pseudo-Differential Inputs Cint

p. Vint
+ Rin
Vin- O-

er
A
f
pn1t uf + Comparator Vcomp
-
Vdd Integrating Vref
V+ Amplifier
~Vref/Rref
Sud v-
Up/Down Vref Rref2 Dummy
Current Sud Switch
Source
Rref
1Vref

Figure 3-6: Landsburg ADC with pseudo-differential inputs & modified up/down
current source

46
 Auto- Zero
Buff er

Saz -Vref
- GMazf
Raz
> Caz

z+

Cint
Sin POVint
Vin+0-0
Rin
Vin-
A V-
.. + Comparator Vcomp
Input Buffer
Vdd Integrating Vref
V+ Amplifier
~Vref/Rref

Sud v-
Vref Rref2 Dummy
Sud Switch

Rref Vref

Figure 3-7: Landsburg ADC with gm-cell replacing Razi, in AZ1 configuration

1 LRref, lint V int

VSUd gmazV Vaz
re re sCint sCaz

Raz

Raz Rre i int gmazf 1 + sRaz Caz

-*
VS.d ----- Rre- - - Va
SCint sRazCaz

Figure 3-8: Block diagram of AZ1 feedback loop with gm-cell replacing Razf, complete
(upper) & simplified (lower)

47
 How do we pick a value for Raz? Denoting vsummingnode as the voltage at the

integrator summing node, the auto-zero current, iaz is:

.az Vaz - Vsummingnode

Raz

Vsummingnode - ref + Vdummyswitch ~+ Vof fset,comp V ref

- az ~~ Vref
azI Raz

The value of Raz is then chosen to set the range of auto-zero current, and hence
the range of acceptable voltages for in_ Values of Raz e 200kQ can be expected for
a 5V ADC input range.

3.3.1 Issues With Switch Leakage Current

One major hurdle in implementing the auto-zero mechanism on die is the leakage
current of Saz during the Measure State. In order to reject 50Hz and 60Hz noise, the
Measure State runs for 0.1 seconds, during which Saz is in the off position to prevent
any change in voltage of Caz. The following calculation estimates the input offset
(doffset, in LSBs) resulting from a switch leakage current, ileak. For an ADC with

R-bit resolution and a Measure State duration of tmeas = 0.1s, we can calculate the
difference in integrated charge caused by a 1 LSB change at the input voltage.

The full input current range, i < I 2R,ef

Vref m-2n
m represents an output code range
of + 2 R-- LSBs. Hence a single LSB of input current:

Vref 1 m-2n
in,1LSB
2 R-1 2ref m

Integrated over tmeas, this creates the following change in integrated charge:

1 Vreftmeas m - 2n
int,1LSB = 2
2 R-1 Rref m

Qint,1LSB is used to normalize the change in integrated charge caused by a non-zero

48
switch leakage current. Calculating the drift in Caz voltage, Avaz:

AVaz = ieakdt

Charge loss due to switch leakage:

tmeas tmeas tmeas

AQint,eak =
J
Aiazdt =
J
[ AVazdt=
Raz J
[ ileak tdt =-leak
Raz Caz 2 RazCaz
trmeas
0 0 0

Normalizing against Qint,iLSB to find the input offset (in LSBs) due to switch leakage:

d _AQint,leak - 1 Rref ileaktmeas M

Qint,1LSB Raz VrefCaz
moffsetm - 2n

If the largest Caz we are willing to fit on-die is about 200pF, we can estimate the

resulting input offset using typical values of R = 19, Rref = 200kQ, Raz = 200kQ,

tmeas = .ls, Caz =200pF, Vref = 1.25V, m = 16 and n = 2. Then:

doffset ~ 1.4 x 10 14
ieak

This formula implies that to get the input offset below 0.5LSB, we would need a worst-

case switch leakage current of under 3.6fA. A more realistic switch leakage current

(while still difficult to achieve) is 200fA, which would result in 56 LSBs of offset. The
following section proposes a method to achieve sub-LSB offset using a switch with a

worst-case leakage of about 200fA.

3.3.2 Mixed-Signal Feedback Loop

Consider the equation from the previous section:

Rref ileaktmeas m 5.6 x 106

doff set = AQintleak - 2 R-1
Qint,1LSB Raz VrefCaz m - 2n~ Raz

A value of Raz = 13MQ can be used to bring the offset below 0.5LSB, but this brings

up two practical problems.

49
 Auto- Z ero
Buffer

Saz --- Vref

1.1Gazf
Razl
Vdd Caz +-Va
V+
offs5et, Es
1 Raz2 4 Raz3 Cn

V- POVint
Sin
Vin+|-* +
Vin-
vv ?
-+ Comparator Vcomp
Input Buffer
Vdd Integrating Vref
V+ Amplifier
-~Vref/ Rref
Sud V-
Vreft Rref2 IDummy
Sud SvWitch

Rref
Vref

Figure 3-9: Landsburg ADC with current-splitting auto-zero resistors

The first problem is that 13MQ is a very large resistor to implement on-chip.
Figure 3-9 shows a current-splitting method to synthesize this large resistor from
three smaller resistors, Razi, Raz2 and Raz3. This generates an equivalent resistance
of Raz,equv = (Razi + Raz2 Raz3) Raz)2Raz3. In order to obtain the desired Raz,equiv =
13MQ, Razi = Raz2 = 600kQ and Raz3 = 30kg can be used. This current-splitting
technique also introduces an offset of soffset,cs Raz 3 +Raz2 IIRaz2 Razi±Raz 2 , which must
be compensated for with an additional ioffset,cs current source into the summing node.

The second problem is that a large Raz, constrained by the limits of the power
supply, can only provide a limited range of auto-zero current. This corresponds to a
limited range of acceptable voltages for vi,_. This is sufficient if we are performing
single-ended measurements, such that vi_ will always be at a known voltage. For
example, if vi,_ is always at Vref, then the center of the auto-zero current range can be
shifted to Vref with an additional 2ref
2rref
current source into the summing node. Then
R az will only need enough auto-zero current range to compensate for the various offset

50
sources discussed in Chapter 2.2.3.

But what if we want to achieve full pseudo-differential behavior, where vi,- can

be anywhere in the full voltage range? One possibility is shown in Figure 3-10: a low-

resolution current DAC (with an output current range of v to 0) can be used to

provide most of the auto-zero current while Raz (the 'analog auto-zero') provides the

residue current, filling in the spaces between the bits of the DAC. This arrangement

couples the sub-LSB precision of the analog auto-zero with the stability and range of

the DAC. This then turns into a controls problem - how can the DAC be controlled in

such a way that the loop is stable, and the sum of DAC and analog auto zero currents

converges to the correct value?

Auto-Zero
Buffer

Vd V -Vref
Saz GMazf
q~ro
8-bit Current DAC loffsetcs Raz1
CaZ Vaz

Raz3 Cint
moVint
Vin+ Q-4
Rin
Viii- 0--4

-- + Comparator Vcornp
Input Buffer
Vdd Integrating Vref
V+ Amlifier
~Vref/Rret

Sud V-
Vref Rref2 Dummy
Sud
ISwitch
Rref
Vref

Figure 3-10: Landsburg ADC with 8-bit auto-zero current DAC

While many different methods were tried, this thesis will only discuss the most
promising approach. The analog auto-zero is simply allowed to run as usual, with
values Vref,equiv =13MQ, gmazf = 1 and Ca, = 200pF. At the same time, every 8

1 is
clock cycles, the DAC output is adjusted based on the comparator output. If v ,p

51
low, the DAC current is decremented, so that Vint tends to increase. If vcomp is high,
the DAC current is incremented, so that Vint tends to decrease. The convergence of
DAC input code is shown for various Vin_ voltages in Figure 3-11. Once the DAC
8-bit input code has converged to within an LSB of the required current, it dithers
back and forth across that last LSB. 40ms after the start of the AZ1 process, its input
code is locked to halt the dithering. This allows the analog auto-zero to converge to
its final value. While gmazf = 1 is the minimum transconductance necessary to
stabilize the DAC feedback loop, it is too much to provide adequate filtering of the
high-frequency switching. As a workaround, after the DAC code is locked, gmaz1 is
reduced to 1ko

Transient Response

V9nd=36.mn (/iond="-222c~(N 1, 1 1 .. -- 36Z.2rrn'Y (A. 54.3; /.

-6.:v v____________
________________________

2.0

1.0

0.0

-2.0

-3.0

-4.0

S.7'

$1----- -.----
_ _ ----- _ _ __-------

0.0 10m 20m 30m 40m 50m

time ( s

Figure 3-11: Transient simulation of mixed-signal AZ for various values of v _: Vaz

(upper) & DAC input code (lower)

It is interesting to note that the DAC feedback loop is not stable unless the analog
auto-zero runs at the same time. To understand this, we will need a way to analyze
the non-linear relationship between the voltage at the input of the comparator (vint)
and the resulting change in output current of the DAC (Aia,). An approximate
analysis will be made using describing functions [11].

52
 Vint - Vref
E
--
- -
-
- 1 1
2f
-4t

-E - ----------------------- L

Aidaz
A--------------------------------- ----

-A ------------------- -- ---------

Figure 3-12: Change in DAC current, Aidac, due to a sine-wave at comparator input

53
 Consider a sine wave at the input of the comparator, centred around vref, of

frequency f and amplitude E. Figure 3-12 shows that during the sine wave's first

half-cycle (of duration -), the comparator output will be high, and the DAC current

will decrement every 8 clock cycles. During the sine wave's second half-cycle (of equal

duration), the comparator output will be low, and the DAC current will increment

every 8 clock cycles. This causes Aidac to take the shape of a stepped triangle wave,

phase-shifted -90' from the input, with amplitude A. Each current DAC bit rep-

vref and
resents a change in current of 28L Rref 1 1 steps will occur during the first
8tclock 2f

half-cycle. Hence:

A Vref
2 - 28 - 16tclockf Rref

A triangle wave of amplitude A contains a first-harmonic of magnitude A, so the

approximate idac(S)
Vint (s)
transfer function is:

idac(S) _ 1 8A __ Vref 1 _ Vref 1 _ Gd! 1

10 2 9 E s
vint (s) j -r2E 2 lr EtclockfRyef jf 2 lrEtclock Ref S

where s = jw and Gdf - 2 9cVrefR . In other words, the Vint to idac transfer function
can be approximated as an integrator with a gain inversely proportional to the input

amplitude, E. We can now model the dynamics of the joint feedback loops, as shown

in Figure 3-13.
Figure 3-14 shows the magnitude of the analog auto-zero loop gain as well as

the DAC loop gain (which is inversely proportional to E).The DAC loop gain has a

consistent logarithmic slope of -2, indicating that it will not be stable on its own. On

the other hand, the analog auto-zero loop will be stable with > 450 phase margin as

long as gmazf Raz cint > 1. The combined loop gain, which is the sum of these loops,
-az

is shown as a solid line. It levels out to a logarithmic slope of -1 before the unity-gain

crossover frequency as long as ga >

The analog auto-zero feedback loop acts as a lead compensator to stabilize the

DAC feedback loop.This loop becomes less stable as it converges, because the value

of E decreases, increasing the effective gain of the DAC feedback loop. It is necessary

for the combined loop to remain stable until the DAC input code is within an LSB

54
 idac
DAC
Loop

iint 1E S
+t-ntn
( sVint

Analog
Auto-Zero 1~n
Loop
Ln

Raz

t
dac
DAC idac
Vint Gdf 1
Loop

SLint sCint E s
E
gmazf 1 + sRazCaz
Analog
Auto-Zero - sCint sRazCaz
Loop
1
az

Figure 3-13: Block diagram of mixed-signal feedback loop, complete (upper) & sim-
plified (lower)

55
 Magnitude
. DAC Loop Gain, proportional to -
E
Analog Auto - Zero
- Loop Gain
Caz - -

gmaz Raz - ---- -- gMaz

Caz

RazCaz

CintE %-

Figure 3-14: Logarithmic plot of analog auto-zero loop gain (dashed line), DAC loop
gain (dash-dotted line) & combined loop gain (solid line)

of its final value, allowing the limited range of the analog auto-zero to fill in the gap.

While this method works well in the nominal case, it requires very good matching

between the input offset of the comparator and gm-cell. Any mismatch will make the

two feedback loops attempt to converge vi,,t to slightly different voltages. A stable

point for both loops will not exist, keeping the system endlessly in oscillation. Figure

3-15 shows the DAC input code of a system with a 20mV offset between comparator

and gm-cell.

Two workarounds were attempted to reduce this sensitivity - first of all, instead

of being directly connected to vi,,t, the gm-cell and comparator were connected to

a preamplified version of vi,,t, through a high-speed, gain-of-10 preamplifier. It was

assumed that the gain of the preamplifier would reduce the effective offset of the gm-

cell and comparator by a factor of 10, and they would share the input offset of the

preamplifier. Unfortunately, the preamplifier's requirements of very high bandwidth,

high-impedance inputs and large linear input range (equal to the full swing of vi,,t)
are mutually incompatible, and this approach was abandoned.

56
 Transient Response
i~ ~~ VN9&: vgd,"128: /,1 I "W e:so e"0.m; NC:. Ygnddc="724.4rn";v /NO1
vgnddc="362.2m";v /NO1,. qnddc="1S.Imn-"; ?NO1 nd=-I11; a:vnd= -322 "v N.- c:-a4 m
. . C=n.. - ;-mVn s

F ; _ _ _ _ odc_ i"v401
_ _ _";

_________ ________ 1~ __ _ 3________________

- -

I _______7

1 i.....
.......
.....
._

- ii 3.00m 5.00m 7.00m 9.00M 11MM 13.0r 15.M 17.0rn MOM

time ( a

Figure 3-15: Transient simulation of mixed-signal AZ for various values of v_,

showing DAC input code, with 20mV offset mismatch between comparator & gm-cell

57
 The second workaround was to use two comparators, with thresholds slightly

above and below the gm-cell's input offset voltage. The DAC input code was only

incremented or decremented if vint was above the top threshold or below the bottom

threshold, creating a middle region where only the analog auto-zero is active, and the

DAC feedback loop does not fight for control. This method was unsuccessful as well,

because the DAC input code would drift around the final value and not converge.

Simulations suggest that the system will work with a < 1mV offset difference

between comparator and gm-cell. While large input devices are too slow for this

application and trimmed input devices are too expensive, perhaps it could be done

with chopped inputs for the comparator and gm-cell. This system was ultimately put

aside in favor of the much simpler method below.

3.3.3 Two Measure States

While the auto-zero method described in Chapter 3.3.2 contains some interesting

ideas, it is complicated and expensive. The system above relies on very well-matched

components, and the gm-cell, large auto-zero capacitor, 8-bit current DAC and Raz

resistor network considerably increase the cost of the system. This chapter discusses a

much simpler idea - removing the analog auto-zero system entirely and simply having

two Measure States. The first Measure State measures vin-, the second Measure State

measures Vin+, and the two digital values are simply subtracted from each other to

obtain the final result. An additional f

re2fRef current is added to the summing node

to cancel out the average current through Ref, thus biasing the range of acceptable

input voltages around Vsummingnode.

Figure 3-16 shows how this might be done. The switch Sre, has been added to

connect the Input Buffer to vref during AZ2 and the Residue State.The sequence of

steps for pseudo-differential measurement is now as follows:

1. AZ2, to set Vint to the comparator threshold.

2. Measure State on Vin_, to measure the output down to a 12 LSB resolution.

3. Residue State on vin_, to measure the mod 12 residue of the output and provide

58
 V.
Cint
Vn+-Sin -Vref/2Rref Vn
Vin-
Rin
Vret 0-* Sres

-- + Comparator Vcomnp
Input Bffer

Vdd Integrating Vref

-VrfRe + Amplifier

~Vru/d e setL atc h

Vref
Dummy
Sref2
Sud

Rreff
Vref

Figure 3-16: Landsburg ADC with latching comparator and without auto-zero loop

unit clock resolution.

4. AZ2, to set Vint to the comparator threshold.

5. Measure State on vin+, to measure the output down to a 12 LSB resolution.

6. Residue State on Vin+, to measure the mod 12 residue of the output and provide

unit clock resolution.

7. The digital output from the vin_ measurement is subtracted from that of the

vin+ measurement, resulting in a differential measurement.

As the two Measure States each take 0.1s and dominate the conversion time,

the entire conversion takes about 0.2s, resulting in a 5 Samples/s sampling rate. If

measurements are being taken continuously, the output can be updated at the end of

every Measure State (using the most recent measurements of Vin_ and vin+) to give

a sampling rate of 10 Samples/s.

There are two main disadvantages which this method. The first is an increase in

noise. As the final output is derived from two digital-to-analog conversions instead of

one, the noise of two conversions will appear at the output. On the other hand, this

is offset by the removal of the current DAC and the auto-zero buffer & resistors, all

of which are significant noise sources.

The second disadvantage is a reduction of vin+ input range. With the auto-zero

59
a) b)
Vin+1

Acceptable Range Atbie Acceptable

Acceptable of vi,, is centered AceptabeAcpal
Range of vi_ around value of v Range of vi,_ Range of Vin+

y in- 2 - ------ - ----------- -

v1 _and vr 4ranges are equal and independent
vin+2

Figure 3-17: Vin_ and vin+ input ranges, with (a) & without (b) auto-zero feedback
loop

feedback loop, the acceptable range of voltages for vin+ is centered around the value

of Vin- which was measured during AZI. This is shown for two sets of possible vin_
and vin+ in Figure 3-17a. vin_, is close to the top of the Vin input range, and the vin+
range is centered around vin 1 , so vin+1 can be at an even higher voltage. Similarly,

Vin- 2 is close to the bottom of the Vin input range, and the vin+ range is centered
around Vin- 2 , so Vin+2 can be at an even lower voltage.

Without the auto-zero feedback loop, the Vin+ input range is no longer centered
around vi,_. As shown in Figure 3-17b, both vin- and Vin+ must fall within the same
range of voltages, resulting in an overall decrease in the input range of the ADC.

On the upside, the removal of the auto-zero feedback loop greatly decreases the
cost of the Landsburg ADC, reducing its active circuitry to two buffers, a comparator
and one high-speed amplifier. Only a single moderately-large capacitor (the 50pF
integrating capacitor) remains. Excluding the input buffer (which is application-
specific and beyond the scope of this thesis), the estimated die area of the ADC is
under 300mils 2 . With the removal of the auto-zero feedback loop, the final design
resembles Figure 3-16.

60
3.4 Regenerative, Latched Comparator

It is necessary for the comparator output to settle well within the duration of one
clock cycle. As the modified Landsburg ADC requires a 3.6MHz clock, the comparator
output must settle in much less than 3.1Hz = 278ns. This settling time is far too
short for a continuous-time comparator with a current budget of under 3OpIA. As a
result, a regenerative latched comparator is used, with an output which settles within
a few nanoseconds when the latch signal goes high. The rest of this section discusses
the details of latch timing.
Comparator latch lifted
Comparator result stored
on clock2 negative edge
Decision made using stored comparator result,
comparator latch lowered.

clock 1
tI
I I
I I

clock 2
tt
I I
tclock I I
latch
1 - t

Figure 3-18: Comparator latch timing, with decision being made on the 4th clocki
rising edge

Suppose that a comparator-based decision must be made on the positive edge of a

specific clock cycle. Just before this decision, the comparator latch must be lifted, and
the comparator output sampled, so that a low-latency comparator output is available.
Figure 3-18 illustrates a suitable timing scheme which uses a 2-phase non-overlapping
clock.
If a comparator-based decision is made at the beginning of every clock cycle, as
in AZ2 and the Residue State, the 'latch' pattern in Figure 3-18 will repeat every

61
clock cycle. During the Measure State, however, it will only repeat every m clock

cycles. Recall the shape of the m-clock sequences from Figure 3-1; the first n pulses

are always high, the last n pulses are always low, and the middle (m - 2n) pulses are

dependent on the comparator. In order to minimize latency, it is best to latch the

comparator just before the 'high' and 'low' sequences deviate. In other words, during

each m-clock sequence in the Measure State, the comparator is latched so that the

decision can be made on the rising edge of the nth clock cycle of the sequence.

3.5 Digital Logic Tweaks

Since the introduction of the original Landsburg ADC, the cost of digital logic has

fallen tremendously, justifying the use of more complicated digital controls. This

chapter introduces a few changes to the digital control logic of the Landsburg ADC.

3.5.1 Residue-State Truncation

Recall the Residue State method discussed in Chapter 2.2.2. As mentioned previously,

the up-integration is always performed before the down-integration to ensure that the

output is always measured on the up-to-down comparator transition, which eliminates

the effects of comparator hysteresis.

The generalized bounds on the residual charge, Qre on the integrating capacitor

are in the range of -(m - 2n) to +(m - 2n) clock cycles of charge. It can be assumed
that vint will be above the comparator threshold if you up-integrate for more than

(m - 2n) clock cycles. In other words, it is necessary for n., to be greater than

(m - 2n). Similarly, nadon,max must be greater than (ns, + m - 2n) clock cycles to
ensure that the up-to-down comparator transition occurs.

This method is suboptimal because it increases the required output swing of the

integrating amplifier. Recall from Chapter 3.1.2 that the integrator output can swing

as high as vref + g jJ, 2 (m - 2n) during the Measure State. If, at the beginning

of the Residue State, vint travels upwards for a further nr,, clock cycles, then the

integrator will have to support an output swing as high as vref + Lck 2 (m - 2n) +

62
 Sre s set tov1reP, *i
saving residual %R duced integrator
Vint - ~ref charge R tput swing

Qres I
- --------- %
---
I %
--
- - - - -- - - - - - - - - %

AA nl
nint

ndownnew
Il-up,new

nup,old ldown,old

Figure 3-19: Lansdburg ADC residual charge measurement, original (dotted line) &
truncated (solid line)

nUp C1 t 2,. Since n, must be greater than (m - 2n), this is a significant increase
in required output swing. Figure 3-19 shows the original Landsburg design (dotted
line) exhibiting this behavior.

This figure also shows the improved method, as a solid line; instead of up-
integrating for a constant number of clock cycles (constant nu,), we truncate the
up-integration and proceed to down-integration almost immediately (in this design, 4
clock cycles) after vit exceeds the comparator threshold. This minimizes the required
increase in integrator output swing. The overall gain is equation is still:

rI n 14(2Nio - Nintegration)
NU
+ nfown -n
Vin ~~ Ure ,(1(Na
2Rre 6
l Nintegration

However, na, is no longer a constant value. It is simply as many up-integration clock

cycles as is required for vint to travel above the comparator threshold.

63
3.5.2 Overrange & Underrange Detection

The modified Landsburg ADC has separate mechanisms for detect overrange and
underrange conditions during the Measure State and Residue State. During the
Measure State, every m-clock sequence causes a change in output code, dt , of ±(m-
2n). A 21-bit signed accumulator is reset at the beginning of the Measure State
and used to keep a running count of these increments. If the accumulator value
significantly exceeds ( 2 R-1 + m - 2n) for an R-bit conversion, the underrange flag is
raised. Similarly, the overrange flag is raised if the accumulator value falls far beneath
-( 2 R-1 + m - 2n). Some safety margin is implied (the flags are raised only if the
accumulator strays far outside these bounds) to make space for the input offset of the
ADC.
The second overrange/underrange mechanism takes place during the Residue
State. If Vin is within range, the residual charge, Qres on the integrating capaci-
tor should be in the range of -(m - 2n) to +(m - 2n) clock cycles of charge. It can

be assumed that vint will be above the comparator threshold if you up-integrate for
more than (m - 2n) clock cycles. If vint is still not above the comparator threshold
after an up-integration of significantly more than (m - 2n) clock cycles, the overrange
flag is raised. Similarly, if Vint is still not below the comparator threshold after much
more than (na, + m - 2n) clock cycles, the underrange flag is raised.

64
Chapter 4

Circuit Design of the Modified

Landsburg ADC

Up/Down Current Source

Input Switch Network

sin CIVII
Vin+" ~Vretj2RreM

+ Vinn

vret asr~esl-
------

+ COmparator Vcmp

Y4 ntegrating Vref

setLatch

~Vref

Vre Dum

Figure 4-1: Final version of Modified Landsburg ADC with labelled blocks

This chapter describes the transistor-level circuit design of the various analog
blocks in the Landsburg ADC. Except for the input buffer', all analog blocks are
described down to transistor-level detail. Each block has been verified in simulation,
across operating temperature range and ±3o device variation. Table 4.1 shows the
'The input buffer design is beyond the scope of this thesis due to time limitations. Nevertheless,
requirements for this block are discussed in Chapter 4.2.

65
allocation of power & area to each block.

Table 4.1: Power & Area Budget of Circuit Blocks in Landsburg ADC
Circuit Block Power Budget (MW) Area Budget (mils2 )
8-Bit Current DAC (removed) 200 100
Auto-Zero Buffer (removed) 125 25
Low-Leakage Switch Saz (removed) - 1
Input Buffer TBD TBD
Input Resistor - 4
Up/Down Current Source 325 35
Integrating Amplifier 600 25
Integrating Capacitor 100
Comparator 125 8
Digital Logic 250 50
TOTAL (minus Input Buffer) 1500 222

As with most designs which operate over long time-scales, we must pay attention
to simulation efficiency to minimize simulation time. Each transistor-level block im-
plementation is built in parallel with a fast-simulating block model, built from analog
primitives and Verilog-AMS. As elaborated in [12], much time can be saved by sim-
ulating the full system with just one transistor-level block at a time, using simplified
models for the other blocks. If certain blocks are likely to interact in a problematic
way, their transistor-level implementations are tested together. Time-consuming, all-
transistor-level simulations are reserved for the final verification process.

4.1 Input Switch Network

The input switch network is the implementation of switches Sin and Sre which allows
us to connect the input buffer to vin+, Vin- or Vref, as shown in Figure 4-1. It

is controlled by two logic signals, inpuLswitch and residueswitch, in the manner

described in Table 4.2:
While Figure 4-1 draws Sin and Sre, as a pair of SPDT switches in series, it is
not ideal to have two switch on-resistances in series with the input buffer. Hence the
input switch network is actually implemented as a single-pole, triple-throw switch,
built from three transmission gates which are controlled with break-before-make logic.

66
 Table 4.2: Truth Table for Input Switch Network
residue-switch input-switch Input buffer connected to
Low Low vi_
Low High Vin+
High Low Vref
High High Vref

Transmission gates are used to ensure low switch on-resistance for a wide range of
input voltages.

4.1.1 Transmission Gate Design

a) b)
QAbar Vdd

10/0.7
terminall
termina12
5/0.8 Q Q ..bar

Figure 4-2: Transmission Gate design: transistor-level (a) & symbol (b)

The required on-resistance of each transmission gate can be approximated based

on the input capacitance of the input buffer. Let's assume an upper bound of 1pF
on this capacitance, Cin,inputbuffer lpF. Within one clock cycle, we need the input
voltage to converge to 19-bit accuracy, which is equivalent to 14 time constants. With
a 3.6MHz clock:
1
tdock = 280ns
fdock

14 ~ 20ns > Ron,switchCin,inputbuffer

If Cin,inputbmffer lpF then Ron,switch < 20kQ.

Figure 4-2 shows the design of one transmission gate, where the transistors have

been sized to achieve a switch on-resistance of < 2kQ across the input range. This

67
is well within the calculated < 20kQ bounds. Figure 4-3 shows the transmission gate
on-resistance over a -1.25V to 1.75V switch voltage range. This is the worst-case
resistance as 3V is the minimum supply voltage, with vref = 1.25V, providing the
least overdrive voltage for the switches.

3.0K

pFET resistance nFET resistiance

2.0K

1.0K

0.0
-1,25 -. 750 -20 Vswitch .5 .750 1.25 1.75

Figure 4-3: Transmission gate resistance over -1.25V to 1.75V range

4.1.2 3-Way Break-Before-Make Logic

Vin+ c
on+ on+_bar

Vi n - 0 -O to input buffer
on- on-_bar

Vref -
onref onref_bar

Figure 4-4: Arrangement of transmission gates in input switch network

The set of 3 transmission gates is arranged as in Figure 4-4 and controlled with

logic signals on+, on+.bar, on-, on-_bar, onref and onrefjbar. These signals are

controlled by break-before-make logic which ensures that only one transmission gate

is on at a time. This prevents vin+, vin- and vref from being connected together. The

68
break-before-make logic takes residue-switch and input-switch as inputs and is shown
in Figure 4-5.

a) b) on+_bar
residue switch
on+
input-switch safe-_bar
on-bar onref
safe+_bar n+ r
onrefbar
on+-_bar
residue-switch on-
input-switch on+C
safe-_bar on-_bar safe+_bar
onref 0
onref bar
residueswitch onref
on-_bar
saferef onrefbar on-
saferef
on+
on+_bar

Figure 4-5: 3-Way Break-Before-Make logic: gate control (a) & break-detection (b)

Signals safe-_bar, safe+_bar and saferef indicate when it is safe to turn on the

_ vin+ and vref transmission gates respectively. These signals are generated by
the break-detection logic in Figure 4-5b. The gate control logic in Figure 4-5a moves
the appropriate gates when it is safe to do so. Figure 4-6 shows this system in action
when transitioning from vin+ to Vin with a 3V power supply. The typical switching
time from one transmission gate to another is 2-3 nanoseconds.

4.2 Input Buffer

While a transistor-level design of the input buffer is beyond the scope of this thesis,
this section will describe how characteristics of the input buffer can affect the overall
performance of the ADC.

69
 i nputswitch (V)
30

0.0

4.0
n-_bar (V)

-1.0
0
0
. .. . . . . .- .- -
n- (V)
4.0

-1.0
0
n+_bar (V)
4.0
1
-1.0

4.0 on+(V)

-1.0
7.4 990u 7.5000u 7.50 1Ou 7.5020u 7.5030u 7.5040u 7. 5050u
time ( s )

Figure 4-6: Break-before-make input transition from o n+ to vi-

4.2.1 Input Properties

It is necessary for the input buffer to have high-impedance inputs. This is because
it is preceded by the input switch network, described in Chapter 4.1, which places
transmission gates in series with the front of the input buffer. These transmission
gates have a non-linear, inconsistent on-resistance of up to 2kQ which forms a voltage
divider with the input buffer's input. In order to prevent this inconsistent transmis-
sion gate resistance from distorting the output of the input buffer (and hence the
ADC output), the input buffer must have an input impedance high enough to ignore
the transmission gate on-resistance on a 19-bit level. In other words:

Zit > 2kQ - 219 ~ 1GQ

This high impedance implies a need for MOS input devices, which carry the penalty
of high - noise. Since the Landsburg ADC is meant for measuring high-resolution,
near-DC signals, the input buffer should have a chopped architecture to mitigate the
1 noise of the input devices.

70
4.2.2 Gain & Nonlinearity

Any nonlinearity exhibited by the input buffer throughout its input range directly

appears as a nonlinearity at the output of the ADC. The input buffer is a high-gain

amplifier in unity gain feedback. As such, nonlinearity can be pushed below the

19-bit level as long as there is sufficient open-loop gain. Consider an amplifier with

an open-loop voltage gain of Av, placed in unity gain feedback. The input-output

transfer function:
Vin AV 1 1
=1-
Vot 1+A, 1+Av
where the second term, represents the deviation from ideal unity-gain behav-

ior. Constraining this term to 1 LSB of the ideal unity gain:

1 < 19
1 1+Av 2

Av > 2 - 219 - 1 106

In other words, as long as the open-loop gain of the input buffer is consistently above

106 (120dB) throughout the input voltage range, non-linearity should be pushed below

the 12 LSB level. It is worth noting that this gain must be achieved while the input

buffer is driving Ri,, which in this design is 350kQ. In order to maintain high gain
while driving this load, the input buffer requires a low-impedance output stage.

4.2.3 Bandwidth & Slew Rate

Figure 4-7 shows the current through RIn during one instance of Measure State fol-

lowed by Residue State. As the input buffer must move sharply from one near-DC

voltage to another, it is assumed that slew rate effects dominate the transition time,

and the transitions can be approximated as linear ramps. At the beginning of the

Measure State, the input buffer's output voltage must slew from vref to vin+, causing

iin (the current through Rin) to ramp up to "" L"V.At the end of the Measure

State, iin ramps back down. In the ideal case, with infinite slew rate, the total inte-

grated charge from vin± should be v"'iref tmeas, where tmeas is the duration of the

71
 ii Vertically-striped area (Q&,,): Horizontally-striped area (Qgaina): Slew-down must complete
Lost charge due to slew-up Extra charge due to slew-down before final up-to-down
Slew Down comparator transition
Slew up
Vin+ - Vref Grey area (Qttal): Totalintegratedcharge from vi,,+

Rin

Measure State on Vin+ Residue State

Figure 4-7: Input buffer slewing behavior during one instance of Measure State &
Residue State

Measure State. Due to the finite slew rate, the actual integrated charge from vi 7 + is:

Qtotal = Vin+ Vref tmeas + Qgained - Qiost

If Qiost = Qgained, then Qtotal = Vin+-Ve"tmea, which is ideal. This is equivalent

to saying that the Qgained triangle will fill in the Qiot triangle if they have equal
area. This occurs when the upwards and downwards slew rates (slewrateup > 0

and slewratedown < 0) are of equal magnitude. If these slew rates are not of equal

magnitude, Qgained-Qlost is a non-zero value which introduces second-order distortion.

It can be shown that the distortion from this effect, in LSBs, is:

1 1 + 1
INLs2ewrate " 2 RFS
12 tmea, 'slewrateup slewrate/own

where R = 19 is the resolution of the ADC and FS = Vin,max - Vin,min is the full-scale

voltage. As mentioned above, if slewrateu, = -slewratedown, then Qgained =Q10st

and slew-rate distortion is zero. Hence the up & down slew rate of the input buffer

must be fast enough or match well enough to push this distortion to sub-LSB levels.

Figure 4-7 shows one more criteria for the slew rate of the input buffer. It must be

fast enough so that, during the Residue State, the input current can slew back to zero

72
before the final up-to-down comparator transition. In order to reduce the required

slew rate, this time can be extended by having the up-down current source perform

a net-zero-charge pattern (such as the 50% duty cycle pattern in Figure 2-8) while

waiting for the input buffer to finish slewing.

4.3 Up/Down Current Source

Current Sources, proportional to vref

Vdd Vdd~

~Vref /2Rref -Vref/Rref

------------------

to integrator
vref buffer summing node

to +ve input pin of

Vref
Dummy integrating amplifier
Rref2
Sud Switch

Rref
Vref

Figure 4-8: Block-level diagram of up/down current source

The up/down current source performs two functions. Depending on whether the

ADC is integrating up or down (indicated by the logic signal updownrin), it either

sinks or sources a current of vf

2Rref from the integrator summing node. It also generates

the bias voltage for the integrating amplifier's positive input pin, to perform the

switch resistance compensation described in Chapter 3.2.1. Figure 4-8 is a block-level

diagram of the up/down current source. It consists of several switches, a vref buffer,

two loosely-matched resistors (Ref and Rej 2 only require matching to < 3%) and a

pair of current sources which are proportional to vref.

Figure 4-9 is a transistor-level diagram of the vref buffer, current sources and bias

cell. The bias cell places a voltage of ~ vref across the 200kQ resistor, generating a

current proportional to vref. This circuit includes an nFET as a 'turn-on device' to

73
 Proportional-to-Vref Vref/Rref current source Vref/2Rref
current biasing cell Vref buffer & dummy switch current source

Vdd

104k 104k 104k 104k< 208k

24.8/1 24.8/1 24.8/1 24.8/1 12.4/1

10/0.8 to summing node

t+ve input of
---- 10081------- integrating amp

0.6/ buffered Vref _|-

v refr
Turn-on Dummy
67k device 200k Switch
=Rref/3 =Rref

Figure 4-9: Schematic of biasing cell, vref buffer, dummy switch and vrf
2R/f current
source in the up/down current source

74
push it out of the zero-current state during turn-on. This bias current is mirrored to
produce the proportional-to-vref currents in Figure 4-8. The vref buffer is built from
a simple source follower. The proportional-to-vref current biasing cell, vref buffer and
dummy switch each sink a current of vref into vref. The 67kQ ~, rf resistor drains

this current from vref to minimize loading on the Vref source.

a) b) to summing node UDgate bar

buffered Vref 10/0.8 to +ve input of

updownin UDgate 10/08 10/0.8

UDgate bar UDgate

UDgate_bar

Rref

Figure 4-10: Schematic of break-before-make logic (a) and switches (b) in the
up/down current source

Figure 4-10b shows the implementation of the Sd switches as nFETs. Break-

before-make logic is used to control these switches, as shown in Figure 4-10a. This is
to ensure that the summing node is never accidentally connected to the vref buffer,
which would modify the integrated charge and affect ADC linearity. This circuit is
essentially a few switches connected to two resistors, where the voltage across the
resistors barely changes (Rref always has Vref across it). The switching time is
thus constrained to the speed of the break-before-make logic, which is < 3ns across
case and temp.
The current draw of the up/down current source is about 5ref, where Rref =
2
200kQ. With Vdd = 5V and vref = 2.5V, power consumption is about 3 0pLW. With

Vdd = 3V and Vref = 1.25V, this decreases to 95pW.

4.4 Integrating Amplifier

Figure 4-11 shows the transistor-level design of the integrating amplifier. On account
of needing both high gain (>120dB) and bandwidth (>25MHz), this is the most

75
 8
Bias Generator Folded-Cascode 11 stage Interstage Buffer CS2 stage

5uA luA 5uA 10uA 5uA SuA 10uA 80uA

Vdd
T ~ 20 0.7 _20/q.7
100k 500k 100k 50k 6.25k

50/1 10/1 50/1 bias 800/1

bias 100/1
1 20/0 32fF
biasi 80/1 80/1 4Vout
Vin- -- V+
bias2 15/0.

5uA bias bias3

current
bias3

10/2 100/2

60k 30k 30k bias2

Figure 4-11: Schematic of integrating amplifier

Table 4.3: Simulated nominal specifications of integrating amplifier

Specification Vdd = 5V, vref = 2.5V vdd = 3V, v,ef = 1.25V
Gain-Bandwidth Product 33MHz 32.5MHz
Phase Margin 640 640
Gain Margin 12.2dB 11.9dB
DC Gain 123dB 122.2dB
Power Consumption 620pW 370pW

power-hungry block in the ADC. Table 4.3 shows its nominal specifications at the

upper and lower limits of its operating voltage. These specs are achieved with a two-

stage Miller-compensated design. A folded cascode first-stage is used to speed up the

pFET input devices by providing more Vod. A buffered common-emitter second-stage

is used to maximize output swing. The >120dB gain requirement necessitates that

NPN transistors be used instead of nFETs, to make use of their superior transcon-

ductance and output resistance.

As covered in Chapter 3.2, the settling time of this amplifier is the main bottleneck

on the speed and resolution of the ADC. Assuming completely linear behavior, the

following approximation can be made about the required bandwidth of this amplifier.

We need this amplifier's output to settle to <0.5LSB (<lppm at 19-bits) within n

76
 Stability Response

-: Loop Gain dB2O

13W

70.0

10.0

-50.0

200 .: Loop Gain Phase

0100

-200

-400
loom 1 10 100 1K 10K 100K iM loM looM 1G lOG 1000
freq ( Hz )

Figure 4-12: Simulated nominal frequency response of integrating amplifier, with

Vdd = 3V, Vref = 1.25V

clock cycles (as in Chapter 3.1.2). It takes about 14 time constants to settle to

<1ppm, so the length of one time constant, r, is:

ntclock
14

Hence with tdock = 36MHz and n =2, the required bandwidth of the integrating

amplifier must exceed ~ 4MHz. This math assumes linear behavior, however,

which is not realistic. In simulations with the architecture in Figure 4-11, a minimum

bandwidth of 25MHz was found necessary to push INL below 1 LSB. The amplifier

is designed to meet this requirement across case and temp. Figure 4-12 shows the

nominal loop gain of the integrating amplifier at the lower limit of its operating

voltage. Figure 4-13 shows the settling behavior of the integrator output when the

integrated current switches between t v every 560ns (two clock cycles).

2Rref

During testing with one transistor-level block (and the others represented with

fast-simulating models), the integrating amplifier was the only block to cause dis-

cernible distortion above the quantization noise. The design shown here causes ±1

LSB of 2nd-order distortion, due to limited bandwidth constrained by the power

budget.

77
 1.230 1: v /N032; tran (V)

.220
1.210

1.200

1.190

11,80

100K -: deriv(v("/N032" ?result "tran"))

50.0K

0.00

-50 0K

4.40u 4.70u 5.00u 5.30u 5.60u 5.90u 6.20u

time ( s )

Figure 4-13: Simulated settling behavior of integrating amplifier with vMj = 3V,
vref = 1.25V: vtt (upper) and -v at (lower)

4.5 Latching Comparator

High-Speed Voltage-to-Current Anti-Hysteresis

Preamplifier Converter Latching Cell Inverters

uA 15uA SuA
Vdd 0- 0 si M5/
10/2 150/2 50/2

set-latch 0-4 - Vout

Vin+ 75/0.7 75/0.7 Vin-

luA bias 25/0.5 25/0.5

current

50fF

25k 25k
12.5/2 12.5/2 12.5/2 12.5/2

Figure 4-14: Schematic of latching comparator

Figure 4-14 shows the transistor-level design of the latching comparator. The main

comparator components are the voltage-to-current converter and the latching cell.

The input-referenced noise and offset voltage of these two components are attenuated

by a high-speed preamplifier with a gain of 3. The 50fF capacitor across the latching

cell outputs helps attenuate high-frequency noise. The output signals of the latching

78
cell are each buffered by three inverters before they reach the main ADC logic. This
is done to present each output of the latching cell with a balanced capacitive load.

Transient Response

5.0 A: v /N3; tran (V)

2.0

-1.0

5.0 -: v /N016; tran (V)

> 2.0

-1.0

500u v (/N030 /vref!); tran (V)

> 0.00

-500U
0.0 400n Boon 1.2u 1.6u Ou
time (s

Figure 4-15: Simulation of comparator response to ±0.5mV overdrive, with vdd = 3V

vref = 1.25V: latch signal (upper), comparator output (middle) & differential input
signal (lower)

Figure 4-15 shows the latching behavior of the comparator. The comparator

output latches on the positive edge of the seLlatch signal. When seLlatch is low, the

comparator output defaults to logic low. As shown in Figure 4-16, each transition

takes 2-3ns, due to the regenerative action of the latched comparator. In between

latch events, the current draw of the comparator is about 20pA. Each latching event

draws an additional 20pC of charge from the power supply. The ADC spends almost

all of its time in the Measure State, during which the comparator is latched every 16

clock cycles. This results in 3.6MHz = 225000 latch transitions per second, producing

an additional current draw of 225000 - 20pC ~ 5pA, for a total current consumption

of 25 1tA. This results in a power dissipation of as much as 125PW when udd = 5V.

Figure 4-17 shows the input-referenced RMS noise of the comparator, integrated
3
over frequency. This integrated noise levels out at 1. mVrms. We can estimate a

peak2 comparator noise voltage of 6 x 1. 3 mVrm, ~ 8mV. As shown in Chapter 3.3.1,

2
lvnoise I < 6Vnoise,rms is a 99.9% confidence interval on the instantaneous noise magnitude

79
 Transient Response

r, . A: v /N3; tran (V)

3.0

-1.0

5.0 -: v /N016; tran (V)

3.0

1.0

-1.0
"vp.on " 0.19 n " 1.2n " Lan 442. 1n .t 2.4n
time ( s )

Figure 4-16: Simulation of comparator transition time, with vdd = 3V vref = 1.25V:
latch signal (upper) & comparator output (lower)

the additional integrated charge from 1LSB of input voltage is:

1 Vreftmeas m - 2n
it,1LsB ~~ 2R-1 2
Rref m

Hence the difference in integrator output voltage (and hence comparator input volt-

age) caused by 1LSB of ADC input voltage is:

1 1 Vref tmeas m - 2n
Vint,1LSB =int 2R-1 2 Rref m

Using Cint = 50pF, m = 16, n = 2, R = 19, Ref = 200kQ and tmeas = 0.1s, we can
quantify this 99.9% peak comparator noise in LSBs. With Vref = 2.5V, Vint,1LSB

36mV, and the peak comparator noise is 0.2LSBs of vin.

O", Similarly, with
8
Vref = 1.25V, Vint,1LSB 18mV, so the peak comparator noise is r"V~ 0.4LSBs of

yin-

80
.: 99.9%peakOutNoise -99.9%PONnormTolnput
5.0m,..
99.9%pookOutNvis. 11 r r .. m
r~t~-: 99.9%P0NnmmToInp~t

gn-M - 27

4r.m _ 1.20m

90OU

1 Om aa

2.Dr _______ 600u

1Dm ______ ____________ ____________ ____________ 300u

0.0 I __G I I 1 .00

10Dm 10 1K 100K 10Mf ( 10 IO 101 IF' loop
f-q ( Hz)

Figure 4-17: Simulation of comparator RMS noise, integrated over frequency, with
Vdd= 3V Vref =1.25V: across 50fF capacitor (left axis) & referenced to comparator
input (right axis)

81
82
Chapter 5

Noise Analysis

VIn+O Sinn~m ~Vrel/2Rref Ins .+ Vints

V- n- VnintAmp

in -

inutIlffr +Conpamnlor Vcunp

Integraing V Vret

rIn, 2 setLaldi

Vred
3.4 In p uc t-ree
pa r o rDv a n

1.InutreerncdInput u ffer votg noiseto VnInnm

4. In pteistrdcrben s eating tef

5. ~ reitrcurn~ ~ ~
Reern.
ose ~ u _a

5. Refrenp c resistor current noise, n,

83
 6. Vref
2Rref current source current noise, in,csl

7. Vref
Rref current source current noise, in,cs2

The final decision of the ADC is made at the comparator, during the Residue

State. In order to analyze how each noise source corrupts this decision, this chapter

will reference each noise source to the input of the comparator. The comparator checks

if Vint is greater than (Vref +Un,Comp), where Vint = Vref +Vdummyswitch +Vn,IntAmp+ VCit,

VCint is the voltage across Cint and Vdummyswitch is the voltage across the dummy switch.

This decision can be written as follows:

Vref + Vdummyswitch + Vn,IntAmp + VCist > Vref + Vn,Comp

Vdummyswitch + Vn,IntAmp + VCing > Vn,Comp

Ignoring the polarity of the noise sources:

VCist > Vn,Comp - Vdummyswitch + Vn,IntAmp

Assuming that the on-resistance of the dummy switch, Rdummyswitch << Rref2,

? Uref
VCint > Vn,Comp - Rdummyswitch I + in,cs2) + Vn,IntAmp
lire!

The left and right hand side of this equation are the two ways in which the listed

noise sources can distort the ADC output. On the left hand side, the integrating

capacitor, VCint, samples the integrated current noise during the Measure State. On

the right hand side, noise sources n,Comp, Vn,IntAmp and in,cs2 are unaffected by the

integration. The following two sections will handle these cases separately, and the

third section combines them.

84
5.1 Integrated Noise Sources

The following table shows the current into the integrator summing node which is
induced by each noise source.

Table 5.1: Integrator summing node currents induced by noise sources

Noise Source Induced Summing Node Current
Vn,InAmp
n,InAmpRin
Vn,Int Amp
Vn,IntAmp R InI|Rre
Vn,Comp
in,Rin in,Rin
in,Rref in,Rref
in,csl in,cs1
Rdummyswitch.
in,cs2 II r -n,cs2

We can now define the total integrated noise current, in,Eint:

1 1 . Rdummyswitch.
n,Eint Rin Vn,InAmp+ RV Ree Vn,IntAmp +n,Rin +in,Rref +in,cs1 Rin Rref mC5Z

Finding the noise power:

n,EintY 7 T2Vn,InAmp(f) + Rin re) ,IntAmp( f ) + in,Rin (f

in ij re

±i2,Rref(f) + i2 + Rummyswitch 2 i2 ,
nrf n,Cs1 Y (Rnjref ) n cs2

The next step is to establish the relationship between this integrated current noise,

i2, and the sampled voltage noise across Cint after integrating for 0.1 seconds
(the duration of the Measure State). To do this, we must understand the frequency
response of an integration of 0.1 seconds. Consider the frequency-domain transfer
function of integrated current (iint) to integrating capacitor voltage (VCi ), integrated
from -oc to t:
t
1
Cint 1 iintdt'
Cint
-00

85
 Vciet(s) _ 1
iint (S) sCint

If we only integrate from (t - tmeas) to t, where tme0a = 0. Is is the duration of the

Measure State:

t t t-tmeas

Vci = iinidt' = iint dt' - ] i ndt'

t-tmeas -00 -00

vc1 ±(s) _ 1 _ 1 e-stmea e-istmeal (e stmeas e-"stmeas

iint(s) sCint sCint Cints

vCe (s) -e-stmeas 2 sin("Wtmeas)

iint(s) Cnt s
This resembles a phase-shifted sinc function, which makes sense as a time-windowed

integration is equivalent to a time-convolution with a square pulse. Taking the mag-

nitude of this function:

vce(s) __ t_ 2 sin(}Wtmeas)
iint(s) Cint s

c1(f) _ 1 (7rftmea,)
iint(f) -rf Cint

This magnitude function is plotted in Figure 5-2. As is expected of a 0.ls inte-

gration, nulls appear in the magnitude response at intervals of 10Hz. The nulls at

50Hz and 60Hz indicate the ADC's rejection of power-line frequencies. The averaging

effects of the integrator also attenuate high-frequencies with a first-order roll-off. We

can now calculate the sampled voltage noise across the integrating capacitor at the

end of the Measure State, Vn,c:

Vn~ (f) = e
n _ mea 1 sin(7rftmeas)
Cint _jrf

Finding the noise power of Vn~nt:

2 1 sin(Crfftmeas )2 2
2 2
n ,Cn(f) =Ci2 frf n ,Ent

86
 10
. ... I . . . . . ... 1 . . . . . .. 11 . I I . . ... I I . . . I .- 1 . . I . .1.11 . . . . . 11.1 . . . . . ... ' . . . . . .. "

10'-

100-

10 --

10.1

10- -

10- -

0 " " " " " " 1

10 10 10 10 10 10 10 10 10 10 10
Frequency (Hz)

Figure 5-2: Log-log magnitude plot of vcinl(s) transfer function with 0.1s integration
time

2 2Vf
V,2n Cn (ff 1 sin(7rftmeas) 1 21
QCt 7r2 f 2 R, n InAmp (f)+ RinhRref nntA,

+2, (f) + i f +2 Rdummyswitch 22 (

+,Rin~f +n,Rref ) +f n,cs1 f + R in I ref ) n cs2 (

5.2 Non-integrated Noise Sources

While Chapter 5.1 covered the sampled voltage noise across the integrating capacitor,
this section will discuss the noise sources which are not attenuated by the Measure
State integration. One side of the voltage across the integrating capacitor, VGCi,,

rides on top of the summing node voltage. During comparator decisions, the other
side of VCin, is compared against the comparator threshold. The non-integrated noise
sources affect the comparator decision by either affecting the comparator threshold
voltage or the summing node voltage. The former is the input-referenced comparator
noise, Vn,co,, and the latter are Vn,IntAmp and in,cs2. Vn,IntAmp and in,cs2 perturb the
positive input of the integrating amplifier, and the summing node voltage tracks this

87
perturbation due to the negative feedback of the integrating amplifier. As such, these
noise sources are band-limited by the finite bandwidth of the integrating amplifier.
Calculating the noise power of the total nonintegrated noise, Vn,nonInt(f):

n~nonrn (f ) = n cOM,(f )+1 + ( (,IntAmp(f) + Rumm yswitch ncs2 (f

(/GBWVntAmp)2

where GBWIntAm, is the gain-bandwidth product of the integrating amplifier, and

we are assuming that Rdummyswitch << Ref2. This is a conservative approximation
as the integrating amplifier's limited bandwidth will band-limit Vn,IntAmp and in,c8 2
more aggressively than the first-order slope in the equation.

5.3 Normalized Total Noise

As established in Chapter 3.3.3, the auto-zero mechanism of the modified Landsburg

ADC requires that every conversion be based on two sets of Measure State and Residue
State. As such, each conversion will have the noise of two sets of Measure State and
Residue State. Calculating the noise power of one conversion, referenced at the input
of the comparator, n,canversion:

Vncero(f) = [vn,c() nonnt (f)) + ±[v,,ci (f) + v,nonInt(f)] V_

onconversion(f) = 2vn,cin, (f) + 2 n,nonnt (f)

Figure 5-3 shows Vvconversion(f) over frequency, based on simulated noise data
from individual blocks. We can square root the area under the graph to estimate the
RMS noise of the full conversion. Integrating from 2Hz to 2GHz:

2GHz

Vn,conversion,rms = ,coneson(f = 0.0118V 2

2Hz

Vn,conversion,rms = 0.109V

As described in Chapter 4.5, a 1LSB change in ADC input voltage produces a

88
 10,2 i i i i' "

10,

10~

0 -
CL1C 10~
4) III 1.
z

0-

10-to

-d ,1 34 I ,I I I , , ,,P,
10 10 10 1e 10 10 10 10 10 10 10
Frequency (Hz)

Figure 5-3: Log-log magnitude plot of total ADC noise power at comparator input,
n, 3cversion(f) over frequency

89
change of Vint,1LSB in integrator output voltage, which can be used to normalize this

noise to input LSBs:

1 1 Vref tmeas m - 2n
Vint,1LSB Cint 2 R-1 2 R-ef
m

Usig== v 2V
Using Vref
Hnc
*36m.
2.5V, Vint,lLSB ~ 36mV. Hence
Vn, conversion, RMS
Vnt,LSB =
input L~
3Om LSBs
of RMS noise, which is fairly high for a precision ADC. The ENOB and SNR are as
follows:
F 219 LSBs 1
ENOB = 1og 2 I I = 15.6bits
[3LSBs x F12
(219 LSBs. 1 1 )21
2
SNR = 10logio 2 = 95.8dB
(3LSBs)2

Noise Response

10-18.: output noise; A**2 / Hz

10-

10-

10-2

10-2

10-2

10 -2

10-2

loin loom 1 10 100 1K 10K 100K iM lom loom iG

freq ( Hz )

Figure 5-4: Log-log magnitude plot of noise power of the 2" current source, i2, 1 (f)

Further inspection reveals the cause of this noise. It originates from the large

7 noise current of the Vrf

2Rref current source, shown in Figure 5-4. Ignoring just this

current source's - noise results in Vn,conversion,rms = 0.033V, which is 0.92 input LSBs.

ENOB (17.3 bits) and SNR (106dB) improve accordingly. This is clearly a target for
future work.

90
Chapter 6

Conclusion & Future Work

6.1 Conclusion

In this project, an unusual charge-balancing ADC topology was revived as a fully-

monolithic, high-resolution, low-cost converter. Designed and simulated on a 0.25pm

CMOS process, the converter fits in under 300mils 2 of die area and produces 5 Sam-

ples/s while consuming under 2mW. The ADC has auto-zero functionality and main-

tains <0.01% gain error over the military temperature range. While it outputs 19-bit

samples, high noise in one analog block reduces its ENOB to 15.6 bits. This should

improve to >17 bits with a slight redesign.

6.2 Future Work

The modified Landsburg is still a simulated prototype. It requires an input buffer with

high input impedance and low - noise, suggesting a chopped MOS-input design. The

excessively-noisy 2"f current source (as elaborated in Chapter 5.3) begs a redesign

to allow the system to meet its full potential.

As the high-gain, high-bandwidth, high-output-current requirements of the inte-

grating amplifier are the main ceiling on the ADC's performance, it may be necessary

to rearchitect the system to relax these constraints. One possibility is supplementing

the integrator output's current drive with a second, complimentary up/down current

91
source. The integrating amplifier's gain and bandwidth might also be augmented

with replica amplifier techniques[13].

Another target for future work is the inclusion of a die-level gain-calibration mech-

anism. As the gain is proportional to the ratio of Rref

Rin and Rej is matched to Rref 2,

this is best implemented as a blown-fuse adjustment of Rin.

Finally, the necessary steps must be taken to ready the design for fabrication.

This involves layout, parasitic extraction and full system verification. We will then

be able to compare theory and simulation against the ADC's real-world performance.

92
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2
[3] Microchip Technology Inc., "16-Bit Analog-to-Digital Converter with 1 C Inter-
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[4] Cirrus Logic Inc., "16-bit/20-bit, Multi-range ADC with 4-bit Latch," CS5526
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[5] J. E. Johnston, "A 24-bit delta-sigma ADC with an ultra-low noise chopper-
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[6] C. B. Wang, "A 20 bit 25 kHz delta sigma A/D converter utilizing frequency-
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[7] V. Quiquempoix. "A low-power 22-bit incremental ADC". IEEE Journalof Solid-
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[8] G. Landsburg."A charge-balancing monolithic a/d converter. IEEE Journal of

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[11] K. Lundberg, "Describing Functions, in Feedback Systems for Analog Circuit De-
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[12] K. Kundert (2001, October). A Formal Top-Down Design Process for

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