8086 Microprocessor

Sukesh Rao M
Assc. Professor,
Dept. of ECE
1 Sukesh Rao M, Dept of ECE, NMAMIT,Nitte NMAMIT, Nitte
 Course Learning Outcome
 Realize the use/meaning of Memory, Central Processing Unit, Arithmetic and
logical unit (ALU), Address Bus, Data Bus and Control lines of an embedded
system.
 Distinguish Microcontroller and Microprocessor design Architecture and the
functionality.
 Understand the Assembly Language Programming for the microprocessor and
microcontroller.
 Write assembly language program for 8086 & 8051 in sequential logic using all
possible kinds of Mnemonics.
 Design and use Timer/ Counter programming application in 8051
microcontroller.
 Design and use interrupt in 8086 & 8051.
 Design any real time system using timer/counter or interrupts (if necessary)
application of 8051.
 Design and study basic interfacing like matrix keypad, DC Motor speed
control, Analog to Digital Conversion, Stepper Motor and Liquid Crystal
Display.
2 Sukesh Rao M, Dept of ECE, NMAMIT,Nitte
 Features of 8086
 It is 16 bit processor
 20 bit address lines to access memory
 16-bit address lines to access I/O devices
 Pipelining: 8086 uses two stage of pipelining. First is Fetch
Stage and the second is Execute Stage
 8086 uses memory banks
 Interrupts:-8086 has 256 vectored interrupts
 Multiplication And Division

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 Architecture

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 Architecture
 Bus Interface Unit
 Instruction Queue
 Instruction Pointer
 Segment Registers
 Execution Unit
 General Purpose Registers
 Arithmetic and Logic Unit
 Flag Register

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 Architecture- Bus Interface Unit
 Instruction Queue
 Pipelining
 Speed up program execution
 Pre-fetch 6 instruction bytes
 Instruction Pointer (IP)
 16-bit register
 Used as the effective memory address
 Added to the Code segment with a displacement of four bits to
obtain the physical address.

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 Architecture- Bus Interface Unit
 Segment Registers
 To obtain 20-bit addresses from the available 16-bit register
 Summing the contents of a segment register and an effective
memory address
 Default effective registers and segment register
Segment Register Effective Address
Code Segment(CS) IP
Data Segment(DS) SI, DI, BX,16-Bit data
Extra Segment(ES) DI
Stack Segment(SS) SP or BP

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 Architecture- Execution Unit
 General Purpose Registers
 The data register group
AH AL AX
BH BL BX
CH CL CX
DH DL DX

 The index register group

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 Architecture- Execution Unit

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 Architecture- Execution Unit
 Arithmetic and Logic Unit
 Arithmetic operations
 Addition, Subtraction, Multiplication, Division
 Logical operations
 Not,And, Or, Exclusive Or,Test
 Flag Register
 Some conditions affected by the execution of an instruction
 Nine active flag bits
MSB LSB
X X X X OV DF IF TF SF ZF X AC X PF X CF

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 Architecture- Execution Unit
 Flag Register
 Condition Flags
 Carry Flag (CF)
 Parity Flag (PF): Even Parity
 Auxiliary Carry Flag (AC)
 Zero Flag (ZF)
 Overflow Flag (OV)
 Sign flag (SF)

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 Architecture- Execution Unit
 Flag Register
 Control flags
 Trap flag (TF)
 Interrupt Flag (IF)
 Direction Flag (DF)

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 Addressing Modes
 Immediate addressing mode
 Register addressing mode
 Direct addressing mode
 Register indirect addressing mode
 Based addressing mode
 Indexed addressing mode.
 Based indexed addressing mode
 Based, Indexed with displacement

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 Addressing Modes

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 Addressing Modes

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 Assembler Directives
 Directions to the assembler
 Pseudo operations
 DB- Define Byte, DW- Define word, DD- define double word,
DQ- define quad word.
 ASSUME, EQU (Equate), ORG (Originate), PROC(Procedure),
END, ENDP,ENDS

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 Instruction Set
 Data transfer instructions
 Arithmetic instructions
 Logical instructions
 Program Execution Transfer instructions (Branch & loop
Instructions)
 Miscellaneous instructions

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 Data Transfer Instructions
 Transfer the data from source operand to destination
operand.
 MOV
 The MOV instruction copies a word or byte of data from a
specified source to a specified destination
 Format: MOV Destination,Source

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 Data Transfer Instructions
 MOV CX, 037AH
 Put immediate number 037AH to CX
 MOV BL, [437AH]
 Copy byte in DS at offset 437AH to BL
 MOV AX,BX
 Copy content of register BX toAX
 MOV DL, [BX]
 Copy byte from memory at [BX] to DL
 MOV DS, BX
 Copy word from BX to DS register
 MOV RESULT [BP],AX
 Copy AX to two memory locations

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 Data Transfer Instructions
 PUSH
 To store data in stack segment,
 Format: PUSH Source
 Copies a word from a specified source to the location in the
stack segment to which the stack pointer points.
 The stack segment register and the stack pointer must be
initialized.
 The PUSH instruction does not affect any flag

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 Data Transfer Instructions
 POP
 To copy data from stack segment
 Format: POP Destination
 To copy a word of data from the stack location pointed to by the
stack pointer to a destination specified in the instruction.
 The POP instruction does not affect any flag

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 Data Transfer Instructions
 Working of Push
 The higher byte data is pushed first (SP-1).
 Then lower byte data is pushed (SP-2).
 Stack pointer is decremented by 2.

 Working of Pop
 Then lower byte data copied from the stack (SP).
 The higher byte data is copied from stack (SP+1).
 Stack pointer is incremented by 2.

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 Data Transfer Instructions
 PUSH BX
 Decrement SP by 2, copy BX to stack.
 PUSH DS
 Decrement SP by 2, copy DS to stack.
 PUSH BL
 Illegal; must push a word
 PUSH TABLE [BX]
 Decrement SP by 2, and copy word from memory in DS at EA
= TABLE + [BX] tostack

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 Data Transfer Instructions
 POP DX
 Copy a word from top of stack to DX; increment SP by 2
 POP DS
 Copy a word from top of stack to DS; increment SP by 2
 POP TABLE [DX]
 Copy a word from top of stack to memory in DS with EA =
TABLE + [BX]; increment SP by 2

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 Data Transfer Instructions
 STRING MANIPULATION INSTRUCTIONS
 MOVS, MOVSB,MOVSW

 LODS / LODSB / LODSW (LOAD STRING BYTE INTOAL

 STOS / STOSB / STOSW (STORE STRING BYTE OR

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 Data Transfer Instructions
 LEA
 Format: LEA Register, Source
 This instruction determines the offset of the variable or
memory location named as the source
 Puts this offset in the indicated 16-bit register

 LEA BX,PRICES
 Load BX with offset of PRICE in DS
 LEA CX,[BX][DI]
 Load CX with EA = [BX] + [DI]

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 Data Transfer Instructions
 LDS
 Format: LDS Register, Memory address of the first word
 Loads new values into the specified register and into the DS
register from four successive memory locations.
 LDS does not affect any flag.
 Example
 LDS BX, [4326];
 Copy content of memory at displacement 4326H in DS to BL, content of
4327H to BH.
 Copy content at displacement of 4328H and 4329H in DS to DS register.

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 Data Transfer Instructions
 LES
 Format: LES Register, Memory address of the first word
 Loads new values into the specified register and into the ES
register from four successive memory locations
 Example
 LES DI,[BX]
 Copy content of memory at offset [BX] and offset [BX] + 1 in DS to DI
register.
 Copy content of memory at offset [BX] + 2 and [BX] + 3 to ES register

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 Arithmetic Instructions
 Addition Instruction
 Format: ADD – ADD Destination, Source
ADC – ADC Destination, Source
 Add a number from Source to a number in Destination
 The result stored in the Destination.
 The source and the destination must be of the same type
 Flags affected: AF, CF, OF, PF, SF,ZF
 source and the destination in an instruction cannot both be
memory locations

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 Arithmetic Instructions
 ADD AL,74H
 Add immediate number 74H to content ofAL. Result inAL
 ADC CL, BL
 Add content of BL plus carry status to content of CL
 ADD DX, BX
 Add content of BX to content of DX
 ADD DX, [SI]
 Add word from memory at offset [SI] in DS to content of DX
 ADC AL, PRICES [BX]
 Add byte from effective address PRICES [BX] plus carry status
to content ofAL

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 Arithmetic Instructions
 INC – INC Destination
 The INC instruction adds 1 to a specified register or to a memory
location.
 AF, OF, PF, SF, and ZF are updated, but CF is notaffected.
 INC BL Add 1 to contains of BL register
 INC CX Add 1 to contains of CXregister
 INCWORD PTR [BX]
 Increment the word at offset of [BX] and [BX + 1] in the data
segment.
 INC TEMP
 Increment byte or word namedTEMP in the data segment. Increment
byte if TEMP declared with DB. Increment word if TEMP is declared
with DW

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 Arithmetic Instructions
 Subtraction Instruction
 Format: SUB – SUB Destination, Source
SBB – SBB Destination, Source
 Subtract a number from Source to a number in Destination
 The result stored in the Destination.
 The source and the destination must be of the same type
 Flags affected: AF, CF, OF, PF, SF,ZF
 source and the destination in an instruction cannot both be
memory locations

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 Arithmetic Instructions
 DEC – DEC Destination
 Subtracts 1 from the destination word or byte.
 The destination can be a register or a memory location.
 AF, OF, SF, PF, and ZF are updated, but CF is notaffected
 DEC CL Subtract 1 from content of CL register
 DEC BP Subtract 1 from content of BP register
 DEC BYTE PTR [BX] Subtract 1 from byte at offset [BX]
in DS.
 DEC WORD PTR [BP] Subtract 1 from a word at offset
[BP] in SS.

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 Arithmetic Instructions
 DAA (Decimal Adjust After BCD Addition)
 DAS (Decimal Adjust After BCD Subtraction)

 The result of adding two packed BCD numbers is adjusted to be

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 Arithmetic Instructions
 Multiplication Instruction
 Format: MUL – MUL Source
 8 bit multiplication result stored in AH-AL register
 16 bit multiplication result stored in DX-AX register
 If the most significant byte of a 16-bit result or the most
significant word of a 32-bit result is 0, CF and OF will both be
0’s.
 AF, PF, SF and ZF are undefined after a MUL instruction.

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 Arithmetic Instructions
 MUL BH
 MultiplyAL with BH; result inAX
 MUL CX
 MultiplyAX with CX; result high word in DX, low word inAX
 MUL BYTE PTR [BX]
 Multiply AL with byte in DS pointed to by [BX]
 MUL FACTOR [BX]
 Multiply AL with byte at effective address FACTOR [BX], if it
is declared as type byte with DB. Multiply AX with word at
effective address FACTOR [BX], if it is declared as type word
with DW.

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 Arithmetic Instructions
 Division Instruction
 Format: DIV – DIV Source
 This instruction is used to divide an word by a byte
 To divide an unsigned double word (32 bits) by a word
 Word division
 Word must be in the AX register.The divisor can be in a register
or a memory location
 AL will contain the 8-bit quotient, and AH will contain the8-
bit remainder

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 Arithmetic Instructions
 When a double word is divided by a word
 Double Word must be in the DX―AX register
 After the division,
 AX will contain the 16-bit quotient
 DX will contain the 16-bit remainder
 If an attempt is made to divide by 0 or if the quotient is too
large to fit in the destination (greater than FFH/FFFFH),the
8086 will generate a type 0 interrupt.
 All flags are undefined after a DIV instruction.

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