STM32F051x4 STM32F051x6

STM32F051x8
Low- and medium-density advanced ARM™-based 32-bit MCU with
16 to 64 Kbytes Flash, timers, ADC, DAC and comm. interfaces
Datasheet − production data

Features
■ Core: ARM 32-bit Cortex™-M0 CPU,
frequency up to 48 MHz
■ Memories LQFP64 10x10 mm UFQFPN32 5x5 mm
LQFP48 7x7 mm
– 16 to 64 Kbytes of Flash memory LQFP32 7x7 mm
– 8 Kbytes of SRAM with HW parity checking – One 16-bit timer, with 2 IC/OC, 1 OCN,
■ CRC calculation unit deadtime generation and emergency stop
– Two 16-bit timers, each with IC/OC and
■ Reset and power management
OCN, deadtime generation, emergency
– Voltage range: 2.0 V to 3.6 V stop and modulator gate for IR control
– Power-on/Power down reset (POR/PDR) – One 16-bit timer with 1 IC/OC
– Programmable voltage detector (PVD) – Independent and system watchdog timers
– Low power modes: Sleep, Stop, Standby – SysTick timer: 24-bit downcounter
– VBAT supply for RTC and backup registers – One 16-bit basic timer to drive the DAC
■ Clock management ■ Calendar RTC with alarm and periodic wakeup
– 4 to 32 MHz crystal oscillator from Stop/Standby
– 32 kHz oscillator for RTC with calibration ■ Communication interfaces
– Internal 8 MHz RC with x6 PLL option – Up to two I2C interfaces; one supporting
– Internal 40 kHz RC oscillator Fast Mode Plus (1 Mbit/s) with 20 mA
■ Up to 55 fast I/Os current sink, SMBus/PMBus, and wakeup
– All mappable on external interrupt vectors from STOP
– Up to 36 I/Os with 5 V tolerant capability – Up to two USARTs supporting master
synchronous SPI and modem control; one
■ 5-channel DMA controller with ISO7816 interface, LIN, IrDA
■ 1 × 12-bit, 1.0 µs ADC (up to 16 channels) capability, auto baud rate detection and
– Conversion range: 0 to 3.6V wakeup feature
– Separate analog supply from 2.4 up to 3.6 – Up to two SPIs (18 Mbit/s) with 4 to 16
programmable bit frame, 1 with I2S
■ One 12-bit D/A converter interface multiplexed
■ Two fast low-power analog comparators with – HDMI CEC interface, wakeup on header
programmable input and output reception
■ Up to 18 capacitive sensing channels ■ Serial wire debug (SWD)
supporting touchkey, linear and rotary touch
■ 96-bit unique ID
sensors
■ Up to 11 timers Table 1. Device summary
– One 16-bit 7-channel advanced-control
Reference Part number
timer for 6 channels PWM output, with
deadtime generation and emergency stop STM32F051x4 STM32F051K4, STM32F051C4, STM32F051R4

– One 32-bit and one 16-bit timer, with up to STM32F051x6 STM32F051K6, STM32F051C6, STM32F051R6
4 IC/OC, usable for IR control decoding STM32F051x8 STM32F051C8, STM32F051R8, STM32F051K8

July 2012 Doc ID 022265 Rev 3 1/105

This is information on a product in full production. www.st.com 1
Contents STM32F051x

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.2 General-purpose timers (TIM2..3, TIM14..17) . . . . . . . . . . . . . . . . . . . . 21
3.14.3 Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17 Universal synchronous/asynchronous receiver transmitters (USART) . . . 24
3.18 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 24
3.19 High-definition multimedia interface (HDMI) - consumer electronics control
(CEC) 25
3.20 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 43
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.16 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.17 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.19 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.20 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.21 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 100

8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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STM32F051x List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F051x family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Capacitive sensing GPIOs available on STM32F051x devices . . . . . . . . . . . . . . . . . . . . . 19
Table 6. No. of capacitive sensing channels available on STM32F051x devices. . . . . . . . . . . . . . . 19
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. STM32F051x I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. STM32F051x USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. STM32F051x SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 33
Table 15. Alternate functions selected through GPIOA_AFR registers for port B . . . . . . . . . . . . . . . 34
Table 16. STM32F051x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 23. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 46
Table 26. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 47
Table 27. Typical and maximum VDD consumption in Stop and Standby modes . . . . . . . . . . . . . . . 48
Table 28. Typical and maximum VDDA consumption in Stop and Standby modes . . . . . . . . . . . . . . 49
Table 29. Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 49
Table 30. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 51
Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 35. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 36. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 40. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 41. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 42. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 43. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 44. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 45. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 46. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 47. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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List of tables STM32F051x

Table 48. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 49. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 50. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 51. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 52. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 53. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 54. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 55. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 56. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 57. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 58. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 59. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 60. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 61. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 62. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 63. WWDG min-max timeout value @48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 64. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 65. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 66. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 67. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 68. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . . 92
Table 69. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 94
Table 70. LQFP32 7 x 7mm 32-pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . 96
Table 71. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 72. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 73. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 74. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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STM32F051x List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP64 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4. LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5. LQFP32 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 6. UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7. STM32F051x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 13. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 15. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 16. TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 17. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 71
Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . 71
Figure 20. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 22. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 23. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 24. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 25. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 27. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 28. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 29. I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 30. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 31. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 92
Figure 32. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 33. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 94
Figure 34. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 35. LQFP32 7 x 7mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 96
Figure 36. LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . . 98
Figure 38. UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 39. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

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Introduction STM32F051x

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of
the STM32F051x microcontrollers.
This STM32F051x4, STM32F051x6, and STM32F051x8 datasheet should be read in
conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is
available from the STMicroelectronics website www.st.com.
For information on the ARM Cortex™-M0 core, please refer to the Cortex™-M0 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html.

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STM32F051x Description

2 Description

The STM32F051x family incorporates the high-performance ARM Cortex™-M0 32-bit RISC
core operating at a 48 MHz frequency, high-speed embedded memories (Flash memory up
to 64 Kbytes and SRAM up to 8 Kbytes), and an extensive range of enhanced peripherals
and I/Os. All devices offer standard communication interfaces (up to two I2Cs, two SPIs, one
I2S, one HDMI CEC, and up to two USARTs), one 12-bit ADC, one 12-bit DAC, up to five
general-purpose 16-bit timers, a 32-bit timer and an advanced-control PWM timer.
The STM32F051x family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes
allows the design of low-power applications.
The STM32F051x family includes devices in four different packages ranging from 32 pins to
64 pins. Depending on the device chosen, different sets of peripherals are included. The
description below provides an overview of the complete range of peripherals proposed in
this family.
These features make the STM32F051x microcontroller family suitable for a wide range of
applications such as application control and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.

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Description STM32F051x

Table 2. STM32F051x family device features and peripheral counts

Peripheral STM32F051Kx STM32F051Cx STM32F051Rx

Flash (Kbytes) 16 32 64 16 32 64 16 32 64
SRAM (Kbytes) 4 8 4 8 4 8
Advanced
1 (16-bit)
control

Timers General 5 (16-bit)

purpose 1 (32-bit)
Basic 1 (16-bit)
(1) (2)
SPI [I2S] 1[1] 1[1] (2) 2[1] 1[1] (2) 2[1]

Comm. I2C 1(3) 1(3) 2 1(3) 2

interfaces USART 1(4) 2 1(4) 2 1(4) 2
CEC 1
12-bit synchronized
1 1
ADC
(10 ext. + 3 int.) (16 ext. + 3 int.)
(number of channels)
25 (on LQFP32)
GPIOs 39 55
27 (on UFQFPN32)

Capacitive sensing 13 (on LQFP32)

17 18
channels 14 (on UFQFPN32)
12-bit DAC 1
(number of channels) (1)
Analog comparator 2
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Operating temperature
Junction temperature: -40 °C to 125 °C
LQFP32
Packages LQFP48 LQFP64
UFQFPN32
1. The SPI1 interface can be used either in SPI mode or in I2S audio mode.
2. SPI2 is not present
3. I2C2 is not present
4. USART2 is not present

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STM32F051x Description

Figure 1. Block diagram

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Functional overview STM32F051x

3 Functional overview

3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM

The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F051x family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.

3.2 Memories
The device has the following features:
● Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0
wait states and featuring embedded parity checking with exception generation for fail-
critical applications.
● The non-volatile memory is divided into two arrays:
– 16 to 64 Kbytes of embedded Flash memory for programs and data
– Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled

3.3 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
● Boot from User Flash
● Boot from System Memory
● Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.

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STM32F051x Functional overview

3.4 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

3.5 Power management

3.5.1 Power supply schemes

● VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
● VDDA = 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL
(minimum voltage to be applied to VDDA is 2.4 V when the ADC and DAC are used).
The VDDA voltage level must be always greater or equal to the VDD voltage level and
must be provided first.
● VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.

3.5.2 Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
● The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
● The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.

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Functional overview STM32F051x

3.5.3 Voltage regulator

The regulator has three operating modes: main (MR), low power (LPR) and power down.
● MR is used in normal operating mode (Run)
● LPR can be used in Stop mode where the power demand is reduced
● Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.

3.5.4 Low-power modes

The STM32F051x family supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC alarm, COMPx, I2C1,
USART1 or the CEC.
The I2C1, USART1 and the CEC can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used, the voltage regulator should not be put in the
low-power mode but kept in normal mode.
● Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pins, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.

3.6 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).

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STM32F051x Functional overview

Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

Figure 2. Clock tree

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3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.

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Functional overview STM32F051x

The I/O configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.

3.8 Direct memory access controller (DMA)

The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14), DAC and ADC.

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

The STM32F051x family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4
priority levels.
● Closely coupled NVIC gives low latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Closely coupled NVIC core interface
● Allows early processing of interrupts
● Processing of late arriving higher priority interrupts
● Support for tail-chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.

3.9.2 Extended interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 55
GPIOs can be connected to the 16 external interrupt lines.

3.10 Analog to digital converter (ADC)

The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature

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STM32F051x Functional overview

sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.

Table 3. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at

TS_CAL1 temperature of 30 °C, 0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V
TS ADC raw data acquired at
TS_CAL2 temperature of 110 °C 0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V

3.10.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.

Table 4. Temperature sensor calibration values

Calibration value name Description Memory address

Raw data acquired at

VREFINT_CAL temperature of 30 °C 0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V

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Functional overview STM32F051x

3.10.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.

3.11 Digital-to-analog converter (DAC)

The 12-bit buffered DAC channel can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in non-inverting configuration.
This digital Interface supports the following features:
● Left or right data alignment in 12-bit mode
● Synchronized update capability
● DMA capability
● External triggers for conversion
Five DAC trigger inputs are used in the device. The DAC is triggered through the timer
trigger outputs and the DAC interface is generating it’s own DMA requests.

3.12 Comparators (COMP)

The device embeds two fast rail-to-rail low-power comparators with programmable reference
voltage (internal or external), hysteresis and speed (low speed for low power) and with
selectable output polarity.
The reference voltage can be one of the following:
● External I/O
● DAC output pin
● Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 24: Embedded
internal reference voltage for the value and precision of the internal reference voltage.
Both comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined into a window comparator.
The internal voltage reference is also connected to ADC_IN17 input channel of the ADC.

3.13 Touch sensing controller (TSC)

The STM32F051x devices provide a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect the presence
of a finger near an electrode which is protected from direct touch by a dielectric (glass,
plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle. It consists of charging the electrode capacitance and then transferring a part of the
accumulated charges into a sampling capacitor until the voltage across this capacitor has
reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly
managed by the hardware touch sensing controller and only requires few external

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STM32F051x Functional overview

components to operate. The STM32F051x devices offer up to 18 capacitive sensing

channels distributed over 6 analog I/O groups.

Table 5. Capacitive sensing GPIOs available on STM32F051x devices

Capacitive sensing Pin Capacitive sensing Pin
Group Group
signal name name signal name name

TSC_G1_IO1 PA0 TSC_G4_IO1 PA9

TSC_G1_IO2 PA1 TSC_G4_IO2 PA10
1 4
TSC_G1_IO3 PA2 TSC_G4_IO3 PA11
TSC_G1_IO4 PA3 TSC_G4_IO4 PA12
TSC_G2_IO1 PA4 TSC_G5_IO1 PB3
TSC_G2_IO2 PA5 TSC_G5_IO2 PB4
2 5
TSC_G2_IO3 PA6 TSC_G5_IO3 PB6
TSC_G2_IO4 PA7 TSC_G5_IO4 PB7
TSC_G3_IO1 PC5 TSC_G6_IO1 PB11
TSC_G3_IO2 PB0 TSC_G6_IO2 PB12
3 6
TSC_G3_IO3 PB1 TSC_G6_IO3 PB13
TSC_G3_IO4 PB2 TSC_G6_IO4 PB14

Table 6. No. of capacitive sensing channels available on STM32F051x devices

Number of capacitive sensing channels
Analog I/O group
STM32F051Kx STM32F051Kx
STM32F051Rx STM32F051Cx
(UFQFPN32) (LQFP32)

G1 3 3 3 3
G2 3 3 3 3
G3 3 2 2 1
G4 3 3 3 3
G5 3 3 3 3
G6 3 3 0 0
Number of capacitive
18 17 14 14
sensing channels

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Functional overview STM32F051x

3.14 Timers and watchdogs

The STM32F051x family devices include up to six general-purpose timers, one basic timer
and an advanced control timer.
Table 7 compares the features of the advanced-control, general-purpose and basic timers.

Table 7. Timer feature comparison

Timer Counter Counter Prescaler DMA request Capture/compare Complementary
Timer
type resolution type factor generation channels outputs

Any integer
Advanced Up, down,
TIM1 16-bit between 1 Yes 4 Yes
control up/down
and 65536
Any integer
Up, down,
TIM2 32-bit between 1 Yes 4 No
up/down
and 65536
Any integer
Up, down,
TIM3 16-bit between 1 Yes 4 No
up/down
and 65536
Any integer
General
TIM14 16-bit Up between 1 No 1 No
purpose
and 65536
Any integer
TIM15 16-bit Up between 1 Yes 2 Yes
and 65536
Any integer
TIM16,
16-bit Up between 1 Yes 1 Yes
TIM17
and 65536
Any integer
Basic TIM6 16-bit Up between 1 Yes 0 No
and 65536

3.14.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
● Input capture
● Output compare
● PWM generation (edge or center-aligned modes)
● One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.

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STM32F051x Functional overview

3.14.2 General-purpose timers (TIM2..3, TIM14..17)

There are six synchronizable general-purpose timers embedded in the STM32F051x
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.

TIM2, TIM3
STM32F051x devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.

TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with
TIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.

3.14.3 Basic timer TIM6

This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit
time base.

3.14.4 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-
defined refresh window. It is clocked from an independent 40 kHz internal RC and as it

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Functional overview STM32F051x

operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.

3.14.5 System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.

3.14.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source (HCLK or HCLK/8)

3.15 Real-time clock (RTC) and backup registers

The RTC and the 5 backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
● Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
● Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.
● Programmable alarm with wake up from Stop and Standby mode capability.
● On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
● Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
● 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
● Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
● A 32.768 kHz external crystal
● A resonator or oscillator
● The internal low-power RC oscillator (typical frequency of 40 kHz)
● The high-speed external clock divided by 32.

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3.16 Inter-integrated circuit interfaces (I2C)

Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s) and I2C1
supports also Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2
addresses, 1 with configurable mask). They also include programmable analog and digital
noise filters.

Table 8. Comparison of I2C analog and digital filters

Analog filter Digital filter

Pulse width of Programmable length from 1 to 15

≥ 50 ns
suppressed spikes I2C peripheral clocks
1. Extra filtering capability vs.
Benefits Available in Stop mode standard requirements.
2. Stable length
Variations depending on Disabled when Wakeup from Stop
Drawbacks
temperature, voltage, process mode is enabled

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 9 for the differences between I2C1 and I2C2.

Table 9. STM32F051x I2C implementation

I2C features(1) I2C1 I2C2

7-bit addressing mode X X

10-bit addressing mode X X

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X

Independent clock X

SMBus X

Wakeup from STOP X

1. X = supported.

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Functional overview STM32F051x

3.17 Universal synchronous/asynchronous receiver transmitters

(USART)
The device embeds up to two universal synchronous/asynchronous receiver transmitters
(USART1 and USART2), which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. The USART1 supports also SmartCard communication
(ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has a
clock domain independent from the CPU clock, allowing the USART1 to wake up the MCU
from Stop mode.
The USART interfaces can be served by the DMA controller.
Refer to Table 10 for the differences between USART1 and USART2.

Table 10. STM32F051x USART implementation

USART modes/features(1) USART1 USART2

Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X X
Smartcard mode X
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X
LIN mode X
Dual clock domain and wakeup from Stop mode X
Receiver timeout interrupt X
Modbus communication X
Auto baud rate detection X
Driver Enable X X
1. X = supported.

3.18 Serial peripheral interface (SPI)/Inter-integrated sound

interfaces (I2S)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I2S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at simplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit

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STM32F051x Functional overview

programmable linear prescaler. When operating in master mode it can output a clock for an
external audio component at 256 times the sampling frequency.
Refer to Table 11 for the differences between SPI1 and SPI2.

Table 11. STM32F051x SPI/I2S implementation

SPI features(1) SPI1 SPI2

Hardware CRC calculation X X

Rx/Tx FIFO X X
NSS pulse mode X X
I2S mode X
TI mode X X
1. X = supported.

3.19 High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.

3.20 Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.

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Pinouts and pin description STM32F051x

4 Pinouts and pin description

Figure 3. LQFP64 64-pin package pinout

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STM32F051x Pinouts and pin description

Figure 4. LQFP48 48-pin package pinout

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Figure 5. LQFP32 32-pin package pinout

"//4

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Pinouts and pin description STM32F051x

Figure 6. UFQFPN32 32-pin package pinout

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Table 12. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function
Pin name
during and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
TTa 3.3 V tolerant I/O directly connected to ADC
I/O structure
TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
Notes
and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions Additional
Functions directly selected/enabled through peripheral registers
functions

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STM32F051x Pinouts and pin description

Table 13. Pin definitions

Pin number Pin functions

I/O structure
Pin type
Pin name
UFQFPN32
LQFP64

LQFP48

LQFP32

(function after Notes

reset) Alternate functions Additional functions

1 1 - - VBAT S Backup power supply

RTC_TAMP1,
(1)(2)
2 2 - - PC13 I/O TC RTC_TS, RTC_OUT,
WKUP2
PC14-OSC32_IN (1)(2)
3 3 - - I/O TC OSC32_IN
(PC14)
PC15-
OSC32_OUT (1)(2)
4 4 - - I/O TC OSC32_OUT
(PC15)
PF0-OSC_IN
5 5 2 2 I/O FT OSC_IN
(PF0)
PF1-OSC_OUT
6 6 3 3 I/O FT OSC_OUT
(PF1)
7 7 4 4 NRST I/O RST Device reset input / internal reset output (active low)
8 - - - PC0 I/O TTa EVENTOUT ADC_IN10
9 - - - PC1 I/O TTa EVENTOUT ADC_IN11
10 - - - PC2 I/O TTa EVENTOUT ADC_IN12
11 - - - PC3 I/O TTa EVENTOUT ADC_IN13
12 8 - 0 VSSA S Analog ground
13 9 5 5 VDDA S Analog power supply
USART2_CTS, ADC_IN0,
TIM2_CH1_ETR, COMP1_INM6,
14 10 6 6 PA0 I/O TTa
COMP1_OUT, RTC_TAMP2,
TSC_G1_IO1 WKUP1
USART2_RTS, TIM2_CH2, ADC_IN1,
15 11 7 7 PA1 I/O TTa
TSC_G1_IO2, EVENTOUT COMP1_INP
USART2_TX, TIM2_CH3,
TIM15_CH1, ADC_IN2,
16 12 8 8 PA2 I/O TTa
COMP2_OUT, COMP2_INM6
TSC_G1_IO3
USART2_RX, TIM2_CH4, ADC_IN3,
17 13 9 9 PA3 I/O TTa
TIM15_CH2, TSC_G1_IO4 COMP2_INP
18 - - - PF4 I/O FT EVENTOUT
19 - - - PF5 I/O FT EVENTOUT

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Pinouts and pin description STM32F051x

Table 13. Pin definitions (continued)

Pin number Pin functions

I/O structure
Pin type
Pin name
UFQFPN32
LQFP64

LQFP48

LQFP32

(function after Notes

reset) Alternate functions Additional functions

ADC_IN4,
SPI1_NSS/I2S1_WS,
COMP1_INM4,
20 14 10 10 PA4 I/O TTa USART2_CK, TIM14_CH1,
COMP2_INM4,
TSC_G2_IO1
DAC1_OUT
SPI1_SCK/I2S1_CK, CEC, ADC_IN5,
21 15 11 11 PA5 I/O TTa TIM2_CH1_ETR, COMP1_INM5,
TSC_G2_IO2 COMP2_INM5
SPI1_MISO/I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
22 16 12 12 PA6 I/O TTa TIM16_CH1, ADC_IN6
COMP1_OUT,
TSC_G2_IO3, EVENTOUT
SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM14_CH1,
23 17 13 13 PA7 I/O TTa TIM1_CH1N, TIM17_CH1, ADC_IN7
COMP2_OUT,
TSC_G2_IO4, EVENTOUT
24 - - - PC4 I/O TTa EVENTOUT ADC_IN14
25 - - - PC5 I/O TTa TSC_G3_IO1 ADC_IN15
TIM3_CH3, TIM1_CH2N,
26 18 14 14 PB0 I/O TTa ADC_IN8
TSC_G3_IO2, EVENTOUT
TIM3_CH4, TIM14_CH1,
27 19 15 15 PB1 I/O TTa ADC_IN9
TIM1_CH3N, TSC_G3_IO3
(3)
28 20 - 16 PB2 I/O FT TSC_G3_IO4
I2C2_SCL, CEC,
29 21 - - PB10 I/O FT
TIM2_CH3, TSC_SYNC
I2C2_SDA, TIM2_CH4,
30 22 - - PB11 I/O FT
TSC_G6_IO1, EVENTOUT
31 23 16 0 VSS S Ground
32 24 17 17 VDD S Digital power supply
SPI2_NSS, TIM1_BKIN,
33 25 - - PB12 I/O FT
TSC_G6_IO2, EVENTOUT
SPI2_SCK, TIM1_CH1N,
34 26 - - PB13 I/O FT
TSC_G6_IO3
SPI2_MISO, TIM1_CH2N,
35 27 - - PB14 I/O FT
TIM15_CH1, TSC_G6_IO4
SPI2_MOSI, TIM1_CH3N,
36 28 - - PB15 I/O FT RTC_REFIN
TIM15_CH1N, TIM15_CH2
37 - - - PC6 I/O FT TIM3_CH1

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STM32F051x Pinouts and pin description

Table 13. Pin definitions (continued)

Pin number Pin functions

I/O structure
Pin type
Pin name
UFQFPN32
LQFP64

LQFP48

LQFP32

(function after Notes

reset) Alternate functions Additional functions

38 - - - PC7 I/O FT TIM3_CH2

39 - - - PC8 I/O FT TIM3_CH3
40 - - - PC9 I/O FT TIM3_CH4
USART1_CK, TIM1_CH1,
41 29 18 18 PA8 I/O FT
EVENTOUT, MCO
USART1_TX, TIM1_CH2,
42 30 19 19 PA9 I/O FT TIM15_BKIN,
TSC_G4_IO1
USART1_RX, TIM1_CH3,
43 31 20 20 PA10 I/O FT TIM17_BKIN,
TSC_G4_IO2
USART1_CTS, TIM1_CH4,
44 32 21 21 PA11 I/O FT COMP1_OUT,
TSC_G4_IO3, EVENTOUT
USART1_RTS, TIM1_ETR,
45 33 22 22 PA12 I/O FT COMP2_OUT,
TSC_G4_IO4, EVENTOUT
PA13 (4)
46 34 23 23 I/O FT IR_OUT, SWDAT
(SWDAT)
47 35 - - PF6 I/O FT I2C2_SCL
48 36 - - PF7 I/O FT I2C2_SDA
PA14 (4)
49 37 24 24 I/O FT USART2_TX, SWCLK
(SWCLK)
SPI1_NSS/I2S1_WS,
USART2_RX,
50 38 25 25 PA15 I/O FT
TIM2_CH1_ETR,
EVENTOUT
51 - - - PC10 I/O FT
52 - - - PC11 I/O FT
53 - - - PC12 I/O FT
54 - - - PD2 I/O FT TIM3_ETR
SPI1_SCK/I2S1_CK,
55 39 26 26 PB3 I/O FT TIM2_CH2, TSC_G5_IO1,
EVENTOUT
SPI1_MISO/I2S1_MCK,
56 40 27 27 PB4 I/O FT TIM3_CH1, TSC_G5_IO2,
EVENTOUT

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Pinouts and pin description STM32F051x

Table 13. Pin definitions (continued)

Pin number Pin functions

I/O structure
Pin type
Pin name
UFQFPN32
LQFP64

LQFP48

LQFP32

(function after Notes

reset) Alternate functions Additional functions

SPI1_MOSI/I2S1_SD,
57 41 28 28 PB5 I/O FT I2C1_SMBA, TIM16_BKIN,
TIM3_CH2
I2C1_SCL, USART1_TX,
58 42 29 29 PB6 I/O FTf TIM16_CH1N,
TSC_G5_IO3
I2C1_SDA, USART1_RX,
59 43 30 30 PB7 I/O FTf TIM17_CH1N,
TSC_G5_IO4
60 44 31 31 BOOT0 I B Boot memory selection

(3) I2C1_SCL, CEC,

61 45 - 32 PB8 I/O FTf
TIM16_CH1, TSC_SYNC
I2C1_SDA, IR_OUT,
62 46 - - PB9 I/O FTf
TIM17_CH1, EVENTOUT
63 47 32 0 VSS S Ground
64 48 1 1 VDD S Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as a current sources (e.g. to drive an LED).
2. After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the reference manual.
3. On LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not available on the
package, they are not forced to a defined level by hardware).
4. After reset, these pins are configured as SWDAT and SWCLK alternate functions, and the internal pull-up on SWDAT pin
and internal pull-down on SWCLK pin are activated.

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 STM32F051x
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

TIM2_CH1_
PA0 USART2_CTS TSC_G1_IO1 COMP1_OUT
ETR
PA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2
PA2 TIM15_CH1 USART2_TX TIM2_CH3 TSC_G1_IO3 COMP2_OUT
PA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_IO4
SPI1_NSS/
PA4 USART2_CK TSC_G2_IO1 TIM14_CH1
I2S1_WS
SPI1_SCK/ TIM2_CH1_
PA5 CEC TSC_G2_IO2
I2S1_CK ETR
Doc ID 022265 Rev 3

SPI1_MISO/
PA6 TIM3_CH1 TIM1_BKIN TSC_G2_IO3 TIM16_CH1 EVENTOUT COMP1_OUT
I2S1_MCK
SPI1_MOSI/
PA7 TIM3_CH2 TIM1_CH1N TSC_G2_IO4 TIM14_CH1 TIM17_CH1 EVENTOUT COMP2_OUT
I2S1_SD
PA8 MCO USART1_CK TIM1_CH1 EVENTOUT
PA9 TIM15_BKIN USART1_TX TIM1_CH2 TSC_G4_IO1
PA10 TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2
PA11 EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3 COMP1_OUT
PA12 EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4 COMP2_OUT

Pinouts and pin description

PA13 SWDAT IR_OUT
PA14 SWCLK USART2_TX
SPI1_NSS/ TIM2_CH1_
PA15 USART2_RX EVENTOUT
I2S1_WS ETR
33/105
34/105

Pinouts and pin description

Table 15. Alternate functions selected through GPIOA_AFR registers for port B
Pin name AF0 AF1 AF2 AF3

PB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3
PB2 TSC_G3_IO4
PB3 SPI1_SCK / I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1
PB4 SPI1_MISO / I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2
PB5 SPI1_MOSI / I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA
PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3
PB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4
PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC
Doc ID 022265 Rev 3

PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT

PB10 CEC I2C2_SCL TIM2_CH3 TSC_SYNC
PB11 EVENTOUT I2C2_SDA TIM2_CH4 TSC_G6_IO1
PB12 SPI2_NSS EVENTOUT TIM1_BKIN TSC_G6_IO2
PB13 SPI2_SCK TIM1_CH1N TSC_G6_IO3
PB14 SPI2_MISO TIM15_CH1 TIM1_CH2N TSC_G6_IO4
PB15 SPI2_MOSI TIM15_CH2 TIM1_CH3N TIM15_CH1N

STM32F051x
STM32F051x Memory mapping

5 Memory mapping

Figure 7. STM32F051x memory map

X&&&&&&&&

X&&
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X%
#ORTEX -)NTERNAL
X% 0ERIPHERALS

RESERVED


X#

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RESERVED
X!

X

 X&&&&&&& "1#
RESERVED
X&&&&#
X
/PTION"YTES
X X&&&&

RESERVED
3YSTEMMEMORY
X
 X&&&%#

"1#

X
X

RESERVED


X 0ERIPHERALS

X


&LASHMEMORY

X 32!-
Y


RESERVED
#/$%
 X

'MBTI
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X PS
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X

2ESERVED

-36

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Memory mapping STM32F051x

Table 16. STM32F051x peripheral register boundary addresses

Bus Boundary address Size Peripheral

0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved

0x4800 1400 - 0x4800 17FF 1KB GPIOF
0x4800 1000 - 0x4800 13FF 1KB Reserved
0x4800 0C00 - 0x4800 0FFF 1KB GPIOD
AHB2
0x4800 0800 - 0x4800 0BFF 1KB GPIOC
0x4800 0400 - 0x4800 07FF 1KB GPIOB
0x4800 0000 - 0x4800 03FF 1KB GPIOA
0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
0x4002 4000 - 0x4002 43FF 1KB TSC
0x4002 3400 - 0x4002 3FFF 3KB Reserved
0x4002 3000 - 0x4002 33FF 1KB CRC
0x4002 2400 - 0x4002 2FFF 3KB Reserved
AHB1 0x4002 2000 - 0x4002 23FF 1KB FLASH Interface
0x4002 1400 - 0x4002 1FFF 3KB Reserved
0x4002 1000 - 0x4002 13FF 1KB RCC
0x4002 0400 - 0x4002 0FFF 3KB Reserved
0x4002 0000 - 0x4002 03FF 1KB DMA
0x4001 8000 - 0x4001 FFFF 32KB Reserved
0x4001 5C00 - 0x4001 7FFF 9KB Reserved
0x4001 5800 - 0x4001 5BFF 1KB DBGMCU
0x4001 4C00 - 0x4001 57FF 3KB Reserved
0x4001 4800 - 0x4001 4BFF 1KB TIM17
0x4001 4400 - 0x4001 47FF 1KB TIM16
0x4001 4000 - 0x4001 43FF 1KB TIM15
0x4001 3C00 - 0x4001 3FFF 1KB Reserved
0x4001 3800 - 0x4001 3BFF 1KB USART1
APB
0x4001 3400 - 0x4001 37FF 1KB Reserved
0x4001 3000 - 0x4001 33FF 1KB SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF 1KB TIM1
0x4001 2800 - 0x4001 2BFF 1KB Reserved
0x4001 2400 - 0x4001 27FF 1KB ADC
0x4001 0800 - 0x4001 23FF 7KB Reserved
0x4001 0400 - 0x4001 07FF 1KB EXTI
0x4001 0000 - 0x4001 03FF 1KB SYSCFG + COMP
0x4000 8000 - 0x4000 FFFF 32KB Reserved

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STM32F051x Memory mapping

Table 16. STM32F051x peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral

0x4000 7C00 - 0x4000 7FFF 1KB Reserved

0x4000 7800 - 0x4000 7BFF 1KB CEC
0x4000 7400 - 0x4000 77FF 1KB DAC
0x4000 7000 - 0x4000 73FF 1KB PWR
0x4000 5C00 - 0x4000 6FFF 5KB Reserved
0x4000 5800 - 0x4000 5BFF 1KB I2C2
0x4000 5400 - 0x4000 57FF 1KB I2C1
0x4000 4800 - 0x4000 53FF 3 KB Reserved
0x4000 4400 - 0x4000 47FF 1KB USART2
0x4000 3C00 - 0x4000 43FF 2KB Reserved
0x4000 3800 - 0x4000 3BFF 1KB SPI2
APB
0x4000 3400 - 0x4000 37FF 1KB Reserved
0x4000 3000 - 0x4000 33FF 1KB IWDG
0x4000 2C00 - 0x4000 2FFF 1KB WWDG
0x4000 2800 - 0x4000 2BFF 1KB RTC
0x4000 2400 - 0x4000 27FF 1KB Reserved
0x4000 2000 - 0x4000 23FF 1KB TIM14
0x4000 1400 - 0x4000 1FFF 3KB Reserved
0x4000 1000 - 0x4000 13FF 1KB TIM6
0x4000 0800 - 0x4000 0FFF 2KB Reserved
0x4000 0400 - 0x4000 07FF 1KB TIM3
0x4000 0000 - 0x4000 03FF 1KB TIM2

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STM32F051x Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Figure 8. Pin loading conditions Figure 9. Pin input voltage

-#5PIN -#5PIN

C = 50 pF 6).

-36 -36

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Electrical characteristics STM32F051x

6.1.6 Power supply scheme

Figure 10. Power supply scheme

6"!4

"ACKUPCIRCUITRY
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6$$!

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62%& 2#S0,,
—& 
633!

-36

Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc..) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.

6.1.7 Current consumption measurement

Figure 11. Current consumption measurement scheme

*
%%@7#"5
6"!4

)$$
6$$

)$$!
6$$!

-36

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STM32F051x Electrical characteristics

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics,
Table 18: Current characteristics, and Table 19: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Table 17. Voltage characteristics(1)

Symbol Ratings Min Max Unit

External main supply voltage

VDD–VSS –0.3 4.0 V
(including VDDA and VDD)
Allowed voltage difference for VDD
VDD–VDDA - 0.4 V
> VDDA
Input voltage on FT and FTf pins VSS − 0.3 VDD + 4.0 V
VIN(2) Input voltage on TTa pins VSS − 0.3 4.0 V
Input voltage on any other pin VSS − 0.3 4.0 V
Variations between different VDD
|ΔVDDx| - 50 mV
power pins
Variations between all the different
|VSSX − VSS| - 50 mV
ground pins
Electrostatic discharge voltage see Section 6.3.11: Electrical
VESD(HBM)
(human body model) sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 18: Current characteristics for the maximum
allowed injected current values.

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Electrical characteristics STM32F051x

Table 18. Current characteristics

Symbol Ratings Max. Unit

IVDD Total current into VDD power lines (source)(1) 100

(1)
IVSS Total current out of VSS ground lines (sink) 100
Output current sunk by any I/O and control pin 25
IIO
Output current source by any I/Os and control pin − 25
Injected current on FT, FTf and B pins -5(2) mA

IINJ(PIN) Injected current on TC and RST pin ± 5(3)

Injected current on TTa pins ± 5(4)
Total injected current (sum of all I/O and control
ΣIINJ(PIN) ± 25
pins)(5)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
3. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN <VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 17: Voltage characteristics for the maximum allowed input voltage
values.
4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 17: Voltage characteristics for the maximum allowed input voltage
values. Negative injection disturbs the analog performance of the device. See note 2 below Table 56 on
page 78.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

Table 19. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C

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STM32F051x Electrical characteristics

6.3 Operating conditions

6.3.1 General operating conditions

Table 20. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency 0 48

MHz
fPCLK Internal APB clock frequency 0 48
VDD Standard operating voltage 2 3.6 V
Analog operating voltage
2 3.6
(ADC and DAC not used) Must have a potential equal
VDDA (1) V
Analog operating voltage to or higher than VDD
2.4 3.6
(ADC and DAC used)
VBAT Backup operating voltage 1.65 3.6 V
LQFP64 - 444
Power dissipation at TA = LQFP48 - 364
PD 85 °C for suffix 6 or TA = mW
105 °C for suffix 7(2) LQFP32 - 357
UFQFPN32 - 526

Ambient temperature for 6 Maximum power dissipation –40 85

°C
suffix version Low power dissipation(3) –40 105
TA
Ambient temperature for 7 Maximum power dissipation –40 105
°C
suffix version Low power dissipation (3)
–40 125
6 suffix version –40 105
TJ Junction temperature range °C
7 suffix version –40 125
1. When the ADC is used, refer to Table 54: ADC characteristics.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 19: Thermal
characteristics).
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 19: Thermal characteristics).

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Electrical characteristics STM32F051x

6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 21 are derived from tests performed under the ambient
temperature condition summarized in Table 20.

Table 21. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate 0 ∞

tVDD
VDD fall time rate 20 ∞
µs/V
VDDA rise time rate 0 ∞
tVDDA
VDDA fall time rate 20 ∞

6.3.3 Embedded reset and power control block characteristics

The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 20.

Table 22. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

Power on/power down Falling edge 1.8(2) 1.88 1.96 V

VPOR/PDR(1)
reset threshold Rising edge 1.84 1.92 2.0 V
(1)
VPDRhyst PDR hysteresis - 40 - mV
tRSTTEMPO(3) Reset temporization 1.5 2.5 4.5 ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production.

Table 23. Programmable voltage detector characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Rising edge 2.1 2.18 2.26 V

VPVD0 PVD threshold 0
Falling edge 2 2.08 2.16 V
Rising edge 2.19 2.28 2.37 V
VPVD1 PVD threshold 1
Falling edge 2.09 2.18 2.27 V
Rising edge 2.28 2.38 2.48 V
VPVD2 PVD threshold 2
Falling edge 2.18 2.28 2.38 V
Rising edge 2.38 2.48 2.58 V
VPVD3 PVD threshold 3
Falling edge 2.28 2.38 2.48 V
Rising edge 2.47 2.58 2.69 V
VPVD4 PVD threshold 4
Falling edge 2.37 2.48 2.59 V

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STM32F051x Electrical characteristics

Table 23. Programmable voltage detector characteristics (continued)

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Rising edge 2.57 2.68 2.79 V

VPVD5 PVD threshold 5
Falling edge 2.47 2.58 2.69 V
Rising edge 2.66 2.78 2.9 V
VPVD6 PVD threshold 6
Falling edge 2.56 2.68 2.8 V
Rising edge 2.76 2.88 3 V
VPVD7 PVD threshold 7
Falling edge 2.66 2.78 2.9 V
VPVDhyst(2) PVD hysteresis - 100 - mV
IDD(PVD) PVD current consumption - 0.15 0.26 µA
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.

6.3.4 Embedded reference voltage

The parameters given in Table 24 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 20.

Table 24. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

–40 °C < TA < +105 °C 1.16 1.2 1.25 V

VREFINT Internal reference voltage
–40 °C < TA < +85 °C 1.16 1.2 1.24(1) V
ADC sampling time when
TS_vrefint(2) reading the internal - 5.1 17.1(3) µs
reference voltage
Internal reference voltage
VRERINT spread over the VDD = 3 V ±10 mV - - 10(3) mV
temperature range

TCoeff Temperature coefficient - - 100(3) ppm/°C

1. Data based on characterization results, not tested in production.

2. Shortest sampling time can be determined in the application by multiple iterations.
3. Guaranteed by design, not tested in production.

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.

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Electrical characteristics STM32F051x

Typical and maximum current consumption

The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at VDD or VSS (no load)
● All peripherals are disabled except when explicitly mentioned
● The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz and 1 wait state above 24 MHz)
● Prefetch is ON when the peripherals are enabled, otherwise it is OFF (to enable
prefetch the PRFTBE bit in the FLASH_ACR register must be set before clock setting
and bus prescaling)
● When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 25 to Table 29 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 20.

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STM32F051x Electrical characteristics

Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6 V
All peripherals enabled All peripherals disabled

Symbol Parameter Conditions fHCLK Max @ TA(1) Max @ TA(1) Unit

Typ Typ
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

48 MHz 22 22.8 22.8 23.8 11.8 12.7 12.7 13.3

HSE
bypass, 32 MHz 15 15.5 15.5 16.0 7.6 8.7 8.7 9.0
PLL on
24 MHz 12.2 13.2 13.2 13.6 7.2 7.9 7.9 8.1
Supply HSE 8 MHz 4.4 5.2 5.2 5.4 2.7 2.9 2.9 3.0
current in bypass,
Run mode, PLL off 1 MHz 1 1.3 1.3 1.4 0.7 0.9 0.9 0.9
code
executing 48 MHz 22 22.8 22.8 23.8 11.8 12.7 12.7 13.3
from Flash HSI clock,
32 MHz 15 15.5 15.5 16.0 7.6 8.7 8.7 9.0
PLL on
24 MHz 12.2 13.2 13.2 13.6 7.2 7.9 7.9 8.1
HSI clock,
8 MHz 4.4 5.2 5.2 5.4 2.7 2.9 2.9 3.0
PLL off
48 MHz 22.2 23.2(2) 23.2 24.4(2) 12.0 12.7(2) 12.7 13.3(2)
HSE
bypass, 32 MHz 15.4 16.3 16.3 16.8 7.8 8.7 8.7 9.0
PLL on
24 MHz 11.2 12.2 12.2 12.8 6.2 7.9 7.9 8.1
Supply HSE 8 MHz 4.0 4.5 4.5 4.7 1.9 2.9 2.9 3.0
current in bypass,
Run mode, PLL off 1 MHz 0.6 0.8 0.8 0.9 0.3 0.6 0.6 0.7
IDD mA
code
executing 48 MHz 22.2 23.2 23.2 24.4 12.0 12.7 12.7 13.3
from RAM HSI clock,
32 MHz 15.4 16.3 16.3 16.8 7.8 8.7 8.7 9.0
PLL on
24 MHz 11.2 12.2 12.2 12.8 6.2 7.9 7.9 8.1
HSI clock,
8 MHz 4.0 4.5 4.5 4.7 1.9 2.9 2.9 3.0
PLL off
48 MHz 14 15.3(2) 15.3 16.0(2) 2.8 3.0(2) 3.0 3.2(2)
HSE
bypass, 32 MHz 9.5 10.2 10.2 10.7 2.0 2.1 2.1 2.3
PLL on
Supply 24 MHz 7.3 7.8 7.8 8.3 1.5 1.7 1.7 1.9
current in HSE 8 MHz 2.6 2.9 2.9 3.0 0.6 0.8 0.8 0.8
Sleep bypass,
mode, PLL off 1 MHz 0.4 0.6 0.6 0.6 0.2 0.4 0.4 0.4
code
executing 48 MHz 14 15.3 15.3 16.0 3.8 4.0 4.1 4.2
from Flash HSI clock,
32 MHz 9.5 10.2 10.2 10.7 2.6 2.7 2.8 2.8
or RAM PLL on
24 MHz 7.3 7.8 7.8 8.3 2.0 2.1 2.1 2.1
HSI clock,
8 MHz 2.6 2.9 2.9 3.0 0.6 0.8 0.8 0.8
PLL off
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production with code executing from RAM.

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Electrical characteristics STM32F051x

Table 26. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V VDDA = 3.6 V
Conditions
Symbol Parameter (1) fHCLK Max @ TA(2) Max @ TA(2) Unit
Typ Typ
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

48 MHz 150 170 178 182 164 183 195 198

HSE
bypass, 32 MHz 104 121 126 128 113 129 135 138
PLL on
24 MHz 82 96 100 103 88 102 106 108
Supply
current in HSE 8 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
Run mode, bypass,
PLL off 1 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
code
executing 48 MHz 220 240 248 252 244 263 275 278
from Flash HSI clock,
or RAM 32 MHz 174 191 196 198 193 209 215 218
PLL on
24 MHz 152 167 173 174 168 183 190 192
HSI clock,
8 MHz 72 79 82 83 83.5 91 94 95
PLL off
IDDA µA
48 MHz 150 170 178 182 164 183 195 198
HSE
bypass, 32 MHz 104 121 126 128 113 129 135 138
PLL on
Supply 24 MHz 82 96 100 103 88 102 106 108
current in HSE 8 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
Sleep bypass,
mode, PLL off 1 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
code
executing 48 MHz 220 240 248 252 244 263 275 278
from Flash HSI clock,
32 MHz 174 191 196 198 193 209 215 218
or RAM PLL on
24 MHz 152 167 173 174 168 183 190 192
HSI clock,
8 MHz 72 79 82 83 83.5 91 94 95
PLL off
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.

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STM32F051x Electrical characteristics

Table 27. Typical and maximum VDD consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA) Max(1)
Symbol Parameter Conditions Unit
TA = TA = TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 °C 85 °C 105 °C

Regulator in run mode,

15 15.1 15.25 15.45 15.7 16 22(2) 48 64(2)
Supply all oscillators OFF
current in Regulator in low-power
Stop mode mode, all oscillators 3.15 3.25 3.35 3.45 3.7 4 7(2) 32 45(2)
IDD OFF µA
Supply LSI ON and IWDG ON 0.8 0.95 1.05 1.2 1.35 1.5 - - -
current in
Standby LSI OFF and IWDG
0.65 0.75 0.85 0.95 1.1 1.3 2(2) 2.5 3(2)
mode OFF

1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production.

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Electrical characteristics STM32F051x

Table 28. Typical and maximum VDDA consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA) Max(1)
Symbol Parameter Conditions Unit
TA = TA = TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 °C 85 °C 105 °C

Regulator in run mode,

Supply 1.85 2 2.15 2.3 2.45 2.6 3.5 3.5 4.5
all oscillators OFF
VDDA monitoring ON

current in
Stop mode Regulator in low-power
mode, all oscillators 1.85 2 2.15 2.3 2.45 2.6 3.5 3.5 4.5
OFF
Supply LSI ON and IWDG ON 2.25 2.5 2.65 2.85 3.05 3.3 - - -
current in
Standby LSI OFF and IWDG
1.75 1.9 2 2.15 2.3 2.5 3.5 3.5 4.5
mode OFF
IDDA µA
Regulator in run mode,
1.11 1.15 1.18 1.22 1.27 1.35 - - -
VDDA monitoring OFF

Supply all oscillators OFF

current in Regulator in low-power
Stop mode mode, all oscillators 1.11 1.15 1.18 1.22 1.27 1.35 - - -
OFF
Supply LSI ON and IWDG ON 1.5 1.58 1.65 1.78 1.91 2.04 - - -
current in
Standby LSI OFF and IWDG
1 1.02 1.05 1.05 1.15 1.22 - - -
mode OFF

1. Data based on characterization results, not tested in production.

Table 29. Typical and maximum current consumption from VBAT supply
Typ @ VBAT Max(1)
= 1.65 V

= 2.7 V

Symbol Parameter Conditions Unit

= 1.8 V

= 2.4 V

= 3.3 V

= 3.6 V

TA = TA = TA =
25 °C 85 °C 105 °C

LSE & RTC ON; "Xtal

mode": lower driving
0.41 0.43 0.53 0.58 0.71 0.80 0.85 1.1 1.5
Backup capability;
domain LSEDRV[1:0] = '00'
IDD_VBAT µA
supply LSE & RTC ON; "Xtal
current mode" higher driving
0.71 0.75 0.85 0.91 1.06 1.16 1.25 1.55 2
capability;
LSEDRV[1:0] = '11'
1. Data based on characterization results, not tested in production.

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Typical current consumption

The MCU is placed under the following conditions:
● VDD=VDDA=3.3 V
● All I/O pins are in analog input configuration
● The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state above)
● Prefetch is ON when the peripherals are enabled, otherwise it is OFF
● When the peripherals are enabled, fPCLK = fHCLK
● PLL is used for frequencies greater than 8 MHz
● AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
● A development tool is connected to the board and the parasitic pull-up current is around
30 µA

Table 30. Typical current consumption in Run mode, code with data processing
running from Flash
Typ
Symbol Parameter Conditions fHCLK Peripherals Peripherals Unit
enabled disabled
48 MHz 23.3 11.5
36 MHz 17.6 9.0
32 MHz 15.9 8.0
24 MHz 12.4 7.5
Supply current in Run 16 MHz 8.5 5.2
IDD mode from VDD mA
supply 8 MHz 4.5 3.0
4 MHz 2.8 1.9
2 MHz 1.7 1.3
Running from 1 MHz 1.3 1.0
HSE crystal
clock 8 MHz, 500 kHz 1.0 0.9
code 48 MHz 158 158
executing
from Flash 36 MHz 120 120
32 MHz 108 108
24 MHz 83 83
Supply current in Run 16 MHz 60 60
IDDA mode from VDDA µA
supply 8 MHz 2.43 2.43
4 MHz 2.43 2.43
2 MHz 2.43 2.43
1 MHz 2.43 2.43
500 kHz 2.43 2.43

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Table 31. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ
Symbol Parameter Conditions fHCLK Peripherals Peripherals Unit
enabled disabled
48 MHz 13.9 2.98
36 MHz 10.55 2.84
32 MHz 9.6 2.6
24 MHz 7.23 2.09

Supply current in 16 MHz 5.01 1.58

IDD Sleep mode from VDD 8 MHz 2.68 0.99 mA
supply 4 MHz 1.81 0.85
2 MHz 1.27 0.77
1 MHz 1.03 0.73
Running from 500 kHz 0.9 0.71
HSE crystal
clock 8 MHz, 125 kHz 0.78 0.69
code executing 48 MHz 158 157
from Flash or
RAM 36 MHz 119 119
32 MHz 108 107
24 MHz 83 83

Supply current in 16 MHz 60 60

IDDA Sleep mode from 8 MHz 2.36 2.38 µA
VDDA supply 4 MHz 2.36 2.38
2 MHz 2.36 2.38
1 MHz 2.36 2.38
500 kHz 2.36 2.38
125 kHz 2.36 2.38

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I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 33: Peripheral current consumption), the I/Os used by an application also contribute to
the current consumption. When an I/O pin switches, it uses the current from the MCU supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or
external) connected to the pin:

I SW = V DD × f SW × C

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

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Table 32. Switching output I/O current consumption

I/O toggling
Symbol Parameter Conditions(1) Typ Unit
frequency (fSW)

4 MHz 0.07

8 MHz 0.15
VDD = 3.3 V
C =CINT 16 MHz 0.31
24 MHz 0.53
48 MHz 0.92
4 MHz 0.18

VDD = 3.3 Volts 8 MHz 0.37

CEXT = 0 pF 16 MHz 0.76
C = CINT + CEXT+ CS 24 MHz 1.39
48 MHz 2.188
4 MHz 0.32

VDD = 3.3 Volts 8 MHz 0.64

CEXT = 10 pF 16 MHz 1.25
C = CINT + CEXT+ CS 24 MHz 2.23

I/O current 48 MHz 4.442

ISW mA
consumption
4 MHz 0.49
VDD = 3.3 Volts 8 MHz 0.94
CEXT = 22 pF
C = CINT + CEXT+ CS 16 MHz 2.38
24 MHz 3.99
4 MHz 0.64
VDD = 3.3 Volts
8 MHz 1.25
CEXT = 33 pF
16 MHz 3.24
C = CINT + CEXT+ CS
24 MHz 5.02
VDD = 3.3 Volts 4 MHz 0.81
CEXT = 47 pF 8 MHz 1.7
C = CINT + CEXT+ CS
C = Cint 16 MHz 3.67

4 MHz 0.66
VDD = 2.4 Volts
CEXT = 47 pF 8 MHz 1.43
C = CINT + CEXT+ CS 16 MHz 2.45
C = Cint
24 MHz 4.97
1. CS = 7 pF (estimated value).

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On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 33. The MCU is placed
under the following conditions:
● all I/O pins are in input mode with a static value at VDD or VSS (no load)
● all peripherals are disabled unless otherwise mentioned
● the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
● ambient operating temperature and VDD supply voltage conditions summarized in
Table 17

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Table 33. Peripheral current consumption

Typical consumption at 25 °C
Peripheral Unit
IDD IDDA

ADC(1) 0.53 0.964

CEC 0.24 -
CRC 0.10 -
DAC(2) 0.27 0.408
DBGMCU 0.18 -
DMA 0.35 -
GPIOA 0.48 -
GPIOB 0.58 -
GPIOC 0.12 -
GPIOD 0.04 -
GPIOF 0.06 -
I2C1 0.43 -
I2C2 0.42 -
PWR 0.22 -
SPI1/I2S1 0.63 - mA
SPI2 0.53 -
SYSCFG & COMP 0.28 See note (3)

TIM1 1.01 -
TIM2 1.00 -
TIM3 0.78 -
TIM6 0.32 -
TIM14 0.45 -
TIM15 0.66 -
TIM16 0.57 -
TIM17 0.59 -
TSC 0.28 -
USART1 1.07 -
USART2 0.48 -
WWDG 0.22 -
1. ADC is in ready state after setting the ADEN bit in the ADC_CR register (ADRDY bit in ADC_ISR is high).
2. DAC channel 1 enabled by setting EN1 bit in DAC_CR.
3. COMP IDDA is specified as IDD(COMP) in Table 58: Comparator characteristics

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6.3.6 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 12.

Table 34. High-speed external user clock characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit

User external clock source

fHSE_ext 1 8 32 MHz
frequency
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
tw(HSEH)
OSC_IN high or low time 15 - -
tw(HSEL)
ns
tr(HSE)
OSC_IN rise or fall time - - 20
tf(HSE)
1. Guaranteed by design, not tested in production.

Figure 12. High-speed external clock source AC timing diagram

T7(3%(

6(3%(


6(3%,

TR(3% T
TF(3% T7(3%,
4(3%

-36

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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 13.

Table 35. Low-speed external user clock characteristics

Symbol Parameter(1) Conditions Min Typ Max Unit

User External clock source

fLSE_ext - 32.768 1000 kHz
frequency
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage
V
OSC32_IN input pin low level
VLSEL VSS - 0.3VDD
voltage
tw(LSEH)
OSC32_IN high or low time 450 - -
tw(LSEL)
ns
tr(LSE)
OSC32_IN rise or fall time - - 50
tf(LSE)
1. Guaranteed by design, not tested in production.

Figure 13. Low-speed external clock source AC timing diagram

T7,3%(

6,3%(


6,3%,

TR,3% T
TF,3% T7,3%,
4,3%

-36

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 36. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 36. HSE oscillator characteristics

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit

fOSC_IN Oscillator frequency 4 8 32 MHz

RF Feedback resistor - 200 - kΩ
(3)
During startup - 8.5
VDD=3.3 V, Rm= 30Ω,
- 0.4 -
CL=10 pF@8 MHz
VDD=3.3 V, Rm= 45Ω,
- 0.5 -
CL=10 pF@8 MHz
IDD HSE current consumption VDD=3.3 V, Rm= 30Ω, mA
- 0.8 -
CL=5 pF@32 MHz
VDD=3.3 V, Rm= 30Ω,
- 1 -
CL=10 pF@32 MHz
VDD=3.3 V, Rm= 30Ω,
- 1.5 -
CL=20 pF@32 MHz
gm Oscillator transconductance Startup 10 - - mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 14). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

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Electrical characteristics STM32F051x

Figure 14. Typical application with an 8 MHz crystal

2ESONATORWITH
INTEGRATEDCAPACITORS
#,
/3#?). F(3%
"IAS
-( Z
CONTROLLED
2&
RESONATOR GAIN
/3#?/5 4
2%84
#,

-36

1. REXT value depends on the crystal characteristics.

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Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 37. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz)

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit

LSEDRV[1:0]=00
- 0.5 0.9
lower driving capability
LSEDRV[1:0]= 01
- - 1
medium low driving capability
IDD LSE current consumption µA
LSEDRV[1:0] = 10
- - 1.3
medium high driving capability
LSEDRV[1:0]=11
- - 1.6
higher driving capability
LSEDRV[1:0]=00
5 - -
lower driving capability
LSEDRV[1:0]= 01
8 - -
Oscillator medium low driving capability
gm µA/V
transconductance LSEDRV[1:0] = 10
15 - -
medium high driving capability
LSEDRV[1:0]=11
25 - -
higher driving capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

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Electrical characteristics STM32F051x

Figure 15. Typical application with a 32.768 kHz crystal

2ESONATORWITH
INTEGRATEDCAPACITORS
#,
/3#?). F,3%
$RIVE
K( Z PROGRAMMABLE
RESONATOR AMPLIFIER

/3#?/5 4
#,

-3

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

6.3.7 Internal clock source characteristics

The parameters given in Table 38 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20.

High-speed internal (HSI) RC oscillator

Table 38. HSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency - 8 MHz

TRIM HSI user trimming step - - 1(2) %
DuCy(HSI) Duty cycle 45(2) - 55(2) %
TA = –40 to 105 °C –3.8(3) - 4.6(3) %
Accuracy of the HSI TA = –10 to 85 °C –2.9(3) - 2.9(3) %
ACCHSI oscillator (factory
calibrated) TA = 0 to 70 °C –1.3(3) - 2.2(3) %
TA = 25 °C –1 - 1 %
HSI oscillator startup
tsu(HSI) 1(2) - 2(2) µs
time
HSI oscillator power
IDD(HSI) - 80 100(2) µA
consumption
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.

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High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

Table 39. HSI14 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI14 Frequency - 14 MHz

(2)
TRIM HSI14 user-trimming step - - 1 %
DuCy(HSI14) Duty cycle (2) (2)
45 - 55 %
TA = –40 to 105 °C –4.2 (3) (3)
- 5.1 %

Accuracy of the HSI14 TA = –10 to 85 °C –3.2(3) - 3.1(3) %

ACCHSI14
oscillator (factory calibrated) TA = 0 to 70 °C –1.3 (3)
- 2.2 (3)
%
TA = 25 °C –1 - 1 %
tsu(HSI14) HSI14 oscillator startup time 1(2) - 2(2) µs
HSI14 oscillator power
IDD(HSI14) - 100 150(2) µA
consumption
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.

Low-speed internal (LSI) RC oscillator

Table 40. LSI oscillator characteristics(1)

Symbol Parameter Min Typ Max Unit

fLSI Frequency 30 40 50 kHz

tsu(LSI)(2) LSI oscillator startup time - - 85 µs
IDD(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.

Wakeup time from low-power mode

The wakeup times given in Table 41 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The event used to wake up the device depends from the current operating mode:
● Stop or sleep mode: the wakeup event is WFE
● The wakeup pin used in stop and sleep mode is PA0 and in standby mode is the PA1.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 20.

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Table 41. Low-power mode wakeup timings

Typ @VDD
Symbol Parameter Conditions Max Unit
= 2.0 V = 2.4 V = 2.7 V =3V = 3.3 V

Regulator in run
4.2 4.2 4.2 4.2 4.2 5
Wakeup from Stop mode
tWUSTOP
mode Regulator in low
8.05 7.05 6.6 6.27 6.05 9
power mode
µs
tWUSTANDBY Wakeup from 60.35 55.6 53.5 52.02 50.96
Standby mode
Wakeup from Sleep
tWUSLEEP 1.1 1.1 1.1 1.1 1.1
mode

6.3.8 PLL characteristics

The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20.

Table 42. PLL characteristics

Value
Symbol Parameter Unit
Min Typ Max

PLL input clock(1) 1(2) 8.0 24(2) MHz

fPLL_IN
(2)
PLL input clock duty cycle 40 - 60(2) %
fPLL_OUT PLL multiplier output clock 16(2) - 48 MHz
tLOCK PLL lock time - - 200(2) µs
JitterPLL Cycle-to-cycle jitter - - 300(2) ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.

6.3.9 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

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Table 43. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

tprog 16-bit programming time TA = –40 to +105 °C 40 53.5 60 µs

tERASE Page (1 KB) erase time TA = –40 to +105 °C 20 - 40 ms
tME Mass erase time TA = –40 to +105 °C 20 - 40 ms
Write mode - - 10 mA
IDD Supply current
Erase mode - - 12 mA
Vprog Programming voltage 2 - 3.6 V
1. Guaranteed by design, not tested in production.

Table 44. Flash memory endurance and data retention

Value
Symbol Parameter Conditions Unit
Min(1)

TA = –40 to +85 °C (6 suffix versions)

NEND Endurance 10 kcycles
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C 30
tRET Data retention 1 kcycle(2) at TA = 105 °C 10 Years
(2)
10 kcycles at TA = 55 °C 20
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.

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6.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.

Table 45. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, LQFP64, TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK = 48 MHz 2B
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, LQFP64, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 48 MHz 3B
pins to induce a functional disturbance conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
● Corrupted program counter
● Unexpected reset
● Critical Data corruption (control registers...)

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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.

Table 46. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
Symbol Parameter Conditions Unit
frequency band
8/48 MHz

0.1 to 30 MHz -3
VDD = 3.6 V, TA = 25 °C,
LQFP64 package 30 to 130 MHz 28 dBµV
SEMI Peak level
compliant with IEC 130 MHz to 1GHz 23
61967-2
SAE EMI Level 4 -

6.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Table 47. ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum value(1) Unit

Electrostatic discharge TA = +25 °C, conforming

VESD(HBM) 2 2000
voltage (human body model) to JESD22-A114
V
Electrostatic discharge TA = +25 °C, conforming
VESD(CDM) II 500
voltage (charge device model) to JESD22-C101
1. Data based on characterization results, not tested in production.

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Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin
● A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 48. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78A II level A

6.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of current injection on adjacent pins (lower than –5 µA
or lower than − 10 µA), or other functional failure (for example reset, oscillator frequency
deviation).
The characterization results are given in Table 49.

Table 49. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on BOOT0, PF0-OSC_IN

–0 NA
and PF1-OSC_OUT pins
Injected current on PA10, PA12, PB4, PB5,
PB10, PB15 and PD2 with current injection –5 NA
on adjacent pins > –5 µA and <–10 µA
mA
IINJ Injected current on other FT and FTf pins
with current injection on adjacent pins –5 NA
<–5 µA
Injected current on PA6 and PC0 pins –0 +5
Injected current on all other TTa pins –5 +5
Injected current on TC and RST pins –5 +5

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6.3.13 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 20. All I/Os are CMOS and TTL
compliant.

Table 50. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

Standard I/O input low

–0.3 - 0.3VDD+0.07
level voltage
TTa I/O input low level
–0.3 - 0.3VDD+0.07
voltage
VIL
FT and FTf(1) I/O input
–0.3 - 0.475VDD–0.2
low level voltage
BOOT0 input low level
0 - 0.3VDD–0.3
voltage
V
Standard I/O input high
0.445VDD+0.398 - VDD+0.3
level voltage
TTa I/O input high level
0.445VDD+0.398 - VDD+0.3
voltage
VIH
FT and FTf(1) I/O input
0.5VDD+0.2 - 5.5
high level voltage
BOOT0 input high level
0.2VDD+0.95 - 5.5
voltage
Standard I/O Schmitt
trigger voltage 200 - -
hysteresis(2)
TTa I/O Schmitt trigger
200 - -
voltage hysteresis(2)
Vhys FT and FTf I/O Schmitt mV
trigger voltage 100 - -
hysteresis(2)
BOOT0 input Schmitt
trigger voltage 300 - -
hysteresis(2)

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Table 50. I/O static characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

VSS ≤ VIN ≤ VDD

- - ±0.1
I/O TC, FT and FTf
VSS ≤ VIN ≤ VDD
2 V≤ VDD ≤ VDDA ≤ 3.6 V
- - ±0.1
I/O TTa used in digital
mode
VIN= 5 V
- - 10
I/O FT and FTf
(3)
Ilkg Input leakage current µA
VIN= 3.6 V,
2 V≤ VDD ≤ VIN
VDDA = 3.6 V - - 1
I/O TTa used in digital
mode
VSS ≤ VIN ≤ VDDA
2 V≤ VDD ≤ VDDA ≤ 3.6 V
- - ±0.2
I/O TTa used in analog
mode
Weak pull-up equivalent
RPU VIN = VSS 30 40 50 kΩ
resistor(4)
Weak pull-down
RPD VIN = VDD 30 40 50 kΩ
equivalent resistor(4)
CIO I/O pin capacitance - 5 - pF
1. To sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Data based on characterization, not tested in production.
3. Leakage could be higher than max. if negative current is injected on adjacent pins.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 16 and Figure 17 for standard I/Os, and
in Figure 18 and Figure 19 for 5 V tolerant I/Os.

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Figure 16. TC and TTa I/O input characteristics - CMOS port

VIL/VIH (V) V DD
= 0.7
nts V IHmin
ir eme
requ +0.3
98
ard
Ss tand 45V DD
CMO = 0.4
VIHmin 2.0 V IHmin

0.07
V DD+
= 0.3
1.3 V ILmax
Input range not
guaranteed
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
VDD (V)
2.0 2.7 3.0 3.3 3.6

MS30255V1

Figure 17. TC and TTa I/O input characteristics - TTL port

VIL/VIH (V)

98
+0.3
45V DD
TTL standard requirements VIHmin = 2 V
min
= 0.4
VIHmin 2.0 V IH

D+
0.07
x=
0.3V D
1.3 V ILma
Input range not
guaranteed

VILmax 0.8
0.7 TTL standard requirements VILmax = 0.8 V
VDD (V)
2.0 2.7 3.0 3.3 3.6

MS30256V1

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Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port

VIL/VIH (V)

0.2
V DD+
CMOS standard requirements VIH min= 0.7VDD = 0.5
2.0 V IHmin

-0.2
75V DD
Input range not = 0.4
1.0 V ILmax
guaranteed

CMOS standard requirements VILmax = 0.3VDD

0.5
VDD (V)
2.0 3.6

MS30257V1

Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port

VIL/VIH (V)

0.2
V DD+
TTL standard requirements VIHmin = 2 V = 0.5
2.0 V IHmin

Input range not -0.2

75V DD
guaranteed = 0.4
1.0 V ILmin

0.8
TTL standard requirements VILmax = 0.8 V

0.5
VDD (V)
2.0 2.7 3.6

MS30258V1

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 18).
● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 18).

Output voltage levels

Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 20. All I/Os are CMOS and TTL compliant (FT, TTa or TC unless otherwise specified).

Table 51. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O pin

VOL(1) CMOS port(2) - 0.4
when 8 pins are sunk at same time
IIO = +8 mA V
Output high level voltage for an I/O pin
VOH(3) 2.7 V < VDD < 3.6 V VDD–0.4 -
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
VOL (1) TTL port(2) - 0.4
when 8 pins are sunk at same time
IIO =+ 8mA V
Output high level voltage for an I/O pin
VOH (3) 2.7 V < VDD < 3.6 V 2.4 -
when 8 pins are sourced at same time
Output low level voltage for an I/O pin
VOL(1)(4) - 1.3
when 5 pins are sunk at same time IIO = +20 mA
V
Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V
VOH(3)(4) VDD–1.3 -
when 5 pins are sourced at same time
Output low level voltage for an I/O pin
VOL(1)(4) - 0.4
when 8 pins are sunk at same time IIO = +6 mA
V
Output high level voltage for an I/O pin 2 V < VDD < 2.7 V
VOH(3)(4) VDD–0.4 -
when 8 pins are sourced at same time
Output low level voltage for an FTf I/O IIO = +20 mA
VOLFM+ - 0.4 V
pin in FM+ mode 2.7 V < VDD < 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 18
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 18 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Data based on characterization results, not tested in production.

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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 20 and
Table 52, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 20.

Table 52. I/O AC characteristics(1)

OSPEEDRy
Symbol Parameter Conditions Min Max Unit
[1:0] value(1)

fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 2 MHz

Output high to low level
tf(IO)out - 125(3)
x0 fall time
CL = 50 pF, VDD = 2 V to 3.6 V ns
Output low to high level
tr(IO)out - 125(3)
rise time
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 10 MHz
Output high to low level
tf(IO)out - 25(3)
01 fall time
CL = 50 pF, VDD = 2 V to 3.6 V ns
Output low to high level
tr(IO)out - 25(3)
rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V - 50 MHz
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V - 30 MHz
CL = 50 pF, VDD = 2 V to 2.7 V - 20 MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
Output high to low level
11 tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
fall time
CL = 50 pF, VDD = 2 V to 2.7 V - 12(3)
ns
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
Output low to high level
tr(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
rise time
CL = 50 pF, VDD = 2 V to 2.7 V - 12(3)
fmax(IO)out Maximum frequency(2) TBD - TBD MHz
FM+ Output high to low level
tf(IO)out TBD - TBD
configuration fall time
(4) ns
Output low to high level
tr(IO)out TBD - TBD
rise time
Pulse width of external
tEXTIpw signals detected by the 10 - ns
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 20.
3. Guaranteed by design, not tested in production.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F05xxx reference manual RM0091 for a
description of FM+ I/O mode configuration.

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Figure 20. I/O AC characteristics definition

90% 10%
50% 50%
10% 90%

EXT ERNAL tr(I O)out tr(I O)out

OUTPUT
ON 50pF T

Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131

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6.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 50).
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 20.

Table 53. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST)(1) NRST Input low level voltage –0.3 - 0.8

V
VIH(NRST)(1) NRST Input high level voltage 2 - VDD+0.3
NRST Schmitt trigger voltage
Vhys(NRST) - 200 - mV
hysteresis
RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ
VF(NRST)(1) NRST Input filtered pulse - - 100 ns
VNF(NRST)(1) NRST Input not filtered pulse 300 - - ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).

Figure 21. Recommended NRST pin protection

6$$
%XTERNAL
RESETCIRCUIT
205 )NTERNAL2ESET
.234
&ILTER
—&

-36

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53. Otherwise the reset will not be taken into account by the device.

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6.3.15 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 54 are preliminary values derived
from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 20.
Note: It is recommended to perform a calibration after each power-up.

Table 54. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for

VDDA 2.4 - 3.6 V
ADC ON
fADC ADC clock frequency 0.6 - 14 MHz

fS(1) Sampling rate 0.05 - 1 MHz

fADC = 14 MHz - - 823 kHz

fTRIG(1) External trigger frequency
- - 17 1/fADC
VAIN Conversion voltage range 0 - VDDA V
See Equation 1 and
RAIN(1) External input impedance - - 50 kΩ
Table 55 for details

RADC(1) Sampling switch resistance - - 1 kΩ

Internal sample and hold

CADC(1) - - 8 pF
capacitor
fADC = 14 MHz 5.9 µs
tCAL(1) Calibration time
83 1/fADC
fADC = fPCLK/2 = 14 MHz 0.196 µs
fADC = fPCLK/2 5.5 1/fPCLK
tlatr(1) Trigger conversion latency fADC = fPCLK/4 = 12 MHz 0.219 µs
fADC = fPCLK/4 10.5 1/fPCLK
fADC = fHSI14 = 14 MHz 0.188 - 0.259 µs
ADC jitter on trigger
JitterADC fADC = fHSI14 - 1 - 1/fHSI14
conversion
fADC = 14 MHz 0.107 - 17.1 µs
tS(1) Sampling time
1.5 - 239.5 1/fADC
tSTAB(1) Power-up time 0 0 1 µs
fADC = 14 MHz 1 18 µs
Total conversion time
tCONV(1) 14 to 252 (tS for sampling +12.5 for
(including sampling time) 1/fADC
successive approximation)
1. Guaranteed by design, not tested in production.

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Electrical characteristics STM32F051x

Equation 1: RAIN max formula

TS
R AIN < -------------------------------------------------------------
N+2
- – R ADC
f ADC × C ADC × ln ( 2 )

The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 55. RAIN max for fADC = 14 MHz(1)

Ts (cycles) tS (µs) RAIN max (kΩ)

1.5 0.11 0.4

7.5 0.54 5.9
13.5 0.96 11.4
28.5 2.04 25.2
41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
1. Guaranteed by design, not tested in production.

Table 56. ADC accuracy(1)(2) (3)

Symbol Parameter Test conditions Typ Max(4) Unit

ET Total unadjusted error ±1.3 ±2

EO Offset error fPCLK = 48 MHz, ±1 ±1.5
fADC = 14 MHz, RAIN < 10 kΩ,
EG Gain error ±0.5 ±1.5 LSB
VDDA = 3 V to 3.6 V
ED Differential linearity error TA = 25 °C ±0.7 ±1
EL Integral linearity error ±0.8 ±1.5
ET Total unadjusted error ±3.3 ±4
EO Offset error fPCLK = 48 MHz, ±1.9 ±2.8
fADC = 14 MHz, RAIN < 10 kΩ,
EG Gain error ±2.8 ±3 LSB
VDDA = 2.7 V to 3.6 V
ED Differential linearity error TA = −40 to 105 °C ±0.7 ±1.3
EL Integral linearity error ±1.2 ±1.7
ET Total unadjusted error ±3.3 ±4
EO Offset error fPCLK = 48 MHz, ±1.9 ±2.8
fADC = 14 MHz, RAIN < 10 kΩ,
EG Gain error ±2.8 ±3 LSB
VDDA = 2.4 V to 3.6 V
ED Differential linearity error TA = 25 °C ±0.7 ±1.3
EL Integral linearity error ±1.2 ±1.7
1. ADC DC accuracy values are measured after internal calibration.

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2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not
affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.

Figure 22. ADC accuracy characteristics

VDDA
1 LSBIDEAL 

 EG
(1) Example of an actual transfer curve
4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1

0
1 2 3 4 5 6 7 4093 4094 4095 4096
VSSA VDDA -36

Figure 23. Typical connection diagram using the ADC

6$$!
Sample and hold ADC
VT converter
0.6 V
RAIN(1) RADC(1)
AINx 12-bit
converter
IL±1 μA
Cparasitic VT
VAIN 0.6 V
CADC(1)

-36

1. Refer to Table 54 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.

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6.3.16 DAC electrical specifications

Table 57. DAC characteristics

Symbol Parameter Min Typ Max Unit Comments

Analog supply voltage for

VDDA 2.4 - 3.6 V
DAC ON
RLOAD(1) Resistive load with buffer ON 5 - - kΩ Load is referred to ground
When the buffer is OFF, the Minimum
Impedance output with buffer resistive load between DAC_OUT
RO(1) - - 15 kΩ
OFF and VSS to have a 1% accuracy is
1.5 MΩ
Maximum capacitive load at
CLOAD(1) Capacitive load - - 50 pF DAC_OUT pin (when the buffer is
ON).
It gives the maximum output
DAC_OUT Lower DAC_OUT voltage excursion of the DAC.
0.2 - - V
min(1) with buffer ON
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VDDA = 3.6 V
DAC_OUT Higher DAC_OUT voltage and (0x155) and (0xEAB) at VDDA =
- - VDDA – 0.2 V
max(1) with buffer ON 2.4 V
DAC_OUT Lower DAC_OUT voltage
- 0.5 - mV
min(1) with buffer OFF It gives the maximum output
DAC_OUT Higher DAC_OUT voltage excursion of the DAC.
- - VDDA – 1LSB V
max(1) with buffer OFF
With no load, middle code (0x800) on
DAC DC current - - 380 µA
the input
IDDA consumption in quiescent
mode (Standby mode) With no load, worst code (0xF1C) on
- - 480 µA
the input

Given for the DAC in 10-bit

Differential non linearity - - ±0.5 LSB
configuration
DNL(2) Difference between two
consecutive code-1LSB) Given for the DAC in 12-bit
- - ±2 LSB
configuration
Integral non linearity Given for the DAC in 10-bit
- - ±1 LSB
(difference between configuration
measured value at Code i
INL(2)
and the value at Code i on a Given for the DAC in 12-bit
line drawn between Code 0 - - ±4 LSB
configuration
and last Code 1023)
Given for the DAC in 12-bit
- - ±10 mV
Offset error configuration
(difference between Given for the DAC in 10-bit at VDDA =
Offset(2) measured value at Code - - ±3 LSB
3.6 V
(0x800) and the ideal value =
VDDA/2) Given for the DAC in 12-bit at VDDA =
- - ±12 LSB
3.6 V
Gain Given for the DAC in 12bit
Gain error - - ±0.5 %
error(2) configuration

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Table 57. DAC characteristics (continued)

Symbol Parameter Min Typ Max Unit Comments

Settling time (full scale: for a

10-bit input code transition
(2) between the lowest and the
tSETTLING - 3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
highest input codes when
DAC_OUT reaches final
value ±1LSB
Max frequency for a correct
Update DAC_OUT change when
- - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
rate(2) small variation in the input
code (from code i to i+1LSB)
Wakeup time from off state CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
tWAKEUP(2) (Setting the ENx bit in the - 6.5 10 µs input code between lowest and
DAC Control register) highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC - –67 –40 dB No RLOAD, CLOAD = 50 pF
measurement
1. Guaranteed by design, not tested in production.
2. Data based on characterization results, not tested in production.

Figure 24. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)
R LOAD
12-bit DACx_OUT
digital to
analog
converter

C LOAD

ai17157

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.

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6.3.17 Comparator characteristics

Table 58. Comparator characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

VDDA Analog supply voltage 2 - 3.6

Comparator input
VIN 0 - VDDA V
voltage range
VBG Scaler input voltage - 1.2
VSC Scaler offset voltage - ±5 ±10 mV
Scaler startup time
tS_SC - - 0.1 ms
from power down
Comparator startup Startup time to reach propagation delay
tSTART - - 60 µs
time specification
Ultra-low power mode - 2 4.5
Low power mode - 0.7 1.5 µs
Propagation delay for
200 mV step with 100 Medium power mode - 0.3 0.6
mV overdrive
VDDA ≥ 2.7 V - 50 100
High speed power mode ns
VDDA < 2.7 V - 100 240
tD
Ultra-low power mode - 2 7
Low power mode - 0.7 2.1 µs
Propagation delay for
full range step with 100 Medium power mode - 0.3 1.2
mV overdrive
VDDA ≥ 2.7 V - 90 180
High speed power mode ns
VDDA < 2.7 V - 110 300
Voffset Comparator offset error - ±4 ±10 mV
Offset error
dVoffset/dT - 18 - µV/°C
temperature coefficient
Ultra-low power mode - 1.2 1.5

COMP current Low power mode - 3 5

IDD(COMP) µA
consumption Medium power mode - 10 15
High speed power mode - 75 100

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Table 58. Comparator characteristics (continued)

Symbol Parameter Conditions Min Typ Max(1) Unit

No hysteresis
- 0 -
(COMPxHYST[1:0]=00)
High speed power
3 13
Low hysteresis mode
8
(COMPxHYST[1:0]=01) All other power
5 10
modes
High speed power
Vhys Comparator hysteresis 7 26 mV
Medium hysteresis mode
15
(COMPxHYST[1:0]=10) All other power
9 19
modes
High speed power
18 49
High hysteresis mode
31
(COMPxHYST[1:0]=11) All other power
19 40
modes
1. Data based on characterization results, not tested in production.

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6.3.18 Temperature sensor characteristics

Table 59. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope 4.0 4.3 4.6 mV/°C
V25 Voltage at 25 °C 1.34 1.43 1.52 V
tSTART(1) Startup time 4 - 10 µs
ADC sampling time when reading the
TS_temp(1)(2) 17.1 - - µs
temperature
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.

6.3.19 VBAT monitoring characteristics

Table 60. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 50 - KΩ

Q Ratio on VBAT measurement - 2 -
Er(1) Error on Q –1 - +1 %
ADC sampling time when reading the VBAT
TS_vbat(1)(2) 5 - - µs
1mV accuracy
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.

6.3.20 Timer characteristics

The parameters given in Table 61 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 61. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz 20.8 - ns

Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 f
TIMxCLK = 48 MHz 0 24 MHz
TIMx (except TIM2) - 16
ResTIM Timer resolution bit
TIM2 - 32

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STM32F051x Electrical characteristics

Table 61. TIMx(1) characteristics (continued)

Symbol Parameter Conditions Min Max Unit

1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 48 MHz 0.0208 1365 µs

Maximum possible count - 65536 × 65536 tTIMxCLK

tMAX_COUNT
with 32-bit counter fTIMxCLK = 48 MHz - 89.48 s
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17
timers.

Table 62. IWDG min/max timeout period at 40 kHz (LSI) (1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF

/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8 ms
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from
30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the
phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of
uncertainty.

Table 63. WWDG min-max timeout value @48 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.0853 5.4613
2 1 0.1706 10.9226
ms
4 2 0.3413 21.8453
8 3 0.6826 43.6906

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Electrical characteristics STM32F051x

6.3.21 Communication interfaces

I2C interface characteristics
Unless otherwise specified, the parameters given in Table 64 are derived from tests
performed under ambient temperature, fPCLK frequency and VDD supply voltage conditions
summarized in Table 20.
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 64. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).

Table 64. I2C characteristics(1)

Standard mode Fast mode Fast Mode Plus
Symbol Parameter Unit
Min Max Min Max Min Max

tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.5 -

µs
tw(SCLH) SCL clock high time 4.0 - 0.6 - 0.26 -
tsu(SDA) SDA setup time 250 - 100 - 50 -
th(SDA) SDA data hold time 0(3) 3450(2) 0(3) 900(2) 0(4) 450(2)
tr(SDA) ns
SDA and SCL rise time - 1000 - 300 - 120
tr(SCL)
tf(SDA)
SDA and SCL fall time - 300 - 300 - 120
tf(SCL)
th(STA) Start condition hold time 4.0 - 0.6 - 0.26 -
Repeated Start condition µs
tsu(STA) 4.7 - 0.6 - 0.26 -
setup time
tsu(STO) Stop condition setup time 4.0 - 0.6 - 0.26 - μs
Stop to Start condition time
tw(STO:STA) 4.7 - 1.3 - 0.5 - μs
(bus free)
Capacitive load for each bus
Cb - 400 - 400 - 550 pF
line
1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in
production.
2. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
4. The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.

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STM32F051x Electrical characteristics

Table 65. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Pulse width of spikes that are

tSP 50 260 ns
suppressed by the analog filter
1. Guaranteed by design, not tested in production.

Figure 25. I2C bus AC waveforms and measurement circuit

6$$ 6$$

2 2 -#5
Ω
3$!
)#BUS Ω
3#,

3 4!242%0%!4%$

3 4!24

TSU34! 3 4!24

3$!
TF3$! TR3$! TSU3$!
3 4/0 TW34/34!
TH34! TW3#,, TH3$!

3#,
TW3#,( TR3#, TF3#, TSU34/
-36

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 66 for SPI or in Table 67 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 20.
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Table 66. SPI characteristics

Symbol Parameter Conditions Min Max Unit

fSCK Master mode - 18

SPI clock frequency MHz
1/tc(SCK) Slave mode - 18
tr(SCK) SPI clock rise and fall
Capacitive load: C = 15 pF - 6 ns
tf(SCK) time

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Electrical characteristics STM32F051x

Table 66. SPI characteristics (continued)

Symbol Parameter Conditions Min Max Unit
(1)
tsu(NSS) NSS setup time Slave mode 4Tpclk -
th(NSS)(1) NSS hold time Slave mode 2Tpclk + 10 -
(1)
tw(SCKH) Master mode, fPCLK = 36 MHz,
SCK high and low time Tpclk/2 -2 Tpclk/2 + 1
tw(SCKL)(1) presc = 4

tsu(MI) (1) Master mode 4 -

Data input setup time
tsu(SI)(1) Slave mode 5 -
(1)
th(MI) Master mode 4 -
Data input hold time ns
th(SI)(1) Slave mode 5 -
ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk
tdis(SO)(1)(3) Data output disable time Slave mode 0 18
tv(SO) (1) Data output valid time Slave mode (after enable edge) - 22.5
tv(MO)(1) Data output valid time Master mode (after enable edge) - 6
th(SO) (1) Slave mode (after enable edge) 11.5 -
Data output hold time
(1)
th(MO) Master mode (after enable edge) 2 -
SPI slave input clock duty
DuCy(SCK) Slave mode 25 75 %
cycle
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

Figure 26. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK)

tSU(NSS) th(NSS)

CPHA= 0
SCK Input

CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1

ta(SO) tv(SO) th(SO) tr(SCK) tdis(SO)

tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
th(SI)
ai14134c

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STM32F051x Electrical characteristics

Figure 27. SPI timing diagram - slave mode and CPHA = 1(1)

NSS input
tSU(NSS) tc(SCK) th(NSS)

CPHA=1
SCK Input

CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1

tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI) th(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

Figure 28. SPI timing diagram - master mode(1)

High

NSS input

tc(SCK)
SCK Output

CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN

th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

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Electrical characteristics STM32F051x

Table 67. I2S characteristics

Symbol Parameter Conditions Min Max Unit

Master mode (data: 16 bits, Audio

fCK 1.597 1.601
I2S clock frequency frequency = 48 kHz) MHz
1/tc(CK)
Slave mode 0 6.5
2
tr(CK) I S clock rise time - 10
Capacitive load CL = 15 pF
2
tf(CK) I S clock fall time - 12
tw(CKH) (1) I2S clock high time Master fPCLK= 16 MHz, audio 306 -
tw(CKL) (1) I2S clock low time frequency = 48 kHz 312 -
ns
(1)
tv(WS) WS valid time Master mode 2 -
th(WS) (1) WS hold time Master mode 2 -
tsu(WS) (1) WS setup time Slave mode 7 -
(1)
th(WS) WS hold time Slave mode 0 -
I2S slave input clock duty
DuCy(SCK) Slave mode 25 75 %
cycle
tsu(SD_MR) (1) Data input setup time Master receiver 6 -
tsu(SD_SR) (1) Data input setup time Slave receiver 2 -
th(SD_MR)(1)(2) Master receiver 4 -
Data input hold time
(1)(2)
th(SD_SR) Slave receiver 0.5 -
Slave transmitter (after enable
tv(SD_ST) (1)(2) Data output valid time - 20
edge) ns
Slave transmitter (after enable
th(SD_ST) (1) Data output hold time 13 -
edge)
Master transmitter (after enable
tv(SD_MT) (1)(2) Data output valid time - 4
edge)
Master transmitter (after enable
th(SD_MT) (1) Data output hold time 0 -
edge)
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.

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STM32F051x Electrical characteristics

Figure 29. I2S slave timing diagram (Philips protocol)

tc(CK)

CK Input CPOL = 0

CPOL = 1

tw(CKH) tw(CKL) th(WS)

WS input

tsu(WS) tv(SD_ST) th(SD_ST)

SDtransmit
LSB transmit(2) MSB transmit Bitn transmit LSB transmit

tsu(SD_SR) th(SD_SR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

ai14881b

1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 30. I2S master timing diagram (Philips protocol)

tf(CK) tr(CK)

tc(CK)
CK output

CPOL = 0
tw(CKH)

CPOL = 1
tv(WS) tw(CKL) th(WS)

WS output

tv(SD_MT) th(SD_MT)

SDtransmit LSB transmit(2) MSB transmit Bitn transmit LSB transmit

tsu(SD_MR) th(SD_MR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

ai14884b

1. Data based on characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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Package characteristics STM32F051x

7 Package characteristics

7.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

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STM32F051x Package characteristics

Figure 31. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline

D

D1 ccc C

D3 A
A2
48 33

49 32

b
L1

E3 E1 E

L
A1 K

64
17
Pin 1
identification 1 16 c
5W_ME

1. Drawing is not to scale.

Table 68. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 11.800 12.000 12.200 0.4646 0.4724 0.4803
D1 9.800 10.000 10.200 0.3858 0.3937 0.4016
D. 7.500
E 11.800 12.000 12.200 0.4646 0.4724 0.4803
E1 9.800 10.00 10.200 0.3858 0.3937 0.4016
e 0.500 0.0197
k 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.75 0.0177 0.0236 0.0295
L1 1.000 0.0394
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package characteristics STM32F051x

Figure 32. LQFP64 recommended footprint

48 33

0.3
49 0.5 32

12.7
10.3

10.3
64 17

1.2
1 16
7.8

12.7

ai14909

1. Drawing is not to scale.

2. Dimensions are in millimeters.

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STM32F051x Package characteristics

Figure 33. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package outline

D1 ccc C

D3 A
A2
36 25

37 24

L1
b
E3 E1 E

48
13 L
A1 K
Pin 1
identification 1 12 c

5B_ME

1. Drawing is not to scale.

Table 69. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.500 0.2165
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.500 0.2165
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0° 3.5° 7° 0° 3.5° 7°
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package characteristics STM32F051x

Figure 34. LQFP48 recommended footprint

0.50
1.20

0.30
36 25
37 24

0.20
7.30
9.70 5.80

7.30

48 13
1 12

1.20

5.80

9.70

ai14911b

1. Drawing is not to scale.

2. Dimensions are in millimeters.

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STM32F051x Package characteristics

Figure 35. LQFP32 7 x 7mm 32-pin low-profile quad flat package outline

CCC #
$
$
$ !
!
 


 ,
B
% % %



,
0IN ! +
IDENTIFICATION   C

6?-%

1. Drawing is not to scale.

Table 70. LQFP32 7 x 7mm 32-pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.600 0.2205
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.600 0.2205
e 0.800 0.0315
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc 0.100 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package characteristics STM32F051x

Figure 36. LQFP32 recommended footprint










6?&0

1. Drawing is not to scale.

2. Dimensions are expressed in millimeters.

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STM32F051x Package characteristics

Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5)
Seating plane

C
ddd C
A

A3 A1

D
e

9 16

8 17

E2 b E

24
1
L
32
Pin # 1 ID
R = 0.30 D2
L
Bottom view A0B8_ME

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must
be connected. It is referred to as pin 0 in Table 13: Pin definitions.

Table 71. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data
mm inches(1)
Dim.
Min Typ Max Min Typ Max

A 0.5 0.55 0.6 0.0197 0.0217 0.0236

A1 0.00 0.02 0.05 0 0.0008 0.0020
A3 0.152 0.006
b 0.18 0.23 0.28 0.0071 0.0091 0.0110
D 4.90 5.00 5.10 0.1929 0.1969 0.2008
D2 3.50 0.1378
E 4.90 5.00 5.10 0.1929 0.1969 0.2008

E2 3.40 3.50 3.60 0.1339 0.1378 0.1417

e 0.500 0.0197
L 0.30 0.40 0.50 0.0118 0.0157 0.0197
ddd 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package characteristics STM32F051x

Figure 38. UFQFPN32 recommended footprint

1. Drawing is not to scale.

2. Dimensions are expressed in millimeters.

7.2 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 20: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
● TA max is the maximum ambient temperature in °C,
● ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
● PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
● PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

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STM32F051x Package characteristics

Table 72. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient
45
LQFP64 - 10 × 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
55
LQFP48 - 7 × 7 mm
ΘJA °C/W
Thermal resistance junction-ambient
56
LQFP32 - 7 × 7 mm
Thermal resistance junction-ambient
38
UFQFPN32 - 5 × 5 mm

7.2.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org

7.2.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F05xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.

Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 72 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Table 20:
General operating conditions.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).

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Package characteristics STM32F051x

Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (45°C/W × 447 mW) = 105-20.115 = 84.885 °C
Suffix 7: TAmax = TJmax - (45°C/W × 447 mW) = 125-20.115 = 104.885 °C

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 72 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation in order to be able to
use suffix 6 parts.
Refer to figure 38 to select the required temperature range (suffix 6 or 7) according to your
ambient temperature or power requirements.

Figure 39. LQFP64 PD max vs. TA

700
600
500
PD (mW)

400 Suffix 6
Suffix 7
300
200
100
0
65 75 85 95 105 115 125 135

TA (°C)

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STM32F051x Part numbering

8 Part numbering

For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.

Table 73. Ordering information scheme

Example: STM32 F 051 R 8 T 6 x

Device family
STM32 = ARM-based 32-bit microcontroller

Product type
F = General-purpose

Sub-family
051 = STM32F051xx

Pin count
K = 32 pins
C = 48 pins
R = 64 pins

Code size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory

Package
U = UFQFPN
T = LQFP

Temperature range
6 = –40 °C to +85 °C
7 = –40 °C to +105 °C

Options
xxx = programmed parts
TR = tape and real

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STM32F051x Revision history

9 Revision history

Table 74. Document revision history

Date Revision Changes

05-Apr-2012 1 Initial release

Updated Table 2: STM32F051x family device features and
peripheral counts for 1 SPI and 1 I2C in 32-pin package
Corrected Group 3 pin order in Table 5: Capacitive sensing
25-Apr-2012 2 GPIOs available on STM32F051x devices.
Updated current consumptionTable 25 to Table 29.
Updated Table 39: HSI14 oscillator characteristics
Features reorganized and Section 3: Functional overview
structure changed.
Added LQFP32 package.
Updated Section 3.4: Cyclic redundancy check calculation
unit (CRC).
Modified number of priority levels in Section 3.9.1: Nested
vectored interrupt controller (NVIC).
Added note 3. for PB2 and PB8, changed TIM2_CH_ETR into
TIM2_CH1_ETR in Table 13: Pin definitions and Table 14:
Alternate functions selected through GPIOA_AFR registers
for port A. Added Table 15: Alternate functions selected
through GPIOA_AFR registers for port B.
23-Jul-2012 3 Updated IVDD, IVSS, and IINJ(PIN) in Table 18: Current
characteristics .
Updated ACCHSI in Table 38: HSI oscillator characteristics
and Table 39: HSI14 oscillator characteristics.
Updated Table 49: I/O current injection susceptibility.
Added BOOT0 input low and high level voltage in Table 50:
I/O static characteristics.
Modified number of pins in VOL and VOH description, and
changed condition for VOLFM+ in Table 51: Output voltage
characteristics.
Changed VDD to VDDA in Figure 23: Typical connection
diagram using the ADC.
Updated Ts_temp in Table 59: TS characteristics.

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STM32F051x

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