Scribd
Upload
62 views

Expt 12

This document describes the design and implementation of SR, JK, D, and T flip-flops using basic logic gates. It provides the theory of operation for each type of flip-flop, including block diagrams, truth tables, and logic diagrams. An experiment was conducted to construct the flip-flops using an IC trainer kit and verify their logic using truth tables by observing the output LEDs for different input combinations.

Uploaded by

Dhrrishith Vikal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
62 views

Expt 12

This document describes the design and implementation of SR, JK, D, and T flip-flops using basic logic gates. It provides the theory of operation for each type of flip-flop, including block diagrams, truth tables, and logic diagrams. An experiment was conducted to construct the flip-flops using an IC trainer kit and verify their logic using truth tables by observing the output LEDs for different input combinations.

Uploaded by

Dhrrishith Vikal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

Expt.No.

12
Date: Design and Implementation SR, JK, T & D Flip-Flops
AIM:
Construct SR, JK, D and T flipflops Flip-Flops using basic logic gates and verify its
logic using truth table.

COMPONENTS REQUIRED:

THEORY:
(a). SR (SET RESET) FLIP-FLOP:
THEORY:
The basic 1-bit digital memory circuit is known as a flip-flop. Flip-Flops are
synchronous bistable devices (has two outputs Q and Q’). In this case, the term
synchronous means that the output changes state only at a specified point on the
triggering input called the clock (CLK). It can have only two states, either the 1 state
or the 0 state. Flip-flops can be constructed by using NAND or NOR gates.
The SR flip-flop, stands for “Set-Reset” flip-flop. This simple flip-flop is basically a
one- bit memory bistable device that has two inputs, one which will “SET” the device
(meaning the output = “1”), and is labelled S and one which will “RESET” the device
(meaning the output = “0”), labelled R. The reset input resets the flip-flop back to its
original state with an output Q. A basic NAND gate SR flip-flop circuit provides
feedback from both of its outputs back to its opposing inputs and is commonly used
in memory circuits to store a single data bit. Then the SR flip-flop has three inputs,
Set, Reset and its current output Q relating to its current state or history. When S
and R at HIGH state both outputs tries to get into HIGH state and not of them get
into state output state. This state is called intermediate or invalid state.
Block diagram:

Truth table:
Logic Diagram

(b). JK (JACK KILBY) FLIP-FLOP:


THEORY:

The JK Flip Flop is the most widely used flip flop. It is a universal
flip-flop circuit. The sequential operation of the JK Flip Flop is same as for the RS flip-flop
with the same SET and RESET input. The difference is that the JK Flip Flop does not the
invalid input states when S and R are both 1. A JK Flip-Flop can be obtained from the
clocked SR Flip-Flop by augmenting two AND gates. If the circuit is in the “SET” condition,
the J input is inhibited by the status 0 of Q through the lower NAND gate. Similarly, the
input K is inhibited by 0 status of Q through the upper NAND gate in the “RESET” condition.
When both J and K are at logic “1”, the JK Flip Flop toggle.

Truth table
Logic Diagram

(c). D (DATA/DELAY) FLIP-FLOP:


THEORY:
This flip-flop, called a Data flip-flop because of its ability to ‘latch’ and remember
data, or a Delay flip-flop because latching and remembering data can be used to
create a delay in the progress of that data through a circuit. A D flip–flop is constructed
by modifying an SR flip – flop. The S input is given with D input and the R input is given with
inverted D input. Hence a D flip – flop is similar to SR flip – flop in which the two inputs are
complement to each other, so there will be no chance of any intermediate state occurs.
The major drawback of SR flip – flop is the race around condition which in D flip – flop is
eliminated (because of the inverted inputs). When we don’t apply any clock input to the
D flip flop or during the falling edge of the clock signal, there will be no change in the
output. It will retain its previous value at the output Q. If the clock signal is high and if D
input is high, then the output is also high and if D input is low, then the output will become
low. Hence the output Q follows the input D in the presence of clock signal.
Block Diagram:

Truth table:
Logic Diagram:

(d). T (TOGGLE) FLIP-FLOP:


THEORY:
T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of
intermediate state in SR flip – flop, we should provide only one input to the flip – flop called
Trigger input or Toggle input (T). Then the flip – flop acts as a Toggle switch. Toggling
means ‘Changing the next state output to complement of the present state output’. The
T (Toggle) Flip-Flop is a modification of the JK Flip-Flop. It is obtained from JK Flip-Flop by
connecting both inputs J and K together, i.e., single input. Regardless of the present state,
the Flip-Flop complements its output when the clock pulse occurs while input T= 1.
Block Diagram:

Truth table
Logic Diagram

PROCEDURE:
1. Place the IC on IC trainer kit
2. Connect the Vcc and ground to respective pins of IC trainer kit
3. Connections are given as per logic diagram.
4. Connect the inputs to the input switches provided in the IC trainer kit
5. Connect the outputs to the switches of output LED’s
6. Apply various combinations of input according to the truth table
7. Observe the condition of output LED’s and verify the truth table.

RESULT:
Thus, basic flip-flops such as SR, JK, D and T are constructed using basic logic gates
and their truth tables are verified.

You might also like