IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO.

4, APRIL 2008 815

Ultra Fast Fixed-Frequency Hysteretic Buck

Converter With Maximum Charging Current
Control and Adaptive Delay Compensation
for DVS Applications
Feng Su, Student Member, IEEE, Wing-Hung Ki, Member, IEEE, and Chi-Ying Tsui, Member, IEEE

Abstract—An integrated DC–DC hysteretic buck converter This provides higher flexibility for the system to optimize
with ultrafast adaptive output transient response for reference the voltage scheduling. Tracking time of the order of 10 s
tracking is presented. To achieve the fastest up-tracking speed, or shorter are preferred, which are much faster than most
the maximum charging current control is introduced to charge
up the output voltage with the maximum designed current. For of the state-of-the-art designs.
down-tracking, the output is discharged by the load only to 3) Reverse current from the output capacitor back to the input
save energy. Although the converter works with hysteretic voltage supply or ground should be avoided to reduce power loss.
mode control, an adaptive delay compensation scheme is employed 4) It is advisable to maintain a constant switching frequency
to keep the switching frequency constant at 850 kHz to within so that electromagnetic interference (EMI) noise spectrum
2.5% across the whole operation range. The integrated buck
converter was fabricated using a 0.35 m CMOS process. With an is known and conform to common practice in the industry.
input voltage of 3 V, the output voltage can be regulated between In this paper, an integrated DC–DC buck (step-down) con-

0.5 and 2.5 V. With a load resistor of 10 , the up-tracking speed verter that has the above characteristics for DVFS applications
of the maximum reference step (0.5 to 2.5 V) is 12.5 s . All V is presented. In Section II, a simple and effective reference
design features are verified by extensive measurements. tracking scheme, denoted as maximum charging current (MCC,
Index Terms—Adaptive delay compensation, adaptive output, or MC ) control, is proposed. Here, the output voltage of
current sensor, dynamic voltage scheduling (DVS), maximum the converter up-tracks the reference voltage using the max-
charging current control, pseudocontinuous conduction mode
imum allowable current within the safe limit of the chip. For
(PCCM), rail-to-rail comparator, reference tracking.
down-tracking, to reduce the power loss, the inductor stops to
supply power to the output capacitor and the output capacitor
I. INTRODUCTION is discharged by the load current only. Section III presents the
system architecture of the converter that operates in hysteretic
D YNAMIC voltage and frequency scheduling (DVFS) is
one of the effective solutions for reducing the power con-
sumption of digital systems [1]–[3]. Depending on the workload
voltage-mode control to ensure stability. Section IV discusses
the detailed circuit implementation that includes two integrated
on-chip current sensors and the adaptive delay compensation
of the task and the slack available from the system, the clock
(ADC) circuitry. The ADC includes a frequency-error detector
frequency of executing a task and the corresponding supply
and a voltage-controlled delay unit to keep the switching fre-
voltage are varied during run-time in order to optimize the dy-
quency at 850 kHz to within 2.5% across the whole operation
namic and leakage power consumption while still satisfying the
range. Section V presents and discusses experimental results,
deadline requirement. A critical component for implementing
and Section VI summarizes our research efforts with some
DVFS is the adaptive power converter that could provide vari-
concluding remarks.
able supply voltage with fast tracking speed. It is usually im-
plemented by a switching converter due to its high efficiency II. MCC CONTROL
[4]–[8]. A switching converter with variable output voltage for
A switching converter implementing DVFS requires fast
DVFS applications should have the following characteristics.
reference tracking. For up-tracking, the output voltage is
1) It should attain system stability across the whole operation
changed from a lower voltage to a higher voltage with
range.
a scheduled change in the reference voltage . To achieve a
2) It should have a fast tracking speed to minimize latency and
fast reference tracking speed, a large current is needed to charge
losses when switching between different voltage levels.
or discharge the output capacitor . To alleviate the metal
electromigration effect, there is a current density limit for the
Manuscript received August 31, 2007; revised December 3, 2007. This work
was supported in part by the Hong Kong Research Grants Council under Grant
on-chip metal rails, which is usually of the order of 1 mA m
CERG 6311/04E and HKUST6256/04E. [9]. At the same time, the metal rails cannot be exceedingly
The authors are with the Department of Electronic and Computer Engi- wide in order to keep the cost down. Thus, there is a maximum
neering, Hong Kong University of Science and Technology, Clear Water current that the design can handle. Hence, the fastest way
Bay, Hong Kong SAR (e-mail: [email protected]; [email protected];
[email protected]). to charge up from to is to keep the charging current
Digital Object Identifier 10.1109/JSSC.2008.917533 at all the time. The up-tracking time is thus equal
0018-9200/$25.00 © 2008 IEEE
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816 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008

For down-tracking, if the system allows reversion current

flow from the output capacitor back to the input voltage source
or to ground, a similar control strategy as the up-tracking
case can be applied, where the maximum charging current is
replaced by the maximum discharging current (and the inductor
current is negative). However, to reduce the DVFS overhead
and to achieve more energy saving, reversion current should
be avoided. In this case, the output is discharged by the load
current only during this period, and the down-tracking speed is
then dominated by that could be quite long under light load
conditions. A long is not important for DVFS applications
as a higher power supply voltage supports a higher switching
frequency, and the task is guaranteed to be completed before
deadline.
From the above discussion, it is clear that in order to obtain
a tracking time close to the theoretical minimum the converter
should have the following capabilities:
• The converter should be able to apply full or zero duty cy-
cles to increase or decrease the inductor current to mini-
Fig. 1. Fast reference tracking strategy.
mize and .
• The converter should have fast response, even for a large
current change, to minimize and .
to . is the theoretical minimum and • The converter should have a current limiting circuit to pre-
is not attainable in practice, because: 1) the inductor current vent the charging current from going beyond of the
has to ramp up from a lower steady-state value and cannot system and a reversion control circuit to prevent reversion
become instantaneously and 2) has to supply the current from flowing back to the input source.
load current also, reducing the effective charging current
for . III. SYSTEM ARCHITECTURE
Here, we propose a fast reference-tracking scheme. The Hysteretic voltage-mode control, also known as band-band
up-tracking process can be divided into the following three control or ripple voltage control, is well known for its fast
phases as shown in Fig. 1. response for line and load transients. Moreover, hysteretic
1) Inductor current ramp up phase ( ): During , the in- switching converters have been shown to have unconditional
ductor current ramps up from the output (load) current stability under all operation conditions [10], [11]. We discuss
to the maximum allowable current with full stability from the operation of the converter here rather than
duty cycle. can be calculated as using state plane analysis. We use Fig. 2 for the illustra-
tion. Without loss of generality, continuous conduction mode
(1) (CCM) is assumed. If the output voltage is lower than the
low-voltage limit , the hysteretic comparator turns on the
Note that the controller should be able to produce full duty pMOS power switch , charging up the output capacitor
ratio if is larger than the switching period. through the inductor , and the output voltage increases. The
2) Maximum current charging phase ( ): During , voltage across the inductor is . Eventually,
the inductor current switches between two predefined will be higher than the preset high-voltage limit . Due to
levels and (the details will be discussed in delay in the loop, the gate drive switches from (0 V) to
Section III) such that the average inductor current is kept after as shown in Fig. 2(b), turning off , turning on
at . The maximum current the nMOS power switch , and allowing the inductor current
is charging the output capacitor at full speed until the to flow from ground to charge up . The inductor voltage is
capacitor voltage reaches the predefined value . is then and ramps down. When ramps below
then given by the average inductor current, decreases and eventually the
load current drains the output capacitor until drops
(2) below the low-voltage limit again. If a change in the input
voltage or the output current causes to be outside the band
3) Inductor current ramp down phase ( ): When the output limited by and , the hysteretic comparator will issue
voltage reaches the predefined value, the inductor current gate drive signals to charge or discharge continuously (that
is then decreased to the new output current . The load is, full or zero duty cycle) to steer back to within the band as
transient time depends on the control methodology of quickly as possible. Thus, the output voltage is corrected as fast
the converter. The total up-tracking time is as the output power filter ( and ) allows and, incidentally,
the converter is unconditionally stable. The propagation delays
(3) and shown in Fig. 2 depend on the delay of the
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SU et al.: FIXED-FREQUENCY HYSTERETIC BUCK CONVERTER WITH MAXIMUM CHARGING CURRENT CONTROL FOR DVS APPLICATIONS 817

monitored by on-chip current sensors [13], [14] to produce volt-

ages and for the maximum charging current control. The
converter is designed to operate in pseudocontinuous conduc-
tion mode (PCCM) in the steady state [15], [16]. The voltage
that corresponds to the current level determines the
valley inductor current, and, as shown in Fig. 4, if is set
to zero, the converter then works in discontinuous conduction
mode (DCM). Whether the converter works in PCCM or DCM,
the freewheel switches and are turned on when
the sensed “diode” current reaches . In any case, is
set to be very low, such that both and are small
switches. In fact, we may use only or to simplify
the control.
As shown in Fig. 1, during the up-tracking period when
is changed from to , in-rush current is needed to charge
up the output capacitor quickly, so that the output voltage could
track the reference voltage as quickly as the system allows under
safe conditions. Voltage levels and define the high and
low limits of the inductor current during tracking transients,
respectively. When is lower than , the power transistor
is turned on, and then charges up the inductor , and
the inductor current ramps up. will be turned off when
, which is manifested as . At the same
time, is turned on to discharge until the current of
is lower than (manifested as ) and then will be
Fig. 2. Conventional hysteretic voltage-mode control of buck converter. turned on again. The swing of the inductor current is around
(a) System architecture. (b) Waveforms of V and V . 200 mA in this design. As has not reached yet, the con-
verter undergoes switching activities, turning on and off and
alternately. As is higher than , will eventu-
hysteretic comparator and the latch. In practice, any functional ally be charged up to , and is then allowed to discharge all
block in the loop, such as the nonoverlapping circuit or the gate the way to and steady state is reached again. Note that, for
drive buffers, would all contribute to the propagation delays. a switching converter, the inductor current cannot be a constant
The hysteretic converter has two main disadvantages. First, during switching, and the maximum charging current should be
as the control loop allows full and zero duty cycles, the inductor considered as . Consequently, the
current could rise beyond the current limit of the power switches converter achieves the fastest practical up-tracking speed sub-
during large signal transient responses, for example, during the ject to the limitation of the charging constraints discussed above.
start-up period. Second, the switching frequency varies with When the output voltage is changed from a higher to a lower
all of the design parameters of the converter, such as , , , , we do not want to have reversion current to flow back to the
, etc. [12]. We use and as an example. If is input supply or to the ground, thus the fastest way is to use the
smaller, then is higher. However, even when , load current to discharge , and .
is not infinitely high, because the control loop has delay. Hence, when is changed from to , both and
In this research, we use so that only one com- are turned off until , and the steady state is reached.
parator is needed. At the same time, in order to achieve a fixed For applications where the tracking speed is more important
switching frequency, we propose an adaptive delay compensa- than power efficiency, the up-tracking response could be en-
tion scheme. The overall system architecture of the proposed hanced by adding a direct charging path (DCP), as shown in
converter, which implements both the maximum charging con- Fig. 3, to charge the output directly with the supply voltage
trol and the hysteretic control, is shown in Fig. 3. through a switch. It is activated only when the inductor cur-
The proposed hysteretic buck converter uses only one refer- rent has ramped up to the predefined maximum current level
ence voltage (instead of and ) to define the output and switches from “0” to “1.” The max-
voltage . An adaptive delay compensator (ADC) is used to imum charging control mechanism remains operative and the
regulate the switching frequency to a preset value. The ADC has output capacitor is charged up by both the inductor current and
two subblocks, a frequency-error detector (FED), and a voltage- the supply voltage. When the output voltage rises above ,
controlled delay (VCD). The switching frequency is determined triggering to switch from “0” to “1,” the DCP switch is
by the preset voltage . The FED detects the error between then turned off immediately. Similarly, a direct discharging path
and and generates a control signal to drive the (DDP) could be added to sink current from the output to ground
VCD to regulate the switching frequency. Synchronous rectifi- directly to improve the down-tracking response. Note that both
cation is implemented by the switches and , and both the DCP and DDP switches are lossy, and they could be dis-
the “switch” current of and the “diode” current of are abled if efficiency is a major concern. Unlike or , these
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818 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008

Fig. 3. System architecture of the proposed hysteretic buck converter.

IV. CIRCUIT IMPLEMENTATION OF THE HYSTERETIC

BUCK CONVERTER

A. Integrated On-Chip Current Sensors

Fig. 5(a) and (b) shows the on-chip CMOS current sensors
for and , respectively. They are based on the matched
current source technique proposed in [13]. More accurate cur-
rent sensors such as those proposed in [14] can also be used. As
the two current sensors operate in a similar fashion, we only use
the current sensor of as an example to illustrate the oper-
ation principle. The sensing nMOS and the power nMOS
have the same gate, source, and bulk connections, and the
Fig. 4. Inductor current in (a) PCCM and (b) DCM. ratio of to is 1/1500. When , and
are turned on. The transistors to form a differen-
tial common-gate amplifier with the drain voltages of and
switches could be very small, as their own resistance is designed ( and , respectively) as inputs. Ideally, and
to limit the charging current to within a safe limit. supply the bias currents and supplies the sensed current
As discussed above, the conventional hysteretic buck con- . As is very small, the gate voltages of and differ
verter is unconditionally stable [10], [11]. However, our by a few hundred millivolts at most, providing a good matching
proposed design has an additional loop for compensating the between the pairs and , and forcing to
loop delay and regulating the switching frequency to a constant. be equal to . Therefore, the sensed current is equal to
An immediate question is thus: Is the modified buck converter and is mirrored to to give for control. The
still unconditionally stable? Clearly, if the delay of the adaptive scaling of 1:1500 is rather accurate when is large, for ex-
delay compensator is fixed (or the control signal is fixed), ample, of the order of 100 mA.
then our proposed converter resembles a regular hysteretic
buck converter and is thus unconditionally stable. It implies B. Frequency Error Detector (FED)
that, if the bandwidth of the delay compensation loop is much The ADC consists of the FED and the VCD, as shown in
slower than the voltage regulation loop, the stability of the Figs. 6 and 8, respectively. The voltage in Fig. 6 is the
buck converter will not be affected. Hence, we design the delay output of the comparator that compares and of the con-
compensation loop such that its bandwidth is much smaller verter shown in Fig. 3. The switching period of is ,
than that of the voltage regulator loop. which is also the switching period of the converter. The FED
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SU et al.: FIXED-FREQUENCY HYSTERETIC BUCK CONVERTER WITH MAXIMUM CHARGING CURRENT CONTROL FOR DVS APPLICATIONS 819

Fig. 5. Current sensor for (a) M and (b) M .

Fig. 6. (a) FED. (b) T =T = 10=3. T =T > 10=3.
10 3
(c)
(d) T =T < = .
detects the frequency error ( ) between and the
switching frequency defined by and converts the error
signal into the control signal , which is fed to the VCD
for adjusting the delay.
Fig. 6(a) shows the detailed implementation of the FED. Ini-
tially, the timing capacitor is discharged ( “1”), the
output of the FED comparator is “0”, and is “0”. When
falls below , switches from “1” to “0”, the FED
latch then switches to give “0”, turning on the current
source to charge up , and setting to “1”. When the
voltage reaches , is reset to “0”, shutting off and
discharging back to GND. The duration for “1” is
. Hence, every time falls to “0”, a pulse of
length is generated at . This pulse train is then filtered
by a subsequent charge pump with a charging current of
and a discharging current of such that the filtered signal
will finally be settled down when ,
as shown in Fig. 6(b). If , as shown in Fig. 6(c), Fig. 7. Demonstrating ambiguity in delay compensation.
will fall, shortening the delay. Similarly, if , as shown
in Fig. 6(d), will rise, lengthening the delay from the VCD
block. Hence, the delay is adaptively adjusted to regulate reaches the steady state, its duty cycle must be larger than
to be . 0.5. For example, assuming that as shown in
The ratio of the charging current to the discharging cur- Fig. 7(a) and (b), and the duty cycle of is 2/3 in the steady
rent has to be larger than 1 (7/3 in this case) to avoid ambi- state. In the frequency error detector, the falling edge of
guity in delay compensation. If the ratio is smaller than 1, when will trigger with a pulse wide only when is “0.”
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820 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008

Fig. 9. Comparators for VCD: (a) CMPa and (b) CMPb.

Fig. 8. (a) VCD. (b) Waveforms of various nodes.

with a rising edge delay of and a falling edge delay of
. Some of the crucial waveforms of the VCD are shown
During the period, “1” and any new coming trig- in Fig. 8(b). The exact description of the action of the three
gering signals will be missed out. As shown in Fig. 7(b), latches is tedious but straightforward, and is not provided. How-
misses one trigger every two periods. Compared with Fig. 7(a), ever, we want to mention that in order to obtain the correct sig-
for the same and waveforms, , nals, and are NOR latches and is a NAND latch.
and both and could be the switching frequency of the Due to forbidden states, the outputs of an SR latch are not com-
system, causing ambiguity. If , then the duty cycle plementary signals and, therefore, inverters are used to convert
of in the steady state must be less than 0.5, which guar- and correctly to drive the switches for and , re-
antees no trigger will be missed when settles in the steady spectively.
state, avoiding ambiguity. It should be noted that the matching The comparator CMPa should have a rail-to-rail input stage
accuracy between and (7:3 in this case) is not critical to accommodate for the wide voltage ranges of and ,
as long as the ratio is larger than 1. and the comparator CMPb should be ground sensing. Fig. 9(a)
shows the schematic of CMPa, which consists of a p-input am-
plifier and an n-input amplifier. When the inputs are close to
C. Voltage Controlled Delay (VCD) , the p-input amplifier is shut off, and when the inputs are
close to ground, the n-input amplifier is shut off. Hence, the
Fig. 8(a) shows the implementation of the VCD. The input gain of the comparator changes with the input signals. As long
signal of VCD is , which is the output of the comparator as the gain is high enough, the comparator could function as
that compares and . The output signal is , and is designed. Fig. 9(b) shows the schematic of CMPb. For both
the delayed version of . When changes from “0” to comparators, built-in offset voltages are introduced by assigning
“1,” the charging current is directed to charge from 0 different sizes to the input transistors. For example, a positive
V to . After a delay of , the offset voltage is introduced at the positive input terminal
output signal jumps from “0” to “1” [Fig. 8(b)]. Similarly, of CMPb, such that the signal switches from “0” to “1”
when changes from “1” to “0,” the discharging current as soon as is discharged below instead of 0 V. The
is directed to discharge from to 0 V. After a delay offset voltages for other comparators are introduced similarly,
of , the output signal jumps and clearly, the delays and have to be adjusted
from “1” to “0.” Hence, is the delayed version of , accordingly.
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SU et al.: FIXED-FREQUENCY HYSTERETIC BUCK CONVERTER WITH MAXIMUM CHARGING CURRENT CONTROL FOR DVS APPLICATIONS 821

Fig. 10. Micrograph of fabricated chip.

Fig. 13. Reference tracking responses under different I . (a) Up-tracking

from 0.5 V to 2.5 V with I = 50mA. (b) Up-tracking from 0.5 V to 2.5 V
with I = 500 mA. (c) Down-tracking from 2.5 V to 0.5 V with I =
50 mA. (d) Down-tracking from 2.5 V to 0.5 V with I = 500mA.

Fig. 11. Typical profiles of I and V in the steady state.

Fig. 12. Typical reference tracking response.

Fig. 14. Reference tracking responses with and without DCP. (a) Up-tracking
from 0.5 V to 2.5 V with DCP at I = 500 mA. (b) Up-tracking from 0.5 V
to 2.5 V without DCP at I = 500 mA. (c) Up-tracking from 0.5 to 2.5 V
V. MEASUREMENT RESULTS with DCP at R = 10
. (d) Up-tracking from 0.5 to 2.5 V without DCP at
The converter was fabricated in a 0.35 m CMOS process, R = 10
.

and the micrograph is shown in Fig. 10. The freewheel switch

is very small as it only needs to conduct a current of 10 mA.
Fig. 11 shows the inductor current and the switching node
voltage when the converter is operating in PCCM in
the steady state. The adaptive delay compensator regulates
the switching frequency at 850 kHz. With the load current
mA and the freewheel current mA, the
control loop gives the peak inductor current as 135 mA. Fig. 12
shows a typical reference tracking response for a switching
of the reference voltage between 0.5 and 2.5 V with a fixed
. For the up-tracking case, the maximum current
charging control worked as expected, limiting the inductor cur-
rent to within the bounds of and A. Fig. 15. Switching frequency with and without ADC.
The up-tracking speed is 12.5 s/V (the ideal up-tracking speed
is 11 s/V, where ). For
down-tracking, (10 F) is discharged by only, and heavy output load current makes the up-tracking time longer
the output settled in 200 s. The ADC controlling voltage and the down-tracking time shorter. Fig. 14 shows the tracking
(which is the output voltage of the frequency error detector) responses when the direct charging path is activated. For a load
settled within 200 s for both the up- and down-tracking cases. current of 500 mA, the up-tracking speed is 5 s/0.5 V with
Fig. 13 shows the tracking responses under different , with DCP [Fig. 14(a)], compared with 30 s/0.5 V without DCP
a step change in the reference voltage of 0.5 V. Obviously, a [Fig. 14(b)]. Fig. 15 shows the converter switching frequency
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822 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008

TABLE I [9] AMS 0.35 m CMOS C35 Process Parameters.

SUMMERY OF FABRICATED CHIP [10] W. W. Burns and T. G. Wilson, “State trajectories used to observe and
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AES-12, no. 6, pp. 706–717, Nov. 1976.
[11] K. Leung and H. Chung, “Dynamic hysteresis band control of the buck
converter with fast transient response,” IEEE Trans. Circuits Syst. II,
Exp. Briefs, vol. 52, no. 7, pp. 398–402, Jul. 2005.
[12] “Designing Fast Response Synchronous Buck Regulators Using the
TPS5210,” Texas Instruments, Mar. 1999.
[13] W. H. Ki, “Current Sensing Technique Using MOS Transistors Scaling
With Matched Bipolar Current Sources,” U.S. U.S. Patent 5 757 174,
May 26, 1998.
[14] H. Lam, W. H. Ki, C. Y. Tsui, and D. Ma, “Integrated 0.9 V charge-
control switching converter with self-biased current sensor,” in Proc.
IEEE Int. Midwest Symp. Circuits Syst., Hiroshima, Japan, Jul. 2004,
pp. II.305–II.308.
[15] D. Ma, W. H. Ki, and C. Y. Tsui, “A pseudo-CCM/DCM SIMO
switching converter with freewheel switching,” IEEE J. Solid-State
with and without adaptive delay compensation. With no delay Circuits, vol. 38, no. 6, pp. 1007–1014, Jun. 2003.
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the average frequency of 1.23 MHz. With delay compensation,
the range is from 828 to 866 kHz, which is a minute change Feng Su (S’03) received the B.Sc. degree in au-
tomations from the Shanghai Jiao Tong University
of only 2.2% and is within 5% of the target frequency of (SJTU), Shanghai, China, in 2003. He is currently
850 kHz. Table I summarizes the design parameters and the working toward the Ph.D. degree at the Hong Kong
measurement results. University of Science and Technology, Hong Kong.
His research interests are fully integrated power
management units for RFID, micro-sensor and
VI. CONCLUSION biomedical systems, analog IC design techniques
We proposed, fabricated, and tested an integrated hysteretic with emphasis on high-performance switch mode
and switched-capacitor power converters.
buck converter with maximum charging current control to
achieve fast reference tracking. The measured up-tracking
speed was close to the ideal tracking speed as discussed in Wing-Hung Ki (S’86–M’91) received the B.Sc. de-
Section II. The variable frequency nature usually associated gree from the University of California, San Diego, in
1984, the M.Sc. degree from the California Institute
with hysteretic converters was corrected by introducing an of Technology, Pasadena, in 1985, and the Engineer
adaptive delay compensator, and a fixed frequency converter Degree and the Ph.D. degree from the University of
was achieved. Measurement results cope well with the the- California, Los Angeles, in 1990 and 1995, respec-
tively, all in electrical engineering.
oretical analysis and simulation results (not shown), and we He joined Micro Linear Corporation, San Jose,
conclude that maximum charging current control is suitable for CA, in 1992 as a Senior Design Engineer with the
power management implementing dynamic voltage scheduling. Department of Power and Battery Management,
working on the design of power converter con-
trollers. He then joined the Hong Kong University of Science and Technology
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voltage CMOS dynamic dc-dc switching regulator,” in IEEE Int.
Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1997, pp. 380–381. Chi-Ying Tsui (M’95) received the B.S. degree in
[5] M. Hiraki et al., “A 63 W standby-power micro-controller with electrical engineering from the University of Hong
on-chip hybrid regulator scheme,” in Symp. VLSI Circuits Dig. Tech. Kong and the Ph.D. degree in computer engineering
Papers, Jun. 2001, pp. 225–228. from the University of Southern California, Los An-
[6] D. Ma, W. H. Ki, and C. Y. Tsui, “An integrated one-cycle control geles, in 1994.
buck converter with adaptive output and dual loops for output error He joined the Hong Kong University of Science
correction,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 140–149, and Technology in 1994 and is currently an Asso-
Jan. 2004. ciate Professor with the Department of Electronic
[7] G. Wei and M. Horowitz, “A fully digital, energy-efficient, adaptive and Computer Engineering. He is also a cofounder
power-supply regulator,” IEEE J. Solid-State Circuits, vol. 34, no. 4, of Perception Digital Ltd., which focuses on mul-
pp. 520–528, Apr. 1999. timedia and wireless design. His research interests
[8] J. Kim and M. Horowitz, “An efficient digital sliding controller for are designing VLSI architectures for low-power multimedia and wireless ap-
adaptive power supply regulation,” in IEEE Symp. VLSI Circuits Dig. plications, designing power management circuits and techniques for embedded
Tech. Papers, Jun. 2001, pp. 133–136. portable devices, and ultralow-power system design.

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