A B C D E

1 1

Compal Confidential
2 2

Nano 110
DIS M/B Schematics Document
Intel Skylake / Kabylake U Processor with DDR4
AMD R17M-M1-70

2016-12-05
3 3

LA-D562P
R E V ：2 . 0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date Deciphered Date Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 1 of 52

A B C D E
 A B C D E

Channel A
On board DDR4 X 4
DDR4 2133MHz (1.2V , 2.5V) 4G
1
PCIe X4 1

AMD Radeon 520M Gen2

VRAM DDR3L x4 Channel B DDR4 SO DIMM X1
2G 2G/4G
DDR4 2133MHz (1.2V , 2.5V)

eDP X1 USB3.0 x1
Left USB3.0 x1
(2 Lanes) USB2.0 x1
eDP Conn. USB30 Port 2
USB20 Port 2

USB2.0 x1 Left USB2.0 x1

USB20 Port 4
DDI X1
(4 Lanes) Intel Kabylake U
HDMI Conn. USB2.0 x1
Int. Camera
2 SOC USB 2.0 Port 5 2

PCIe X1 PCIe X1 for WLAN

LAN (1 Lanes) 1356 pin BGA
RJ45 Conn. RTL8107E-CG (1 Lanes)
10/100 WLAN / BT
PCIe Port 6
PCIe Port 5 USB2.0 x1 for BT

Card Reader SATA X1 HDD Conn.

Realtek USB2.0 x1
SATA Port 0
RTS5170
USB 2.0 Port 6
SATA X1 ODD Conn.
SATA Port 1

DC to DC
3
HDA Audio Codec 3

CONEXANT
CX11802
LPC SPI

EC SPI ROM Int. MIC Conn. Int. Speaker Conn. Audio Combo Jack
Nuvoton 8MB HP & MIC
NPCE388N

LED Touch Pad Int. KBD

4 4

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 2 of 52

A B C D E
 1 2 3 4 5

BOM Structure Table

Item BOM Structure
Voltage Rails USB Port Table CIWP0 (14") 14@
CIWP1 (15") 15@
3 External
USB 2.0 Port USB Port GPU R16M-M1-30 M1@
GPU R17M-M1-70 M2@
+5VS
UHCI0 For DIS PX@
+3VS 1 USB Port (Left Side) USB3.0
power For UMA UMA@
plane +1.35VGS 2
UHCI1 Camera CMOS@
+VCCSA 3
A A

EHCI1 EMI pop EMI@

+5VALW +VCCCORE 4 USB Port (Left Side) USB2.0
+1.2V UHCI2 EMI Un-pop @EMI@
+B +VCCGT 5 Camera
ESD pop ESD@
+3VALW +VGACORE 6 Card Reader
UHCI3 ESD Un-pop @ESD@
+1.8VS 7 NGFF(WLAN)
RF pop RF@
State +0.6VS
RF unpop @RF@
+1VS
R-Short RS@
Port USB 3.0 Port Table Test Point TP@
VRAM indentify X76@
1 PCIE Port Table System RAM indentify X76RAM@
2 USB3 MB(JUSB1)
HDMI Royalty 45@
3
Port Lane Connector ME@
S0
O O O O 4
SA000092P60 CPU1@
5 1 1
SA000092OA0 CPU2@
6 2 2 GPU
SA000094250 CPU3@
S3
O O O X SATA Port Table
3 3
SA000093780 CPU4@
4 4
SA00009QZ10 CPU5@
S5 S4/AC
O O X X Port
5 LAN
SA00009QX10 CPU6@
6 NGFF WLAN+BT
SA0000ACL40 CPU7@
X X X
B B
S5 S4/ Battery only
O 0 HDD 7
SA0000A3430 CPU8@
1 ODD 8
SA0000A3730 CPU9@
S5 S4/AC & Battery
don't exist X X X X 9
SA0000A3870 CPU10@
10
X7667538L01 S4G@
X7667538L02 M4G@
X7667538L06 M4G2@
EC SM Bus1 address X7672938L04 S4G2@
X7672938L05 H4G@
Device Address
Smart Battery 0001 011x
X7667538L03 JS2G@
X7667538L04 JM2G@
X7667538L05 JH2G@

PCH SM Bus address UC1 UC1 UC1 UC1 UC1 UC1 UC1

Device Address
DDR_JDIMM1 1010 000x A0h

CPU1@ CPU2@ CPU3@ CPU4@ CPU5@ CPU6@ CPU7@

CPU i7 6500U CPU i5 6200U CPU 4405U CPU 3855U CPU i5 6198DU CPU i7 6498DU CPU i3-6006U
SA000092P60 SA000092OA0 SA000094250 SA000093780 SA00009QZ10 SA00009QX10 SA0000ACL40
C C

SMBUS Control Table UC1 UC1 UC1

SOURCE GPU BATT NECP388 SODIMM SOC

CPU8@ CPU9@ CPU10@
SMB_EC_CK1 CPU i7-7500U CPU i5-7200U CPU i3-7100U

SMB_EC_DA1
NECP388 X V
+3VALW
X X X SA0000A3430 SA0000A3730 SA0000A3870
+3VALW ZZZ ZZZ
SMB_EC_CK2
SMB_EC_DA2
NECP388
+3VGS
V X X X V
+3VALW
+3VS
PCH_SMBCLK
PCH
PCH_SMBDATA +3VALW
X X X V
+3VS
X 14@ 15@
PCB PCB
DA6001KC320 DA6001KC220
PCH_SML0CLK
PCH
PCH_SML0DATA +3VALW
X X X X X UV1 UV1

SML1CLK
SML1DATA
PCH
+3VALW
V
+3VGS
X V
+3VS
X X
M1@ M2@
VGA VGA
SA000087TA0 SA000098VA0
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V(RAM) +VS Clock ZZZ ZZZ ZZZ ZZZ ZZZ

D Full ON HIGH HIGH HIGH HIGH ON ON ON ON D

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S4G@ M4G@ M4G2@ S4G2@ H4G@
4G SAMSUNG 2133 4G MICRON 2133 4G MICRON 2400 4G Samsung 2400 4G Hynix 2400
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF X7667538L01 X7667538L02 X7667538L06 X7672938L04 X7672938L05

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

Security Classification Compal Secret Data Compal Electronics, Inc.
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LA-D562P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 10, 2017 Sheet 3 of 52
1 2 3 4 5
 5 4 3 2 1

M1-70 VRAM STRAP Power-Up/Down Sequence

X76@ X76@ "M1" has the following requirements with regards to power-supply
Vendor R_pu R_pd sequencing to avoid damaging the ASIC:
UV3, UV4, UV5, UV6
ID PS_3[ 3 ] PS_3[ 2 ] PS_3[ 1 ] ‧All the ASIC supplies must reach their respective nominal voltages within 20ms
RV21 RV24
of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.
Samsung 4096Mbits 2GBytes The maximum slew rate on all rails is 50 mV/μ s.
JS2G@ SA000076P80
D 256MX16 K4W4G1646E-BC1A 0 0 0 0 NC 4.75K ‧It is recommended that the 3.3-V rail ramp up frist. D
X7667538L03 ‧It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later
Micron 4096Mbits 2GBytes than 2ms from the start of VDDC ramping up.
JM2G@ SA00009HF00 The power rails that are shared with other components on the system should be gated for
256Mx16 MT41J256M16LY-091G:N 1 0 0 1 8.45K 2K ‧
X7667538L04 the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state),
Hynix 4096Mbits 2GBytes all the power rails are removed from the dGPU.
JH2G@ SA00008DN00 The gate circuits must meet the slew rate requirement (such as ≦ 50mV/us)
256MX16 H5TC4G63CFR-N0C 2 0 1 0 4.53K 2K
X7667538L05 ‧VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
‧For power down, reversing the ramp-up sequence is recommended.
4 1 0 0 4.53K 4.99K

5 1 0 1 3.24K 5.62K

6 1 1 0 3.4K 10K

ZZZ ZZZ ZZZ VDDR3(+3VGS)

C
PCIE_VDDC(+0.95VGS) C

JH2G@ JM2G@ JS2G@

2G HYNIX 2G MICRON 2G SAMSUNG
X7667538L05 X7667538L04 X7667538L03
VDD_CT(+1.8VGS)

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

DGPU_PWROK

PERSTb

REFCLK

Straps Reset
B B

Straps Valid

Global ASIC Reset

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 4 of 52

5 4 3 2 1
 A B C D E

1 1

UC1A SKL-U
Rev_1.0
E55 C47
DDI1_TXN[0] EDP_TXN[0] EDP_TXN0 [27]
F55 C46
DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 [27]
E58 D46
DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 [27]
F58 C45
DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 [27]
F53 A45
DDI1_TXN[2] EDP_TXN[2]
G53
DDI1_TXP[2] EDP_TXP[2]
B45 <eDP>
F56 A47
G56 DDI1_TXN[3] EDP_TXN[3] B47
DDI1_TXP[3] EDP_TXP[3]
C50 E45 EDP_AUXN [27]
[28] HDMI_TX2-_CK DDI2_TXN[0] DDI EDP_AUXN
D50 EDP F45
[28] HDMI_TX2+_CK DDI2_TXP[0] EDP_AUXP EDP_AUXP [27]
C52
[28] HDMI_TX1-_CK DDI2_TXN[1]
D52 B52
[28] HDMI_TX1+_CK DDI2_TXP[1] EDP_DISP_UTIL
<HDMI> [28] HDMI_TX0-_CK
A50
DDI2_TXN[2]
B50 G50
[28] HDMI_TX0+_CK DDI2_TXP[2] DDI1_AUXN
D51 F50
[28] HDMI_CLK-_CK DDI2_TXN[3] DDI1_AUXP
C51 E48
[28] HDMI_CLK+_CK DDI2_TXP[3] DDI2_AUXN F48
DDI2_AUXP G46
DISPLAY SIDEBANDS RSVD F46
L13 RSVD
L12 GPP_E18/DDPB_CTRLCLK L9
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 From HDMI
GPP_E14/DDPC_HPD1 TMDS_B_HPD [28]
N7 L6
[28] HDMICLK_NB GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2
HDMI DDC (Port C) [28] HDMIDAT_NB
N8
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3
N9
EC_SCI# [9,33] From eDP
L10
GPP_E17/EDP_HPD EDP_HPD [27]
N11
N12 GPP_E22 R12
2 GPP_E23 EDP_BKLTEN ENBKL [27,33] 2
R11
EDP_COMP EDP_BKLTCTL INVPWM [27]
E52 1 OF 20 U13
EDP_RCOMP EDP_VDDEN PCH_ENVDD [27]

+1.0VS_VCCIO < Compensat i on P UFor e DP > SKL-U_BGA1356

@

1 2 EDP_COMP
RC3 24.9_0402_1%

Trace width=20 mils, Spacing=25mil, Max length=100mils

+1.0VS_VCCIO
1

UC1D SKL-U
RC4 Rev_1.0
SOC_CATERR# D63
1K_0402_5%
H_PECI T99 TP@
A54 CATERR# < PU/PD for CMC Debug > +1.0VS_VCCIO
[33] H_PECI H_PROCHOT#_R PECI
C65 JTAG
H_PROCHOT#_R H_THERMTRIP# PROCHOT#
2

1 2 C63
[33] H_PROCHOT# SOC_OCC# THERMTRIP# SOC_XDP_TMS
RC6 499_0402_1% A65 RC11 1 @ 2 51_0402_5%
T100 TP@ SKTOCC# CPU_XDP_TCK0
CPU MISC B61
XDP_BPM#0 C55 PROC_TCK D60 SOC_XDP_TDI SOC_XDP_TDI RC12 1 @ 2 51_0402_5%
T103 TP@ XDP_BPM#1 BPM#[0] PROC_TDI SOC_XDP_TDO
T105 TP@ D55 A61
+1.0V_VCCST XDP_BPM#2 B54 BPM#[1] PROC_TDO C60 SOC_XDP_TMS SOC_XDP_TDO RC13 1 @ 2 51_0402_5%
T107 TP@ XDP_BPM#3 BPM#[2] PROC_TMS SOC_XDP_TRST#
C56 B59
T109 TP@ BPM#[3] PROC_TRST#
1 2 H_THERMTRIP# T111 TP@
SOC_GPIOE3 A6 B56 PCH_JTAG_TCK1
RC5 1K_0402_5% A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI CPU_XDP_TCK0 RC14 1 @ 2 51_0402_5%
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 SOC_XDP_TDO
SOC_GPIOB4 AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 SOC_XDP_TMS PCH_JTAG_TCK1 RC15 1 @ 2 51_0402_5%
T115 TP@ GPP_B4/CPU_GP3 PCH_JTAG_TMS PCH_XDP_TRST#
C61 T116 TP@
3 RC7 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 PCH_TRST# A59 CPU_XDP_TCK0 3
RC8 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
RC9 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP SOC_XDP_TRST# RC23 1 2 51_0402_5%
RC10 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
4 OF 20
SKL-U_BGA1356
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(1/12)DDI,EDP,MISC,CMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

LA-D562P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 10, 2017 Sheet 5 of 52
A B C D E
 5 4 3 2 1

Interleaved Memory

D D

SKL-U
UC1B SKL-U UC1C
Rev_1.0 Rev_1.0
[17] DDR_A_D[0..15] DDR_A_D0 DDR_A_CLK#0
AL71 AU53 DDR_A_CLK#0 [17]
DDR_A_D1 DDR0_DQ[0] DDR0_CKN[0] DDR_A_CLK0 [18] DDR_B_D[0..15] DDR_B_D0 Interleave / Non-Interleaved DDR_B_CLK#0
AL68 AT53 DDR_A_CLK0 [17] AF65 AN45 DDR_B_CLK#0 [18]
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_B_D1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1
DDR_A_D3 DDR0_DQ[2] DDR0_CKN[1] DDR_A_CLK1 @ T20 DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK0 DDR_B_CLK#1 [18]
AN69 AT55 @ T19 AK65 AP45 DDR_B_CLK0 [18]
DDR_A_D4 AL70 DDR0_DQ[3] DDR0_CKP[1] DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1
DDR_A_D5 DDR0_DQ[4] DDR_A_CKE0 DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 [18]
AL69 BA56 DDR_A_CKE0 [17,19]
AF66
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D7 DDR0_DQ[6] DDR0_CKE[1] @ T21 DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE1 DDR_B_CKE0 [18]
AN71 AW 56 AK67 AP55 DDR_B_CKE1 [18]
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[2] AY56 DDR_B_D7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR_A_D9 AR68 DDR0_DQ[8] DDR0_CKE[3] DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 [17,19] DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25] DDR_B_CS#0
AU68 AU43 @ T23 AH71 BB42 DDR_B_CS#0 [18]
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_B_D11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 [17,19] DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_ODT0 DDR_B_CS#1 [18]
AR69 AT43 @ T22 AF71 BA42 DDR_B_ODT0 [18]
DDR_A_D14 AU70 DDR0_DQ[13] DDR0_ODT[1] DDR_B_D13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW 42 DDR_B_ODT1
DDR_A_D15 DDR0_DQ[14] DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 [18]
AU69 AH70
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4
BA51 DDR_A_MA5 DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA9 DDR_A_MA5 [17,19] [18] DDR_B_D[16..31] DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4 DDR_B_MA5
BB54 DDR_A_MA9 [17,19]
AT66 AY48 DDR_B_MA5 [18]
[17] DDR_A_D[16..31] DDR_A_D16 Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR_B_D17 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA9
BB65 BA52 DDR_A_MA6 [17,19] AU66 AP50 DDR_B_MA9 [18]
DDR_A_D17 AW 65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_B_D18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_MA8 [17,19] DDR_B_D19 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA8 DDR_B_MA6 [18]
AW 63 AW 52 DDR_A_MA7 [17,19]
AN65 BB48 DDR_B_MA8 [18]
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_B_D20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 [17,19] DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_BG0 DDR_B_MA7 [18]
BA65 AW 54 DDR_A_MA12 [17,19]
AP66 AP52 DDR_B_BG0 [18]
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_B_D22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12
DDR_A_D22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_A_ACT# DDR_A_MA11 [17,19] DDR_B_D23 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR_B_MA11 DDR_B_MA12 [18]
BA63 BA55 M_A_ACT# [17,19] AU65 AN48 DDR_B_MA11 [18]
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_B_D24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 M_B_ACT#
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_MA13 @ T16 DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_BG1 M_B_ACT# [18]
BA61 AU46 DDR_A_MA13 [17,19] AU61 AN52 DDR_B_BG1 [18]
C DDR_A_D25 AW 61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 DDR_B_D26 AP60 DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] BA43 DDR_B_MA13 C
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA14 DDR_A_MA15 [17,19] DDR_B_D27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA15 DDR_B_MA13 [18]
BB59 AT46 DDR_A_MA14 [17,19] AN60 AY43 DDR_B_MA15 [18]
DDR_A_D27 AW 59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16 DDR_B_D28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_MA14
DDR_A_D28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_BA0 DDR_A_MA16 [17,19] DDR_B_D29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA16 DDR_B_MA14 [18]
BB61 AU52 DDR_A_BA0 [17,19]
AP61 AW 44 DDR_B_MA16 [18]
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_B_D30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BA0
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_BA1 DDR_A_MA2 [17,19] DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_MA2 DDR_B_BA0 [18]
BA59 AT48 DDR_A_BA1 [17,19]
AU60 AY47 DDR_B_MA2 [18]
DDR_A_D31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_MA10 [18] DDR_B_D[32..47] DDR_B_D32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_BA1
AY59 AT50 DDR_A_MA10 [17,19] AU40 BA44 DDR_B_BA1 [18]
[17] DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA1 DDR_B_D33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_MA10
AY39 BB50 DDR_A_MA1 [17,19] AT40 AW 46 DDR_B_MA10 [18]
DDR_A_D33 AW 39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_B_D34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1
DDR_A_D34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA0 [17,19] DDR_B_D35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR_B_MA0 DDR_B_MA1 [18]
AY37 AU37 BA46 DDR_B_MA0 [18]
DDR_A_D35 AW 37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR_A_D36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA4 DDR_A_MA3 [17,19] DDR_B_D37 DDR1_DQ[36]/DDR1_DQ[20] DDR_B_MA3
BB39 BB52 DDR_A_MA4 [17,19] AP40 BB46 DDR_B_MA3 [18]
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AM70 DDR_A_DQS#0 DDR_B_D38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] BA47 DDR_B_MA4
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS0 DDR_A_DQS#0 [17] DDR_B_D39 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4] DDR_B_MA4 [18]
BA37 AM69 DDR_A_DQS0 [17]
AR37
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_B_D40 AT33 DDR1_DQ[39]/DDR1_DQ[23]
DDR_A_D40 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] DDR_A_DQS1 DDR_A_DQS#1 [17] DDR_B_D41 DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved DDR_B_DQS#0
AY35 AT70 DDR_A_DQS1 [17]
AU33 AH66 DDR_B_DQS#0 [18]
DDR_A_D41 AW 35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0
DDR_A_D42 DDR0_DQ[41]/DDR1_DQ[9] DDR_B_D43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS#1 DDR_B_DQS0 [18]
AY33 AT30 AG69 DDR_B_DQS#1 [18]
DDR_A_D43 DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR_A_DQS#2 DDR_B_D44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS1
AW 33 BA64 DDR_A_DQS#2 [17]
AR33 AG70 DDR_B_DQS1 [18]
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2
DDR_A_D45 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#3 DDR_A_DQS2 [17] DDR_B_D46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_B_DQS2 DDR_B_DQS#2 [18]
BA35 AY60 DDR_A_DQS#3 [17]
AR30 AR65 DDR_B_DQS2 [18]
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3
DDR_A_D47 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS3 [17] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS3 DDR_B_DQS#3 [18]
BB33 BA38 DDR_A_DQS#4 [17] AR60 DDR_B_DQS3 [18]
[17] DDR_A_D[48..63] DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] DDR_A_DQS4 [18] DDR_B_D[48..63] DDR_B_D48 DDR1_DQSP[3]/DDR0_DQSP[7] DDR_B_DQS#4
AY31 AY38 DDR_A_DQS4 [17]
AU27 AT38 DDR_B_DQS#4 [18]
DDR_A_D49 AW 31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS4
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS5 DDR_A_DQS#5 [17] DDR_B_D50 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS#5 DDR_B_DQS4 [18]
AY29 BA34 DDR_A_DQS5 [17]
AT25 AT32 DDR_B_DQS#5 [18]
DDR_A_D51 AW 29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS5
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS6 DDR_A_DQS#6 [17] DDR_B_D52 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS5 [18]
BB31 AY30 DDR_A_DQS6 [17] AP27
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 DDR_B_D53 AN27 DDR1_DQ[52] AR25 DDR_B_DQS#6
DDR_A_D54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS7 DDR_A_DQS#7 [17] DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[6] DDR_B_DQS6 DDR_B_DQS#6 [18]
BA29 BA26 DDR_A_DQS7 [17] AN25 AR27 DDR_B_DQS6 [18]
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_A_D56 DDR0_DQ[55]/DDR1_DQ[39] DDR_B_D56 DDR1_DQ[55] DDR1_DQSN[7] DDR_B_DQS7 DDR_B_DQS#7 [18]
AY27 AW 50 DDR_A_ALERT# [17] AT22 AR21 DDR_B_DQS7 [18]
DDR_A_D57 AW 27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# AT52 DDR_B_D57 AU22 DDR1_DQ[56] DDR1_DQSP[7] AN43 DDR_B_ALERT#
DDR_A_D58 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR DDR_A_PARITY [17,19] DDR_B_D58 DDR1_DQ[57] DDR1_ALERT# DDR_B_PARITY DDR_B_ALERT# [18]
AY25 AU21 AP43 DDR_B_PARITY [18]
DDR_A_D59 AW 25 DDR0_DQ[58]/DDR1_DQ[42] DDR CH - A AY67 +0.6V_VREFCA Trace width/Spacing >= 20mils DDR_B_D59 AT21 DDR1_DQ[58] DDR1_PAR AT13 DDR_DRAMRST#
DDR_A_D60 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA +0.6V_VREFCA [17] Place componment near SODIMM DDR_B_D60 DDR1_DQ[59] DRAM_RESET# DDR_DRAMRST# [17,18]
B BB27 AY68 @ T25
AN22 DDR CH - B AR18 B
DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67 +0.6V_B_VREFDQ DDR_B_D61 AP22 DDR1_DQ[60] DDR_RCOMP[0] AT18
DDR_A_D62 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ +0.6V_B_VREFDQ [18] DDR_B_D62 DDR1_DQ[61] DDR_RCOMP[1] SM_RCOMP0
BA25 AP21 AU18 RC16 1 2 121_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW 67 DDR_PG_CTRL DDR_B_D63 AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2] SM_RCOMP1 RC17 1 2 80.6_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL #543016 PDG0.9 P.163 RC place near SODIMM DDR1_DQ[63] SM_RCOMP2 RC18 1 2 100_0402_1%
SKL-U_BGA1356 SKL-U_BGA1356
#543016 PDG0.9 P.117
@ @ W=12-15 Space= 20/25 L=500mil

+1.2V

+1.2V +3VS +3VALW

1
< For ODT & VTT Power Control > RC20
DDR_VTT_CNTL to DDR 470_0402_5%
VTT supplied ramped @

CRB ORB
1

<35uS 1

2
(tCPU18) CC1
0.1U_0201_10V6K RC132 RC19 @ DDR_DRAMRST#
220K_0402_5% 100K_0402_5%
UC2 2
2

1 5
NC VCC
DDR_PG_CTRL 2
A 4
Y DDR_VTT_PG_CTRL [42]
3
GND
74AUP1G07GW_TSSOP5
SA00007WE00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/29 Deciphered Date 2016/01/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(2/12)DDR3L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Dat e: Monday, April 10, 2017 Sheet 6 of 52

5 4 3 2 1
 5 4 3 2 1

SMBALERT# (Internal Pull Down): SML0ALERT# (Internal Pull Down):

0 = Disable Intel ME TLS function ==> Default eSPI or LPC

1 = Enable Intel ME TLS function 0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

D UC1E SKL-U D
+3VALW Rev_1.0
SPI - FLASH
SMBUS, SMLINK
RC126 1 2 10K_0402_5% KB_RST# SOC_SPI_CLK AV2 R7 SOC_SMBCLK
SMB
SOC_SPI_SO SPI0_CLK GPP_C0/SMBCLK SOC_SMBDATA SOC_SMBCLK [18]
AW3 R8
SOC_SPI_SI SPI0_MISO GPP_C1/SMBDATA SOC_SMBALERT# SOC_SMBDATA [18] (Link to DDR)
AV3 R10 TP@ T124
RC21 1 @ 2 1K_0402_5% SOC_SPI_IO2 SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C2/SMBALERT#
SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK
SOC_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SOC_SML0DATA
RC22 1 @ 2 1K_0402_5% SOC_SPI_IO3 AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SOC_SML0ALERT#
SPI0_CS1# GPP_C5/SML0ALERT# TP@ T125
AU1
SPI0_CS2# EC_SMB_CK2
GPP_C6/SML1CLK
W3
V3 EC_SMB_DA2 EC_SMB_CK2 [21,33] SML1
GPP_C7/SML1DATA SOC_SML1ALERT# EC_SMB_DA2 [21,33]
SPI - TOUCH AM7 (Link to EC,DGPU)
M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2 AY13 LPC_AD0
GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 [33]
M1 LPC BA13
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 [33]
BB13
GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 [33]
AY12
C LINK GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3 [33]
BA12
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# [33]
G3 BA11
G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
G1 CL_DATA
CL_RST# AW9 LPC_CLK0 RC26 1 EMI@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CK_LPC_KBC [33]
AY9
KB_RST# AW13 GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN#
[33] KB_RST# GPP_A0/RCIN# GPP_A8/CLKRUN#
C C

[33] SERIRQ SERIRQ AY11

GPP_A6/SERIRQ 5 OF 20
+1.8VS_3VS_PGPPA
SKL-U_BGA1356
@
RC25 1 2 8.2K_0402_5% SERIRQ +3VS

RPC1, RPC3 and RC30 are close to UC3 SOC_SML1ALERT# RC54 2 1 150K_0402_5%
< SPI ROM - 8M > +3VALW
@

RPC1 SOC_SML0CLK RC28 1 2 499_0402_1%

SOC_SPI_SO 1 8 SOC_SPI_SO_0_R @
SOC_SPI_IO2 2 7 SOC_SPI_IO2_0_R UC3 CC2 1 2 0.1U_0201_10V6K SOC_SML0DATA RC29 1 2 499_0402_1%
SOC_SPI_SI 3 6 SOC_SPI_SI_0_R SOC_SPI_CS#0 1 8
SOC_SPI_IO3 4 5 SOC_SPI_IO3_0_R SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R
From CPU 33_0804_8P4R_5% 4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R SOC_SMBCLK 1
RPC2
8
EMI@ GND DI(IO0) SOC_SMBDATA 2 7
1
SOC_SPI_CLK 1 2 SOC_SPI_CLK_0_R W 25Q64FVSSIQ_SO8 EC_SMB_CK2 3 6
B RC30 EMI@ 33_0402_5% CC3 EC_SMB_DA2 4 5 B

10P_0402_50V8J
2 @EMI@ 1K_0804_8P4R_5%

RPC3
EC_SPI_CLK 1 8 SOC_SPI_CLK_0_R +1.8VS_3VS_PGPPA
[33] EC_SPI_CLK EC_SPI_MOSI SOC_SPI_SI_0_R
2 7
[33] EC_SPI_MOSI EC_SPI_CS0# SOC_SPI_CS#0
From EC 3 6
[33] EC_SPI_CS0# EC_SPI_MISO SOC_SPI_SO_0_R PM_CLKRUN#
4 5 1 @ 2
[33] EC_SPI_MISO
RC31 8.2K_0402_5%
33_0804_8P4R_5%
EMI@ Follow 543016_SKL_U_Y_PDG_0_9

A A

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(3/12)SPI,SMB,LPC,ESPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 7 of 52

5 4 3 2 1
 5 4 3 2 1

< HD AUDIO >

RPC4
1 8 HDA_BIT_CLK
[35] HDA_BITCLK_AUDIO HDA_SYNC
[35] HDA_SYNC_AUDIO 2 7
3 6 ME_EN
[35] HDA_SDOUT_AUDIO HDA_RST#
[35] HDA_RST_AUDIO# 4 5
D D
33_0804_8P4R_5%
EMI@

UC1G SKL-U
Rev_1.0
AUDIO

HDA_SYNC BA22
HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
ME_EN BB22 HDA_BLK/I2S0_SCLK
< To Enable ME Override > [33] ME_EN
BA21 HDA_SDO/I2S0_TXD
SDIO / SDXC
[35] HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 RC109 2 @ 1 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
D8 AF13
C C8 GPP_D17/DMIC_CLK1 GPP_F23 C
GPP_D18/DMIC_DATA1
HDA_SPKR AW5
[35] HDA_SPKR GPP_B14/SPKR
7 OF 20

SKL-U_BGA1356
@

+3VS
UC1I SKL-U
Rev_1.0
CSI-2
1 @ 2 HDA_SPKR
RC33 2.2K_0402_5% A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
CSI2_DP1 CSI2_CLKP1
SPKR (Internal Pull Down): C36
D36 CSI2_DN2 CSI2_CLKN2
C29
D29
A38 CSI2_DP2 CSI2_CLKP2 B26
TOP Swap Override B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
B C31 E13 RC117 2 @ 1 100_0402_1% B
0 = Disable TOP Swap mode. ==> Default D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
CSI2_DN5
1 = Enable TOP Swap Mode. D33
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 RC116 2 @ 1 200_0402_1%
EMMC_RCOMP
SKL-U_BGA1356
@

A A

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 8 of 52

5 4 3 2 1
 5 4 3 2 1

SOC_XTAL24_IN

SOC_XTAL24_OUT
+3VS 1 2
RC34 1M_0402_5%
UC1J SKL-U
Rev_1.0
CLOCK SIGNALS YC1
24MHZ_12PF_7V24000020
D42
RPC6 [20] CLK_PCIE_GPU# CLKOUT_PCIE_N0
EC_SCI# DGPU [20] CLK_PCIE_GPU GPUCLK_REQ#
C42
CLKOUT_PCIE_P0
3
3 1
1
8 1 AR10

15P_0402_50V8J

15P_0402_50V8J
WLANCLK_REQ# EC_SCI# [5,33] [21] GPUCLK_REQ# GPP_B5/SRCCLKREQ0# GND GND
7 2
6 3 B42

CC4

CC5
[34] CLK_PCIE_LAN# CLKOUT_PCIE_N1
D
5 4 LANCLK_REQ#
LAN [34] CLK_PCIE_LAN LANCLK_REQ#
A42
CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
F43 4 2
D
[34] LANCLK_REQ# AT7 E43
10K_0804_8P4R_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17 SUSCLK
[30] CLK_PCIE_WLAN# CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK [30]
NGFF WL+BT(KEY E) [30] CLK_PCIE_WLAN WLANCLK_REQ#
C41
CLKOUT_PCIE_P2 SOC_XTAL24_IN
RC61 1 UMA@ 2 10K_0402_5% [30] WLANCLK_REQ# AT8 E37
GPP_B7/SRCCLKREQ2# XTAL24_IN
XTAL24_OUT
E35 SOC_XTAL24_OUT YC1 need to be replaced by
GPUCLK_REQ#
1 PX@ 2 D40
CLKOUT_PCIE_N3 XCLK_BIASREF
38.4MHz (30ohm ESR) XTAL for Cannonlake-U
RC55 10K_0402_5% C40 E42
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5_F24NS
GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1
B40 RTCX1 AM20 SOC_RTCX2 XCLK_BIASREF 1 2
A40 CLKOUT_PCIE_N4 RTCX2 RC35 2.7K_0402_1%
AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST# 1 @ 2
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST# RC110 60.4_0402_1%
E40 RTCRST#
E38 CLKOUT_PCIE_N5
AU7 CLKOUT_PCIE_P5
+3VL_RTC GPP_B10/SRCCLKREQ5#
Follow 546765_2014WW48_Skylake_MOW_Rev_1_0
10 OF 20
SOC_SRTCRST#
RC36 1 2 20K_0201_5% Stuff 2.7k ohm(RC35) PU for Skylake-U
SKL-U_BGA1356
CC6 1 2 1U_0402_6.3V6K @ Stuff 60.4 ohm(RC110) PD for Cannonlake-U

RC38
RC37 1 2 20K_0402_5% SOC_RTCRST# 1 2
EC_CLEAR_CMOS# [33]
1 2 SOC_RTCX2
CC7 1U_0402_6.3V6K
0_0402_5% < PCH PLTRST Buf f er >
CLRP2 1 2 SHORT PADS CLR CMOS RS@
RC42 1 RS@ 2 0_0402_5%
SOC_RTCX1
RC39 1 2 1M_0402_5% SM_INTRUDER#
C +3VS 1 2 C
RC41 10M_0402_5%

5
UC4
SOC_PLTRST# 1 YC2
B

P
4 1 2
Y PCIRST# [20,30,33,34]
2
A

G
32.768KHZ 9PF 20PPM 9H03280012

1
TC7SH08FUF_SSOP5

1
@

RC44
100K_0402_5%
1 1
+3VALW CC8
100P_0402_50V8J CC9 CC10

2
4.7P_0402_50V8B 4.7P_0402_50V8B
RPC7 ESD@ 2 2

2
8 1 PCH_PWROK
7 2 EC_RSMRST#
6 3 LAN_WAKE#
5 4 SYS_RESET#

10K_0804_8P4R_5%

ESD
UC1K SKL-U
EC_RSMRST# RC115 1 @ 2 0_0402_5% PCH_DPWROK Rev_1.0
ESD@ 1 2 SYS_RESET# SYSTEM POWER MANAGEMENT
CC97 100P_0402_50V8J AT11 PM_SLP_S0#
EC_RSMRST# GPP_B12/SLP_S0# PM_SLP_S3# TP@T130
ESD@ 1 2 AP15
SOC_PLTRST# GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# [33]
CC94 100P_0402_50V8J AN10 BA16
SYS_PWROK SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# [33,40,42]
ESD@ 1 2 B5 AY16 TP@T135
CC95 100P_0402_50V8J EC_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5#
[33] EC_RSMRST# RSMRST# AN15
SLP_SUS#
Only For Power Sequence Debug T132 TP@
H_CPUPWRGD
EC_VCCST_PG
A68
PROCPWRGD SLP_LAN#
AW15
SLP_WLAN#
B B65 BB17 TP@T133
B
VCCST_PWRGD GPD9/SLP_WLAN# AN16 PM_SLP_A#
SYS_PWROK GPD6/SLP_A# TP@T134
B6
[33] SYS_PWROK PCH_PWROK SYS_PWROK PBTN_OUT#
BA20 BA15
[33] PCH_PWROK PCH_DPWROK PCH_PWROK GPD3/PWRBTN# AC_PRESENT RC103 PBTN_OUT# [33]
BB20 AY15 1 @ 2 0_0402_5%
+3VALW DSW_PWROK GPD1/ACPRESENT PM_BATLOW# VCIN1_AC_IN [21,33,40]
AU13
SUSWARN# AR13 GPD0/BATLOW#
T138 TP@ GPP_A13/SUSWARN#/SUSPWRDNACK +3VALW
1 2 WAKE# AP11
RC47 1K_0402_5% GPP_A15/SUSACK# AU11
WAKE# BB15 GPP_A11/PME# AP16 SM_INTRUDER#
LAN_WAKE# AM15 WAKE# INTRUDER# PM_BATLOW# 1 2
AW17 GPD2/LAN_WAKE# AM10 RC46 8.2K_0402_5%
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT#
GPD7/RSVD 11 OF 20 GPP_B2/VRALERT#
SOC_VRALERT# 1 @ 2
SKL-U_BGA1356
@
DVT delete 10K PU for DDR layout RC50 10K_0402_5%

+1.0V_VCCST
From EC (Open-Drain)
1

RC52
1K_0402_5%

EC_VCCST_PG
2

A RC53 1 2 60.4_0402_1% A
[33] VCCST_PWRGD

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(5/12)CLK,PM,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 9 of 52

5 4 3 2 1
 5 4 3 2 1

SKL KBL
RAM vender OBRAM_ID0 OBRAM_ID1 RAM vender OBRAM_ID0 OBRAM_ID1
Samsung K4A8G165WB-BCPB 0 0 Samsung K4A8G165WB-BCRC 0 0
Micron MT40A512M16HA-083E:A 0 1 Micron MT40A512M16JY-083E:B 0 1
Micron MT40A512M16JY-083E:B Hynix H5AN8G6NAFR-UHC 1 0
1 0 1 1
1 1 +3VS +3VS
D D

1
RC135 RC133
10K_0402_5% 10K_0402_5%
X76RAM@ X76RAM@
GSPI0_MOSI (Internal Pull Down): OBRAM_ID0 OBRAM_ID1

2
No Reboot

1
RC136 RC134
0 = Disable No Reboot mode. ==> Default
10K_0402_5% 10K_0402_5%
X76RAM@ X76RAM@
1 = Enable No Reboot Mode. (PCH will disable the TCO
Timer system reboot feature). This function is useful

2
when running ITP/XDP.

GSPI1_MOSI (Internal Pull Down):

UC1F SKL-U
Boot BIOS Strap Bit
Rev_1.0
LPSS ISH
0 = SPI Mode ==> Default
AN8 P2
+3VS 1 = LPC Mode OBRAM_ID0 AP7 GPP_B15/GSPI0_CS# GPP_D9 P3
OBRAM_ID1 AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1
1 @ 2 GSPI0_MOSI GPP_B18/GSPI0_MOSI GPP_D12
RC59 2.2K_0402_5% AM5 M4
1 @ 2 GSPI1_MOSI AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
RC60 2.2K_0402_5% AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
AB1 GPP_D8/ISH_I2C1_SCL +3VS
C AB2 GPP_C8/UART0_RXD AD11 C
W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
WLBT_OFF# AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
[30] WLBT_OFF# GPP_C11/UART0_CTS#
1 2 UART_2_CRXD_DTXD UART_2_CRXD_DTXD AD1 U1
[30] UART_2_CRXD_DTXD UART_2_CTXD_DRXD GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
RC67 49.9K_0402_1% AD2 U2
UART_2_CTXD_DRXD [30] UART_2_CTXD_DRXD GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
1 2 AD3 U3
RC66 49.9K_0402_1% AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 RPC8
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# DGPU_PWR_EN 1 8
AC1 DGPU_PWR_EN DGPU_HOLD_RST# 2 7
GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_HOLD_RST# DGPU_PWR_EN [22,33,48] DGPU_PWROK
U7 AC2 3 6
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD DGPU_PWROK DGPU_HOLD_RST# [20] WLBT_OFF#
U6 AC3 DGPU_PWROK [48] 4 5
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 DGPU_PRSNT#
U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS# 10K_0804_8P4R_5%
U9 GPP_C18/I2C1_SDA AY8
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
BA8 DGPU_PRSNT# PD for DIS SKU
AH9 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
AF11
AF12 GPP_F8/I2C4_SDA Funct i on GPPA12
GPP_F9/I2C4_SCL 6 OF 20 UMA 1
SKL-U_BGA1356 DIS 0
@
+3VS

RC1281 UMA@ 2 10K_0402_5% DGPU_PRSNT#

RC1291 2 10K_0402_5%
PX@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(6/12)GPIO,I2C,GSPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 10 of 52

5 4 3 2 1
 5 4 3 2 1

UC1H SKL-U
Rev_1.0

SSIC / USB3
PCIE / USB3 / SATA
D H8 D
USB3_1_RXN G8
PCIE_CRX_GTX_N1 H13 USB3_1_RXP C13
[20] PCIE_CRX_GTX_N1 PCIE1_RXN/USB3_5_RXN USB3_1_TXN
[20] PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 G13 D13
CC11 PX@ 1 2 0.1U_0201_10V6K PCIE_CTX_GRX_N1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP
[20] PCIE_CTX_C_GRX_N1 PCIE_CTX_GRX_P1 PCIE1_TXN/USB3_5_TXN
[20] PCIE_CTX_C_GRX_P1 CC14 PX@ 1 2 0.1U_0201_10V6K A17 J6 USB3_RX_N2 [32]
PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6
PCIE_CRX_GTX_N2 USB3_2_RXP / SSIC_RXP USB3_RX_P2 [32]
[20] PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2
G11
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN
B13
A13
USB3_TX_N2 [32] USB2/3 MB(Left)
[20] PCIE_CRX_GTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_TX_P2 [32]
CC15 PX@ 1 2 0.1U_0201_10V6K PCIE_CTX_GRX_N2 D16
[20] PCIE_CTX_C_GRX_N2 CC16 PX@ 1 2 0.1U_0201_10V6K PCIE_CTX_GRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
[20] PCIE_CTX_C_GRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN H10
USB3_3_RXP
dGPU [20] PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3
H16
PCIE3_RXN USB3_3_TXN
B15
G16 A15
[20] PCIE_CRX_GTX_P3 CC17 PX@ 1 2 0.1U_0201_10V6K PCIE_CTX_GRX_N3 D17 PCIE3_RXP USB3_3_TXP
[20] PCIE_CTX_C_GRX_N3 PCIE3_TXN
CC18 PX@ 1 2 0.1U_0201_10V6K PCIE_CTX_GRX_P3 C17 E10
[20] PCIE_CTX_C_GRX_P3 PCIE3_TXP USB3_4_RXN F10
PCIE_CRX_GTX_N4 G15 USB3_4_RXP C15
[20] PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 F15 PCIE4_RXN USB3_4_TXN D15
[20] PCIE_CRX_GTX_P4 CC101 PX@ 1 2 0.1U_0201_10V6K PCIE_CTX_GRX_N4 B19 PCIE4_RXP USB3_4_TXP
[20] PCIE_CTX_C_GRX_N4 PCIE_CTX_GRX_P4 PCIE4_TXN
CC102 PX@ 1 2 0.1U_0201_10V6K A19 AB9
[20] PCIE_CTX_C_GRX_P4 PCIE4_TXP USB2N_1 AB10
PCIE_CRX_DTX_N5 F16 USB2P_1
[34] PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 E16 PCIE5_RXN AD6 USB20_N2
PCIE5_RXP USB2N_2 USB20_N2 [32]
LAN
[34] PCIE_CRX_DTX_P5 2 0.1U_0201_10V6K PCIE_CTX_DRX_N5 USB20_P2
[34] PCIE_CTX_C_DRX_N5
CC19
CC20
1
1 2 0.1U_0201_10V6K PCIE_CTX_DRX_P5
C19
D19 PCIE5_TXN USB2P_2
AD7
USB20_P2 [32] USB 3.0
[34] PCIE_CTX_C_DRX_P5 PCIE5_TXP AH3
PCIE_CRX_DTX_N6 G18 USB2N_3 AJ3
[30] PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PCIE6_RXN USB2P_3
[30] PCIE_CRX_DTX_P6 F18
PCIE6_RXP
C NGFF WLAN+BT [30] PCIE_CTX_DRX_N6
PCIE_CTX_DRX_N6
PCIE_CTX_DRX_P6
D20
PCIE6_TXN USB2N_4
AD9 USB20_N4
USB20_P4 USB20_N4 [32]
C

[30] PCIE_CTX_DRX_P6
C20
PCIE6_TXP USB2P_4
AD10
USB20_P4 [32] USB 2.0
F20 AJ1 USB20_N5
[29] SATA_CRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 [27]
E20
PCIE7_RXP/SATA0_RXP USB2P_5
AJ2
USB20_P5 [27] Camera
HDD
[29] SATA_CRX_DTX_P0 B21 USB2
[29] SATA_CTX_DRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
[29] SATA_CTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_P6 USB20_N6 [36]
G21 USB2P_6
AF7
USB20_P6 [36] Card Reader
[29] SATA_CRX_DTX_N1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 [30]
ODD
[29] SATA_CRX_DTX_P1 USB20_P7
[29] SATA_CTX_DRX_N1
D21
C21 PCIE8_TXN/SATA1A_TXN USB2P_7
AH2
USB20_P7 [30] NGFF WLAN+BT
[29] SATA_CTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
E23 PCIE9_RXN USB2P_8
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC70 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID RC62 1 2 1K_0402_5%
RC71 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC63 1 2 1K_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
GPP_E9/USB2_OC0# USB_OC0# [32]
When PCIE8/SATA1A is used T147 TP@
XDP_PRDY#
XDP_PREQ#
D56
PROC_PRDY# GPP_E10/USB2_OC1#
C9 USB_OC1#
USB_OC2#
as SATA Port 1 (ODD), then T148 TP@ D61
BB11 PROC_PREQ# GPP_E11/USB2_OC2#
D9
B9 USB_OC3#
B PCIE11/SATA1B (M.2 SSD) GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
cannot be used as SATA E28
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0
J1
Port 1. E27
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1
J2
J3
EC_W L_OFF# [30]
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
E30 PCIE11_TXP/SATA1B_TXP H2
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 EC pin 72 change to PCH GPP_E5
B25 PCIE12_TXN/SATA2_TXN
PCIE12_TXP/SATA2_TXP
GPP_E2/SATAXPCIE2/SATAGP2
H1 PCH_SATALED#
need to check with BIOS
8 OF 20 GPP_E8/SATALED# +3VALW

SKL-U_BGA1356
@ RPC9
USB_OC3# 8 1
USB_OC0# 7 2
USB_OC1# 6 3
USB_OC2# 5 4

10K_0804_8P4R_5%

+3VS

PCH_SATALED# 1 2
A
RC112 10K_0402_5% A

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 11 of 52

5 4 3 2 1
 5 4 3 2 1

+1.2V +1.0VS_VCCIO
UC1N SKL-U
Rev_1.0
+5VALW +1.0VALW CPU POWER 3 OF 4
AU23 AK28
+1.0V_VCCST AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
VDDQ_AU35 VCCIO
I(Max) : 0.16 A(+1.0V_VCCST)
+1.0VALW TO +1.0V_VCCST
AU42 AL42

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 VDDQ_AU42 VCCIO
RON(Max) : 25 mohm BB23 AM28

CC21

CC22
BB32 VDDQ_BB23 VCCIO AM30
D
@
V drop : 0.004 V BB41 VDDQ_BB32 VCCIO AM42 +VCCSA
D

0.1U_0201_10V6K
2 2 1 VDDQ_BB41 VCCIO
+1.0VS_VCCIO BB47

CC23
BB51 VDDQ_BB47 AK23
VDDQ_BB51 VCCSA AK25
UC5 2 VCCSA G23
1 14 +1.0V_VCCST AM40 VCCSA G25
2 VIN1 VOUT1 13 VDDQC VCCSA G27
VIN1 VOUT1 A18 VCCSA G28
VCCST VCCSA
RC74 1 RS@ 2 0_0402_5% EN_1.0V_VCCSTU 3
ON1 CT1
12 1 2 Follow 543977_SKL_PDDG_Rev0_91 VCCSA
J22
[33,37,42] SYSON CC24 CC24 10PF ->22us(Spec:<= 65us) A22
VCCSTG_A22 VCCSA
J23
4 11 10P_0402_50V8J J27
VBIAS GND AL23 VCCSA K23
RC75 1 RS@ 2 0_0402_5% EN_1.8VS 5 10 1 2 VCCPLL_OC VCCSA K25
[33,37,42] SUSP# ON2 CT2 CC25 K20 VCCSA K27
6 9 1000P_0402_50V7K K21 VCCPLL_K20 VCCSA K28

0.1U_0402_25V6

0.1U_0402_25V6
1 +1.8VALW VIN2 VOUT2 VCCPLL_K21 VCCSA

1
7 8 K30

CC88

CC89
@ @ VIN2 VOUT2 +1.8VS VCCSA
15 AM23
GPAD VCCIO_SENSE
2

2
AM22
VSSIO_SENSE
+1.8VALW TO +1.8VS
EM5209VF_DFN14_2X3
H21 VSSSA_SENSE

1U_0402_6.3V6K

0.1U_0201_10V6K
1 1 VSSSA_SENSE VSSSA_SENSE [45]
H20 VCCSA_SENSE

CC26

CC27
VCCSA_SENSE VCCSA_SENSE [45]
14 OF 20
@
2 I(Max) : 0.2 A(+1.8VS) 2 SKL-U_BGA1356 Trace Length Match < 25 mils
RON(Max) : 25 mohm @
V drop : 0.005 V
C C

+1.0VALW TO +1.0VS_VCCIO
+1.0V_VCCST +1.0VS_VCCIO
+5VALW +1.0VALW I(Max) : 3.04 A(+1.0VS_VCCIO)
RON(Max) : 6.2 mohm PSC Side BSC Side
V drop : 0.019 V
0.1U_0201_10V6K

1U_0402_6.3V6K

1 1
CC30

CC32

UC6
@ 1 +1.0VS_VCCIO

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2 2 VIN1 1 1 1
2
VIN2

CC28

CC34

CC35
7 6 +1.0VS_VCCIO_STG RC79 1 RS@ 2 0_0805_5% @
VIN thermal VOUT 2 2 2
3 1
VBIAS
SUSP# RC81 1 RS@ 2 0_0402_5% 4 5 CC33
ON GND @ 0.1U_0201_10V6K
B 2 B
0.1U_0402_25V6

Close to A18 Close to K20 Close to A22

1

TPS22961DNYR_W SON8
CC90

@
2

+1.0VS_VCCIO +1.2V

BSC Side PSC Side BSC Side PSC Side BSC Side
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC37

CC38

CC49

CC50
CC36

CC39

CC40

CC41

CC42

CC29

CC43

CC44

CC45

CC46

CC47

CC48
@ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Underneath CPU Close to CPU Close to AL23 Close to AM40 Close to CPU Underneath CPU
A A

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(8/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 12 of 52

5 4 3 2 1
 5 4 3 2 1

Follow 543016_SKL_U_Y_PDG_1_0
D +1.0VALW +1.0V_APLL D
+1.0VALW +1.0VALW +1.8VALW
+1.0V_PRIM_CORE UC1O SKL-U
LC1 Rev_1.0 +3VALW
MURATA BLM15EG221SN1D CPU POWER 4 OF 4
1 2 CC51 1 2 1U_0402_6.3V6K AB19
SM01000HC00 RC83 1 RS@ 2 0_0805_5% AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3V_1.8V_PGPPA
R_0402 RF@ 1 @ P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16
CC52
Imax : 2.57A AF18 VCCPGPPC Y15

1U_0402_6.3V6K
1 +1.0V_PRIM_CORE VCCPRIM_CORE VCCPGPPD
0.1U_0201_10V K X5R AF19 T16
2 VCCPRIM_CORE VCCPGPPE
V20 AF16 VCCPGPPF support 1.8V only

CC54
RF@
@ V21 VCCPRIM_CORE VCCPGPPF AD15
2 VCCPRIM_CORE VCCPGPPG
CC55 1 2 1U_0402_6.3V6K DCPDSW AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
Follow 543016_SKL_U_Y_PDG_1_0 CC56 1 2 1U_0402_6.3V6K K17
VCCMPHYAON_1P0 VCCPRIM_1P0_T1
T1 +1.0VALW
Close to K17 L1
+1.0V_AMPHYPLL +1.0V_MPHYGT VCCMPHYAON_1P0 AA1 CC57 1 2 1U_0402_6.3V6K
N15 VCCATS_1P8
+1.0V_MPHYGT VCCMPHYGT_1P0_N15
N16 AK17
RC84 1 RS@ 2 0_0805_5% N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
LC2 1 RS@ 2 0_0603_5% P15 VCCMPHYGT_1P0_N17 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
P16 BB14
Imax : 3.5A
22U_0603_6.3V6M

1U_0402_6.3V6K

VCCMPHYGT_1P0_P16 VCCRTC_BB14

22U_0603_6.3V6M

1U_0402_6.3V6K
1 1 1 1
K15 BB10 DCPRTC CC62 1 2 0.1U_0201_10V6K
CC58

CC59

CC60

CC61
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
L15
@ @ VCCAMPHYPLL_1P0 A14
2 2 2 2 VCCCLK1 +1.0V_CLK6_24TBT
V15
+1.0V_APLL VCCAPLL_1P0
@ K19
AB17 VCCCLK2
Y18 VCCPRIM_1P0_AB17 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL
AD17 N20
+3VALW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4_F100OC
AD18
+1.0V_CLK5_F24NS AJ17 VCCDSW_3P3_AD18 L19
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS
C
Follow 543016_SKL_U_Y_PDG_1_0 C
+3VALW +1.8V_HDA AJ19 A10
+1.8V_HDA VCCHDA VCCCLK6 +1.0V_CLK6_24TBT
RC85 1 RS@ 2 0_0603_5%
RC86 RF@ AJ16 AN11
+3VALW VCCSPI GPP_B0/CORE_VID0
MURATA BLM15EG221SN1D AN13
22U_0603_6.3V6M

HD Audio : 3.3V or 1.5V

1 2 AF20 GPP_B1/CORE_VID1

0.1U_0201_10V K X5R
1 VCCSRAM_1P0
SM01000HC00 AF21
CC63

I2S : 1.8V or 3.3V

T19 VCCSRAM_1P0
R_0402 1 VCCSRAM_1P0
@ T20

CC66
RF@
2 VCCSRAM_1P0
AJ21
2 VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
+3VALW +1.0VALW VCCAPLLEBB_1P0 15 OF 20
+1.0V_CLK4_F100OC
Follow 543016_SKL_U_Y_PDG_1_0 +1.8VALW +3V_1.8V_PGPPA SKL-U_BGA1356
@
RC87 1 RS@ 2 0_0603_5% 2 2 2
RC88 1 @ 2 0_0402_5% @ @

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
22U_0603_6.3V6M

CC67

CC65

CC68
1 1 1 1
CC70

+3VALW
LPC 3.3V
@
2 RTC Bat t er y
RC89 1 RS@ 2 0_0402_5%
Close to AJ21 Close to AF20 Close to N18
+3VL_RTC +RTCBATT

W=20mils
+1.0V_CLK6_24TBT RC90 1 RS@ 2 0_0402_5%
+1.8VS +1.8VS_3VS_PGPPA
B Follow 543016_SKL_U_Y_PDG_1_0 1 B
CC82
RC91 1 RS@ 2 0_0603_5% 1 2 0_0402_5% 1U_0402_6.3V6K
RC92 @ Follow 543016_SKL_U_Y_PDG_1_0
2
Delete CC77 , CC78 for DDR layout modify
22U_0603_6.3V6M

+3VS +1.0VALW +3VALW +1.8VALW +3VALW

1U_0402_6.3V6K

1 1
CC85

LPC 3.3V
CC84

@ @ Saf t y s ugges t i on r emove EE s i de , Keep PW

R s i de
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2 2 RC93 1 RS@ 2 0_0402_5% 1 1 1 1 1 1
CC71

CC72

CC73

CC74

CC75

CC76

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_10V6K
1 1 1
@ @ @ @ @ @ @

CC80

CC81

CC79
2 2 2 2 2 2
2 2 2

Close to AG15 Close to Y16 Close to T16 Close to AK17

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(9/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 13 of 52

5 4 3 2 1
 5 4 3 2 1

+VCCCORE +VCCCORE +VCCGT +VCCGT

UC1M SKL-U
UC1L SKL-U Rev_1.0
Rev_1.0 CPU POWER 2 OF 4
CPU POWER 1 OF 4
N70
A30 G32 A48 VCCGT N71
A34 VCC_A30 VCC_G32 G33 A53 VCCGT VCCGT R63
A39 VCC_A34 VCC_G33 G35 A58 VCCGT VCCGT R64
D D
A44 VCC_A39 VCC_G35 G37 A62 VCCGT VCCGT R65
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
AM37 VCC_AM35 VCC_K38 K40 AC67 VCCGT VCCGT W64
AM38 VCC_AM37 VCC_K40 K42 AC68 VCCGT VCCGT W65
VCC_AM38 VCC_K42 VCCGT VCCGT
G30
VCC_G30 VCC_K43
K43 Trace Length Match < 25 mils AC69
VCCGT VCCGT
W66
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
RSVD VCC_SENSE VCCCORE_SENSE [45] VCCGT VCCGT
E33 J43 W69
VSS_SENSE VSSCORE_SENSE [45] VCCGT VCCGT
AK32 J45 W70
RSVD B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
AB62 VIDALERT# A63 VR_SVID_CLK J48 VCCGT VCCGT Y62
VCCOPC_AB62 VIDSCK VR_SVID_CLK [45] VCCGT VCCGT
Delete GT3 Power trace P62
VCCOPC_P62 VIDSOUT
D64 VR_SVID_DATA J50
VCCGT
V62 J52
VCCOPC_V62 VCCGT
VCCSTG_G20
G20 ALERT signal must be routed between CLK and DATA signals J53
VCCGT VCCGTX_AK42
AK42
H63 J55 AK43
VCC_OPC_1P8_H63 VCCGT VCCGTX_AK43
For GT3 SKU +1.0VS_VCCIO J56
VCCGT VCCGTX_AK45
AK45
G61 J58 AK46
VCC_OPC_1P8_G61 J60 VCCGT VCCGTX_AK46 AK48
C VCCOPC_SENSE AC63 K48 VCCGT VCCGTX_AK48 AK50 C
T157 TP@ VSSOPC_SENSE VCCOPC_SENSE VCCGT VCCGTX_AK50
T158 TP@ AE63 K50 AK52
VSSOPC_SENSE K52 VCCGT VCCGTX_AK52 AK53
AE62 K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
AL63 K58 VCCGT VCCGTX_AK58 AK60
AJ62 VCCEOPIO_SENSE K60 VCCGT VCCGTX_AK60 AK70
VSSEOPIO_SENSE 12 OF 20 L62 VCCGT VCCGTX_AK70 AL43
VCCGT VCCGTX_AL43
L63
VCCGT VCCGTX_AL46
AL46 For GT3 SKU
SKL-U_BGA1356 L64 AL50
L65 VCCGT VCCGTX_AL50 AL53
@ VCCGT VCCGTX_AL53
L66 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
SVID ALERT N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
VCCGT VCCGTX_AU63
+1.0V_VCCST
Place the PU N67
VCCGT VCCGTX_BB57
BB57
resistors close to CPU N69
VCCGT VCCGTX_BB66
BB66
VCCGT_SENSE J70 AK62 VCCGTX_SENSE
[45] VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE T161 TP@
VSSGT_SENSE VSSGTX_SENSE
1

J69 AL61 T162 TP@

[45] VSSGT_SENSE VSSGT_SENSE
RC94 13 OF 20VSSGTX_SENSE
56_0402_5%
B
Trace Length Match < 25 mils SKL-U_BGA1356 B

@
2

SOC_SVID_ALERT# 1 2
VR_ALERT# [45] (To VR)
RC95 220_0402_5%

+1.0V_VCCST

SVID DATA Place the PU

resistors close to CPU
1

RC96
100_0402_5%
2

VR_SVID_DATA
VR_SVID_DATA [45] (To VR)

A A

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(10/12)Power,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 14 of 52

5 4 3 2 1
 5 4 3 2 1

D D
UC1P SKL-U UC1Q SKL-U
Rev_1.0 Rev_1.0 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3 Rev_1.0
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
C AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 C
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46
VSS VSS VSS VSS @
AJ4 AR35 B30 E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
B AK27 VSS VSS AR5 B58 VSS VSS F1 B
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @

A A

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(11/12)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 15 of 52

5 4 3 2 1
 5 4 3 2 1

D D

UC1S SKL-U UC1T SKL-U

Rev_1.0 Rev_1.0
RESERVED SIGNALS-1 SPARE

T164 TP@ CFG0 E68 BB68 AW69 F6

CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 AW68 RSVD_AW69 RSVD_F6 E3
T163 TP@ CFG[1] RSVD_TP_BB69 RSVD_AW68 RSVD_E3
T165 TP@ CFG2 D65 AU56 C11
CFG3 D67 CFG[2] AK13 AW48 RSVD_AU56 RSVD_C11 B11
T175 TP@ CFG[3] RSVD_TP_AK13 RSVD_AW48 RSVD_B11
T166 TP@ CFG4 E70 AK12 C7 A11
CFG5 C68 CFG[4] RSVD_TP_AK12 RSVD_U12 U12 RSVD_C7 RSVD_A11 D12
T167 TP@ CFG[5] RSVD_U11 U11 RSVD_U12 RSVD_D12
T168 TP@ CFG6 D68 BB2 C12
CFG7 C67 CFG[6] RSVD_BB2 BA3 H11 RSVD_U11 RSVD_C12 F52
T169 TP@ CFG[7] RSVD_BA3 RSVD_H11 RSVD_F52
T170 TP@ CFG8 F71
CFG9 G69 CFG[8] 20 OF 20
T171 TP@ CFG[9]
T172 TP@ CFG10 F70 AU5
CFG11 G68 CFG[10] TP5 AT5 SKL-U_BGA1356
T173 TP@ CFG[11] TP6
T176 TP@ CFG12 H70 @
CFG13 G71 CFG[12]
T174 TP@ CFG[13]
T177 TP@ CFG14 H69 D5
CFG15 G70 CFG[14] RSVD_D5 D4
T178 TP@ CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
T179 TP@ CFG[16] RSVD_C2
T180 TP@ CFG17 F63 +1.8VALW
CFG[17] B3
CFG18 E66 RSVD_B3 A3
T181 TP@ CFG[18] RSVD_A3
T182 TP@ CFG19 F66
C CFG[19] AW1 RSVD_U12 RC122 1 @ 2 0_0402_5% C
CFG_RCOMP E60 RSVD_AW1
CFG_RCOMP E1 RSVD_U11 RC123 1 @ 2 0_0402_5%
XDP_ITP_PMODE E8 RSVD_E1 E2
T183 TP@ ITP_PMODE RSVD_E2 2
@
AY2 BA4 CC87
AY1 RSVD_AY2 RSVD_BA4 BB4 1U_0402_6.3V6K
RSVD_AY1 RSVD_BB4 1
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56 LPM_ZVM#
B RSVD_J68 ZVM# T186 TP@ B
F65 AW71
G65 VSS_F65 RSVD_TP AW70
VSS_G65 RSVD_TP
F61 AP56 PM_MSM# T185 TP@
E61 RSVD_F61 MSM# C64 SKL_CNL# +1.0V_VCCST
RSVD_E61 PROC_SELECT#
19 OF 20 1 @ 2
RC99 100K_0402_5%
1 2 CFG_RCOMP SKL-U_BGA1356
RC100 49.9_0402_1% @
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0
1 2 CFG4
RC101 1K_0402_5% Stuff 100k(RC99) for Cannonlake.

Un-stuff 100k(RC99) for Skylake

Display Port Presence Strap

1 : Disabled; No Physical Display Port

attached to Embedded Display Port
CFG4
0 : Enabled; An external Display Port device is
A connected to the Embedded Display Port A

Security Classification
2014/05/19
Compal Secret Data
2015/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(12/12)CFG,RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 16 of 52

5 4 3 2 1
 5 4 3 2 1

+DDR_VREF_CA +DDR_VREF_CA +DDR_VREF_CA

+DDR_VREF_CA

U2 U3 U4
U5
M1 G2 DDR_A_D3 M1 G2 DDR_A_D19 M1 G2 DDR_A_D35
VREFCA DQL0 DDR_A_D1 VREFCA DQL0 DDR_A_D17 VREFCA DQL0 DDR_A_D33 DDR_A_D51

0.047U_0402_25V7K

0.047U_0402_25V7K

0.047U_0402_25V7K
F7 F7 F7 M1 G2
DQL1 DDR_A_D2 DQL1 DDR_A_D18 DQL1 DDR_A_D34 VREFCA DQL0 DDR_A_D49

0.047U_0402_25V7K
H3 H3 H3 F7
DDR_A_MA0 P3 DQL2 H7 DDR_A_D0 DDR_A_MA0 P3 DQL2 H7 DDR_A_D16 DDR_A_MA0 P3 DQL2 H7 DDR_A_D32 DQL1 H3 DDR_A_D50
DDR_A_MA1 A0 DQL3 DDR_A_D7 DDR_A_MA1 A0 DQL3 DDR_A_D23 DDR_A_MA1 A0 DQL3 DDR_A_D39 DDR_A_MA0 DQL2 DDR_A_D48

1
P7 H2 P7 H2 P7 H2 P3 H7

CD124

CD125

CD126
DDR_A_MA2 A1 DQL4 DDR_A_D5 DDR_A_MA2 A1 DQL4 DDR_A_D21 DDR_A_MA2 A1 DQL4 DDR_A_D37 DDR_A_MA1 A0 DQL3 DDR_A_D55

1
R3 H8 R3 H8 R3 H8 P7 H2

CD127
DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D6 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D22 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D38 DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D53
DDR_A_MA4 A3 DQL6 DDR_A_D4 DDR_A_MA4 A3 DQL6 DDR_A_D20 DDR_A_MA4 A3 DQL6 DDR_A_D36 DDR_A_MA3 A2 DQL5 DDR_A_D54
2

2
N3 J7 N3 J7 N3 J7 N7 J3
DDR_A_MA5 A4 DQL7 DDR_A_MA5 A4 DQL7 DDR_A_MA5 A4 DQL7 DDR_A_MA4 A3 DQL6 DDR_A_D52

2
P8 P8 P8 N3 J7
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA7 R8 A6 A3 DDR_A_D10 DDR_A_MA7 R8 A6 A3 DDR_A_D26 DDR_A_MA7 R8 A6 A3 DDR_A_D42 DDR_A_MA6 P2 A5
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D8 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D24 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D40 DDR_A_MA7 R8 A6 A3 DDR_A_D58
D DDR_A_MA9 A8 DQU1 DDR_A_D11 DDR_A_MA9 A8 DQU1 DDR_A_D27 DDR_A_MA9 A8 DQU1 DDR_A_D43 DDR_A_MA8 A7 DQU0 DDR_A_D56 D
R7 C3 R7 C3 R7 C3 R2 B8
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D9 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D25 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D41 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D59
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D14 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D30 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D46 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D57
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D13 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D29 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D45 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D62
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D15 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D31 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D47 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D61
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D12 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D28 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D44 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D63
A14/WE DQU7 A14/WE DQU7 A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D60
DDR_A_BA0 N2 DDR_A_BA0 N2 DDR_A_BA0 N2 A14/WE DQU7
[6,17,19] DDR_A_BA0 DDR_A_BA1 BA0 [6,17,19] DDR_A_BA0 DDR_A_BA1 BA0 [6,17,19] DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA0
N8 B3 +1.2V N8 B3 +1.2V N8 B3 +1.2V N2 +1.2V
[6,17,19] DDR_A_BA1 BA1 VDD [6,17,19] DDR_A_BA1 BA1 VDD [6,17,19] DDR_A_BA1 BA1 VDD [6,17,19] DDR_A_BA0 DDR_A_BA1 BA0
B9 B9 B9 N8 B3
VDD VDD VDD [6,17,19] DDR_A_BA1 BA1 VDD
+1.2V E2 D1 +1.2V E2 D1 +1.2V E2 D1 B9
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E2 VDD D1
DML/DBIL VDD DML/DBIL VDD DML/DBIL VDD +1.2V DMU/DBIU VDD
J1 J1 J1 E7 G7
VDD J9 VDD J9 VDD J9 DML/DBIL VDD J1
VDD L1 VDD L1 VDD L1 VDD J9
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 VDD L1
[6,17] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD [6,17] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD [6,17] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD
K8 R1 K8 R1 K8 R1 K7 L9
[6,17] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD [6,17] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD [6,17] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD [6,17] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD
K2 T9 K2 T9 K2 T9 K8 R1
[6,17,19] DDR_A_CKE0 CKE VDD [6,17,19] DDR_A_CKE0 CKE VDD [6,17,19] DDR_A_CKE0 CKE VDD [6,17] DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD
K2 T9
[6,17,19] DDR_A_CKE0 CKE VDD
A1 A1 A1
VDDQ A9 VDDQ A9 VDDQ A9 A1
VDDQ C1 VDDQ C1 VDDQ C1 VDDQ A9
VDDQ D9 VDDQ D9 VDDQ D9 VDDQ C1
VDDQ F2 VDDQ F2 VDDQ F2 VDDQ D9
VDDQ F8 VDDQ F8 VDDQ F8 VDDQ F2
DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 VDDQ F8
[6,19] DDR_A_ODT0 DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_ODT0 VDDQ
L7 G9 L7 G9 L7 G9 K3 G1
[6,17,19] DDR_A_CS#0 DDR_A_MA16 CS VDDQ [6,17,19] DDR_A_CS#0 DDR_A_MA16 CS VDDQ [6,17,19] DDR_A_CS#0 DDR_A_MA16 CS VDDQ DDR_A_CS#0 ODT VDDQ
L8 J2 L8 J2 L8 J2 L7 G9
DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ [6,17,19] DDR_A_CS#0 DDR_A_MA16 CS VDDQ
M8 J8 M8 J8 M8 J8 L8 J2
CAS VDDQ CAS VDDQ CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8
B2 B2 B2 CAS VDDQ
VSS E1 VSS E1 VSS E1 B2
VSS E9 VSS E9 VSS E9 VSS E1
VSS G8 VSS G8 VSS G8 VSS E9
DDR_A_DQS#1 A7 VSS K1 DDR_A_DQS#3 A7 VSS K1 DDR_A_DQS#5 A7 VSS K1 VSS G8
DDR_A_DQS1 B7 DQSU_c VSS K9 DDR_A_DQS3 B7 DQSU_c VSS K9 DDR_A_DQS5 B7 DQSU_c VSS K9 DDR_A_DQS#7 A7 VSS K1
DDR_A_DQS#0 F3 DQSU_t VSS M9 DDR_A_DQS#2 F3 DQSU_t VSS M9 DDR_A_DQS#4 F3 DQSU_t VSS M9 DDR_A_DQS7 B7 DQSU_c VSS K9
DDR_A_DQS0 G3 DQSL_c VSS N1 DDR_A_DQS2 G3 DQSL_c VSS N1 DDR_A_DQS4 G3 DQSL_c VSS N1 DDR_A_DQS#6 F3 DQSU_t VSS M9
DQSL_t VSS T1 DQSL_t VSS T1 DQSL_t VSS T1 DDR_A_DQS6 G3 DQSL_c VSS N1
MEMRST# P1 VSS MEMRST# P1 VSS MEMRST# P1 VSS DQSL_t VSS T1
RESET RESET RESET MEMRST# P1 VSS
1 2 RU160 F9 1 2 RU161 F9 1 2 RU162 F9 RESET
240_0402_1% ZQ 240_0402_1% ZQ 240_0402_1% ZQ 1 2 RU163 F9
240_0402_1% ZQ
C M_A_ACT# M_A_ACT# M_A_ACT# C
[6,19] M_A_ACT# L3 A2 L3 A2 L3 A2
DDR_A_BG0 M2 ACT VSSQ A8 DDR_A_BG0 M2 ACT VSSQ A8 DDR_A_BG0 M2 ACT VSSQ A8 M_A_ACT# L3 A2
[6,19] DDR_A_BG0 BG0 VSSQ BG0 VSSQ BG0 VSSQ DDR_A_BG0 ACT VSSQ
N9 C9 N9 C9 N9 C9 M2 A8
DDR_A_ALERT P9 TEN VSSQ D2 DDR_A_ALERT P9 TEN VSSQ D2 DDR_A_ALERT P9 TEN VSSQ D2 N9 BG0 VSSQ C9
[6] DDR_A_ALERT# DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ DDR_A_ALERT TEN VSSQ
[6,19] DDR_A_PARITY T3 D8 T3 D8 T3 D8 P9 D2
PAR VSSQ E3 PAR VSSQ E3 PAR VSSQ E3 DDR_A_PARITY T3 ALERT VSSQ D8
T7 VSSQ E8 T7 VSSQ E8 T7 VSSQ E8 PAR VSSQ E3
B1 NC VSSQ F1 B1 NC VSSQ F1 B1 NC VSSQ F1 T7 VSSQ E8
+2.5V VPP VSSQ +2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ
R9 H1 R9 H1 R9 H1 +2.5V B1 F1
VPP VSSQ H9 VPP VSSQ H9 VPP VSSQ H9 R9 VPP VSSQ H1
96-BALL VSSQ 96-BALL VSSQ 96-BALL VSSQ VPP VSSQ H9
SDRAM DDR4 SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ
K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 K4A8G165WB-BCPB_FBGA96 SDRAM DDR4
X76RAM@ X76RAM@ X76RAM@ K4A8G165WB-BCPB_FBGA96
X76RAM@

[6,19] DDR_A_MA[0..16]

[6] DDR_A_DQS#[0..7]

[6] DDR_A_DQS[0..7]

[6] DDR_A_D[0..63]
Data mapping
CLOCK TERMINATION +0.6VS
U2 DQ U3 DQ U4 DQ U5 DQ
DQL0 D3 DQL0 D19 DQL0 D35 DQL0 D51
DDR_A_CLK0 RU166 1 2 36_0402_1% RD47 1 RS@ 2 0_0402_5%
DDR_A_CLK#0 DQL1 D1 DQL1 D17 DQL1 D33 DQL1 D49
RU167 1 2 36_0402_1%
DQL2 D2 DQL2 D18 DQL2 D34 DQL2 D50
DQL3 D0 DQL3 D16 DQL3 D32 DQL3 D48
+1.2V
DQL4 D7 DQL4 D23 DQL4 D39 DQL4 D55
DQL5 D5 DQL5 D21 DQL5 D37 DQL5 D53
DDR_A_ALERT RD41 2 1 49.9_0402_1%
B DQL6 D6 DQL6 D22 DQL6 D38 DQL6 D54 B

INTEL suggest 50ohm 1% DQL7 D4 DQL7 D20 DQL7 D36 DQL7 D52
DQU0 D10 DQU0 D26 DQU0 D42 DQU0 D58
DQU1 D8 DQU1 D24 DQU1 D40 DQU1 D56
DQU2 D11 DQU2 D27 DQU2 D43 DQU2 D59
DDR_DRAMRST# DQU3 D9 DQU3 D25 DQU3 D41 DQU3 D57
RD46 1 RS@ 2 0_0402_5% MEMRST#
[6,18] DDR_DRAMRST#
DQU4 D14 DQU4 D30 DQU4 D46 DQU4 D62
1 DQU5 D13 DQU5 D29 DQU5 D45 DQU5 D61
CD36
0.1U_0201_10V6K DQU6 D15 DQU6 D31 DQU6 D47 DQU6 D63
@
2
DQU7 D12 DQU7 D28 DQU7 D44 DQU7 D60

+1.2V
2

RD195
1.8K_0402_1%
RD11 +DDR_VREF_CA
2.7_0402_1%
1

2 1
[6] +0.6V_VREFCA
A A

1
CD24
0.022U_0402_16V7K
2
1

RD13 RD200
24.9_0402_1% 1.8K_0402_1%
2

LA-D301P
Security Classification Compal Secret Data
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 ON BOARD CHIPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P
Date: Monday, April 10, 2017 Sheet 17 of 52
5 4 3 2 1
 A B C D E

[6]

[6]
DDR_B_DQS#[0..7]

DDR_B_D[0..63]
Reverse Type
[6] DDR_B_DQS[0..7] 2-3A to 1 DIMMs/channel
+1.2V +1.2V
[6] DDR_B_MA[0..16]
DDR_B_BA0 JDIMM1
[6] DDR_B_BA0 DDR_B_BA1 +1.2V
1 2
[6] DDR_B_BA1 DDR_B_BG0 DDR_B_D14 VSS VSS DDR_B_D11
3 4
[6] DDR_B_BG0 DDR_B_BG1 DQ5 DQ4
5 6
[6] DDR_B_BG1 DDR_B_D15 VSS VSS DDR_B_D10
7 8
9 DQ1 DQ0 10
DDR_B_DQS#1 11 VSS VSS 12 +DIMM_VREF_DQ
DDR_B_DQS1 13 DQS0_C DM0*/DBI0* 14
DDR_B_CLK0 DQS0_T VSS DDR_B_D8

2
15 16
[6] DDR_B_CLK0 DDR_B_CLK#0 DDR_B_D13 VSS DQ6
17 18 RD194
[6] DDR_B_CLK#0 DDR_B_CLK1 DQ7 VSS DDR_B_D9
1 19 20 1K_0402_1% 1
[6] DDR_B_CLK1 DDR_B_CLK#1 DDR_B_D12 VSS DQ2
21 22 RD10
[6] DDR_B_CLK#1
23 DQ3 VSS 24 DDR_B_D4 20mil 2_0402_1%
DDR_B_D1 VSS DQ12

1
25 26 2 1
DDR_B_CKE0 DQ13 VSS DDR_B_D0 [6] +0.6V_B_VREFDQ
27 28
[6] DDR_B_CKE0 DDR_B_CKE1 DDR_B_D5 VSS DQ8
29 30
[6] DDR_B_CKE1 DDR_B_CS#0 DQ9 VSS DDR_B_DQS#0
31 32 1
[6] DDR_B_CS#0 DDR_B_CS#1 VSS DQS1_C DDR_B_DQS0
33 34
[6] DDR_B_CS#1 DM1*/DBI1* DQS1_T
35 36 CD21
DDR_B_D3 37 VSS VSS 38 DDR_B_D6 0.022U_0402_16V7K
SOC_SMBDATA 39 DQ15 DQ14 40 2
[7] SOC_SMBDATA SOC_SMBCLK DDR_B_D2 VSS VSS DDR_B_D7
41 42
[7] SOC_SMBCLK DQ10 DQ11

2
43 44
DDR_B_D21 45 VSS VSS 46 DDR_B_D20 RD12 RD199
DDR_B_ODT0 47 DQ21 DQ20 48
[6] DDR_B_ODT0 VSS VSS 24.9_0402_1% 1K_0402_1%
DDR_B_ODT1 DDR_B_D17 49 50 DDR_B_D16
[6] DDR_B_ODT1 DQ17 DQ16
51 52
DDR_B_DQS#2 VSS VSS

1
53 54
DDR_B_DQS2 55 DQS2_C DM2*/DBI2* 56
DQS2_T VSS
Note: 57
VSS DQ22
58 DDR_B_D19
Layout Note: Check voltage tolerance of
DDR_B_D23 59
DQ23 VSS
60
DDR_B_D18
Place near JDIMM1 VREF_DQ at the DIMM socket DDR_B_D22
61
63 VSS DQ18
62
64
65 DQ19 VSS 66 DDR_B_D28
DDR_B_D29 67 VSS DQ28 68
69 DQ29 VSS 70 DDR_B_D24
DDR_B_D25 71 VSS DQ24 72
73 DQ25 VSS 74 DDR_B_DQS#3
+1.2V 75 VSS DQS3_C 76 DDR_B_DQS3
77 DM3*/DBI3* DQS3_T 78
DDR_B_D30 79 VSS VSS 80 DDR_B_D31
81 DQ30 DQ31 82
DDR_B_D26 83 VSS VSS 84 DDR_B_D27
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

85 DQ26 DQ27 86
1 1 1 1 1 1 1 1 VSS VSS
87 88
89 CB5_NC CB4_NC 90
CD4

CD5

CD6

CD7

CD8

CD9

CD17

CD18

91 VSS VSS 92
2 2 2 2 2 2 2 2 @ 93 CB1_NC CB0_NC 94
1 2 95 VSS VSS 96
RD165
1 240_0402_1%
2 97 DQS8_C DM8*/DBI8* 98
RD166 @ 240_0402_1% 99 DQS8_T VSS 100
101 VSS CB6_NC 102
CB2_NC VSS
4 as near side of the DIMM close to VDD pins 103
VSS CB7_NC
104
105 106
107 CB3_NC VSS 108 DDR_DRAMRST#_R
2 +1.2V DDR_B_CKE0 109 VSS RESET* 110 DDR_B_CKE1 2
111 CKE0 CKE1 112
DDR_B_BG1 VDD1 VDD2 1
113 114 CD34
DDR_B_BG0 BG1 ACT* M_B_ACT# [6]
115 116 0.1U_0201_10V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

BG0 ALERT* DDR_B_ALERT# [6]

117 118 @
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11 2
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
1 1 1 1 1 1 1 1 A9 A7
123 124 +1.2V
CD10

CD11

CD12

CD13

CD14

CD19

CD15

CD20

DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5

DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
2 2 2 2 2 2 2 2 129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134
135 A1 EVENT* 136
DDR_B_CLK0 VDD9 VDD10 DDR_B_CLK1

1
137 138
DDR_B_CLK#0 139 CK0_T CK1_T 140 DDR_B_CLK#1 RD43
141 CK0_C CK1_C 142
VDD11 VDD12 470_0402_1%
143 144 DDR_B_MA0
[6] DDR_B_PARITY PARITY A0

2
DDR_DRAMRST#_R RD45 1 RS@ 2 0_0402_5%
DDR_B_BA1 DDR_B_MA10 DDR_DRAMRST# [6,17]
145 146
147 BA1 A10_AP 148
DDR_B_CS#0 149 VDD13 VDD14 150 DDR_B_BA0
DDR_B_MA14 151 S0* BA0 152 DDR_B_MA16
153 A14_WE* A16_RAS* 154 +DIMM_VREF_DQ
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15
DDR_B_CS#1 157 ODT0 A15_CAS* 158 DDR_B_MA13
159 S1* A13 160
DDR_B_ODT1 161 VDD17 VDD18 162
+3VS 163 ODT1 S2*/C0 164
VDD19 VREFCA
Place these caps on the VTT plane close to DIMM 165
S3*/C1 SA2
166
167 168
DDR_B_D37 169 VSS VSS 170 DDR_B_D36
+0.6VS 171 DQ37 DQ36 172
DDR_B_D33 173 VSS VSS 174 DDR_B_D32
+3VS_DIMM 175 DQ33 DQ32 176
DDR_B_DQS#4 177 VSS VSS 178
DDR_B_DQS4 179 DQS4_C DM4*/DBI4* 180
181 DQS4_T VSS 182 DDR_B_D39
10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1 1 DDR_B_D38 VSS DQ39

CD30 CD31 CD32 CD33 CD28 183 184
CD22

CD23

C2142 0.1U_0201_10V6K 185 DQ38 VSS 186 DDR_B_D35

2.2U_0402_6.3V6M DDR_B_D34 187 VSS DQ35 188
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

2 2 2 2 2 2 2 2 189 DQ34 VSS 190 DDR_B_D45

DDR_B_D44 191 VSS DQ45 192
3 3
193 DQ44 VSS 194 DDR_B_D41
DDR_B_D40 195 VSS DQ41 196
DQ40 VSS DDR_B_DQS#5
close to DIMM 197
VSS DQS5_C
198
DDR_B_DQS5
199 200
201 DM5*/DBI5* DQS5_T 202
DDR_B_D43 203 VSS VSS 204 DDR_B_D47
205 DQ46 DQ47 206
DDR_B_D42 207 VSS VSS 208 DDR_B_D46
209 DQ42 DQ43 210
DDR_B_D52 211 VSS VSS 212 DDR_B_D53
213 DQ52 DQ53 214
DDR_B_D49 215 VSS VSS 216 DDR_B_D48
217 DQ49 DQ48 218
DDR_B_DQS#6 219 VSS VSS 220
DDR_B_DQS6 221 DQS6_C DM6*/DBI6* 222
223 DQS6_T VSS 224 DDR_B_D54
DDR_B_D55 225 VSS DQ54 226
+2.5V 227 DQ55 VSS 228 DDR_B_D51
DDR_B_D50 229 VSS DQ50 230
231 DQ51 VSS 232 DDR_B_D60
DDR_B_D61 233 VSS DQ60 234
235 DQ61 VSS 236 DDR_B_D57
DDR_B_D56 237 VSS DQ57 238 +3VS
239 DQ56 VSS 240 DDR_B_DQS#7
+2.5V 241 VSS DQS7_C 242 DDR_B_DQS7 +0.6VS
243 DM7*/DBI7* DQS7_T 244
DDR_B_D59 245 VSS VSS 246 DDR_B_D63
10U_0603_6.3V6M

1 1 DQ62 DQ63
C2140 CD29 247 248
DDR_B_D58 VSS VSS DDR_B_D62

2
249 250
251 DQ58 DQ59 252 RD108
1U_0402_6.3V6K

2 2 SOC_SMBCLK 253 VSS VSS 254 SOC_SMBDATA

SCL SDA 10K_0402_5%
+3VS_DIMM 255 256
257 VDDSPD SA0 258
VPP1 VTT

1
259 260
VPP2 SA1

1
261 RD138
GND 262 0_0402_5%
GND
CONN@ FOX_AS0A827-H2SB-7H @

4
2 4

Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_DIMM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 18 of 52

A B C D E
 5 4 3 2 1

[6,17] DDR_A_MA[0..16]

+0.6VS
D D

+1.2V
RP17
DDR_A_MA9 1 8
DDR_A_MA5 2 7

CU198

CU195

CU197

CU200

CU199

CU196

CU201

CD211

CD210

CD212

CD213

CD214

CD215

CD216

CD217

CD218
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_A_MA0 3 6
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_MA1 4 5

36_0804_8P4R_5%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

RP18
DDR_A_MA6 1 8
DDR_A_MA11
4 as near each on board RAM device as possible DDR_A_MA7
2 7
3 6
DDR_A_MA4 4 5

36_0804_8P4R_5%

Follow MA51
RP19
DDR_A_MA14 1 8
1 DDR_A_MA15 2 7
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 DDR_A_BA0
+ CU89 3 6
CD25

CD26

CD27

CD39

CD40
330U_D2_2V_Y [6,17] DDR_A_BA0 DDR_A_BA1 4 5
[6,17] DDR_A_BA1
@
2 2 2 2 2 2
SGA00009S00 36_0804_8P4R_5%
330U 2V H1.9
9mohm POLY
RP20
DDR_A_ODT0 1 8
[6,17] DDR_A_ODT0 DDR_A_CS#0 2 7
[6,17] DDR_A_CS#0 DDR_A_MA16 3 6
DDR_A_MA10 4 5

C
36_0804_8P4R_5% C

RP21
DDR_A_BG0 1 8
[6,17] DDR_A_BG0 DDR_A_MA12 2 7
M_A_ACT# 3 6
[6,17] M_A_ACT# DDR_A_CKE0 4 5
[6,17] DDR_A_CKE0
36_0804_8P4R_5%

+2.5V +0.6VS
RP22
1 8
DDR_A_MA13 2 7
CU206

CU203

CU205

CU208

CU207

CU204

CU209

CU210

CU216

CU212

CU213

CU218

CU215

CU214

CU217

CU211
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_A_MA8 3 6
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 5

36_0804_8P4R_5%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2 as near each on board RAM device as possible

2 as near each on board RAM device as possible DDR_A_MA3
RP24
1 8
2 7
DDR_A_MA2 3 6
DDR_A_PARITY 4 5
[6,17] DDR_A_PARITY
36_0804_8P4R_5%
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 1 1
CD41

10U_0402_6.3V6M

CD220

10U_0402_6.3V6M

CD219

CD42

CD43

CD47

CD46

B 2 2 2 2 2 2 2 B

@ @

A A

LA-D301P
Security Classification Compal Secret Data
Issued Date 2014/02/14 Deciphered Date 2015/02/14 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 ON BOARD CHIPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 19 of 52

5 4 3 2 1
 1 2 3 4 5

UV1A
A A

AF30 AH30 PCIE_CRX_C_GTX_P1 CV1 PX@ 1 2 0.1U_0201_10V6K

[11] PCIE_CTX_C_GRX_P1 PCIE_RX0P PCIE_TX0P PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_P1 [11]
AE31 AG31 CV2 PX@ 1 2 0.1U_0201_10V6K
[11] PCIE_CTX_C_GRX_N1 PCIE_RX0N PCIE_TX0N PCIE_CRX_GTX_N1 [11]

AE29 AG29 PCIE_CRX_C_GTX_P2 CV3 PX@ 1 2 0.1U_0201_10V6K

[11] PCIE_CTX_C_GRX_P2 PCIE_RX1P PCIE_TX1P PCIE_CRX_C_GTX_N2 PCIE_CRX_GTX_P2 [11]
AD28 AF28 CV4 PX@ 1 2 0.1U_0201_10V6K
[11] PCIE_CTX_C_GRX_N2 PCIE_RX1N PCIE_TX1N PCIE_CRX_GTX_N2 [11]

AD30 AF27 PCIE_CRX_C_GTX_P3 CV5 PX@ 1 2 0.1U_0201_10V6K

[11] PCIE_CTX_C_GRX_P3 PCIE_RX2P PCIE_TX2P PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_P3 [11]
AC31 AF26 CV6 PX@ 1 2 0.1U_0201_10V6K
[11] PCIE_CTX_C_GRX_N3 PCIE_RX2N PCIE_TX2N PCIE_CRX_GTX_N3 [11]

AC29 AD27 PCIE_CRX_C_GTX_P4 CV7 PX@ 1 2 0.1U_0201_10V6K

[11] PCIE_CTX_C_GRX_P4 PCIE_RX3P PCIE_TX3P PCIE_CRX_C_GTX_N4 PCIE_CRX_GTX_P4 [11]
AB28 AD26 CV8 PX@ 1 2 0.1U_0201_10V6K
[11] PCIE_CTX_C_GRX_N4 PCIE_RX3N PCIE_TX3N PCIE_CRX_GTX_N4 [11]

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
B
V28 PCIE_RX7P PCIE_TX7P Y26 B
PCIE_RX7N PCIE_TX7N

V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23

U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
No Use GPU Display Port outpud
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 UV1F @
+VGA_CORE
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23 AB11 0_0402_5% 2 M2@ 1 RV177
VARY_BL AB12 0_0402_5% 2 M2@ 1 RV176 FOR TOPAS CORE POWER USE
N29 P27 DIGON
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24 AL15

L31 NC#M30 NC#P24 P23 TXCAP_DPA3P AK14
NC#L31 NC#P23 TXCAM_DPA3N
AH16
L29 M27 TX0P_DPA2P AJ15
K30 NC#L29 NC#M27 N26 TX0M_DPA2N
NC#K30 NC#N26 AL17
TX1P_DPA1P AK16
C C
TX1M_DPA1N
CLOCK AH18
CLK_PCIE_GPU AK30 TX2P_DPA0P AJ17
[9] CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP TX2M_DPA0N
AK32
[9] CLK_PCIE_GPU# PCIE_REFCLKN +0.95VGS AL19
+3VGS NC_TXOUT_L3P AK18
CALIBRATION NC_TXOUT_L3N
Y22 RV1 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX TMDP
RV2 1 PX@ 2 1K_0402_5% N10 AA22 RV3 1 PX@ 2 1K_0402_5%
TEST_PG PCIE_CALR_RX
5

UV2 PX@ AH20

PCIRST# 2 TXCBP_DPB3P AJ19
[9,30,33,34] PCIRST# B
P

4 GPU_RST# AL27 TXCBM_DPB3N

DGPU_HOLD_RST# 1 Y PERSTB AL21
[10] DGPU_HOLD_RST# A TX3P_DPB2P
G

AK20
TX3M_DPB2N
1
3

RV4 216-0841018 A0 SUN PRO S3 @ AH22

MC74VHC1G08DFT2G_SC70-5 100K_0402_5% TX4P_DPB1P AJ21
PX@ TX4M_DPB1N
AL23
TX5P_DPB0P
2

AK22
TX5M_DPB0N
AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N

216-0841018 A0 SUN?PRO S3

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R16M-M1-70(1/5)_PCIE/DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 20 of 52

1 2 3 4 5
 1 2 3 4 5

+3VGS

+1.8VGS
PS_0[3:1]=001 Strap Name :

1
PX@ PX@ UV1B @ U?
RV157 RV158 PS_0[5:4]=11

1
47K_0402_5% 47K_0402_5% PS_0[1] ROM_CONFIG[0]

2
PX@
AF2 RV12 PS_0[2] ROM_CONFIG[1]
VGA_SMB_DA2 NC#AF2

2
6 1 AF4 8.45K_0402_1%
[7,33] EC_SMB_DA2 NC#AF4
PS_0 PS_0[3] ROM_CONFIG[2]

2
PX@ QV9A N9 AG3
DBG_DATA16 NC#AG3

5
L2N7002DW1T1G 2N SC88-6 L9 AG5 Resistor Divider Lookup Lable PS_0[4] N/A
DBG_DATA15 NC#AG5

1
AE9 DPA 1

0.68U_0402_10V
3 4 VGA_SMB_CK2 Y11 DBG_DATA14 AH3 PX@
[7,33] EC_SMB_CK2 AE8 DBG_DATA13 NC#AH3 AH1
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
PX@ QV9B AD9 DBG_DATA12 NC#AH1 R_pu (ohm) R_pd (ohm) Bitd [3:1] CV30 RV7
2K_0402_1%
A L2N7002DW1T1G 2N SC88-6 AC10 DBG_DATA11 AK3 @ 2 A
DBG_DATA10 NC#AK3

2
AD7 AK1 NC 4.75k 000
AC8 DBG_DATA9 NC#AK1
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3
8.45k 2k 001
AB8 DBG_DATA6 NC#AM3
AB7 DBG_DATA5 AK6
4.53k 2k 010
AB4 DBG_DATA4 NC#AK6 AM5
AB2 DBG_DATA3 NC#AM5 6.98k 4.99k 011 +1.8VGS
Y8 DBG_DATA2 DPB
AJ7
PS_1[3:1]=000 Strap Name :
Y7 DBG_DATA1 NC#AJ7 AH6
4.53k 4.99k 100
DBG_DATA0 NC#AH6 PS_1[5:4]=11

1
AK8
3.24k 5.62k 101 @
PS_1[1] STRAP_BIF_GEN3_EN_A
NC#AK8 AL7
NC#AL7 3.4k 10k 110 RV9
8.45K_0402_1%
PS_1[2] TRAP_BIF_CLK_PM_EN
4.75k NC 111 PS_1 PS_1[3] N/A

2
+1.8VGS W6
V6 NC#W6
NC#V6 0402 1% resistors are equired PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

1
V4 1

0.68U_0402_10V
AC6 NC#V4 U5 PX@
AC5 NC#AC5 NC#U5 PS_1[5] STRAP_TX_DEEMPH_EN
CV31 RV14
NC#AC6 W3 4.75K_0402_1%
NC#W3 2

2
AA5 V2 Capacitor Divider Lookup Lable @
NC#AA5 NC#V2

2
RV16 RV11 AA6 DPC
4.7K_0402_5% 4.7K_0402_5% NC#AA6 Y4
M2@ M2@ NC#Y4 W5
NC#W5 Cap (nF) Bitd [5:4]
AA3 PLL_ANALOG_OUT

1
U1 1 PX@ 2
TP@ 1 FB_VDDCI W1 NC#U1 NC#AA3 Y2 RV17
TV23 U3 NC#W1 NC#Y2 16.2K_0402_1%
680nF 00
Y6 NC#U3 J8 +1.8VGS
TP@ 1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 82nF 01 PS_2[3:1]=000 Strap Name :
TV18 NC#AA1
10nF 10 PS_2[5:4]=11

1
AMD recommend 09/25
PS_2[1] N/A
NC 11 @
RV57 PS_2[2] N/A
I2C 8.45K_0402_1%
PS_2 PS_2[3] STRAP_BIOS_ROM_EN

2
B R1 B
+3VGS R3 SCL
SDA +3VGS PS_2[4] STRAP_BIF_VGA_DIS

1
REAK CURRENT CONTROL ( M2 only reserve ) 1

0.68U_0402_10V
AM26 @ PX@ PS_2[5] N/A
+VGA_CORE R
2

GENERAL PURPOSE I/O AK26 CV32 RV19

AVSSN#AK26 +3VGS

2
RV10 U6 4.75K_0402_1%
RV170 1 M2@ 2 0_0402_5% U10 GPIO_0 AL25 2
10K_0402_5% GPIO_1 G

2
@ RV174 1 M2@ 2 0_0402_5% T10 AJ25 @ RV373
VGA_SMB_DA2 GPIO_2 AVSSN#AJ25

2
RV15 U8 4.7K_0402_5%
VGA_SMB_CK2 SMBDATA
1

1K_0402_5% U7 AH24 RV371

GPU_GPIO6 GPU_PROCHOT# GPU_GPIO5 SMBCLK B

2 1
1 2 @ DV1 1 2 T9 AG25 4.7K_0402_5%
GPU_PROCHOT# [48] [9,33,40] VCIN1_AC_IN GPU_GPIO6 T8 GPIO_5_AC_BATT AVSSN#AG25
@ @

G
1 GPIO_6 DAC1
RB751V_SOD323 T7 AH26
GPIO_7_BLON HSYNC GPU_WAKEB

1
CV17 P10 AJ27 3 1 1 TP@
GPIO_8_ROMSO VSYNC TV26 +1.8VGS
0.1U_0201_10V7K P4 PS_3[3:1]=000 Strap Name :

D
2 GPIO_9_ROMSI

2
@
P2
+VGA_CORE N6 GPIO_10_ROMSCK AD22 RV372 2N7002H_SOT23-3
GPIO_11 RSET PS_3[5:4]=11

1
N5 4.7K_0402_5% @ QV20 PS_3[1] BOARD_CONFIG[0] (Memory ID)
GPIO_12
RV172 1 M2@ 2 0_0402_5%
N3
Y9 GPIO_13 AVDD
AG24
AE22
PX@ OBFF OPTION: X76@
RV21
GPU_SVD RV182 1 M1@ 2.2K_0402_5% GPU_VID3 GPIO_14_HPD2 AVSSQ reserved for AMD request PS_3[2] BOARD_CONFIG[1] (Memory ID)

1
@ 2 N1 8.45K_0402_1%
+3VGS 10K_0402_5% CV180 10U_0603_6.3V6M M4 GPIO_15_PWRCNTL_0 AE23 Pull down for none OBFF design
THM_ALERT# THM_ALERT#_R R6 GPIO_16 VDD1DI PS_3 PS_3[3] BOARD_CONFIG[2] (Memory ID)

2
RV136 2 1 DIR 2 1 FOR TOPAS CORE POWER USE RV194 1 RS@ 2 0_0402_5% AD23
RV173 1 M2@ 2 0_0402_5% W10 GPIO_17_THERMAL_INT VSS1DI
GPIO19_CTF GPIO_18 PS_3[4] AUD_PORT_CONN_PINSTRAP[1]

1
@ CV196 M2 FutureASIC/SEYMOUR/PARK 1

0.68U_0402_10V
2 1 0.1U_0201_10V7K GPU_SVC RV183 1 M1@ 2.2K_0402_5%
2 GPU_VID1 P8 GPIO_19_CTF AM12 X76@ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]

CV33
P7 GPIO_20_PWRCNTL_1 CEC_1 @ RV24
@ N8 GPIO_21 2K_0402_1%
AK10 GPIO_22_ROMCSB AK12 SVI2_SVD RV166 1 M2@ 2 0_0402_5% GPU_SVD 2
GPIO_29 RSVD#AK12 SVI2_SVT RV167 1 M2@ GPU_SVD [48]
2 0_0402_5% GPU_SVT

2
+1.8VGS AM10 AL11 GPU_SVT [48]
N7 GPIO_30 RSVD#AL11 AJ11 SVI2_SVC RV168 1 M2@ 2 0_0402_5% GPU_SVC
GPIO19_CTF [9] GPUCLK_REQ# CLKREQB RSVD#AJ11 GPU_SVC [48]
1 RV13 2
10K_0402_5% JTAG_TRSTB L6 FOR MESO
@ JTAG_TDI L5 JTAG_TRSTB EXO doesn't have native SVI2
JTAG_TCK JTAG_TDI
2

L3
RV22 1 @ 2 TP@ JTAG_TMS L1 JTAG_TCK AL13
+3VGS JTAG_TDO JTAG_TMS GENLK_CLK
10K_0402_5% RV26 5.11K_0402_5% 1 K4 AJ13
TV24 JTAG_TDO GENLK_VSYNC
1 PX@ 2 TESTEN K7
C RV27 1K_0402_5% AF24 TESTEN C
NC#AF24
1

+VGA_CORE AG13
+3VGS SWAPLOCKA AH12
RV169 1 M2@ 2 0_0402_5% AB13 SWAPLOCKB
RV18 2 PX@ 1 4.7K_0402_5% THM_ALERT# W8 GENERICA
RV171 1 M2@ 2 0_0402_5% W9 GENERICB
W7 GENERICC AC19 PS_0
AD10 GENERICD PS_0
AJ9 GENERICE AD19 PS_1
+3VGS TP@ 1 AL9 NC#AJ9 PS_1
TV22 NC#AL9 PS_2
AE17
RV175 1 M2@ 2 0_0402_5% AC14 PS_2
TP@ 1 PX_EN AB16 HPD1 AE20 PS_3
GPU_GPIO5 TV25 PX_EN PS_3
RV58 1 @ 2
10K_0402_5%
RV20 1 @ 2 JTAG_TDO AE19
10K_0402_5% AC16 TS_A
DBG_VREFG
VGA_AC_BATT
pull up DDC/AUX
+3VGS AE6
PLL/CLOCK DDC1CLK AE5
DDC1DATA OPTIAN FOR 3.3V tolerance VR,
RPV1 @ AD2 Check with VR vendor
1 8 JTAG_TRSTB AUX1P AD4 +VGA_CORE +1.8VGS +3VGS
2 7 JTAG_TDI AUX1N RV185 RV186
3 6 JTAG_TMS AC11 RV178 1 M2@ 2 0_0402_5% 1 @ 2 1 @ 2
4 5 JTAG_TCK DDC2CLK AC13 RV179 1 M2@ 2 0_0402_5% FOR MESO CORE POWER USE 0_0402_5% 0_0402_5%
DDC2DATA

2
10K_8P4R_5% XTALIN AM28 AD13 RV164 RV163
XTALOUT AK28 XTALIN AUX2P AD11 10K_0402_5% @ 10K_0402_5%
XTALOUT AUX2N @
RV28 RV29 1 PX@ 2 10K_0402_5% AC22 AD20 FB_GND RV37 1 M2@ 2 0_0402_5%
XO_IN NC#AD20 FB_VDDC RV51 1 M2@ GPU_SVD

1
XTALIN 1M_0402_5% XTALOUT RV31 1 PX@ 2 10K_0402_5% AB22 AC20 2 0_0402_5% GPU_VDD_RUN_FB_L [48]
PX@ TO EXTERNAL THERMAL SENSOR XO_IN2 NC#AC20 ONLY AVAILABLE ON TOPAZ, NC BALLS ON JET/SUN GPU_VDD_SEN [48] GPU_SVC
AE16
NC#AE16

2
AD16
D YV1 PX@ NC#AD16 D
4 3 SEYMOUR/FutureASIC AC1 RV30 PX@PX@
NC OSC T4 DDCVGACLK AC3 10_0402_5% RV165 RV184
1 2 T2 DPLUS THERMAL DDCVGADATA GPU_VDD_RUN_FB_L 1 2 PX@ 10K_0402_5% 10K_0402_5%
OSC NC DMINUS

1
27MHZ 10PF +-20PPM 7V27000023 +1.8VGS GPU_VDD_SEN 1 2
2 2 +VGA_CORE
SJ10000G300 Enable MLPS RV33 1 M1@ 2 10K_0402_5% GPIO28 R5 RV32 PX@
PX@ CV19 PX@ CV20 AD17 GPIO28_FDO 10_0402_5%
LV4 1 RS@ 2 0_0402_5% +TSVDD AC17 TSVDD
8.2P_0402_50V8J 8.2P_0402_50V8J TSVSS
1 1
1
CV21
1U_0402_6.3V6K Security Classification Compal Secret Data Compal Electronics, Inc.
2
PX@
Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title
216-0841018 A0 SUN PRO ?S3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(2/5)_MSIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 21 of 52

1 2 3 4 5
 1 2 3 4 5

+1.8VALW TO +1.8VGS
+1.0VALW TO +1.0VGS UV1E @ U?

Load switch
No Use GPU Display Port outpud AA27
AB24 GND GND
A3
A30
+1.8VGS AB32 GND GND AA13
AC24 GND GND AA16
UV1G @ AC26 GND GND AB10
U?
AC27 GND GND AB15
NC/DP POWER AD25 GND GND AB6
DP POWER

CV23

CV24
+1.0VALW AD32 GND GND AC9
1 1 GND GND
A AG15 AE11 AE27 AD6 A
AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
C29 AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
2 2 DP_VDDR#AF16 NC#AE13 GND GND

1U_0402_6.3V6K

10U_0603_6.3V6M
AG17 AF13 AH32 AG12
AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10

PX@

PX@
1U_0402_6.3V6K

1 DP_VDDR#AG18 NC#AG8 GND GND

@ AG19 AG10 K32 AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
+0.95VGS DP_VDDR#AF14 M32 GND GND B12
2 UV1895 N25 GND GND B14
1 14 +0.95VGS_LS RV5 1 RS@ 2 0_0805_5% N27 GND GND B16
2 VIN1 VOUT1 13 P25 GND GND B18
R1642 VIN1 VOUT1 GND GND
AG20 AF6 P32 B20
DGPU_PWR_EN DGPU_PWR_EN_R DP_VDDC#AG20 NC#AF6 GND GND

2
PX@ 3 12 @ 1 2 PX@ AG21 AF7 R27 B22
ON1 CT1 2200P_0402_50V7K C28 C32 +0.95VGS AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
33K_0402_5% 4 11 AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
+VL VBIAS GND 0.1U_0201_10V7K DP_VDDC#AG22 NC#AF9 GND GND

1
AD14 U25 B6
5 10 @ 1 2 DP_VDDC#AD14 U27 GND GND B8
0.1U_0402_25V6

ON2 CT2 +1.8VGS GND GND

1

2200P_0402_50V7K C27 V32 C1

C1380

CV28

CV29
PX@ +1.8VALW 6 9 W25 GND GND C32
VIN2 VOUT2 +1.8VGS_LS RV6 1 1 GND GND
7 8 1 RS@ 2 0_0805_5% AG14 AE1 W26 E28
VIN2 VOUT2 DP_VSSR NC#AE1 GND GND
2

AH14 AE3 W27 F10

15 AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
GPAD 2 2 DP_VSSR NC#AG1 GND GND

1U_0402_6.3V6K

0.1U_0201_10V7K
2
PX@ AM16 AG6 Y32 F14
EM5209VF DFN 14P C31 AM18 DP_VSSR NC#AG6 AH5 GND GND F16

PX@

PX@
AF23 DP_VSSR NC#AH5 AF10 GND F18
0.1U_0201_10V7K DP_VSSR NC#AF10 GND

1
1 AG23 AG9 F2
PX@ DP_VSSR NC#AG9 GND
@ C30 AM20 AH8 F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
SA00007PM00 AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
1U_0402_6.3V6K

2 AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26

AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
P9 GND GND G27
R12 GND GND G31
B
AF17 AE10 R15 GND GND G8 B
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
216-0841018 A0 SUN PRO? S3 T18 GND GND H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
T11 GND VSS_MECH AM1
GND VSS_MECH

+3VS to +3VGS
AA11 AM32
M12 GND VSS_MECH
N11 GND
V11 GND
GND

216-0841018 A0 SUN PRO

? S3

+3VALW +3VGS
PX@

C 3 1 4.7U_0603_6.3V6K 1U_0402_6.3V6K C
1

QV16 1 1 @
ME2310DC-G CV36 CV37 RV40
680_0603_5%
2

PX@ @
2 2
3VGS_EN#

+5VALW
@
D
1

2
PX@ QV17 G
RV42 PX@ DGPU_PWR_EN# 1 2 S 2N7002H_SOT23-3
3

RV43 10K_0402_5%
20K_0402_5%
+VGA_CORE +1.8VGS +0.95VGS
1

D QV19 1 PX@
R1640 1 RS@ 2 0_0402_5% DGPU_PWR_EN_3VGS 2 2N7002K_SOT23-3
DGPU_PWR_EN#
[10,33,48] DGPU_PWR_EN CV38

2
G
0.1U_0201_10V7K
1

S PX@ RV39 RV53 RV56

RV41 2 470_0603_5% 470_0603_5% 470_0603_5%
3

@ PX@ @ @

ME2N7002D1KW-G 2N_SOT363-6

ME2N7002D1KW-G 2N_SOT363-6
1 1

6 1

3 1
100K_0402_5%
2

D QV11
DGPU_PWR_EN# 2 2N7002K_SOT23-3
G 2 DGPU_PWR_EN# 5 DGPU_PWR_EN#
S PX@
QV21A QV21B

4
@ @

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(3/5)_PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 22 of 52

1 2 3 4 5
 1 2 3 4 5

A A

+1.35VGS
UV1D @ +1.8VGS
U?

AM30
MEM I/O PCIE_PVDD

PCIE

CV47

CV48
+1.35VGS H13 AB23 1 1
H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24

CV75

CV88

CV74

CV80

CV83

CV87

CV76

CV77

CV78

CV79

CV81

CV82

CV89

CV86

CV85

CV84
1 VDDR1 NC#AD24

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0201_10V7K

0.1U_0201_10V7K

0.1U_0201_10V7K

0.1U_0201_10V7K

0.1U_0201_10V7K
220U_B2_2.5VM_R35
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 J10 AE24
VDDR1 NC#AE24 2 2

10U_0603_6.3V6M

1U_0402_6.3V6K
+ J23 AE25
@ J24 VDDR1 NC#AE25 AE26

PX@

PX@
J9 VDDR1 NC#AE26 AF25
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 K10 VDDR1 NC#AF25 AG26

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
@

@
K23 VDDR1 NC#AG26
K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +0.95VGS
L21 VDDR1 PCIE_VDDC N22
L22 VDDR1 PCIE_VDDC N23
VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22

CV49

CV50

CV51

CV52

CV53

CV54
+1.8VGS LEVEL PCIE_VDDC U22
TRANSLATION PCIE_VDDC 1 1 1 1 1 1
V22
AA20 PCIE_VDDC
AA21 VDD_CT
VDD_CT 2 2 2 2 2 2

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AB20 AA15

CV55
B
AB21 VDD_CT CORE VDDC N15 B

PX@

PX@

PX@

PX@

PX@

@
1 VDD_CT VDDC N17
+3VGS VDDC R13
I/O VDDC R16
2 VDDC

1U_0402_6.3V6K
AA17 R18
AA18 VDDR3 VDDC Y21

PX@
AB17 VDDR3 VDDC T12

CV56
AB18 VDDR3 VDDC T15 +VGA_CORE
1 VDDR3 VDDC T17
V12 VDDC T20
Y12 VDDR4 VDDC U13
2 VDDR4 VDDC

1U_0402_6.3V6K
U12 U16
VDDR4 VDDC U18
VGA_CORE Caps in power side sheet

PX@
VDDC V21
VDDC V15
VDDC V17
VDDC V20
VDDC Y13

POWER
VDDC Y16
VDDC Y18
VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDC
+1.8VGS
PLL
LV1 1 RS@ 2 0_0603_5% +MPLL_PVDD

+0.95VGS
R21
CV39

CV40

CV41
1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

BIF_VDDC U21
1 1 1 BIF_VDDC
L8
+1.8VGS MPLL_PVDD
C C
2 2 2 +VGA_CORE
PX@

PX@

PX@

CV62
ISOLATED
LV2 1 RS@ 2 0_0402_5% +SPLL_PVDD
CORE I/O 1
M13
H7 VDDCI M15

CV42

CV43
10U_0603_6.3V6M

1U_0402_6.3V6K
SPLL_PVDD VDDCI M16
1 1 VDDCI 2

1U_0402_6.3V6K
M17
+0.95VGS VDDCI M18

@
VDDCI M20
2 2 LV3 1 RS@ 2 0_0402_5% +SPLL_VDDC H8 VDDCI M21
PX@

PX@
SPLL_VDDC VDDCI N20
J7 VDDCI
SPLL_PVSS
VGA_CORE Caps in power side sheet

CV46

CV90
1U_0402_6.3V6K

0.1U_0201_10V7K
1 1

216-0841018 A0 SUN PRO S3?

2 2

PX@

PX@
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(4/5)_PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 23 of 52

1 2 3 4 5
 1 2 3 4 5

@
M_DA[63..0] UV1C
[25,26] M_DA[63..0] U?

M_MA[15..0] GDDR5/DDR3 GDDR5/DDR3

[25,26] M_MA[15..0] M_DA0 M_MA0
A K27 K17 A
M_DQM[7..0] M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
[25,26] M_DQM[7..0] M_DA2 DQA0_1 MAA0_1/MAA_1 M_MA2
H30 H23
M_DQS[7..0] M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
[25,26] M_DQS[7..0] M_DA4 DQA0_3 MAA0_3/MAA_3 M_MA4
G29 G24
M_DQS#[7..0] M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
[25,26] M_DQS#[7..0] M_DA6 DQA0_5 MAA0_5/MAA_5 M_MA6
F32 J19
M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
M_DA11 C28 DQA0_10 J14 M_MA8
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2
M_DA17 DQA0_16 MAA1_5/MAA_BA2 M_BA0 M_BA2 [25,26]
C25 J16
M_DA18 DQA0_17 MAA1_6/MAA_BA0 M_BA1 M_BA0 [25,26]
E25 L15
M_DA19 DQA0_18 MAA1_7/MAA_BA1 M_MA14 M_BA1 [25,26]
D24 G14
M_DA20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD
M_DA22 D22 DQA0_21 E32 M_DQM0
+1.35VGS M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3
M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
M_DA27 DQA0_26 WCKA1_0/DQMA1_0 M_DQM5
1

A19 D12
PX@ M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
RV44 M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
40.2_0402_1% M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
M_DA32 DQA0_31 EDCA0_0/QSA0_0 M_DQS1
2

E17 C27
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
B M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4 B
M_DA36 DQA1_3 EDCA1_0/QSA1_0 M_DQS5
1

1 D14 D10
PX@ PX@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV46 CV65 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
100_0402_1% 1U_0402_6.3V6K M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
2 M_DA40 E11 DQA1_7 H27 M_DQS#0
M_DA41 DQA1_8 DDBIA0_0/QSA0_0B M_DQS#1
2

A11 A27
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
M_DA43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 M_DQS#3
M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
+1.35VGS M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B
M_DA49 A7 DQA1_16 L18 VRAM_ODT0
M_DA50 DQA1_17 ADBIA0/ODTA0 VRAM_ODT1 VRAM_ODT0 [25]
C7 K16
M_DA51 DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 [26]
F7
M_DA52 DQA1_19 M_CLK0
1

A5 H26
M_DA53 DQA1_20 CLKA0 M_CLK#0 M_CLK0 [25]
PX@ E5 H25
M_DA54 DQA1_21 CLKA0B M_CLK#0 [25]
RV45 C3
40.2_0402_1% M_DA55 E1 DQA1_22 G9 M_CLK1
M_DA56 DQA1_23 CLKA1 M_CLK#1 M_CLK1 [26]
G7 H9
M_DA57 DQA1_24 CLKA1B M_CLK#1 [26]
2

G6
M_DA58 G1 DQA1_25 G22 M_RAS#0
M_DA59 DQA1_26 RASA0B M_RAS#1 M_RAS#0 [25]
G3 G17
M_DA60 DQA1_27 RASA1B M_RAS#1 [26]
J6
M_DA61 DQA1_28 M_CAS#0
1

1 J1 G19
M_DA62 DQA1_29 CASA0B M_CAS#1 M_CAS#0 [25]
PX@ PX@ J3 G16
M_DA63 DQA1_30 CASA1B M_CAS#1 [26]
RV47 CV66 J5
100_0402_1% 1U_0402_6.3V6K DQA1_31 H22 M_CS0B#0
2 CSA0B_0 M_CS0B#0 [25]
+MVREFDA K26 J22
MVREFDA CSA0B_1
2

+MVREFSA J26
MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS1B#0 [26]
J25 K13
RV52 1 PX@ 2 120_0402_1% K25 NC#J25 CSA1B_1
C C
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE1 M_CKE0 [25]
PX@ PX@ J17
CKEA1 M_CKE1 [26]
RV48 RV49
49.9_0402_1% 10_0402_1% G25 M_WE#0
WEA0B M_WE#1 M_WE#0 [25]
1 2 2 1 DRST L10 H10
[25,26] DRAM_RST DRAM_RST WEA1B M_WE#1 [26]

1 RV54 @ 1 2 51.1_0402_1% CV69 @1 2 0.1U_0201_10V7K K8

CLKTESTA
1

1 @ RV55 @ 1 2 51.1_0402_1% CV70 @1 2 L7

PX@ PX@ CV67 0.1U_0201_10V7K CLKTESTB
CV68 RV50 68P_0402_50V8J
120P_0402_50V8J 5.1K_0402_1% 2 Route 50ohms single-ended/100ohm dif f and keep s hort
2 debug only, for clock observat i on,if not need, DNI. 216-0841018 A0 SUN PRO S3
?
2

Place close to GPU (within 25mm)

and place componment close to each other

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(5/5)_MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 24 of 52

1 2 3 4 5
 1 2 3 4 5

DDR3L Memory Channel Rank 0:A0

M_DA[63..0]
[24,26] M_DA[63..0]
M_MA[15..0]
[24,26] M_MA[15..0]
M_DQM[7..0] +1.35VGS +1.35VGS
[24,26] M_DQM[7..0]
M_DQS[7..0]
[24,26] M_DQS[7..0]

1
M_DQS#[7..0] PX@ PX@
A A
[24,26] M_DQS#[7..0]
RV63 RV62
4.99K_0402_1% UV5 4.99K_0402_1% UV6
+FBA_VREF0 M_DA8 +FBA_VREF1 M_DA18

2
M8 E3 M8 E3
H1 VREFCA DQL0 F7 M_DA14 H1 VREFCA DQL0 F7 M_DA19
VREFDQ DQL1 F2 M_DA10 VREFDQ DQL1 F2 M_DA16
M_MA0 DQL2 M_DA13 M_MA0 DQL2 M_DA20

1
1 N3 F8 1 N3 F8
PX@ PX@ M_MA1 P7 A0 DQL3 H3 M_DA9 PX@ PX@ M_MA1 P7 A0 DQL3 H3 M_DA21
RV75 CV72 M_MA2 P3 A1 DQL4 H8 M_DA12 RV66 CV71 M_MA2 P3 A1 DQL4 H8 M_DA23
4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA11 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA17
2 M_MA4 P8 A3 DQL6 H7 M_DA15 2 M_MA4 P8 A3 DQL6 H7 M_DA22
M_MA5 A4 DQL7 M_MA5 A4 DQL7

2
P2 P2
M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA5 M_MA7 R2 A6 D7 M_DA31
M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA27
M_MA9 R3 A8 DQU1 C8 M_DA6 M_MA9 R3 A8 DQU1 C8 M_DA30
M_MA10 L7 A9 DQU2 C2 M_DA2 M_MA10 L7 A9 DQU2 C2 M_DA24
M_MA11 R7 A10/AP DQU3 A7 M_DA4 M_MA11 R7 A10/AP DQU3 A7 M_DA28
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA25
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA29
M_MA14 T7 A13 DQU6 A3 M_DA0 M_MA14 T7 A13 DQU6 A3 M_DA26
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35VGS A15/BA3 +1.35VGS

M_BA0 M2 B2 M_BA0 M2 B2
[24,26] M_BA0 M_BA1 BA0 VDD M_BA1 BA0 VDD
N8 D9 N8 D9
[24,26] M_BA1 M_BA2 BA1 VDD M_BA2 BA1 VDD
M3 G7 M3 G7
[24,26] M_BA2 BA2 VDD BA2 VDD
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK0 M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
M_CLK#0 [24] M_CLK0 M_CLK#0 CK VDD M_CLK#0 CK VDD
K7 R1 K7 R1
[24] M_CLK#0 M_CKE0 CK VDD M_CKE0 CK VDD
K9 R9 K9 R9
[24] M_CKE0 CKE/CKE0 VDD +1.35VGS CKE/CKE0 VDD +1.35VGS
B B
1

PX@ PX@
RV102 RV103 VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
[24] VRAM_ODT0 M_CS0B#0 ODT/ODT0 VDDQ M_CS0B#0 ODT/ODT0 VDDQ
40.2_0402_1% 40.2_0402_1% L2 A8 L2 A8
[24] M_CS0B#0 M_RAS#0 CS/CS0 VDDQ M_RAS#0 CS/CS0 VDDQ
J3 C1 J3 C1
[24] M_RAS#0 M_CAS#0 RAS VDDQ M_CAS#0 RAS VDDQ
K3 C9 K3 C9
[24] M_CAS#0 M_WE#0 CAS VDDQ M_WE#0 CAS VDDQ
2

L3 D2 L3 D2
[24] M_WE#0 WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
M_DQS1 F3 VDDQ H2 M_DQS2 F3 VDDQ H2
1 M_DQS0 DQSL VDDQ M_DQS3 DQSL VDDQ
PX@ C7 H9 C7 H9
CV73 DQSU VDDQ DQSU VDDQ
0.01U_0402_16V7K
2 M_DQM1 E7 A9 M_DQM2 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#1 G3 VSS J2 M_DQS#2 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
[24,26] DRAM_RST RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1
PX@ L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9
RV111 J9 NC/CS1 VSSQ D1 RV110 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ NCZQ1 VSSQ
SINGLE RANK:RV102,RV103 install 40.2 ohms VSSQ
E2
VSSQ
E2
2

2
E8 E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
C C
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
X76@ X76@

+1.35VGS +1.35VGS +1.35VGS

10U_0603_6.3V6M
CV105

1U_0402_6.3V6K
CV106

1U_0402_6.3V6K
CV107

1U_0402_6.3V6K
CV108

1U_0402_6.3V6K
CV109

1U_0402_6.3V6K
CV112

1U_0402_6.3V6K
CV113

0.1U_0201_10V7K
CV125

10U_0603_6.3V6M
CV115

10U_0603_6.3V6M
CV116

1U_0402_6.3V6K
CV117

1U_0402_6.3V6K
CV120

1U_0402_6.3V6K
CV121

1U_0402_6.3V6K
CV126

1U_0402_6.3V6K
CV123

1U_0402_6.3V6K
CV122

1U_0402_6.3V6K
CV124
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

@
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO_DDR3L_A1 Rank 0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 25 of 52

1 2 3 4 5
 1 2 3 4 5

DDR3L Memory Channel Rank 0:A1

+1.35VGS
+1.35VGS

1
1
PX@
PX@ RV119
RV118 4.99K_0402_1% UV4
4.99K_0402_1% UV3
M_DA[63..0] +FBA_VREF3 M_DA34

2
A M8 E3 A
[24,25] M_DA[63..0] +FBA_VREF2 M_DA58 VREFCA DQL0 M_DA38

2
M8 E3 H1 F7
M_MA[15..0] H1 VREFCA DQL0 F7 M_DA61 VREFDQ DQL1 F2 M_DA35
[24,25] M_MA[15..0] VREFDQ DQL1 M_DA59 M_MA0 DQL2 M_DA39

1
F2 1 N3 F8
M_DQM[7..0] M_MA0 DQL2 M_DA62 M_MA1 A0 DQL3 M_DA32

1
1 N3 F8 PX@ PX@ P7 H3
[24,25] M_DQM[7..0] M_MA1 A0 DQL3 M_DA56 M_MA2 A1 DQL4 M_DA37
PX@ PX@ P7 H3 RV127 CV118 P3 H8
M_DQS[7..0] RV126 CV119 M_MA2 P3 A1 DQL4 H8 M_DA63 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA33
[24,25] M_DQS[7..0] M_MA3 A2 DQL5 M_DA57 2 M_MA4 A3 DQL6 M_DA36
4.99K_0402_1% 0.1U_0201_10V7K N2 G2 P8 H7
M_DQS#[7..0] 2 M_MA4 A3 DQL6 M_DA60 M_MA5 A4 DQL7

2
P8 H7 P2
[24,25] M_DQS#[7..0] M_MA5 A4 DQL7 M_MA6 A5

2
P2 R8
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA47
M_MA7 R2 A6 D7 M_DA52 M_MA8 T8 A7 DQU0 C3 M_DA43
M_MA8 T8 A7 DQU0 C3 M_DA51 M_MA9 R3 A8 DQU1 C8 M_DA46
M_MA9 R3 A8 DQU1 C8 M_DA55 M_MA10 L7 A9 DQU2 C2 M_DA42
M_MA10 L7 A9 DQU2 C2 M_DA50 M_MA11 R7 A10/AP DQU3 A7 M_DA44
M_MA11 R7 A10/AP DQU3 A7 M_DA54 M_MA12 N7 A11 DQU4 A2 M_DA41
M_MA12 N7 A11 DQU4 A2 M_DA49 M_MA13 T3 A12 DQU5 B8 M_DA45
M_MA13 T3 A12 DQU5 B8 M_DA53 M_MA14 T7 A13 DQU6 A3 M_DA40
M_MA14 T7 A13 DQU6 A3 M_DA48 M_MA15 M7 A14 DQU7
M_MA15 M7 A14 DQU7 A15/BA3 +1.35VGS
A15/BA3 +1.35VGS
M_BA0 M2 B2
M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
[24,25] M_BA0 M_BA1 BA0 VDD M_BA2 BA1 VDD
N8 D9 M3 G7
[24,25] M_BA1 M_BA2 BA1 VDD BA2 VDD
M3 G7 K2
M_CLK1 [24,25] M_BA2 BA2 VDD VDD
K2 K8
M_CLK#1 VDD K8 VDD N1
VDD N1 M_CLK1 J7 VDD N9
M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
[24] M_CLK1 M_CLK#1 CK VDD M_CKE1 CK VDD
1

PX@ PX@ K7 R1 K9 R9
[24] M_CLK#1 M_CKE1 CK VDD CKE/CKE0 VDD +1.35VGS
RV139 RV140 K9 R9
[24] M_CKE1 CKE/CKE0 VDD +1.35VGS
40.2_0402_1% 40.2_0402_1%
VRAM_ODT1 K1 A1
VRAM_ODT1 K1 A1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
[24] VRAM_ODT1 M_CS1B#0 ODT/ODT0 VDDQ M_RAS#1 CS/CS0 VDDQ
2

L2 A8 J3 C1
B [24] M_CS1B#0 M_RAS#1 CS/CS0 VDDQ M_CAS#1 RAS VDDQ B
J3 C1 K3 C9
[24] M_RAS#1 M_CAS#1 RAS VDDQ M_WE#1 CAS VDDQ
K3 C9 L3 D2
[24] M_CAS#1 M_WE#1 CAS VDDQ WE VDDQ
1 L3 D2 E9
[24] M_WE#1 WE VDDQ VDDQ
PX@ E9 F1
CV154 VDDQ F1 M_DQS4 F3 VDDQ H2
0.01U_0402_16V7K M_DQS7 F3 VDDQ H2 M_DQS5 C7 DQSL VDDQ H9
2 M_DQS6 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
M_DQM4 E7 A9
M_DQM7 E7 A9 M_DQM5 D3 DML VSS B3
M_DQM6 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 M_DQS#4 G3 VSS J2
M_DQS#7 G3 VSS J2 M_DQS#5 B7 DQSL VSS J8
M_DQS#6 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
VSS P1 DRAM_RST T2 VSS P9
DRAM_RST T2 VSS P9 RESET VSS T1
[24,25] DRAM_RST RESET VSS VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS

1
J1 B1
NC/ODT1 VSSQ
1

J1 B1 PX@ L1 B9
PX@ L1 NC/ODT1 VSSQ B9 RV138 J9 NC/CS1 VSSQ D1
RV137 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
NCZQ1 VSSQ VSSQ
SINGLE RANK:RV139,RV140 install 40.2 ohms

2
E2 E8
VSSQ VSSQ
2

E8 F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 C
H5TC2G63FFR-11C_FBGA96 X76@
X76@

+1.35VGS +1.35VGS +1.35VGS

10U_0603_6.3V6M
CV128

1U_0402_6.3V6K
CV152

1U_0402_6.3V6K
CV158

1U_0402_6.3V6K
CV132

1U_0402_6.3V6K
CV164

0.1U_0201_10V7K
CV134

1U_0402_6.3V6K
CV135

1U_0402_6.3V6K
CV136

10U_0603_6.3V6M
CV138

10U_0603_6.3V6M
CV139

1U_0402_6.3V6K
CV141

1U_0402_6.3V6K
CV144

1U_0402_6.3V6K
CV145

1U_0402_6.3V6K
CV146

0.1U_0201_10V7K
CV147

1U_0402_6.3V6K
CV193

1U_0402_6.3V6K
CV148
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/07 Deciphered Date 2016/01/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO_DDR3L_A2 Rank 0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 26 of 52

1 2 3 4 5
 5 4 3 2 1

Camera
LCD Power Circuit +LCDVDD_CONN
W=60mils
W=60mils 5
UCD1
1 +LCDVDD_CONN_R2 RS@ 1 +LCDVDD_CONN

4.7U_0603_6.3V6K
+3VS IN OUT R271 0_0603_5%
+3VS +3VS_CMOS 2

C128
D GND 1 D
4 3
[5] PCH_ENVDD EN OC
Q4 1 2
CMOS@ @ C1220 G524B1T11U SOT-23-5
ME2310DC-G

1
1U_0402_6.3V6K
W=20mils 3 1
W=20mils 2 R120

D
1 1 100K_0402_5% @
C129 CMOS@ C130 @

2
0.1U_0201_10V6K 10U_0603_6.3V6M

G
2
R119 CMOS@
150K_0402_5% 2 2

[33] CMOS_ON#
1
C132 @
0.1U_0201_10V6K
2
+3VS

5
U15 @
From PCH 2
[5,33] ENBKL B

P
C C
4 DISPOFF#
1 Y
From EC [33] BKOFF# A

G
R1251 RS@ 2 0_0402_5%

2
3
2
R124
R211 U74AHC1G08G-AL5-R_SOT353-5 100K_0402_5%
USB20_N5_R 100K_0402_5% @
[11] USB20_N5

1
USB20_P5_R

1
[11] USB20_P5
R123 1 RS@ 2 0_0402_5%

R1271 RS@ 2 0_0402_5%

eDP PANEL Conn.
+3VS_CMOS
JEDP1
1 2 USB20_N5_R
3 1 2 4 USB20_P5_R +INVPWR_B+ B+
5 3 4 6
CX3 1 2 0.1U_0201_10V6K EDP_AUXN_C 7 5 6 8
[5] EDP_AUXN EDP_AUXP_C 7 8 INVPWM [5]
[5] EDP_AUXP CX4 1 2 0.1U_0201_10V6K 9
11 9 10
10
12
DISPOFF#
EDP_HPD_R W=60mils W=60mils
CX5 1 2 0.1U_0201_10V6K EDP_TXP0_C 13 11 12 14
B [5] EDP_TXP0 B
CX6 1 2 0.1U_0201_10V6K EDP_TXN0_C 15 13 14 16 LC4 1 RS@ 2 0_0805_5%
[5] EDP_TXN0 17 15 16 18 +LCDVDD_CONN
EDP_TXP1_C 17 18
[5] EDP_TXP1
CX7
CX8
1
1
2 0.1U_0201_10V6K
2 0.1U_0201_10V6K EDP_TXN1_C
19
21 19 20
20
22
W=60mils 1
@
[5] EDP_TXN1 23 21 22 24 CX9
25 23 24 26 +INVPWR_B+ 4.7U_0805_25V6-K
27 25 26 28 2
27 28
29
29 30
30 W=60mils
31 32

33P_0402_50V8K

33P_0402_50V8K
GND GND
2 2
ACES_87242-3001-09_30P

@EMI@

@EMI@
CX14

CX15
ME@ EDP_HPD_R
1 1 [5] EDP_HPD
SP02000NB00

1
R128
100K_0402_5%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 27 of 52

5 4 3 2 1
 5 4 3 2 1

EMI
Near JHDMI1 For HDMI
+5V_Display
U6

R1650 1 EMI@ 2 6.8_0402_1% +5VS 3

W=40mils
Near JHDMI1 OUT
D 1 D
1
HDMI_CLK-_CK_C HDMI_CLK-_CONN IN

1
[5] HDMI_CLK-_CK C229 1 2 0.1U_0201_10V6K 1 C140
R1658 EMI@ @ 2 0.1U_0201_10V6K
150_0402_5% C141 GND 2
C230 1 2 0.1U_0201_10V6K HDMI_CLK+_CK_C HDMI_CLK+_CONN
[5] HDMI_CLK+_CK 0.1U_0201_10V6K
2 G5250Q1T73U SOT-23

2
R1651 1 EMI@ 2 6.8_0402_1%

R1652 1 EMI@ 2 6.8_0402_1%

HDMI_TX0-_CK_C HDMI_TX0-_CONN

1
[5] HDMI_TX0-_CK C231 1 2 0.1U_0201_10V6K
R1659 EMI@
150_0402_5%
C232 1 2 0.1U_0201_10V6K HDMI_TX0+_CK_C HDMI_TX0+_CONN
[5] HDMI_TX0+_CK

2
+3VS
R1653 1 EMI@ 2 6.8_0402_1%

R1654 1 EMI@ 2 6.8_0402_1%

2
R133
HDMI_TX1-_CK_C HDMI_TX1-_CONN

1
[5] HDMI_TX1-_CK C233 1 2 0.1U_0201_10V6K 1M_0402_5%

2
R1660 EMI@ Q5
150_0402_5% 2N7002K_SOT23-3

G
HDMI_TX1+_CK_C HDMI_TX1+_CONN

1
[5] HDMI_TX1+_CK C234 1 2 0.1U_0201_10V6K JHDMI1 ZZZ 45@
3 1 HDMI_DET 19
[5] TMDS_B_HPD HP_DET

2
18

D
+5V_Display +5V

2
17
R1655 1 EMI@ 2 6.8_0402_1% R137 HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
20K_0402_5% SCL
R1656 1 EMI@ 2 6.8_0402_1% 14
Reserved
HDMI Logo
13
HDMI_CLK-_CONN CEC

1
12 20 RO0000003HM
HDMI_TX2-_CK_C HDMI_TX2-_CONN CK- GND

1
C [5] HDMI_TX2-_CK C235 1 2 0.1U_0201_10V6K 11 21 C
R1661 EMI@ HDMI_CLK+_CONN 10 CK_shield GND 22
150_0402_5% HDMI_TX0-_CONN 9 CK+ GND 23
C236 1 2 0.1U_0201_10V6K HDMI_TX2+_CK_C HDMI_TX2+_CONN 8 D0- GND
[5] HDMI_TX2+_CK HDMI_TX0+_CONN D0_shield
7
HDMI_TX1-_CONN D0+

2
6
5 D1-
R1657 1 EMI@ 2 6.8_0402_1% HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
LOTES_AHDM0006-P004A_19P
+3VS
+3VS ME@
DC232002A00
R143 1 2 2.2K_0402_5% HDMIDAT_NB
Q6A
R144 1 2 2.2K_0402_5% HDMICLK_NB
2

L2N7002DW1T1G 2N SC88-6
HDMICLK_R
HDMIDAT_NB(Internal Pull Down): [5] HDMICLK_NB
1 6
RP29
HDMI_TX1-_CK_C
5

5 4
Display Port C Detected HDMIDAT_R
HDMI_TX1+_CK_C
HDMI_TX2-_CK_C
6 3
[5] HDMIDAT_NB 4 3 7 2
HDMI_TX2+_CK_C 8 1
0 = Port C is not detected. Q6B
L2N7002DW1T1G 2N SC88-6 470 +-5% 8P4R
1 = Port C is detected.
RP30
HDMI_TX0-_CK_C 5 4
HDMI_TX0+_CK_C 6 3
+5V_Display HDMI_CLK-_CK_C 7 2
HDMI_CLK+_CK_C 8 1
R145 1 2 2.2K_0402_5% HDMIDAT_R
470 +-5% 8P4R
B
R146 1 2 2.2K_0402_5% HDMICLK_R B

+3VS

1
D
2

ESD
G
S Q7
2N7002K_SOT23-3

3
@ESD@ D1 @ESD@ D2 @ESD@ D3
HDMIDAT_R HDMIDAT_R HDMI_TX0-_CONN HDMI_TX0-_CONN HDMI_TX1-_CONN 1 HDMI_TX1-_CONN
9 10 1 1 9 10 1 1 9 10 1
HDMICLK_R HDMICLK_R HDMI_TX0+_CONN HDMI_TX0+_CONN HDMI_TX1+_CONN 2 HDMI_TX1+_CONN
8 9 2 2 8 9 2 2 8 9 2
HDMI_DET HDMI_DET HDMI_CLK-_CONN HDMI_CLK-_CONN HDMI_TX2-_CONN HDMI_TX2-_CONN
7 7 4 4 7 7 4 4 7 7 4 4
HDMI_CLK+_CONN 6 HDMI_CLK+_CONN HDMI_TX2+_CONN HDMI_TX2+_CONN
6 6 5 5 6 5 5 6 6 5 5

3 3 3 3 3 3

8 8 8

L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9
SC300002C00 SC300002C00 L05ESDL5V0NA-4_SLP2510P8-10-9
SC300002C00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 28 of 52

5 4 3 2 1
 A B C D E F G H

HDD
SATA HDD Conn.
Near Connector JHDD2

1
CO2 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND
[11] SATA_CTX_DRX_P0 SATA_PTX_C_DRX_N0 A+
[11] SATA_CTX_DRX_N0 CO3 1 2 0.01U_0402_16V7K 3
4 A-
CO7 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND
[11] SATA_CRX_DTX_N0 CO1 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 B-
[11] SATA_CRX_DTX_P0 7 B+
GND
1 1
8
9 V33
10 V33
11 V33
12 GND
13 GND
1 RS@ 2 +5VS_HDD 14 GND
+5VS V5
RH142 0_0805_5% 15
16 V5
17 V5
18 GND
19 Reserved
+5VS 20 GND
21 V12 24
V12 GND
100mils 22
V12 GND
23

10U_0603_6.3V6M
CO10

1U_0402_6.3V6K
CO11

0.1U_0201_10V K X5R
CO12
1
1 1 SDAN_603015-022041
ME@
DC011411210
@ 2
2 2
+5VS_HDD CO14 1 2 0.1U_0201_10V K X5R

@ESD@

ODD
2 2

FOR 15"
SATA ODD FFC Conn.
JODD1
1
2 1
[11] SATA_CTX_DRX_P1 2
3
[11] SATA_CTX_DRX_N1 3
4
5 4
[11] SATA_CRX_DTX_N1 6 5
[11] SATA_CRX_DTX_P1 7 6
8 7
+5V_ODD 8
9
10 9
+5VS +5V_ODD 10 11
GND 12
JP5 GND
1 2 ACES_88058-100N
1 2 ME@
JUMP_43X39 SP010016C00
@

1
@ C2143
1U_0402_6.3V6K
3 2 3

FOR 14"
SATA ODD Conn.
Near Connector JODD2

1
SATA_CTX_DRX_P1 14@ C151 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_P1_14 2 GND
SATA_CTX_DRX_N1 14@ C152 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_N1_14 3 A+
4 A-
SATA_CRX_DTX_N1 14@ C153 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_N1_14 5 GND
SATA_CRX_DTX_P1 14@ C154 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P1_14 6 B-
7 B+
GND

8
9 DP
+5V_ODD +5V
10
11 +5V
12 MD 14
13 GND GND 15
GND GND

SANTA_201501-2
SP01001MV00
ME@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 29 of 52

A B C D E F G H
 A B C D E

1 1
+3VS +3VS_WLAN

NGFF for WLAN / BT(Key E) R153 1 RS@ 2 0_0603_5%

Support ISCT(Intel Smart Connect Technology)

1 1
+3VS_WLAN C155
C156
JWLAN1 4.7U_0603_6.3V6K @ 0.1U_0201_10V6K
1 2 2 2
3 GND 3.3VAUX 4
[11] USB20_P7 USB_D+ 3.3VAUX
BT [11] USB20_N7
5
USB_D- LED1#
6
7 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22 UART_2_CRXD_DTXD_R R175 1 2 RS@ 0_0402_5%
SDIO_WAKE# UART_RX UART_2_CRXD_DTXD [10]
23
SDIO_RESET#

24 UART_2_CTXD_DRXD_R R176 1 2 RS@ 0_0402_5%

UART_TX UART_2_CTXD_DRXD [10]
25 26
CC31 1 2 0.1U_0402_25V6 PCIE_CTX_C_DRX_P6 27 GND UART_CTS 28
[11] PCIE_CTX_DRX_P6 PCIE_CTX_C_DRX_N6 PETP0 UART_RTS
CC98 1 2 0.1U_0402_25V6 29 30 R155 1 2 RS@ 0_0402_5%
[11] PCIE_CTX_DRX_N6 PETN0 RESERVED EC_TX [33]
31 32 R156 1 2 RS@ 0_0402_5%
33 GND RESERVED 34 EC_RX [33]
[11] PCIE_CRX_DTX_P6 PERP0 RESERVED
2 35 36 2
[11] PCIE_CRX_DTX_N6 37 PERN0 COEX3 38
WLAN 39 GND COEX2 40
[9] CLK_PCIE_WLAN REFCLKP0 COEX1 SUSCLK_R
41 42 R157 1 2 RS@ 0_0402_5%
[9] CLK_PCIE_WLAN# 43 REFCLKN0 SUSCLK 44 WL_RST# SUSCLK [9]
R164 1 2 RS@ 0_0402_5% PCIRST# [9,20,33,34]
R158 1 RS@ 2 0_0402_5% WLANCLK_REQ#_R 45 GND PERST0# 46 BT_DISABLE_R R159 1 2 RS@ 0_0402_5%
[9] WLANCLK_REQ# WAKE#_R CLKEQ0# W_DISABLE2# WLBT_OFF# [10]
[33,34] EC_PCIE_WAKE# R162 1 RS@ 2 0_0402_5% 47 48 R161 1 2 RS@ 0_0402_5%
PEWAKE0# W_DISABLE1# EC_WL_OFF# [11]
For ISCT 49 50
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
Note: The real behavior of BT_DISABLE are
57 GND RESERVED 58 BT_DISABLE=LOW, BT=OFF
59 RSRVD/PERP1 RESERVED 60 BT_DISABLE=HIGH, BT=ON
61 RSRVD/PERN1 RESERVED 62
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
67 RESERVED 3.3VAUX
GND

69 68
MTG77 MTG76

LOTES_APCI0019-P009A
SP070011H00
ME@

2
R507
100K_0402_5%

1
3 3

4 4

Security Classification
2011/06/24
Compal Secret Data
2012/07/12 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF CARD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 30 of 52

A B C D E
 Lid switch KB
@
1 R279 2 R179 1 2 100_0402_5%
+3VALW +5VS
100K_0402_5%

JKB1

2
+3VS R1781 2 1
1
For Debug 1 [33] CAPS_LED# 100_0402_5% 2

VDD
C198 KSO15 3 2
@ESD@ KSO10 4 3
0.1U_0201_10V6K 3 LID_SW# KSO11 5 4
2 OUTPUT LID_SW# [33] 5
J11: TOP 1 KSO14 6
6

ESD
KSO13 7
J12: BOT

GND
7

0.1U_0201_10V K X5R
2 C201 KSO12 8
J1 8
ESD@ KSO3 9
1 2 C249 2 KSO6 10 9
10

1
10P_0402_50V8J KSO8 11
SHORT PADS U16 1 KSO7 12 11
KSO4 13 12 KSI[0..7]
J2 13 KSI[0..7] [33]
KSO2 14
1 2 ON/OFF# TCS20DLR SOT-23F 3P KSI0 15 14 KSO[0..17]
16 15 KSO[0..17] [33]
SA00008K800 KSO1
16
KB Power BTN
SHORT PADS KSO5 17
KSI3 18 17
KSI2 19 18
KSO0 20 19
KSI5 21 20
+3VLP KSI4 22 21
KSO9 23 22
KSI6 24 23
24

2
KSI7 25
25
For Debug
KSI1 26
R170 KSO16 27 26
100K_0402_5% 15@ KSO17 28 27
R180 1 2 29 28
+3VS 29

1
100_0402_5% 30 @
[33] NUM_LED# 30
31 SW6
[33] ON/OFF# 31
32 SMT1-05_4P
32

5
6
3

2
33 4 2
D6 GND 34 ON/OFF#
JTP1 ESD@ GND 3 1
TP_L 1
1
TP_R 1

0.1U_0201_10V K X5R
2 L03ESDL5V0CC3-2_SOT23-3 C202
3 2 SCA00002900
3 ESD@
TP_CLK 4 2 SP011509010
[33] TP_CLK TP_DATA 5 4 ME@
[33] TP_DATA TP_VCC 5

ESD
+3VS R258 1 RS@ 2 0_0402_5% 6 ACES_51510-0320N-P01
6

1
7
8 GND
GND
ACES_88058-060N
ME@

LED
SP010010T00

0.1U_0201_10V6K

C168

C169

C166

C167
0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
1 1 1 1 1

C163
3

R6
@ @ @ @ @
2 2 2 2 2 BATT_LOW_LED# 1 2 1 2
@ESD@ Bat t er y ( A mber)[33] BATT_LOW_LED# +3VLP
D5 LED1 A 100_0402_5%
PSOT24C_SOT23-3 LTST-C191KFKT-2CA_ORANGE
SC500005930
1

R7
BATT_CHG_LED# 1 2 1 2
CHG (White) [33] BATT_CHG_LED# +3VLP

ESD
LED2 100_0402_5%
LTW-C193TS5-C_WHITE
SC50000A200

R8
PWR_LED# 1 2 1 2
Power On (White) [33] PWR_LED#
LED3 100_0402_5%
+3VLP
LTW-C193TS5-C_WHITE
SC50000A200

For TP module
1 1 L CPU VGA NPTH
2 2 R
L L R R H1
HOLEA
H2
HOLEA
H3
HOLEA
H14
HOLEA
H15
HOLEA
H13
HOLEA
H22
HOLEA
H24
HOLEA
3 3 GND

1
4 4 CLK SW1
SMT1-05_4P
SW3
SMT1-05_4P
SW2
SMT1-05_4P
SW4
SMT1-05_4P H_2P5X3P0N H_2P5X3P0N H_2P5N
5
6

5
6

5
6

5
6

4 2 4 2 4 2 4 2
5 5 DAT TP_L TP_L TP_R TP_R
H_3P3 H_3P3 H_3P3 H_3P3 H_3P3

3 1 3 1 3 1 3 1
6 6 VCC 14@ 15@ 14@ 15@
H6 H7 H10
HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4

1
+3VLP
H_2P3 H_2P3 H_2P8

NOVO BTN FAN Conn H11 H8 H9

100K_0402_5%
2

HOLEA HOLEA HOLEA

R16

SW5
1

1
TSS31-EG2-160-T18-S017_3P
JFAN1
1

1
2 +5VS 1
[33] NOVO# 3 2 1 H_2P3 H_2P8 H_2P8
[33] EC_FAN_PWM1 2
3
G
G
G
G

[33] 2 EC_FAN_SPEED1 3
R168 1 +FAN 4
4
4
5
6
7

0_0603_5%
3

RS@ 5
D4 6 GND1
ESD@ GND2
2
ACES_50271-0040N-001
Compal Electronics, Inc.
L03ESDL5V0CC3-2_SOT23-3 C162
SCA00002900 10U_0603_6.3V6M SP02000TS00 Security Classification Compal Secret Data
1 ME@
Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title
ROM/KBD/PWR/CR/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 31 of 52

 5 4 3 2 1

D D

0_0402_5% 2 RS@ 1RS6

2 1 USB3_TX_P2_C U3TXDP2
[11] USB3_TX_P2
CS1 0.1U_0201_10V K X5R
USB3_TX_N2_C

USB3.0_Port
[11] USB3_TX_N2 2 1 U3TXDN2
CS2 0.1U_0201_10V K X5R DS1 ESD@
U3RXDN2 1 1 10 9 U3RXDN2

U3RXDP2 2 2 9 8 U3RXDP2
0_0402_5% 2 RS@ 1RS7
U3TXDN2 4 4 7 7 U3TXDN2

5 5
SF000002Y00
U3TXDP2 6 6 U3TXDP2
220U 6.3V OSCON
3 3 ESR 17mohm@100Khz
0_0402_5% 2 RS@ 1RS8
8
W=100mils +USB3_VCCA
L05ESDL5V0NA-4_SLP2510P8-10-9
USB3_RX_P2 U3RXDP2 SC300002C00
[11] USB3_RX_P2
C
JUSB1 ME@ C
1
USB3_RX_N2 U3RXDN2 USB20_N2_L 2 VBUS
[11] USB3_RX_N2 USB20_P2_L D-
3
4 D+
GND

ESD
U3RXDN2 5
U3RXDP2 6 STDA_SSRX-
0_0402_5% 2 RS@ 1RS9 7 STDA_SSRX+
U3TXDN2 8 GND
U3TXDP2 9 STDA_SSTX-
DS2 ESD@ STDA_SSTX+
+USB3_VCCA USB20_N2_L 6 3 10
I/O4 I/O2 11 GND
GND
W=80mils W=80mils 12
GND
13
+5VALW +USB3_VCCA 5 2 GND
LS3 EMI@ VDD GND SINGA_2UB4039-200011F_9P
CS3 1 2 USB20_P2_L DC23300AQ00
[11] USB20_P2
1 2 US1
1 USB20_P2_L 4 1
0.1U_0201_10V K X5R 5 OUT 4 3 USB20_N2_L I/O3 I/O1
IN [11] USB20_N2
2 RS2 AZC099-04S.R7G_SOT23-6
USB_EN# 4 GND 0_0402_5% EXC24CQ900U_4P SC300001G00
[33] USB_EN# EN

USB2.0_Port
3 1 @ 2 SM070004400
OCB USB_OC0# [11]
SY6288D20AAC_SOT23-5
220U_6.3V_M
CS4

1 +USB3_VCCA
+
1
@
W=80mils
ESD
CS5
470P_0402_50V7K
2 2
JUSB2 ME@
LS4 EMI@ 1 5
1 2 USB20_P4_L DS3 ESD@ VBUS SHLD1
[11] USB20_P4 +USB3_VCCA USB20_N4_L USB20_N4_L
6 3 2 6
I/O4 I/O2 D- SHLD2
B USB20_N4_L USB20_P4_L B
4 3 3 7
[11] USB20_N4 D+ SHLD3
EXC24CQ900U_4P 5 2 4 8
VDD GND GND SHLD4
SM070004400

USB20_P4_L 4 1 DC23300I800
I/O3 I/O1 SDAN_608050-004041
AZC099-04S.R7G_SOT23-6
SC300001G00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/05/19 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Dat e: Monday, April 10, 2017 Sheet 32 of 52

5 4 3 2 1
 +3VLP +EC_VCCA
+3VLP

L20
FBMA-L11-160808-601LMT_2P R2017 1 RS@ 2 0_0402_5% +3VLP_EC
1 2 1 EMI@
1 1 C179
C184 C185 100P_0402_50V8J
0.1U_0201_10V6K 1000P_0402_50V7K
EMI@ 2
1 2 2 ECAGND 2
L21 1 1 1 1
FBMA-L11-160808-601LMT_2P +EC_VCCA

0.1U_0201_10V6K
C180

0.1U_0201_10V6K
C181

1000P_0402_50V7K
C182

1000P_0402_50V7K
C183
+5VALW
ECAGND 2 2 EMI@2 EMI@2
USB_EN#

111
125
R194 1 2 10K_0402_5%

22
33
96

67
9
U11

VCC1/LPC
VCC2
VCC3
VCC4

VCC5/SPI

AVCC
VSBY
+3VS
1 21
[31] NOVO# GPIO85/GA20 GPIO15/A_PWM VCCST_PWRGD [9]
2 23 BEEP#
[7] KB_RST# GPIO86/KBRST# GPIO21/B_PWM BEEP# [35]
3 PWM Output 26
[7] SERIRQ SERIRQ/GPIOF0 GPIO32/D_PWM EC_VCIN1_AC_BYPASS_R EC_FAN_PWM1 [31]
RS@ 2 0_0402_5% EC_VCIN1_AC_BYPASS
EMI
4 27 R222 1
[7] LPC_FRAME# LPC_AD3 LFRAME#/GPIOF6 GPIO45/E_PWM
5
[7] LPC_AD3 LPC_AD2 7 LAD3/GPIOF4 TP_CLK R260 1 2 4.7K_0402_5%
[7] LPC_AD2 LPC_AD1 LAD2/GPIOF3
8 63
[7] LPC_AD1 LPC_AD0 LAD1/GPIOF2 GPIO90/AD0 VCIN1_BATT_TEMP [39,40]
LAD0/GPIOF1 LPC & MISC
@EMI@ @EMI@ 10 64
2 1 [7] LPC_AD0 GPIO91/AD1 VCIN1_BATT_DROP [41]
R190 2 1 10_0402_1% 65
GPIO92/AD2 ADP_I [40] TP_DATA
C186 22P_0402_50V8J
[7] CK_LPC_KBC
12
LCLK/GPIOF5 AD Input GPIO93/AD3
66
DCHG_I [40]
R261 1 2 4.7K_0402_5%
13 75
[9,20,30,34] PCIRST# EC_RST# LRESET#/GPIOF7 GPIO05/AD4
1 2 37 76
+3VLP R192 47K_0402_5% EC_SCI# 20 ECRST# GPIO04/AD5
[5,9] EC_SCI# 38 GPIO54/ECSCI# VCIN1_BATT_TEMP 1 2
1 GPIO11/CLKRUN#
C187 68 C189 100P_0402_50V8J
GPIO94/DA0

ESD
0.1U_0201_10V6K 70
GPIO95/DA1
2
DA Output GPIO96/DA2
71
DGPU_PWR_EN [10,22,48]
KSO[0..17] KSI0 55 72
[31] KSO[0..17] 56 KBSIN0/GPIOA0 GPIO97/DA3 USB_EN# [32]
KSI1
KSI[0..7] KSI2 57 KBSIN1/GPIOA1
[31] KSI[0..7] KSI3 58 KBSIN2/GPIOA2 83 VCCST_PWRGD 1 2
KSI4 59 KBSIN3/GPIOA3 GPIO31/SCL3/PSCLK1 84 C194 100P_0402_50V8J
KSI5 60 KBSIN4/GPIOA4/N2TCK GPIO23/SDA3/PSDAT1 85
KBSIN5/GPIOA5/N2TMS GPIO47/SCL4/PSCLK2 ESD@
KSI6 61
KBSIN6/GPIOA6 PS2 InterfaceGPIO53/SDA4/PSDAT2 86
TP_CLK
KSI7 62 87
39 KBSIN7/GPIOA7 GPIO50/PSCLK3 88 TP_DATA TP_CLK [31]
KSO0
KBSOUT0/GPIOB0/SOUT_CR/JENK# GPIO52/PSDAT3 TP_DATA [31]
+3VLP KSO1 40
KBSOUT1/GPIOB1/TEST#
KSO2 41
R201 KSO3 42 KBSOUT2/GP(I)OB2/TRIST# 97
EC_SMB_CK1 KBSOUT3/GP(I)OB3/XORTR# GPIO02 ENBKL [5,27]
1 2 KSO4 43 98
44 KBSOUT4/GPIOB4/SDP_VIS# GPIO75 99 SYS_PWROK [9]
2.2K_0402_5% KSO5
KBSOUT5/GPIOB5/TDO GPIO GPIO76 ME_EN [8]
R202 KSO6 45 109
EC_SMB_DA1 KBSOUT6/GPIOB6/RDY# VCIN1/GPIO16 VCIN0_PH1 [39]
1 2 KSO7 46 Int. K/B
2.2K_0402_5% KSO8 47 KBSOUT7/GPIOB7
48 KBSOUT8/GPIOC0 Matrix 119
KSO9
49 KBSOUT9/GPIOC1 F_SDI&F_SDIO1/GPO80 120 EC_SPI_MISO [7]
KSO10
KBSOUT10&P80_CLK/GPIOC2 F_SDIO&F_SDIO0/GPIOC6 EC_SPI_MOSI [7]

ESD
KSO11 50 126
KBSOUT11&P80_DAT/GPIOC3 F_CLK/GPIOC4 EC_SPI_CLK [7]
KSO12 51
KBSOUT12/GPIO64/TCK SPI Flash ROM F_CS0#/GPIOC5 128
EC_SPI_CS0# [7]
KSO13 52
KSO14 53 KBSOUT13/GPIO63/TMS
KSO15 54 KBSOUT14/GPIO62/TDI 73 SYSON
KSO16 81 KBSOUT15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM 74
GPIO60/KBSOUT16 GPIO07/AD7/CIRTX1 CMOS_ON# [27]
KSO17 82 89
GPIO57/KBSOUT17 GPIO67/N2TMS EC_MUTE# [35]

1
90 1
GPIO51/N2TCK BATT_CHG_LED# [31]
91 CAPS_LED# [31]
EC_SMB_CK1 77 GPIO36 92
[39,40] EC_SMB_CK1 EC_SMB_DA1 GPIO17/SCL1/N2TCK GPIO GPIO40/F_PWM PWR_LED# [31]
@ R239 C193
78 93 100K_0402_5% 0.1U_0201_10V6K
[39,40] EC_SMB_DA1 EC_SMB_CK2 GPIO22/SDA1/N2TMS GPIO35 BATT_LOW_LED# [31] 2
79 95 SYSON @ESD@
[7,21] EC_SMB_CK2 EC_SMB_DA2 GPIO73/SCL2 GPIO06/IOX_DOUT SYSON [12,37,42]

2
[7,21] EC_SMB_DA2
80
GPIO74/SDA2 SM Bus GPIO81/F_WP#
121
127
GPIO84/IOX_SCLK

6 100
14 GPIO24 GPIO26/RSMRST# 101 EC_RSMRST# [9]
15 GPIO10/LPCPD# GPIO20/TA2/IOX_DIO 102
[9] EC_CLEAR_CMOS# 16 GPIO65/SMI# VC_IN2/GPIO72 103
T187 TP@ GPIO34/1_WIRE/CIRRXL VC_OUT2/GPIO37 VCOUT1_PROCHOT# [40] VCOUT1_PROCHOT#
T188 TP@ 17 104 R204 1 RS@ 2 0_0402_5%
GPIO01/TB2 VC_OUT1/GPIO25 VCOUT0_MAIN_PWR_ON [41]
+3VALW 18 GPIO 105 BKOFF#
19 GPIO43 GPIO77 106 BKOFF# [27]
[30,34] EC_PCIE_WAKE# GPIO42/CIRTX2 GPIO GPIO44 PM_SLP_S3# [9]
T189 TP@ 25 107 R205 1 RS@ 2 0_0402_5% H_PROCHOT# [5]
1 2 EC_PCIE_WAKE# 28 GPIO13/C_PWM GPIO12 108 VR_PWRGD [45] [45] VR_HOT#
[31] EC_FAN_SPEED1 VCIN1_AC_IN GPIO56/TA1 GPIO30/F_WP# VR_ON [45]
R212 1K_0402_5% 29
[9,21,40] VCIN1_AC_IN EC_TX GPIO14/TB1
30
[30] EC_TX EC_RX 31 GPIO83/SOUT_CR/P80_DATA 110 EC_VCIN1_AC_BYPASS VCIN1_AC_IN
R2006 1 @ 2 0_0402_5% 1
[30] EC_RX PCH_PWROK GPIO87/SIN_CR/P80_CLK AC_IN/GPIO41/F_WP# EC_ON
32 112 @
[9] PCH_PWROK 34 GPIO27/RSMRST# EC_ON/GPIO71 114 EC_ON [41]
GPIO66/G_PWM GPIO ON_OFFBTN#/GPIO70 LID_SW# ON/OFF# [31] C191
36 115 47P_0402_50V8J
[31] NUM_LED# GPIO33/H_PWM GPO82/IOX_LDSH/LIDIN LID_SW# [31] 2
116 SUSP#
GPIO46/CIRRXM/PLCIN 117 NUVOTON_VTT SUSP# [12,37,42]
VTT
PECI PECI
118 PECI R208 1 2 43_0402_1%
H_PECI [5]
122
[9] PBTN_OUT# PM_SLP_S4#_R GPIO00/EXTCLK
1 RS@ 2 123 124 +V18R R209 1 @ 2 0_0402_5% +3VLP
[9,40,42] PM_SLP_S4# GPIO55/CLKOUT/IOX_DIO VCORF
R269 0_0402_5% 1
1 2 VCIN1_AC_IN
AGND
GND1
GND2
GND3
GND4
GND5

C192
4.7U_0603_6.3V6K
C190 100P_0402_50V8J
1 2
R203 @ 4.7K_0402_5% 2 SUSP#
113
11
24
35
94

69

NPCE388NA0DX_LQFP128_14X14
ECAGND

2
ESD @
R2016
100K_0402_5%
PCH_PWROK

1
+1.0V_VCCST
1

ESD@
C250
100P_0402_50V8J NUVOTON_VTT R210 1 RS@ 2 0_0402_5%
2

+3VS

1 2 EC_FAN_SPEED1
R214 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/09/01 Deciphered Date 2015/09/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC_NPCE388N
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 33 of 52

 5 4 3 2 1

RJ-45 CONN.
+3VALW +3V_LAN
D D

W=60mil R154 1 RS@ 2 0_0603_5%

W=60mil +LAN_VDD JLAN1 ME@
RJ45_TX0+ 1
2 PR1+
CL1 RJ45_TX0- 2
1U_0402_6.3V6K +3VS PR1-

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

1U_0402_6.3V6K

0.1U_0201_10V K X5R
1 1 1 1 1 1 RJ45_RX1+
1 3
CL2 CL3 CL4 CL5 CL6 CL17 PR2+

1
4
2 2 2 2 2 2 RL2 PR3+
1K_0402_5% 5
PR3-
RJ45_RX1- 6
PR2-

2
ISOLATE#
7 9
PR4+ GND 10
Close to Pin3, Pin8, Pin22, Pin30, Pin22 Pin24 8 GND
RL3 PR4-
15K_0402_5% SANTA_130452-S
DC234005N10

Rising time (10%~90%)要

>1mS and <100mS

+3V_LAN
LANGND LANGND1
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

1 1 1 1 1
C @ @ @ C
CL18 CL7 CL8 CL9 CL10
2 2 2 2 2 UL1

+LAN_VDD +LAN_VDD

+3V_LAN
These components close to Pin 17, 18

W=60mils CL11 1 2 0.1U_0201_10V K X5R

PCIE_CRX_DTX_N5 [11]
LAN_MDIP0 1 17 PCIE_CRX_C_GTX_N5
LAN_MDIN0 2 MDIP0 HSOP 18 PCIE_CRX_C_GTX_P5 CL12 1 2 0.1U_0201_10V K X5R
MDIN0 HSON PCIE_CRX_DTX_P5 [11]
CL7, CL9 close to Pin 11 3 19 PCIRST#
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# PCIRST# [9,20,30,33]
LAN_MDIN1 5 MDIP1 ISOLATEB 21 EC_PCIE_WAKE# R129 2 RS@ 1 0_0402_5%
CL8, CL10 close to Pin 32 6 MDIN1 LANWAKEB 22 EC_PCIE_WAKE# [30,33]
LANGND1

7 MDIP2 DVDD10 23 R126 1 @EMI@ 2 0_0402_5%

+3V_LAN 8 MDIN2 VDDREG 24 +3V_LAN
9 AVDD10 REGOUT 25 TPL1@
10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPIO 27 RL4 10K_0402_5% LANGND1
LANCLK_REQ# 12 AVDD33 LED0 28 XTLO TPL2@
[9] LANCLK_REQ# PCIE_CTX_C_DRX_P5 13 CLKREQB CKXTAL1 29 XTLI R131 2 RS@ 1 0_0402_5% LANGND
[11] PCIE_CTX_C_DRX_P5 PCIE_CTX_C_DRX_N5 14 HSIP CKXTAL2 30
[11] PCIE_CTX_C_DRX_N5 CLK_PCIE_LAN 15 HSIN AVDD10 31 2.49K_0402_1% 2 1 RL6 R130 1 @EMI@ 2 0_0402_5%
[9] CLK_PCIE_LAN CLK_PCIE_LAN# 16 REFCLK_P RSET 32
[9] CLK_PCIE_LAN# REFCLK_N AVDD33
GND
33
reserved GPIO pin
LANGND

25MHz CRYSTAL
RTL8107E-CG QFN 32P E-LAN CTRL
SA000065Y00
B B

TL1
CL13
1 2 XTLO LAN_MDIN1 1 16 RJ45_RX1-
LAN_MDIP1 RD+ RX+ RJ45_RX1+

ESD
2 15 RL8 EMI@ CL14 EMI@
10P_0402_50V8J 3 RD- RX- 14 1 2 1 2 LANGND
4 RDCT RXCT 13
5 NC NC 12 75_0805_5% 10P_0603_50V
YL1 6 NC NC 11 2 1
LAN_MDIN0 7 TDCT TXCT 10 RJ45_TX0-
1 3 @ESD@ LAN_MDIP0 8 TD+ TX+ 9 RJ45_TX0+ DL1 LANGND
1 3 DL2 TD- TX- BS4200N-C-LV_SMB-F2
GND GND LAN_MDIN0 1 4 LAN_MDIP1 @EMI@
I/O1 I/O3 1
300UH_NS681612A
2 4 CL15
0.01U_0402_16V7K
25MHZ_10PF_7V25000014 2 5 2 EMI@
GND VDD
CL16
1 2 XTLI
LAN_MDIP0 3 6 LAN_MDIN1
10P_0402_50V8J I/O2 I/O4
AZC099-04S.R7G_SOT23-6
SC300001G00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/12 Deciphered Date 2014/04/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8107E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 34 of 52

5 4 3 2 1
 A B C D E

CX11802 Speaker wide 40MIL

0.1U_0201_10V6K
2.2U_0402_6.3V6M
1 1

1U_0402_6.3V6K

0.1U_0201_10V6K
1

CA39

CA38
1
CA31

CA32
EMI
2 2 JSPK1 ME@
2 SPK_L1- SPK_L1-_CONN

2
LA3 1 RS@ 2 0_0603_5% 1
SPK_L2+ LA2 1 RS@ 2 0_0603_5% SPK_L2+_CONN 2 1
RA5 +5VS 2
GNDA GNDA 0_0603_5%
1
+AVDD_CODEC RS@ 2 3
4 G1
G2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
+3VDD_CODEC 1 CA16 2 2 1 1
CA13 CA12 E-T_3806K-F02N-03R_2P

1000P_0402_50V7K

1000P_0402_50V7K

2
SP02E005320

0.1U_0201_10V K X5R

CA8
CA40
+IOVDD_CODEC
1 1 DA4

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
2 1 1 2 2 @ESD@

EMI@ CA28

EMI@ CA29
1 1
L03ESDL5V0CC3-2_SOT23-3
CA14 2 1 4.7U_0603_6.3V6K SCA00002900
2 2

18

24

29

27

28

13
16

11

1
3

2
7
UA1

VDDO33

DVDD33

LPWR5.0
RPWR5.0

CLASS_D_REF
VDD_IO

AVDD_3.3V
FILT_1.8V

AVDD_HP

FILT_1.65V

AVDD_5V
[8] HDA_RST_AUDIO#
9
RESET#
Combo Jack
2 1 1 RA19 2
PLUG_IN_R EXT_MIC_SLEEVE
C188 22P_0402_50V8J 33_0402_5%
JSENSE
38 W=40mils R10 1 2 100_0402_5% CA23 2 1 1U_0402_10V6K HGNDB
@EMI@ @EMI@ CX11802-33Z W=40mils
EXT_MIC_RING2 R11 1
HP_OUTL
2 100_0402_5% CA24 2 1 1U_0402_10V6K HGNDA
HPOUT_L
5 35 MICBIASC 1 EMI@ 2
[8] HDA_BITCLK_AUDIO BIT_CLK MICBIASC HP_OUTR HPOUT_R
[8] HDA_SYNC_AUDIO 8 34 MICBIASB RA22 1 EMI@ 2 47_0402_5%
1 RA15 2 HDA_SDIN0_AUDIO 6 SYNC MICBIASB RA23 47_0402_5%
[8] HDA_SDIN0 SDATA_IN
33_0402_5% 4 33 LINE1-R

@EMI@

@EMI@

@EMI@

@EMI@
[8] HDA_SDOUT_AUDIO SDATA_OUT PORT_B_R_LINE 32 LINE1-L
PORT_B_L_LINE
RA9 1 RS@ 2 0_0603_5% 39
For Universal Audio Jack
[33] EC_MUTE# SPKR_MUTE# 1 1 1 1
LINE1-L 1 R5 2 1 2 CA21 CA33 CA34 CA36 CA37
2

26 HGNDB 100_0402_5% 1U_0603_6.3V6M

RA10 PC_BEEP 10 HGNDB 25 HGNDA LINE1-R 1 R9 2 1 2 CA22
PC_BEEP HGNDA

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
@ 10K_0402_5% 31 EXT_MIC_RING2 100_0402_5% 1U_0603_6.3V6M 2 2 2 2
1 PORTD_B_MIC 30 EXT_MIC_SLEEVE
DMIC_DAT/GPIO1 PORTD_A_MIC
40
DMIC_CLK/MUSIC_REQ/GPIO0
MICBIASB 1 2 GNDA
1

RA2 3K_0402_5%
23 HP_OUTR MICBIASB 1 2
37 PORTA_R 22 HP_OUTL RA4 3K_0402_5%
LINE2-L 36 GPIO1/PORTC_R_MIC PORTA_L
MUSIC_REQ/GPIO0/PORTC_L_MIC
SPK_L2+ 12
LEFT+ 21 AVEE
2 1 2
SPK_L1- 14 AVEE 20
LEFT- FLY_N 19 CA20 1 2 1U_0402_6.3V6K CA18

Combo Jack
15 FLY_P
RIGHT- 2.2U_0402_6.3V6M
2

(Normal Open)
EP_GND
17

wide 60MIL
RIGHT+

JHP1
HGNDB 3
HPOUT_L HPOUT_L1
41

CX11802-33Z_QFN40_5X5 RA121 RS@ 2 0_0402_5% 1

PLUG_IN 6
HPOUT_R RA161 RS@ 2 0_0402_5% HPOUT_R1 2

Each Pla or m Po wer Net Support Li st：

HGNDA 4
7

SINGA_2SJ3095-067111F
+1.5VS +1.8VS +3VS +5VS +3VALW
+3VS → +I OVDD_CODEC
DC23000DY00
RA11 ME@

2
33K_0402_5%
1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5)

2
DA5 GNDA
DA3 @ESD@
AMD Carrizo V V V V V ESD@

+3VS +IOVDD_CODEC
AMD Carrizo-L V V V V V L03ESDL5V0CC3-2_SOT23-3
L03ESDL5V0CC3-2_SOT23-3 SCA00002900
Intel Broadwell V V V V SCA00002900

Intel Braswell V V V V V EMI

1
1
RA3 1 RS@ 2 0_0603_5% GNDA
Intel Skylake V V V V V
0.1U_0201_10V6K

3 1 3
Intel Bay trail-M V V V V V
CA6

place close audio codec

RA21 1 RS@ 2 0_0402_5%
2
Place near Pin7 +3VS
Each Pla or m HDA Li nk Volt age Support ( Pi n 7)： RA24 1 RS@ 2 0_0402_5%

3.3V 1.5V/1.8V

1
RA17 RA25 1 RS@ 2 0_0402_5%
AMD Carrizo V 5.11K_0402_1%

AMD Carrizo-L V RA28 1 RS@ 2 0_0402_5%

2
RA20 1 2 5.11K_0402_1%
Intel Broadwell V V
PLUG_IN_R PLUG_IN
Intel Braswell V RA18 1 2 13.3K_0402_1% GND GNDA
Intel Skylake V V
Intel Bay trail-M V

PC Beep
MICBIASC

AMIC

2
RA147
+AVDD_CODEC +3VDD_CODEC 2.2K_0402_5%

@ 1 2 1 2 PC_BEEP MIC1
[33] BEEP# LINE2-L_R

1
+3VALW RA1 1 2 0_0603_5% RA39
1 2
4.7K_0402_5% CA17
1 2
0.1U_0201_10V K X5R for 14 +
1 R4 1 2 100_0402_5% 1 2 LINE2-L
[8] HDA_SPKR CA41 2.2U_0402_6.3V6M
RA40 4.7K_0402_5% CA19 0.1U_0201_10V K X5R 2 GNDA

1000P_0402_50V7K
1 RS@ 2 0_0603_5% -
+3VS 1
RA13 RA14 1 RS@ 2 0_0603_5% KECG2242PFL-B4_2P GNDA

CA188

@EMI@
+3VS
4 45@ 4
1U_0402_6.3V6K

0.1U_0201_10V6K

1 MIC2
1U_0402_6.3V6K

LINE2-L_R 2
1

for 15 1
CA15

CA30

+
1
CA27

2
2 -
2

GNDA
2

KECG2242PFL-B4_2P
45@ GNDA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/09/01 Deciphered Date 2015/09/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_Conexent_11802
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 35 of 52

A B C D E
 5 4 3 2 1

D D

+3VS

UR1

RR1 2 1 6.19K_0402_1% RREF 1

RREF 22
N/A 21 SD_D2
1 CR1 1 CR2 USB20_CR_N6 SD_D2 SD_D3
2 20
USB20_CR_P6 3 DM SD_D3 19

0.1U_0201_10V K X5R

4.7U_0603_6.3V6K
DP SD_D4 18 SD_CMD
2 2 SD_CMD 16
4 SD_D5 15 SD_CLK_R RR2 1 RS@ 2 0_0402_5% SD_CLK
+3VS 3V3_IN SD_CLK
Trace width:40mil +Card_3V3
5
CARD_3V3 SD_D6
14
13 SD_CD_N
SD_CD# 1
12 @EMI@
7 SD_D7 11 SD_D0 CR3
23 N/A SD_D0 10 SD_D1 5P_0402_50V8C
17 N/A SD_D1 9 2
6 GPIO0 N/A 8 SD_WP
SDREG SD_WP
V18 24
V18
25
Thermal pad
2 2
RTS5170-GR_QFN24_4X4
CR4 CR5
C C

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1

SD/SDXC
+Card_3V3
JSD1
SD_D0 7 4
D0 VDD
LR1 EMI@ SD_D1 8 11 SD_WP
1 2 USB20_CR_N6 D1 WP
[11] USB20_N6 SD_D2 9 CR6 1 1 CR7
D2 10 SD_CD_N
4 3 USB20_CR_P6 SD_D3 1 CD2

4.7U_0603_6.3V6K

0.1U_0201_10V K X5R
[11] USB20_P6 D3/CD1 3
MCM1012B900F06BP_4P VSS1 6 2 2
SM070003Z00 SD_CLK 5 VSS2
CLK 12
SD_CMD 2 GND 13
CMD GND
FOX_WK21921-R93-9H
SP070014L00
B
ME@
Close to connector B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CardRead/RTS5170
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 36 of 52

5 4 3 2 1
 A B C D E

+3VALW +5VALW

10U_0603_6.3V6M
C205
1 1
+3VALW to +3VS

C206
@ +3VS
0.1U_0201_10V6K U13 J4
2 2 1 14 +3VALW_3VS 2 1 R235 1 @ 2 470_0603_5%
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1 D

1
JUMP_43X79

10U_0603_6.3V6M
3 12 1 2 C207 1 1 2 SUSP
ON1 CT1 470P_0402_50V7K C212 G

C211
1 [12,33,42] SUSP# 1
4 11 @ S Q14 @
VBIAS GND

3
0.1U_0201_10V6K 2N7002H_SOT23-3
+5VALW 5 10 1 2 C213 2 2
ON2 CT2 220P_0402_50V7K
6 9 +5VALW_5VS
7 VIN2 VOUT2 8
10U_0603_6.3V6M

VIN2 VOUT2
1 1
C214 15
C215

@ GPAD +5VS
0.1U_0201_10V6K EM5209VF_DFN14_2X3 J5
2 2 2 1
2 1

+5VALW to +5VS JUMP_43X79

10U_0603_6.3V6M
1 1
C218

C217
@
0.1U_0201_10V6K
2 2

2 2

+5VALW +0.6VS

1
R230 R228
@ @
100K_0402_5% 470_0402_5%

2
SUSP
D D

1
Q23 Q21
SUSP# 2 @ SUSP 2 @
G G
S S

3
2N7002H_SOT23-3 2N7002H_SOT23-3

3 3

+5VALW

2
@
R233
220K_0402_5% +1.35VGS

1
SYSON#

@ Q24 R234
DRC2124E0L NPN MINI3-G3-B 1 470_0603_5%
OUT @

1 2
D
2 2 SYSON#
[12,33,42] SYSON IN G
GND

S Q25

3
2N7002H_SOT23-3
@
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-D562P 2.0

Date: Monday, April 10, 2017 Sheet 37 of 52

A B C D E
 5 4 3 2 1

ACES_50278-00401-001 EMI@ PL101

G2 5
6
PF101
5A_Z120_25M_0805_2P
1 2
+19V_VIN
G1 4 APDIN 7A_32VDC_0437007.WRML
4 3 1 2 +19V_APDIN
3 2 EMI@ PL102
2 1 5A_Z120_25M_0805_2P
1 1 2

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
JDCIN1
CONN@

1
EMI@ PC101

EMI@ PC102

EMI@ PC103

EMI@ PC104
2

2
D D

C C
2

PR107
+CHGRTC
45.3K_0603_1%

PR108
1.5K_0603_5%
1

1 2
PD101
+3VL
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1 JRTC1
3 PR109
1K_0603_5%
1 2 1 2
+ -

LOTES_AAA-BAT-054-K01
CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
SKL 2.0

Date: Monday, April 10, 2017 Sheet 38 of 52

5 4 3 2 1
 5 4 3 2 1

EMI@ PL201
VMB2 +8.4V_VMB 5A_Z120_25M_0805_2P
PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
1 1 2
1 2 +12.6V_BATT+
EMI@ PL202
2 3 EC_SMCA 5A_Z120_25M_0805_2P
3 4 EC_SMDA 1 2
4 5
5 6
6

1
7
7

1
8

100_0402_1%

100_0402_1%
8 9 PC201 EMI@ PC202 EMI@
D GND 10 1000P_0402_50V7K 0.01U_0402_25V7K D
GND

2
11

PR201

PR202
GND

2
12
GND
SUYIN_125022HB008M200ZL
CONN@

EC_SMB_CK1 [33,40]

EC_SMB_DA1 [33,40]
1 2
+3VL
PR203
1 2 200K_0402_1% +3VALW
PR204
@ 200K_0402_1%
1 2
PR205
VCIN1_BATT_TEMP [33,40] PH201 under CPU botten side :
10K_0402_5%
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

+EC_VCCA

16.5K_0402_1%
1
C C

PR206
2
[33] VCIN0_PH1

1
PH201
100K +-1% 0402 B25/50 4250K

2
ECAGND

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
SKL 2.0

Date: Monday, April 10, 2017 Sheet 39 of 52

5 4 3 2 1
 A B C D

0x3CH <BIT9> PSYS current gain **Design Notes**

Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 10mΩ and Rs2 = 10 mΩ For 45W/65W /90W system, 2S/3S/4S battery
BIT0 = 1.14uA/W Maximum Charging current 3.5A
BIT1 = 0.285uA/W
========================================================= Maximum Battery discharge power 55W
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20 Ω
m #Register Setting
BIT0 = 2.28uA/W 1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function
BIT1 = 0.57uA/W 2. Disable turbo when AC only
#Circuit Design
1. ACLIM and CCLIM are devider voltage control.
Ipsys = KPSYS  x ( VAD P x IAD P + VBA T x IBA
 T ) 2. Use 7X7 choke and 3X3 H/L side MOSFET
R_Psys = 1.2V / Ipsys Protection for reverse input Charge current 3A
KPSYS = 1.14uA/W Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
adapter wattage = 45W Power density : 0.61 (23X16)
Battery wattage = 40Wh #Protect function
Ipsys = 1.14 x (45+40) = 96.9uA 1. ACOVP : VCC voltage > 24V
1
R_Psys = 1.2V / 96.9uA = 12.3K-ohm. Vgs = 20V 1

===================================== Vds = 60V 2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).
adapter wattage = 65W Id = 250mA 3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
Battery wattage = 40Wh D 4. CHGOCP : based on charge current setting

1
Ipsys = 1.14 x (65+40) = 119.7uA 2 PQ301 5. BATOVP : 4.6V/Cell
R_Psys = 1.2V / 96.9uA = 10K-ohm. G L2N7002WT1G_SC70-3 6. BATLOWV : No.
S max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W 7. TSHUT : 150C

3
Rds(on) = 15.8mohm max CSR rating: 1W
1 2 1 2
Vgs = 20V VCSIP-VCSIN spec < 81mV
PR301 PR302 Vds = 30V
1M_0402_1% 3M_0402_5% ID = 10.5A (Ta=70C) B+
PQ302 +19V_P1 PQ303
Need check the SOA for inrush MDU1512RH_POWERDFN56-8-5 AON7506_DFN33-8-5 PR303
1 1 +19V_P2 0.01_1206_1% +19VB_CHG
2 2 PJP301
5 3 3 5 1 4 1 2
+19V_VIN 1 2
Module model information

PC205 @EMI@

EMI@
2 3

2200P_0402_25V7K
JUMP_43X79

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V7K
4

4
@
ISL95520_Hybrid_Boost_V2.mdd

1
PC203

PC204
CSIN_CHG_R
CSIP_CHG_R

PC206
2

2
Co-lay jump and ISN choke.

1
2_0402_5%
1

PR305
0_0402_5%
PR304
1

PR306
ASGATE_CHG_R

2
392K_0402_1% @

2
PC207
PQ304
2

1 2

4.02K_0402_1%

4.02K_0402_1%
AON7506_DFN33-8-5
2 2

1
0.1U_0402_25V6

1
2
5 3

PR729 and PR732 are ACDET set t i ng base on your proj ect to set. PR309
100_0402_1%

4
PR307

PR308
1 2 +12.6V_BATT+ Rds(on) = 32mohm max
Vgs = 20V
0.22U_0402_16V7K Vds = 30V
CMSRC_CHG ID = 8A (Ta=70C)
1

PC209 @ PC210
2200P_0402_50V7K
49.9K_0402_1%

1
PR310

PC208

ASGATE_CHG

1
1 2
2

BGATE_CHG
0.1U_0402_25V7K
2

OPCN_CHG 2
CSIN_CHG
CSIP_CHG

OPCP_CHG

VBAT_CHG
Rds(on) = 32mohm max
1 VDD_CHG

Vgs = 20V
Vds = 30V

5
PU301
ID = 8A (Ta=70C) PQ305
support Turbo boost : 2200P Support max charge 3.5A
100K_0402_1%

32

31

30

29

28

27

26

25
no support Turbo boost : 0.1u ISL88739HRZ-T QFN 32P CHARGER
AON7408L_DFN8-5 Power loss: 0.245W
7X7X3
PR311

CSR rating: 1W

CSIN

CMSRC

OPCN

VBAT
ASGATE

BGATE
CSIP

QPCP
PC211 4
PR312 0_0603_5% 0.22U_0603_25V7K
Isat: 6.5A VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2 DCR: 28mohm
ACIN BOOT
2

PL302 PR315
2 23 UG_CHG 0.01_1206_1%
[9,21,33] VCIN1_AC_IN ACOK UGATE
+12.6V_BATT+

3
2
1
4.7UH_5.5A_20%_7X7X3_M
LX_CHG +17.4V_BATT_CHG
1

@ PR313 1 2 0_0402_5% 3 22 1 2 1 4
158K_0402_1%

[33,39] EC_SMB_DA1 SDA PHASE

PR314

@ PR320 1 2 0_0402_5% 4 21 LG_CHG 2 3

680P_0603_50V7K 4.7_1206_5%
[33,39] EC_SMB_CK1 SCL LGATE

@EMI@ PR317

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
VDDP_CHG

5
3
5 20 PQ306 3

PROCHOT# VDDP
2

AON7752_DFN3X3EP8-5
2 0_0402_5% AMON_ISL95520 6 VDD_CHG

1
@ PR318 1 19 1 2

PC212

PC213

PC214
[33] ADP_I AMON VDD
2 0_0402_5% BMON_ISL95520 7

2
@ PR321 1 18 PR319 4.7_0402_5%
[33] DCHG_I BMON DCIN

2
1

1
4
8 17 PC215 PC216

BATGONE
[45] PMON_SKYLAKE PSYS NTC

@EMI@ PC217
1U_0402_16V6K 1U_0402_16V6K

2
CCLIM

ACLIM
COMP
PROG
AGND

CSON
PR323

CSOP
FSET

1
PC219 100K_0402_1%
10K_0402_1%

3
2
1

2
1

PC218 1000P_0402_25V8J
PR322

PD102
Follow adapter and
9
33

10

11

12

13

14

15

16
1000P_0402_25V8J PR324 10_1206_5% 3
+19V_VIN
battery wattage in
2

@ 1 2 1

2
Vsys current source.

3
Close to 2 PQ307
EC.
2

VF = 0.38V
1

2
Base on CPU Core VR design.
FSET_CHG

PC220
1U_0603_25V6
PR326 LRB715FT1G_SOT323-3 LMUN5113T1G_SOT323-3
The resistor is pop on CPU VR schematic.
1

0_0402_5% @ PR316 2

1
@ PR325 0_0603_5%
10K_0402_1% 1 2
+12.6V_BATT+
VDD=5V VDD_CHG
2

1
2

1 2
CCLIM_CHG BA

1
@ PR339 0_0603_5% 2
200K_0402_1%

ACLIM_CHG [9,33,42] PM_SLP_S4#

1

[33] VCOUT1_PROCHOT# A31 connect to BA

PR329
PR328

200K_0402_1%
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R Other team connect to bat t conn PQ308

BA
COMP_CHG

3
PR331 2_0402_5% LMUN5236T1G NPN SOT323-3
2

1
100_0402_1%

@ PR332 Fs=729KHZ ~ +/- 15% PC221 BA

1

76.8K_0402_1%
0_0402_5%

0.1U_0402_25V6

2
1 2
PR333

PR334

CSON_CHG CSON_CHG_R
1

1 2
150K_0402_1%

560P_0402_50V7K
1
PR335

@ PQ310 @ @ PR336 0_0402_5%

PC222
53.6K_0402_1%

D
2

2
1

4 4

VCIN1_AC_IN For A31 only.

2
1

2 PR338
0.022U_0402_25V7K

Turn off Charger IC on battery only.

2

G @
PR337

82.5K_0402_1%
VCIN1_BATT_TEMP [33,39]
Depend on customer design for
1

S
PC223

BATGONE(BATT_TEMP)
3

L2N7002WT1G_SC70-3 system power consumption.

logic high: above 2.4V
2

<BOM Structure>
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ) . Hybrid boost power mode
2

logic low: under 0.8V

CC_LIM = VccLIM / 64 x Rs2 Cell = 4s
2

U45W@
============================================================= PC224
10P_0402_25V8J
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ) . PR337 U65W@
1

CC_LIM = VccLIM / 32 x Rs2

=============================================================
76.8k_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
2015/07/27 2016/07/27
PWR_CHARGER
Title
AC_LIM = Vac_LIM / 32 x Rs1 Adapter current limimed:
Issued Date Deciphered Date
For U22(45W)_adp: Battery current limimed by CCLIm ~ 3.89A. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PR337=53.6k Adapter current limimed by ACLIm ~ 4.33A. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
For U23e(65W) and DIS_adp: (PR779 and PQ741 are for change ACLIm when AC in) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
PR337=76.8k MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 10, 2017 Sheet 40 of 52
A B C D
 A B C D E

Module model information

SY8286B_V1.mdd

1 1

PU401
B+ EMI@ SY8286BRAC_QFN20_3X3 @ PR402
PL401
0_0603_5% PC402
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2

2200P_0402_50V7K
5A_Z120_25M_0805_2P 0.1U_0603_25V7K

10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC401

EMI@ PC403
0.1U_0402_25V6
1

1
PC429

PC404
PL402

IN

IN

IN

IN

BS
LX_3V6 LX_3V

2
20 1 2
@ LX LX +3VALWP
7 19 1.5UH_6A_20%_5X5X3_M

PR403
RF@
GND LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
680P_0603_50V7K 4.7_1206_5%

1
8 18
+3VLP GND GND

PC405

PC406

PC407

PC408
9 17
PG LDO +3VL

2
1 3V_SN
2
1
10 16
NC NC
Check pull up resistor of SPOK at HW side

1
PC409

OUT
EN2

EN1
21 4.7U_0603_6.3V6M

NC
FF
GND

2
PR401
100K_0402_5%

PC410
RF@
11

12

13

14

15

2
3.3V LDO 150mA~300mA
Vout is 3.234V~3.366V Ipeak=4.65A

2
[43] 3V/5VALW_PG ENLDO_3V5V
Imax=3.25A
2 PC411
1000P_0402_25V8J
PR404
1K_0402_1%
TDC=6A Iocp=10A
2

5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2

EN :H>0.8V ; L<0.4V
EN1 and EN2 dont't be floating @ PJ401
+3VALWP 1
1 2
2
+3VALW
JUMP_43X118

Module model information @ PJP402

SY8286C_V1.mdd JUMP_43X39
+3VL 1
1 2
2
+3VLP

B+ +19VB_5V
EMI@ @ PR405
PL403 PC412
PR407 PU402 SY8286CRAC_QFN20_3X3 0_0603_5%
499K_0402_1% 1 2 +19VB_5V BST_5V1 2 BST_5V_R 1 2
1 2 ENLDO_3V5V
B+ 5

1
5A_Z120_25M_0805_2P
1

0.1U_0603_25V7K
150K_0402_1%

BS
IN

IN

IN

IN
1
PR408

PC328 LX_5V 6 20 PL404

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

1U_0402_16V6K LX LX 2.2UH_7.8A_20%_7X7X3_M
LX_5V
2

7 19 1 4 +5VALWP
PC430

GND LX
2

1
PC413

PC414

EMI@ PC415

@EMI@ PC416

8 18 2 3 @ @ @
3 @ GND GND PC417 4.7U_0603_6.3V6M 3

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VCC_5V 1
2

1
9 17 2
PG VCC

1
@

PR406

PC418

PC419

PC420

PC421

PC423

PC422

PC428
4.7_1206_5%
10 16

RF@
NC NC

2
PR410
OUT

LDO
EN2

EN1

2.2K_0402_5% 21
FF

1 2 GND
[33] EC_ON

2
@ PR411
11

12

13

14

15

0_0402_5%
1 2 +5VLP

15V_SN
4.7U_0603_6.3V6M

[33] VCOUT0_MAIN_PWR_ON 5V LDO 150mA~300mA

1

680P_0603_50V7K
PC424

ENLDO_3V5V

PC425
RF@
5V_3V_EN
2

5V_3V_EN
Vout is 4.998V~5.202V

2
1M_0402_1%

4.7U_0402_6.3V6M
1

EN :H>0.8V ; L<0.4V TDC=6A Ipeak=9A

1
PR413

PC427

PC426 PR412
1000P_0402_25V8J
5V_FB 1
1K_0402_1% Imax=6.25A
2 5V_FB_1 1
2

EN1 and EN2 dont't be floating 2

Iocp=10A
2

+19VB_5V

@BATTDROP@ @ PJ403
+5VALWP +5VALW
1

1 2
PR341 1 2
JUMP_43X118
560K_0402_5%
4 @ PJP404 4
2

JUMP_43X39
VCIN1_BATT_DROP [33]
+5VLP 1
1 2
2
+VL
1

@BATTDROP@ @BATTDROP@
PR342 PC327
1000P_0402_25V8J
2

105K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 3VALW/5VALW-SY8286B&C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 10, 2017 Sheet 41 of 52
A B C D E
 A B C D E

Pin19 need pull separate from +1.35VP. 0.675Volt +/- 5%

If you have +1.35V and +0.675V sequence question, TDC 0.7A
you can change from +1.35VP to +1.35VS.
B+
EMI@ PL501
5A_Z120_25M_0805_2P Peak Current 1A
1 2 +12.6VB_DDR PR501
2.2_0603_5%
BST_DDR_R 1 2 BST_DDR
+1.2VP

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
@EMI@ PC501

EMI@ PC502

PC503

PC504
UG_DDR +0.6VSP

2
1 1

LX_DDR

10U_0603_6.3V6M

10U_0603_6.3V6M
1
PC505

1
0.1U_0603_25V7K

PC506

PC507
16

17

18

19

20
2
PU501

2
PQ501 4

BOOT

VTT
VLDOIN
PHASE

UGATE
21
AON7408L_DFN8-5 PAD
LG_DDR 15 1
LGATE VTTGND

1
2
3
14 2
PL502 PR502 PGND VTTSNS
1UH_11A_20%_7X7X3_M 13K_0402_1%
1 2 1 2 CS_DDR 13 3
+1.2VP CS GND

5
PC508 RT8207PGQW_WQFN20_3X3

1
PQ502 1U_0402_10V6K
AON7506_DFN33-8-5 1 2 12 4 VTTREF_DDR
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

RF@ PR503 PR504 VDDP VTTREF

1

4.7_1206_5% 5.1_0603_5%
PC509

PC510

PC511

PC512

PC513

PC514

4 1 2 VDD_DDR 11 5
+5VALW VDD VDDQ +1.2VP

1 2

1
PGOOD
2

PC516
+5VALW PR505

TON
0.033U_0402_16V7K

1
RF@ PC515

FB
S5

S3

2
680P_0402_50V7K PC517 1 2

1
2
3
1U_0402_10V6K 5.1_0603_5%

10

6
FB_DDR
EN_DDR
TON_DDR

EN_0.6VSP
PR507
1 2 +1.2VP
PR508 470K_0402_1%
+12.6VB_DDR 1 2
6.04K_0402_1%

1
@ PR510 0_0402_1% PR509
10K_0402_1%
1 2
[12,33,37] SYSON

2
MOSFET: 3x3 DFN

1
2 H/S Rds(on): 27mohm(Typ), 34mohm(Max) @ PC518
0.1U_0402_10V7K 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

2
L/S Rds(on): 19mohm(Typ), 23.5mohm(Max)
Mode Level +0.675VSP VTTREF_1.35V Idsm: 11A@Ta=25C, 8.8A@Ta=70C
@ PR511
0_0402_1%
S5 L off off 1 2 @ PJ501
S3 L off on Choke: 7x7x3 [12,33,37] SUSP# +1.2VP 1 2 +1.2V
1 2
S0 H on on Rdc=6.7mohm(Typ), 7.4mohm(Max) @ PR518 0_0402_1% JUMP_43X118
Note: S3 - sleep ; S5 - power off Switching Frequency:540kHz 1 2
[6] DDR_VTT_PG_CTRL
Ipeak=8A

1
Iocp~9.6A @ PC519
OVP: 113%~120% 0.1U_0402_10V7K PJ503 @
VFB=0.75V, Vout=1.3545V

2
1 2
+0.6VSP 1 2 +0.6VS
JUMP_43X39

3 3

Module model information

SY8003A_V1.mdd

@ PR512
0_0402_5%
+2.5VSP_ON 1 2 PM_SLP_S4# [9,33,40]
0.1U_0402_16V7K

1
PC520
1

PR514
@ 1M_0402_5%
Note:Iload(max)=2.5A
2

PU502
2

9 @
PGND PJ504
1 8
FB SGND 1 2
PJ505 @ 2 7 +2.5VP 1 2 +2.5V
PG EN PL503
+3VALW 1 2 3 6 LX_2.5V 1 2 JUMP_43X79
1 2 IN LX 1UH_2.8A_30%_4X4X2_F +2.5VP
1

4 5
68P_0402_50V8J

JUMP_43X79 PGND NC
1

PC521 PR516
4.7_0603_5%

1
PR515

PC522
22U_0603_6.3V6M

Rup
2

36.5K_0402_1%
22U_0603_6.3V6M

22U_0603_6.3V6M

SY8003ADFC_DFN8_2X2
@EMI@

PC523

PC524
2

2
2

FB_2.5V
1
1

FB=0.6V PR517
680P_0402_50V7K

Note:Iload(max)=3A Rdown
PC525

11.5K_0402_1%
2

@EMI@

Vout=0.6V* (1+Rup/Rdown)
4 4

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage

Security Classification
2015/07/27
Compal Secret Data
2016/07/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.2VP/+0.6VSP/+2.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
SKL 2.0

Date: Monday, April 10, 2017 Sheet 42 of 52

A B C D E
 A B C D

1 1

Module model information

APL5930_V2.mdd

+3VALW +5VALW

2
1
Ultra Low Dropout 0.23V(typical) at 3A Output Current 2

1
1 PC601
1U_0402_6.3V6K
JUMP_43X79
@ PJ601

2
2
2

PU601
G971ADJF11U SO 8P
1

PC602 6
4.7U_0603_6.3V6K 5 VCNTL 3
9 VIN VOUT 4 PJ602
@ PR601 @
VIN VOUT
+1.8VALWP
2

0_0402_5% +1.8VALWP 1 2 +1.8VALW

1 2

1
1 2 8

0.01U_0402_25V7K
[41] 3V/5VALW_PG EN

1
7 2 PR603 JUMP_43X79
POK GND FB 12.7K_0402_1%

PC604

22U_0603_6.3V6M
Rup
1

0.1U_0402_16V7K

1
PC603

2
PR604

PC605
2

1M_0402_5%

2
2

@
2

PR606

1
100K_0402_5%
PR605
10K_0402_1%
Rdown
1

2
[44] PGOOD

Vout=0.8V* (1+Rup/Rdown)
3 3

+3VALW

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8V_PRIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 10, 2017 Sheet 43 of 53
A B C D
 5 4 3 2 1

D D

C C

Module model information

SY8288_V1.mdd

Confirm HW side
+19VB_1V @EMI@ PR703 @EMI@ PC702
4.7_1206_5% 680P_0603_50V7K
PR710 +3VALW 1 2 SNUB_1V 1 2
@ 10K_0402_5%
@ PJ701 PU701

B+ (Common Part SH00000YE00)

1 2 +19VB_1V 2 9 1 2 @ PR704 PC704
1 2 IN PG 0_0402_5% 0.1U_0201_10V6K
10U_0805_25V6K
0.1U_0402_25V6

3 1 BST_1V 1 2 BST_1V_R 1 2 PL504

JUMP_43X79 IN BS
2200P_0402_50V7K
1

1UH_11A_20%_7X7X3_M
EMI@ PC701

@EMI@ PC703

PC705

4
IN LX
6 LX_1V 1 2
+1.0VALWP
2

5 19

14K_0402_1%
IN LX

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
7 20

PR705

PC706

PC707

PC708

PC709

PC710

PC714

PC715
GND LX
8 14 FB_1V R1
GND FB

2
LDO_3V_1V

2
@ PR701 18 17
0_0402_5% GND VCC
1 2 EN_1V 11 10 1 @ @
[43] PGOOD EN NC
ILMT_1V
PC711 FB=0.6V

1
@ PC712 13 12 2.2U_0402_6.3V6M
B ILMT NC B
2
1

0.22U_0402_10V6K
PR706
1M_0402_1% +3VALW 15
BYP NC
16
Vout=0.6V* (1+R1/R2) R2 PR707
20K_0402_1%
+3VALW =0.6*(1+(14/20))
2

21 @ PJ702
PAD

2
JUMP_43X118
Vout=1.02V
2

SY8286RAC_QFN20_3X3 1 2
+1.0VALWP 1 2 +1.0VALW
1

PC713
EN :H>0.8V ; L<0.4V
2

1U_0402_6.3V6K
2

PR708
0_0402_5%
EN pin don't floating
If have pull down resistor at HW side,
1

please delete PR601.

1

@ PR709
0_0402_5%
2

The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.0VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Z_SKL 2.0

Date: Monday, April 10, 2017 Sheet 44 of 52

5 4 3 2 1
 1 2 3 4 5

CPU CORE
IccMAX@SA= 5A
RIccMAX@SA= 15.8K --->PRI65
Module model information
RIccMAX@SA= IccMAX*2V/10uA/64A
NCP81208_U22_V1A.mdd for IC portion
IOUTSP@SA= 5A
NCP81208_U22_V1B.mdd for SW portion RIOUTSP@SA=69.8K --->PRI14

RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR
/(RPHSP+Rth+RCSSP))
A PSYS: A
PMON_SKYLAKE [40]
Please confirm charger pull low resistance.
Charger side should be unpop. OCP@SA= 9.5A
RLIMSP@SA=24K --->PRI5
PCI1 PRI1
8200P_0402_25V7K 1.5K_0402_1% RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR
OCP for VCCSA 1 2 1 2 /(RPHSP+Rth+RCSSP))
PRI2, PRI8 place near CPU side.
If the resisters are at HW side and POP. PRI2, PRI8 can be canceled.
COMP_1b_CPU 1
PCI3 2 PCI2 Load line@SA= 10.3m
1000P_0402_50V7K 15P_0402_50V8J
+VCCSA PRI2 1 2
RDRPSP@SA=1.78K --->PRI4
100_0402_1%

24K_0402_1%
RDRPSP= Load line*(RPHSP+Rth+RCSSP)

1000P_0402_50V7K
1 2 @ PRI3 PRI4
CSN_1b_VCCSA [46]

2
0_0402_5%
VSPP_1b_CPU_R
1.78K_0402_1%
VSP_1b_CPU /(gm * DCR) /(Rth+RCSSP)

1
1 2 1 2

PRI5
[12] VCCSA_SENSE
PHI1 Close to SA choke

1200P_0402_50V7K
1
RDRPSP

1
100K_0402_1%_NCP15WF104F03RC

PCI4

0.01U_0402_25V7K
@ PRI6 PCI5 PRI7

1
0_0402_5% 1000P_0402_50V7K 1K_0402_1%

PCI7
VSNN_1b_CPU_R VSN_1b_CPU CSN_1b_VCCSA_NTC

1 2
1

1
1 2 1 2

PCI6
[12] VSSSA_SENSE
1 2 1 2 PRI9

2
PRI8 100_0402_1% PCI8 12K_0402_1%
+VCCGT PRI10 2200P_0402_50V7K CSP_1b_VCCSA +3VS
2 1 CSP_1b_VCCSA_R [46]

2
1 2 @ PRI13 20K_0402_1% PRI14 1 2

1
PRI11 100_0402_1% 0_0402_5% 66.5K_0402_1% 7.5K_0603_1%
1 2 VSP_2ph_CPU 1 2 PRI12 PRI15
[14] VCCGT_SENSE
10K_0402_1%

1
1 2
[14] VSSGT_SENSE @ PRI17 PCI9 PRI18 PCI10 470P_0402_50V7K

2
0_0402_5% 1000P_0402_50V7K 604_0402_1% VR_PWRGD [33]
VSN_2ph_CPU_R VSN_2ph_CPU

2
1 2 1 2 1 2
PRI16 100_0402_1%
1 2 IMVP8_EN confirm with power sequence,
PCI11
Upper Threshold > 0.8V +1.0V_VCCST
it need behind +5VS.
B 3300P_0402_50V7K B
Lower Threshold < 0.3V PRI26 and PRI33 pull high resistor are pop at the end of VR SVID.

1
PRI11, PRI16 place near CPU side. PRI19 Other VR is unpop.

604_0402_1%
1
If the resisters are at HW side and POP. PRI11, PRI16 can be canceled. 49.9_0402_1% @ PRI21
0_0402_5%

PRI20
1 2

110_0402_1%

100_0402_1%
45.3_0402_1%
RIOUT@GT

1 2
VR_ON [33]

IOUT_1b_CPU
ILIM_1b_CPU
2
PCI12 PWM_1b_CPU [46]

EN_CPU

1
470P_0402_50V7K
470P_0402_50V7K

PCI13
2

1
Close to VGT1 choke
CSCOMP_2ph_CPU_R

DRVON [46]

1
PRI23 PRI24 @
25.5K_0402_1% PCI14 110_0402_1% PRI34

2
1

4.75K_0402_1%
PHI2 0.1U_0402_25V6 7.5K_0603_1%

49

48
47
46
45
44
43
42
41
40
39
38
37

2
THERM_ 220K 5% 0402 @ 1 2
CSP_1a_VCORE_R [46]

PRI25

2
1
1 2

VSP_2ph

VSN_1b
VSN_2ph

COMP_1b

CSP_1b
VSP_1b

ILIM_1b
CSN_1b

IOUT_1b

EN
PSYS
TAB

VR_RDY

2
PCI15 PUI1 VR_HOT# [33] PRI29
OCP for VGT

PRI26

PRI27

PRI33
RPH@GT: 15P_0402_50V8J NCP81208-MNTXG_QFN48_6X6 12K_0402_1%
IOUT_2ph_CPU
2

1 2
PRI31 PRI32 1 36 PCI17 1 2
DIFFOUT_2ph_CPU IOUT_2ph PWM_1b CSN_1a_VCORE_NTC

8200P_0402_25V7K
165K_0402_1% 75K_0402_1% 2 35 PRI36 49.9_0402_1% 470P_0402_50V7K
FB_2ph_CPU DIFFOUT_2ph DRVON SCLK_CPU

0.022U_0402_16V7K
[46] CSP1_VGT1 1 2 1 2 1 2 PRI39 PCI16 3 34 1 2 VR_SVID_CLK [14] 1 2
COMP_2ph_CPU FB_2ph SCLK ALERT#_CPU
1

1
PRI30 86.6K_0603_1% 12.4K_0402_1% 2200P_0402_50V7K 4 33 @ PRI37 1 20_0402_5% VR_ALERT# [14] Close to VCORE choke

PCI20
ILIM_2ph_CPU COMP_2ph ALERT# SDIO_CPU
2

PCI18 PCI19 1 2 5 32 PRI40 1 2 10_0402_1% PRI42 PHI3

PCI21
CSCOMP_2ph_CPU ILIM_2ph SDIO VR_HOTL# VR_SVID_DATA [14]

1
1000P_0402_50V7K 82P_0402_50V7K 6 31 PRI41 1 2 100_0402_1% 59K_0402_1% 100K_0402_1%_NCP15WF104F03RC
CSSUM_2ph_CPU CSCOMP_2ph VR_HOT# IOUT_1a_CPU
2

7 30 1 2
1 2 CSREF_2ph_CPU 8 CSSUM_2ph IOUT_1a 29 CSP_1a_VCORE
[46] CSN1_VGT1 CSP2_2ph_CPU CSREF_2ph CSP_1a

2
PRI44 10_0402_1% 9 28
CSP1_2ph_CPU CSP2_2ph CSN_1a ILIM_1a_CPU CSN_1a_VCORE [46]
1

10 27

ROSC_COREGT
CSP1_2ph ILIM_1a
0.1U_0402_25V6

TSENSE_2ph_CPU_R 1 2 TSENSE_2ph_CPU 11 26 COMP_1a_CPU

ADDR_VBOOT
PCI22

TSENSE_2ph COMP_1a
1

1
TSENSE_1ph
1 2 12 25

RSOC_SAUS
@ PRI45 0_0402_5%

ICCMAX_2ph
PCI24

ICCMAX_1a
ICCMAX_1b
VRMP VSN_1a
2

PWM1_2ph
PWM2_2ph

1
PCI26 PRI46 3300P_0402_50V7-K PCI27

VRMP_CPU
+19VB_CPU 1K_0402_1%
100K_0402_1%_NCP15WF104F03RC

VSN_1a_CPU_R

PWM_1a
1

0.1U_0402_25V6 1 2 PCI25 PCI29 1000P_0402_50V7K

VSP_1a
2

2
PHI4 PRI48 15P_0402_50V8J 1500P_0402_50V7K

VCC

1 2
1

61.9K_0402_1% PCI28 PRI49 @ PRI50 PRI51

1
1000P_0402_50V7K 604_0402_1% 0_0402_5% 100_0402_1%
CSP1_VGT1 VSN_1a_CPU

1
1 2 PCI30 1 2 1 2 1 2 PRI52 PRI53
2

13
14
1ROSC_SAUS_CPU 15
16
17
18
19
20
21
22
23
24
PRI47 2K_0402_1% 0.01U_0402_50V7K 2.49K_0402_1% 33.2K_0402_1%

1
PCI31 VSSCORE_SENSE [14]
C C

2
1 2 1000P_0402_50V7K
+5VS

ICCMAX_2ph_CPU

2
ADDR_VBOOT_CPU
VCC_CPU

ICCMAX_1a_CPU
ICCMAX_1b_CPU
PRI54 Close to VGT1 MOS
+5VS

2
1K_0402_1%
PRI55 RDRPSP PRI56 @ PRI57 OCP for VCORE
2_0402_1% 2.1K_0402_1% 0_0402_5%
1 2 1 2VSP_1a_CPU_R 1 2 VCCCORE_SENSE
+VCCCORE
[14]
VSP_1a_CPU 1 1 2 2 1 2

1ROSC_COREGT_CPU

24K_0402_1%
2.1K_0402_1% PRI58 100_0402_1%
472mV/120uA=3.933K
1

PCI32 PRI115

PRI60
U22 OCP@GT= 40A Active Point110 degreeC = 4.206K PCI33 1000P_0402_50V7K @ PRI61
RLIM@GT=12.4K --->PRI39 1U_0603_10V6K 0_0402_5% PRI51, PRI58 place near CPU side.
TSENSE_1ph_CPU TSENSE_1ph_CPU_R
2

1 2 If the resisters are at HW side and POP. PRI51, PRI58 can be canceled.
RLIM= IoutLIMIT * Load line/10 2

1000P_0402_50V7K
33.2K_0402_1%

61.9K_0402_1%
1

1
Fsw for SA
U22 Load line@VCORE= 2.35m

2
PWM_1a_CPU [46] PHI5
PRI59

PCI34
100K_0402_1%_NCP15WF104F03RC
RDRPSP@VCORE=2.1K --->PRI56
U22 IccMAX@GT= 31A

PRI62
10K_0402_1%
48.7K_0402_1%

90.9K_0402_1%

15.8K_0402_1%
RIccMAX2ph= 48.7K --->PRI63 Fsw for CORE & GT
RDRPSP= Load line*(RPHSP+Rth+RCSSP)
2

2
Close to VCORE MOS
/(gm * DCR) /(Rth+RCSSP)
RIccMAX2ph= (IccMAX2Ph+32)*200K Ohn/ 127 NCP81208 Operating Frequency Rosc=33.2K
I/A and GT are 450KHz
IccMAX@VCORE= 28A
1

NCP81208 Operating Frequency Rosc=24K 1 472mV/120uA=3.933K

and SA is 600KHz RIccMAX@VCORE= 87.6K --->PRI64
SKL@ Active Point110 degreeC = 4.206K
U22 Iout@GT= 31A
RIOUT@GT=25.5K --->PRI23 RIccMAX2ph RIccMAX@VCORE= IccMAX*2V/10uA/64A
PRI63

PRI64

PRI65

PRI66
2

RIOUT= 2* RLIM /(10 *IOUTICCMAX * Load line) IOUTSP@VCORE= 28A

RIOUTSP@VCORE=64.9K --->PRI42
VBOOT:
KBL_ICCMAX@ 22.1K for debuge setting. RIOUTSP= 2V/(gm*(Rth+RCSSP)*ICCMAX*DCR
U22 Load line@GT= 3.1m PRI64 /(RPHSP+Rth+RCSSP))
100K_0402_1%
D
RPH@GT=84.5K --->PRI30,PRI38 D

OCP@VCORE= 35A
Load line= (RCS2+(RCS1*Rth/(RCS1+Rth))) PWM1_2ph_CPU [46]
RLIMSP@VCORE=33.4K --->PRI53
*IOUTTOTAL * DCR/RPH
RLIMSP= 1.3V/(gm*(Rth+RCSSP)*IoutLIMIT*DCR
/(RPHSP+Rth+RCSSP))

Title
NCP81208
Size Document Number Rev
2.0

Date: Monday, April 10, 2017 Sheet 45 of 52

1 2 3 4 5
 1 2 3 4 5

CPU POWER STAGES EMI@ PLI1

5A_Z120_25M_0805_2P
1 2
InputCapacitor:
EMI@ PLI2
+19VB_CPU 10uF_0805_X5R_25V 5A_Z120_25M_0805_2P B+
1 2

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
22P_0402_50V8J

0.1U_0402_25V6
@EMI@ PCI40

PCI41
1 1

33U_25V_NC_6.3X4.5

33U_25V_NC_6.3X4.5
+ +

1
EMI@ PCI38

EMI@ PCI39

PCI94

PCI95

PC1473

PC1474
PCI98

EMI@
2 2

2
5
PRI68 PCI42
2.2_0603_5% 0.22U_0603_16V7K
1 2BST_VCORE_R 1 2
A A
PRI114

BST_VCORE
0_0603_5%
UG_VCORE 1 2UG_VCORE_R 4

PQI6
PUI2
AON6428L_DFN8-5
VCC_CORE
NCP81253MNTBG_DFN8_2X2 FSW=450kHz

3
2
1
1 8
PLI3
0.24UH_22A_+-20%_7X7X3_M +VCCCORE DCR = 1.19 mohm +/- 5%
BST DRVH
LX_VCORE TYP MAX
H/S Rds(on) :11.3mohm , 14.5mohm
[45] PWM_1a_CPU 2 7 1 4
PW M SW

220U_D2 SX_2VY_R9M
+5VS
DRVON 3
EN GND
6 2 3 1
PCI91
L/S Rds(on) :2.8mohm , 3.5mohm
4 5 +

5
PQI7
VCC DRVL
PAD

1
@EMI@

AON6794_DFN5X6-8-5
CSN_1a_VCORE [45] 2
1

PRI71
9
2.2U_0603_16V6K

4.7_1206_5%
PCI70

LG_VCORE 4
2

2
SNB_VCORE CSP_1a_VCORE_R [45]

3
2
1

1
@EMI@
PCI45
680P_0603_50V7K

2
B B

+19VB_CPU

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
@EMI@ PCI46

PCI47
1
PRI73

100U_25V_NC_6.3X6
+

1
2.2_0603_5%

EMI@ PCI50

EMI@ PCI51

PCI96

PCI97
BST1_VGT1 1 2 BST1_VGT1_R

PC148
EMI@
2

2
5

PQI2
1

PCI57
VCCGT
UG_VGT1_R

4
FSW=450kHz
0.22U_0603_16V7K
2

PUI3

1
NCP81151MNTBG_DFN8_2X2
9 PRI112 AON6428L_DFN8-5 DCR = 1.19 mohm +/- 5%
TYP MAX
[45] PWM1_2ph_CPU BST FLAG 0_0603_5% PLI4
UG_VGT1 1
3
2
1

H/S Rds(on) :11.3mohm , 14.5mohm

2 8 2 0.24UH_22A_+-20%_7X7X3_M
PW M DRVH +VCCGT
L/S Rds(on) :2.8mohm , 3.5mohm
3 7 LX_VGT1 1 4
[45] DRVON EN SW
4 6 2 3
PRI77 @EMI@

VCC GND
5

5 LG_VGT1
1

+5VS PQI3
4.7_1206_5%

DRVL

220U_D2 SX_2VY_R9M
AON6794_DFN5X6-8-5
1

1 1
PCI58 @ PCI93

330U_D1_2VY_R9M
2.2U_0603_16V6K 4 + PCI92 +
CSN1_VGT1 [45]
2

SNUB_VGT1 2

C C
2 2
PCI64 @EMI@

CSP1_VGT1 [45]
3
2
1

680P_0603_50V7K
1
2

+19VB_CPU
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
@EMI@ PCI67

PCI68
1

1
PCI65

PCI66

PRI83 PCI69
EMI@
2

2.2_0603_5% 0.22U_0603_16V7K
VCCSA
1 2 BST_VCCSA_R 1 2

FSW=450kHz
BST_VCCSA

UG_VCCSA
DCR 6.2mohm(TYP), 6.51mohm(Max)
TYP MAX
PUI5 PQI1 H/S Rds(on) :12.4mohm , 15.8mohm
NCP81253MNTBG_DFN8_2X2
L/S Rds(on) :9.1mohm , 11.6mohm
4

AON7934_DFN3X3A8-10

+VCCSA
D1

D1

D1

G1

1 8
BST DRVH PLI6
2 7 10 9 LX_VCCSA 1 4
[45] PWM_1b_CPU PW M SW D1 D2/S1
D D
DRVON 3 6 2 3
PRI84

+5VS EN GND
4.7_1206_5%
G2
S2

S2

S2

4 5
1

VCC DRVL 0.47UH_MMD05CZR47M_12A_20%

PAD

@EMI@
1

PCI43
CSN_1b_VCCSA [45]
2

2.2U_0603_16V6K
SNB_VCCSA
2

680P_0603_50V7K
PCI71
1

LX_VCCSA CSP_1b_VCCSA_R [45] Title

Power Stage
2

LG_VCCSA Size Document Number Rev

@EMI@

2.0

Dat e: Monday, April 10, 2017 Sheet 46 of 52

1 2 3 4 5
 A

D
+VCCGT

+VCCCORE
2

1
PC1220
22U_0603_6.3V6M

1
PC1221
22U_0603_6.3V6M

1
PC1222

22U_0603 * 28 pcs +1U_0201*35 pcs

VCC_CORE Place on CPU Back Side @ V09
22U_0603_6.3V6M

1
PC1223
5

5
22U_0603_6.3V6M

2 1 2 1 2 1

1
PC1224

1
22U_0603_6.3V6M PC1189 PC1174 PC1137 PC1101
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

1
PC1225

1
22U_0603_6.3V6M PC1190 PC1175 PC1138 PC1102
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

1
PC1226

1
22U_0603_6.3V6M PC1191 PC1176 PC1139 PC1103
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1

1
PC1227

2@

1
22U_0603_6.3V6M PC1192 PC1177 PC1140 PC1104
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 2 1 2 1 2 1

1
PC1228

2@

1
22U_0603_6.3V6M PC1193 PC1178 PC1141 PC1105
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2

PC1229

2@

1
22U_0603_6.3V6M PC1194 PC1179 PC1142 PC1106
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2

PC1230

2@

1
22U_0603_6.3V6M PC1195 PC1180 PC1143 PC1107
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2

2@

1
PC1231 PC1108
22U_0603_6.3V6M PC1196 PC1181 PC1144 22U_0603_6.3V6M
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1
2

PC1232

1
22U_0603_6.3V6M PC1197 PC1182 PC1145 PC1109

+VCCSA
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2

PC1233
4

4
2

1
22U_0603_6.3V6M 2 1 PC1183 PC1146 PC1110
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1198 2 1 2 1

@EMI@
2

PC1234 PC1201 0.1U_0402_25V6

22U_0603_6.3V6M 22U_0603_6.3V6M PC1184 PC1147
2 1 1U_0201_6.3V6M 1U_0201_6.3V6M

1
2 1 2 1 PC1111
2

PC1235 PC1199 22U_0603_6.3V6M

@EMI@
22U_0603_6.3V6M 0.1U_0402_25V6 PC1185 PC1148
1U_0201_6.3V6M 1U_0201_6.3V6M

1
2 1 2 1 2 1 PC1112
2

PC1203 22U_0603_6.3V6M
22U_0603_6.3V6M PC1200 PC1186 PC1149
@EMI@
0.1U_0402_25V6 1U_0201_6.3V6M 1U_0201_6.3V6M

1
PC1113
2

PC1204 22U_0603_6.3V6M
22U_0603_6.3V6M

1
PC1114
2@

PC1205 22U_0603_6.3V6M
22U_0603_6.3V6M

1
PC1115

@
2

1
PC1150 22U_0603_6.3V6M
22U_0603_6.3V6M

1
PC1116
2@

2@

1
PC1207 PC1151 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M

1
PC1117
2

1
PC1208 PC1152 22U_0603_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603 * 9 (4 CPU back+8 outside)pcs + 1U_0201*7
VCC_SA Place on CPU Back Side @ V09

1
PC1118

1
PC1153 22U_0603_6.3V6M
22U_0603_6.3V6M
2

2@

1
PC1209 PC1119

1
22U_0603_6.3V6M PC1154 22U_0603_6.3V6M
3

3
22U_0603_6.3V6M
2

1
PC1210 PC1120

1
22U_0603_6.3V6M PC1155 22U_0603_6.3V6M
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

22U_0603_6.3V6M
2@

1
Issued Date

PC1211

2@

1
22U_0603_6.3V6M PC1156
22U_0603_6.3V6M
2@

PC1212
2

1
22U_0603_6.3V6M PC1157
2 1 22U_0603_6.3V6M

PC1213
2

2@

1
1U_0201_6.3V6M PC1158 PC1121
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1214
2

1
1U_0201_6.3V6M PC1159 PC1122
2 1 22U_0603_6.3V6M 22U_0603_6.3V6M
2015/07/27

PC1215

1
1U_0201_6.3V6M PC1123
2 1 22U_0603_6.3V6M

+VCCGT
PC1216
1U_0201_6.3V6M
2 1

PC1217
Compal Secret Data

1U_0201_6.3V6M
2 1

PC1218
Deciphered Date

1U_0201_6.3V6M
2 1

PC1219
1U_0201_6.3V6M
2

2
2 1 2 1
2

PC1187 PC1160 PC1124

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
22U_0603 * 29 pcs +1U_0201*12 pcs
VCC_GT Place on CPU Back Side @ V09
2

PC1188 PC1161 PC1125

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2016/07/27

2 1
2

PC1162 PC1126
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2

PC1163 PC1127
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2

PC1164 PC1128
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2

PC1165 PC1129
C
Date:

Size

Title

1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2

1
Document Number

PC1166 PC1130
PWR-PROCESSOR_DECOUPLING
Compal Electronics, Inc.

1U_0201_6.3V6M 22U_0603_6.3V6M
Monday, April 10, 2017

2 1
2

PC1167 PC1131
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2

PC1168 PC1132
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1
2

PC1169 PC1133
1

1U_0201_6.3V6M 22U_0603_6.3V6M
2

PC1170 PC1134
Sheet

22U_0603_6.3V6M 22U_0603_6.3V6M
2

PC1171 PC1135
22U_0603_6.3V6M 22U_0603_6.3V6M
47

PC1172 PC1136
of

22U_0603_6.3V6M 22U_0603_6.3V6M
52

PC1173
22U_0603_6.3V6M
Rev
2.0

D
 5 4 3 2 1

Module model information

10K_0402_1%

10K_0402_1%
PR1402 41.2K_0402_1%
ISL62771_CZ_GFX35W_V1A.mdd for IC portion

2
ISL62771_CZ_GFX35W_V1B.mdd for SW portion

2
1

PR1403

PR1404
1

1
+5VS
+19VB_GFX VEMI@PL1401
5A_Z120_25M_0805_2P
D 1 2 B+ D

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K
41

40

39

38

37

36

35

34

33

32

31

1
1

1
PU1401 @VRF@

VEMI@ PC1405
PC1402

PC1403

@VEMI@ PC1404
PC1475

TP

ISUMP_NB

UGATE_NB
ISUMN_NB

VSEN_NB

PHASE_NB

BOOT_NB
FB_NB

COMP_NB

PGOOD_NB

LGATE_NB
UG1_GFX
22P_0402_50V8J

2
2

2
PR1401 1100K_0402_1%
2 1 30 BST2_GFX
NTC_NB BOOT2
VR_ON PR1405 1100K_0402_1%
2 2 29 UG2_GFX PR1406 PC1406
SH000011H00 (DCR:0.98mohm +/-5%)
High > 1.6V IMON_NB UGATE2

1
2.2_0603_1% 0.22U_0603_25V7K PQ1401
3 28 LX2_GFX BST1_GFX
1 2BST1_GFX_R 1 2
Low < 1V

D1

G1
[21] GPU_SVC SVC PHASE2 PL1402
4 27 LG2_GFX +5VS 0.22UH_24A_20%_ 7X7X4_M
[21] GPU_PROCHOT# VR_HOT_L LGATE2 LX1_GFX LX1_GFX
@VGA@ PR1407 7 1 4
M170@ PR1408
0_0402_5%
+3VS
1 2
100K_0402_1%
[21] GPU_SVD
5
SVD ISL62771HRTZ-T_TQFN40_5X5 VDDP
26 D2/S1
2 3
+VGA_CORE
1 2 VDDIO_GFX 6 25 1 PR1409 2 @VEMI@

G2
+1.8VGS

S2

S2

S2
VDDIO VDD

1
PR1411

1U_0603_10V6K
LG1_GFX ISUMP_GFX1 PR1412 2
1

7 24 1_0603_5% AON6992_DFN5X6D-8-7 4.7_1206_5%

[21] GPU_SVT SVT LGATE1

6
1

1
1 2 @VGA@ PR1413 3.65K_0603_1%

1U_0603_10V6K
+3VGS
PC1401 1 2ENABLE_GFX 8 23 LX1_GFX

PC1408
[10,22,33,48] DGPU_PW R_EN ENABLE PHASE1
2

M130@ PR1410

PC1407
UG1_GFX PR1414

2
0_0402_5% 0_0402_5% 9 22
[10] DGPU_PW ROK PWROK UGATE1 SNB_GFX ISEN1_GFX 1
0.1U_0402_25V6K 2

LG1_GFX
1 2 IMON 10 21 BST1_GFX 10K_0402_1%
IMON BOOT1 +3VS

1
PR1415
@VEMI@

PGOOD
133K_0402_1%

ISUMN
ISUMP

COMP
ISEN2

ISEN1
PC1409 PR1416

VSEN
ISUMN_GFX_R 1

NTC

RTN
2 PC1410

2
1 680P_0603_50V7K 2

FB

1
1000P_0402_50V7K 1_0402_1%
PR1418 PR1419

11

12

13

14

15

16

17

18

19

20
27.4K_0402_1% 20K_0402_1% @VGA@ PR1417
1 2 NTC_GFX_R 1 2 NTC_GFX 100K_0402_1%
+VGA_CORE
GFX_core

2
M170@
DGPU_PW ROK

ISUMN_GFX
PH1002 near APU_CORE H/S mos PH1402 PC1411

COMP_GFX
TDC 28(1H1L)

ISEN1_GFX

VSEN_GFX

FB_GFX
RTN_GFX
1 2 0.22U_0402_6.3V6K
VRHOT Assert Threshold : 0.64V 1 2
ISEN2_GFX Peak Current 42A
TSENSE Bias Current : 30uA 470K_0402_5%_TSM0B474J4702RE
C
PH1002=27.4K, 110C active +5VS
M130@ 1 1 1 OCP current > 42A C

Load line -2.1mV/A

PR1428
Reset Threshold: 0.66V, 98C active 0_0402_5% + PC1412 + PC1413 + PC1414
110C Assert Threshold: PR1031=27.4K ISUMN_GFX_R
1
M130@
2 330U_2V_M 330U_2V_M 330U_2V_M
FSW=400kHz
100C Assert Threshold: PR1031=16.9K 2 PR1450 1 2 2 2 DCR 0.98mohm +/-5%
10K_0402_1%
M170@
VGA@
PC1417 TYP MAX
1 2 PC1415 PC1416 PR1420 270P_0402_50V7K M170@ PR1421 H/S Rds(on) :6.8mohm , 8.6mohm
L/S Rds(on) :2mohm , 2.5mohm
0.22U_0402_6.3V6K 1000P_0402_50V7K 301_0402_1% 73.2K_0402_1%
ISUMP_GFX 1 2 1 2 1 2 1 2
1 2ISUMP_GFX_NTC

330P_0402_50V7K
@VGA@ PC1418
2.61K_0402_1%

0.1U_0402_25V6K
1

M170@PC1421 PR1425 PC1419

M130@ PC1421

PR1424
10K_0402_5%_ERTJ0ER103J

0.15U_0402_10V6K M130@ 137K_0402_1% 390P_0402_50V7K

PR1422

11K_0402_1%

.022U_0402_25V4

+19VB_GFX
1

1 2 1 2 1 2
2
1

1
PR1423

PC1420

1.37K_0402_1%
PR1426 PC1422

10U_0805_25V6K

10U_0805_25V6K
2

M170@PR1424 2K_0402_1% 330P_0402_50V7K

2

1 2 1 2
PH1003 near GFX_CORE choke 1K_0402_1%
PH1401

PR1058=3.65K, PR1040=2.1K and

1
M130@

PC1423

PC1424
PR1427
PR1046=604 to set loadline -2.1mV/A
2

562_0402_1%
ISUMN_GFX_R UG2_GFX

2
1 2 M170@
M170@
@VGA@ @VGA@ @VGA@ PR1429
1

PR1431 PC1426 0_0402_5% M170@ M170@

1 2
PC1425 100_0402_1% 820P_0402_25V7K
GPU_VDD_SEN [21]
PR1430 PC1427 M170@
SH000011H00 (DCR:0.98mohm +/-5%)

1
0.1U_0402_25V6 1 2 1 2 2.2_0603_1% 0.22U_0603_25V7K PQ1402
BST2_GFX 1 2BST2_GFX_R 1
2

D1

G1
M170@ PL1403
PR1046 set 750 ohm to OCP 43.75A 1 2 0.22UH_24A_20%_ 7X7X4_M
GPU_VDD_RUN_FB_L [21] LX2_GFX 7 LX2_GFX 1 4
0.01U_0402_50V7K

@VGA@ 0_0402_5% D2/S1

+VGA_CORE
1

2 3
PC1428

M170@PR1427 PR1432
464_1%_0402 @M170_EMI@

G2
S2

S2

S2

1
PR1434 M170@
ISUMP_GFX1 PR1435 2
2

AON6992_DFN5X6D-8-7 4.7_1206_5%

6
3.65K_0603_1%

B B

2
M170@ PR1436
SNB_GFX2 ISEN2_GFX 1 2

LG2_GFX
10K_0402_1%

1
@M170_EMI@
PC1429 M170@ PR1437
ISUMN_GFX_R 1

2
680P_0603_50V7K 2
1_0402_1%
EN pin don't floating PR1058=3.65K, PR1040=2.1K and
If have pull down resistor at HW side, pls delete PR702PR1046=604 to set loadline -2.1mV/A
while PR1046=594 to set OCP 57.16A Confirm HW side
for EDC 45A application.
+19VB_1.35V +VGA_CORE
keep short pad, @VEMI@ PR1449 @VEMI@ PC1477
snubber is for EMI only. 4.7_1206_5% 680P_0603_50V7K
1 2 SNUB_1.35V 1 2
PU1402
@ PJ1402

B+ (Common Part SH00000Z200)

1 2 +19VB_1.35V 2 9 @VRAM@ PR1446 PC1476

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
1 2 IN PG 0_0402_5% 0.1U_0201_10V6K
10U_0805_25V6K
0.1U_0402_25V6

BST_1.35V 2 BST_1.35V_R 1

1
3 1 1 2

PC1435

PC1436

PC1437

PC1438

PC1439

PC1440

PC1441

PC1442

PC1443

PC1444

PC1445

PC1446

PC1447

PC1448

PC1449

PC1450
2200P_0402_50V7K

JUMP_43X79 IN BS PL602
1

1
VEMI@ PC1479

@VEMI@ PC1480

PC606

+1.35VGSP
4 6 LX_1.35V 1 2
IN LX

2
2

5 19 1UH_6.6A_20%_5X5X3_M
14K_0402_1%

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
IN LX
1

1
7 20
PR608

PC608

PC609

PC610

PC611

PC612
GND LX
8 14 FB_1.35V R1
GND FB
2

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
LDO_3V_1.35
2

PR1447 18 17

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
100K_0402_1% GND VCC
EN_1.35V
1

1
1 2 11 10

PC1457

PC1458

PC1459

PC1460

PC1461

PC1462

PC1463

PC1464

PC1465

PC1466

PC1467

PC1468

PC1469

PC1470
[10,22,33,48] DGPU_PWR_EN EN NC
ILMT_1.35V 13
PC613 FB=0.6V
1

12 2.2U_0402_6.3V6M
ILMT NC
2

2
1

PC1478
PR1448
1M_0402_1%
0.22U_0402_25V6 +3VALW
15
BYP NC
16
Vout=0.6V* (1+R1/R2) R2 PR610
11K_0402_1%
=0.6*(1+(14/11))
2

21
+3VALW PAD
2

EN :H>0.8V ; L<0.4V Vout=1.36V

2

SY8286RAC_QFN20_3X3
A A
1

PC614
EN pin don't floating
2

1U_0402_6.3V6K
If have pull down resistor at HW side,
2

PR607
please delete PR601. 0_0402_5%
@VRAM@
1
1

@ PJ1401
PR609 JUMP_43X118
0_0402_5% 1 2
+1.35VGSP 1 2 +1.35VGS
@VRAM@
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2013/01/04 Deciphered Date 2015/01/04 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE/CPU_CORE_NB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
The current limit is set to 6A, 9A or 12A when this pin DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
ISL62771 Module 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
is pull low, floating or pull high. Date: Monday, April 10, 2017 Sheet 48 of 52
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1 for

PWR
Item Reason for change PG# Modify List Date Phase

P R 1 4 0 8 改M 1 7 0 @
1 導R 1 7 - M 1 - 7 0 P49 PR1410從 r-short 改M150 @ 2016/11/3
PR1428 ，PR1450 改 M150 @
D
增 P C 1 4 11 ， P C 1 415，都 改 為 M 1
新 70 @
D

PC1417 from 150P change to 270P

PR1424 M130 pop 1.37K， M170 pop 1K
PR1421 A phase 定
決
後是否 p op
3

C C
9

10

11

12

13

14

B B

15

16

17
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
Z_BDW 2.0

Date: Monday, April 10, 2017 Sheet 49 of 52

5 4 3 2 1