8086 Hardware Specifications

Dept. of Computer Science and Engineering

BRAC University
CSE 341 Team
Lecture References:
Book:

Microprocessors and Interfacing: Programming and Hardware,

Author: Douglas V. Hall

The 8086/8088 Family: Design, Programming, And Interfacing,

Author: John Uffenbeck.

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification
is a 40-pin DIPs; Dual in-line package
DIP refers to a rectangular housing with two parallel rows of electrical
connection pins.
DIPs have a notch on one end to show its correct orientation.
The pins are then numbered as shown in the figure below.

CSE – 341: Microprocessors

BRAC University
8086 Pin Diagram
 

min mode

max mode

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

S4 S3 Function
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Pin Specification
 

min mode

max mode

CSE – 341: Microprocessors

BRAC University
Minimum Mode Pin Specification

CSE – 341: Microprocessors

BRAC University
Minimum Mode Pin Specification

CSE – 341: Microprocessors

BRAC University
Minimum Mode Pin Specification

CSE – 341: Microprocessors

BRAC University
Minimum Mode Pin Specification

CSE – 341: Microprocessors

BRAC University
Minimum Mode Pin Specification

CSE – 341: Microprocessors

BRAC University
8086 Maximum Mode Pins
Dept. of Computer Science and Engineering
BRAC University
CSE 341 Team
Maximum Mode Pin Specification
 

Function
0 0 No Operation. During the last clock cycle,
nothing was
taken from the queue.
0 1 First Byte. The byte taken from the queue was
the first byte of the instruction.
1 0 Queue Empty. The queue has been
reinitialized as a result
of the execution of a transfer instruction.
1 1 Fetch subsequent byteSubsequent Byte. The
byte taken from the queue was a subsequent
byte of the instruction.
CSE – 341: Microprocessors
BRAC University
Maximum Mode Pin Specification
 

Function
0 0 0 Interrupt acknowledgement
0 0 1 Read data from I/O port
0 1 0 Write data from I/O port
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive state
CSE – 341: Microprocessors
BRAC University
Maximum Mode Pin Specification

CSE – 341: Microprocessors

BRAC University
Maximum Mode Pin Specification

CSE – 341: Microprocessors

BRAC University
QUIZ
 

CSE – 341: Microprocessors

BRAC University
8086 Clocks & Timing Diagrams
Dept. of Computer Science and Engineering
BRAC University
CSE 341 Team
Microprocessor Operation

Fetch Decode

Execute

An instruction e.g. MOV [7531h], AX ; SUB CH, [0ABCh] etc

The time a µP requires to complete fetch-(decode)-execute

operation of a single instruction is known as Instruction
Cycle CSE – 341: Microprocessors
BRAC University
Microprocessor Operation
Instruction Cycle consists of one or more Machine
Cycles
A basic µP operation such as reading/writing a byte from or
to memory or I/O port is called a Machine/Bus cycle

CSE – 341: Microprocessors

BRAC University
Microprocessor Operation
A Machine (bus) cycle consists of at least four clock
cycles, called T states.

One cycle of a clock is called a State

Each read or write operation takes 1 bus cycle.

CSE – 341: Microprocessors

BRAC University
Clock Generation
Clock generator circuit is 8284A and connected to pin
19 (CLK) of 8086.

CSE – 341: Microprocessors

BRAC University
 System Clock Concept
• 8086 is found to operate in between 5 to 10 Mhz.
   
• An 8086 running at 5MHz, its clock pulses will be
of 200ns and it would take 800ns for a complete
bus cycle.

For a 10MHz 8086, its clock pulses will be of

100ns and it would take 400ns for a complete
bus cycle.
CSE – 341: Microprocessors
BRAC University
 Clock States - Why are there T states?
 

CSE – 341: Microprocessors

BRAC University
READ BUS Timing (Complete BUS Cycle)
T1: Address is output

Address of memory is sent out by 8086 via address bus

Used Control signals: ALE, DT/R’, M/IO’ shows some output
CSE – 341: Microprocessors
BRAC University
READ BUS Timing (Complete BUS Cycle)
T2: Bus cycle type (MEMORY/IO, READ/WRITE)

8086 issues either RD’ or WR’ and DEN’

In case of WRITE (WR) operation, data to be written appear on data bus
CSE – 341: Microprocessors
BRAC University
READ BUS Timing (Complete BUS Cycle)
T3: Data is supplied

READY is sampled at the end of T2

If READY is low, T3 becomes a wait state (Tw), means no operation (NOP).
In READ bus cycle data bus is sampled at end of T3
CSE – 341: Microprocessors
BRAC University
READ BUS Timing (Complete BUS Cycle)
T4: Data latched by µP, control signals removed

All bus signals deactivated in preparation for next bus cycle

µP sampled data bus for data that read from M or I/O
CSE – 341: Microprocessors
BRAC University
Clock States
A specific, defined action occurs during each T states (T1 – T4)

T1: Address is output

Address of memory is sent out by 8086 via address bus

Used Control signals: ALE, DT/R’, M/IO’ shows some output

T2: Bus cycle type (MEMORY/IO, READ/WRITE)

8086 issues either RD’ or WR’ and DEN’

In case of WRITE (WR) operation, data to be written appear on

data bus

CSE – 341: Microprocessors

BRAC University
Clock States
T3: Data is supplied

READY is sampled at the end of T2

If READY is low, T3 becomes a wait state (Tw), means no operation
(NOP).

In READ bus cycle data bus is sampled at end of T3

T4: Data latched by µP, control signals removed

All bus signals deactivated in preparation for next bus cycle

µP sampled data bus for data that read from M or I/O

At trailing edge of WR’, transfer data to M or I/O

CSE – 341: Microprocessors

BRAC University
8086 Ready pin
The READY input is controlled to insert “Wait states” into the timing of
the microprocessor for slower memory and I/O components..

If the READY pin is at a logic 0 level, the micro-processor enters into

wait states and remains idle.

When it is high (logic 1), it indicates that the device is ready to transfer
data.

A wait state is a situation in which a computer processor is waiting for

the completion of some event before resuming activity.

A program or process in a wait state is inactive for the duration of the

wait state.
CSE – 341: Microprocessors
BRAC University
Ready pin and Wait state
When a computer processor works at a faster clock speed  than the
random access memory ( RAM ) that sends it instructions, it is set to
go into a wait state for one or more clock cycles so that it is
synchronized with RAM speed. In general, the more time a processor
spends in wait states, the slower the performance of that processor.

Wait states are a pure waste for a processor's performance. Modern

designs try to eliminate or hide them using a variety of techniques: CPU
caches, instruction pipelines, instruction prefetch, simultaneous
multithreading and others.

CSE – 341: Microprocessors

BRAC University
 Thank
You
Questions are welcome in the
discussion class

CSE – 341: Microprocessors

BRAC University