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Comprehensive Analysis of Voltage Step-Up Techniques For Isolated SEPIC

High step-up converters are often used in photovoltaic applications due to low voltage of photovoltaic modules. In this paper, a study of several voltage step-up cells added on primary and secondary sides of an isolated dc-dc SEPIC (single ended primary inductor converter) is made, in order to increase its static gain and synthesize a family of converters. To perform this study and select the most appropriate resulting converter, theoretical and comparative analyzes are accomplished. They includ

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Comprehensive Analysis of Voltage Step-Up Techniques For Isolated SEPIC

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Bernardo Andres

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AQ7 - According to the page of CALTECH, the citation for this thesis is
Maksimović, Dragan (1989) Synthesis of PWM and Quasi-Resonant DC-to-DC Power Converters. Dissertation (Ph.D.),
California Institute of Technology.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1

Comprehensive Analysis of Voltage Step-Up

Techniques for Isolated SEPIC
AQ:1 Bernardo Andres , Leonardo Romitti, Member, IEEE,
António Manuel Santos Spencer Andrade , Member, IEEE, Leandro Roggia ,
and Luciano Schuch, Member, IEEE

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1 Abstract— High step-up converters are often used in photo-
2 voltaic applications due to low voltage of photovoltaic modules.
3 In this paper, a study of several voltage step-up cells added on
4 primary and secondary sides of an isolated dc-dc SEPIC (single
5 ended primary inductor converter) is made, in order to increase
6 its static gain and synthesize a family of converters. To perform
7 this study and select the most appropriate resulting converter, Fig. 1. MIC converter with emphasis on first stage.
8 theoretical and comparative analyzes are accomplished. They
9 include a brief description of each converter, tables and curves the focus is an ac photovoltaic module (module-integrated- 33
10 with relevant information, such as voltage gain, voltage stresses
11
12
13
14
15
16
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and component count, and the identification of the use of coupled
inductor or transformer based on the analysis of dc magnetizing
current. Moreover, theoretical analysis and experimental results
on a 50 kHz and 200 W prototype of selected isolated SEPIC
with voltage doubler cell are presented to validate the proposed
topology and concept.
Index Terms— Isolated SEPIC, magnetizing current, voltage
converter – MIC), where a high step-up converter, in first stage,
provides a high voltage gain, as shown in Fig. 1.
In this particular situation, galvanic isolation is desirable
in order to maintain security of the whole system, besides
mitigating leakage current and electromagnetic interference
(EMI) [6]. Isolated converters employing those aforemen-
34

39
17 tioned techniques are often found, integrating cascaded boost 40
18 step-up cells. with an isolated buck-boost [7] or adding a voltage multiplier 41

on secondary side [8]. However, single switch converters are 42

19 I. I NTRODUCTION more suitable for low power application, reducing volume, 43

E
costs and complexity. A several number of isolated single
H IGH step-up converters are widely used in renew-
20 44

21 able systems, where the output voltage of generating switch converters found in literature has the problem of high 45

22 sources, like photovoltaic module or fuel cell, is low, typically leakage inductance, requiring the use of a snubber circuit 46

23 20-40 V [1]. This low voltage level has to be boosted to a high associated to another technique to increase the static gain, 47

24 dc-bus voltage in order to allow grid connection [2], therefore, with unattractive results, without reaching a high efficiency, 48
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25 a great number of isolated and non-isolated topologies have besides the increase of complexity, volume and cost of the 49

26 been proposed for this application. whole system [9]–[12]. 50

27 Several classic step-up converters can be used, such as dc-dc The leakage inductance on isolated converters causes several 51

28 boost converter, due to simple structure and input current spikes over semiconductors, may harm these semiconduc- 52

29 feature [3], however, many of them present reduced voltage tors and reduces converter’s efficiency. These high values of 53
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30 step-up ratio [4]. To solve this problem, those converters leakage inductance occur on isolated converters with coupled 54

31 employ cascade, voltage multiplier, and/or coupled inductors inductor for magnetic isolation, like flyback, where leakage 55

32 techniques in order to elevate static gain [5]. In this work, flux is necessary to store energy, resulting in a dc compo- 56

nent on magnetizing current [13], however, this problem is 57

AQ:2 Manuscript received 25 February 2022; revised 4 June 2022; accepted mitigated using a transformer, where no dc component on 58
4 July 2022. This work was supported in part by the Coordenação de Aper-
AQ:3 feiçoamento de Pessoal de Nível Superior–Brazil (CAPES/PROEX) under magnetizing current is present. Other isolated single switch 59

Grant 001, in part by the INCTGD, in part by the CNPq under Grant topologies are ZETA, SEPIC (single ended primary inductor 60
465640/2014-1, in part by the CAPES under Grant 23038.000776/2017 – 54, converter) and Ćuk, on isolated versions. Isolated Ćuk con- 61
and in part by the FAPERGS under Grant 17/2551-0000517-1. This article
was recommended by Associate Editor G. Di Capua. (Corresponding author: verter is the only option that intrinsically uses a transformer for 62

Bernardo Andres.) isolation instead of coupled inductor, however, it also has the 63
The authors are with the Power Electronics and Control Research higher component count, in standard version and with increase 64
Group, Department of Electrical Engineering, Federal University of
Santa Maria, Santa Maria 97015900, Brazil (e-mail: [email protected]; of cells [14]. Still, isolated ZETA has discontinuous input 65

[email protected]; [email protected]; roggia@ current and always requires coupled inductor for isolation, 66
gmail.com; [email protected]). even with the use of cells. On the other hand, isolated 67
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCSI.2022.3189884. SEPIC (iSEPIC) has lower component count, continuous input 68

Digital Object Identifier 10.1109/TCSI.2022.3189884 current and, although the use of coupled inductor on standard 69

1549-8328 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 2. Cells used on primary side.

70 version, it is possible to use a transformer with the appropriate

71 choice of cells and techniques, being a suitable converter for

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72 this application.
73 The concern in this case, as in the other isolated con-

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74 verters, is that when the switch is off, the current through
75 the leakage inductance has a significantly variation. The Fig. 3. Generalized structure using cells on primary side.
76 induced voltage is directly proportional to this current vari-
verifying the effects shown on previous sections. Section V 121
77 ation and the value of inductance. Since these values are
concludes the paper. 122
78 considerable higher on isolated converters with coupled induc-
79 tor for isolation, some snubbers were proposed for iSEPIC,
II. T HEORETICAL A NALYSIS AND G ENERAL S TRUCTURE 123
80 such as [15], where a passive regenerative snubber cell is
81 presented, and [16], where a ripple-free input current and A. Cells Used on Primary Side 124

lossless snubber is presented. Besides mitigating the voltage The main cells used on primary side, shown in Fig. 2,
82

88
Pr
spikes, these alternatives have the aforementioned problems of
increased complexity, volume and cost, without obtaining high
efficiency.
Therefore, this work makes a theoretical study of cells
applied on primary and secondary sides of an isolated dc-dc
SEPIC in order to increase its static gain, without the use
are found in [18], considering the isolated SEPIC and the
position on its circuit where cells are inserted, shown in
Fig. 3. Table I shows the circuit of synthesized converters
using cells of Fig. 2, considering the position indicated in
Fig. 3. Moreover, some relevant information is presented,
such as component count, maximum voltage over diodes, V Do ,
125

126

127

128

129

130

131

89 of snubber circuits. Techniques that increase the number of and switch, V D S , besides static gain of each topology. The 132

90 active switches, such as cascading or integration with other switched inductor (SL) technique consists of two inductors 133

91 converters, or include coupled inductor, are disregarded. Sim- with same inductance, magnetized in parallel when switch is 134
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92 ilar concept and methodology of conception of converters are on and demagnetized in series when switch is off [19]. The 135

93 presented in [17], where passive switched-capacitor-inductor voltage lift (VL) concept is based on a capacitor charge until 136

94 cells are inserted in a boost converter, and [3], where different it reaches a certain voltage level, adding this voltage level 137

95 techniques are presented and analyzed to improve the static to output. Combining both techniques, SL and VL, results 138

96 gain of a boost converter. Despite that, the main difference in the self-lift SL. It is possible to add more capacitors to 139
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97 in those works is that the converters are non-isolated, which this cell, increasing voltage gain, but also increasing voltage 140

98 implies in relevant differences, such as the component count stress over semiconductors. 141

99 to achieve a similar static gain and analysis involving leakage The quadratic voltage multiplier cell (VMC2 ) is found 142

100 inductance and the effects of using transformer or coupled on quadratic boost converter [20], lately presented in [21], 143

101 inductor, such as voltage spikes. Moreover, in [17] the increase obtained from the cascade of traditional boost converter. The 144

reduced redundant power processing (R2 P2 ) is also presented

102 of static gain is directly proportional to voltage over switch, 145

103 therefore, to increase the gain, it is necessary to select a switch in [21] and it is similar to VMC2 , changing the position of 146

104 with higher voltage ratings, decreasing converter efficiency. diode D1 with capacitor C1 , modifying principle of operation 147

105 This will be considered in the comparative analysis on next and voltage gain. Both quadratic cells are found in [18] 148

106 sections. as voltage multiplier cells used on non-isolated converters. 149

107 In section II, the cells configuration is shown and each Finally, quasi-z-source (QZS) cell is obtained replacing the 150

108 generated converter contains a brief description, presenting diode D2 of VMC2 cell with a capacitor, increasing the 151

109 its main characteristics, besides the analysis of static gain, voltage gain. This cell is generally used as previous stage of 152

110 voltage stress, etc. Curves are shown for comparison purposes inverters [22], but is also found in combination with other 153

111 among these topologies and, in order to define which cell is cells on secondary [23]. 154

112 more appropriate, the analysis takes into account some relevant Each cell added on primary, as indicated in Fig. 3, propor- 155

113 issues of isolated SEPIC, besides low static gain, such as: high tionally elevates voltage stresses over switch and output diode. 156

114 leakage inductance, due to coupled inductor, voltage stresses A comparison between the converter with SL and QZS cell 157

115 and voltage spikes over semiconductors. An analysis of dc shows that the lower number of diodes and the higher number 158

116 magnetizing current, relating this with the coupled inductor of capacitors cause an increase in static gain, but also elevates 159

117 and transformer is shown, having a great relevance on cell’s voltage stress over switch and output diode. Curves of static 160

118 choice. In Section III, a case study with brief theoretical analy- gain for all converters obtained with the use of each cell are 161

119 sis of the proposed converter is presented. Experimental results shown in Fig. 4, for turn ratio equal to one, three and five, 162

120 are shown in Section IV, validating the proposed concept and in order to show significant changes in static gain as long as n 163
ANDRES et al.: COMPREHENSIVE ANALYSIS OF VOLTAGE STEP-UP TECHNIQUES FOR ISOLATED SEPIC 3

TABLE I
S YNTHESIZED C ONVERTERS U SING C ELLS ON P RIMARY S IDE

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Pr
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Fig. 4. Comparison of converters static gain for turn ratio equal to one, three and five.
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164 has higher values. It is important to mention that the quadratic voltage over switch is lower than other converters. More 187

165 converters (iSEPIC with R2 P2 and iSEPIC with VMC2 ) have relevant information, like dc magnetizing current and voltage 188

166 the same static gain. spikes over elements, will be later detailed and compared with 189

167 From Fig. 4, it is possible to observe that converter with cells used on secondary side, defining which option is more 190

168 QZS cell has a static gain higher than the others, mainly for appropriate for this converter for high step-up applications. 191
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169 duty cycle equal to 0.4 or above, therefore, this converter can
170 obtain a high static gain even with low turn ratio. For unitary
171 turn ratio, the others have similar static gain until reaching the B. Cells Used on Secondary Side 192

172 duty cycle of 0.6. For values higher than this, quadratic con- The main cells used on secondary side, shown in Fig. 6, 193

173 verters have their static gain considerably increased, however, are also found in [18], considering the isolated SEPIC and the 194

174 for duty cycle values lower than 0.5, the converter with self- position on its circuit where cells are inserted, shown in Fig. 7. 195

175 lift SL cell has higher static gain than quadratic converters, Table II shows the circuit of synthesized converters using 196

176 while the opposite occurs for values higher than 0.5. Finally, cells of Fig. 6, considering the position indicated in Fig. 7. 197

177 the converter with SL cell has the lower static gain and, for Moreover, some relevant information are presented, such as 198

178 high step-up applications, it is necessary to use a high value maximum voltage over diode, V D , which is the same in each 199

179 of turn ratio or duty cycle. converter (for example, on iSEPIC with VD cell, maximum 200

180 In order to analyze voltage stresses of converters, voltage over D1 and D2 is the same) and average voltage over 201

181 Fig. 5 shows the voltage over switch and output diode, normal- capacitors, besides static gain of each topology. It is important 202

182 ized with respect to input voltage. In the case of output diode, to highlight that voltage over switch is given by Vin /(1 − D) 203

183 for unitary turn ratio, curves are equal to voltage over switch. for all converters, wich is the same of iSEPIC. 204

184 From Fig. 5, it can be seen that, for cells added on primary, The technique based on switched capacitor (SC), or charge 205

185 the increase of static gain results in an increase of voltage over pump, consists in transfer of capacitive energy, without mag- 206

186 switch and output diode. As to isolated SEPIC, as expected, netic elements. They are modular and easily integrated to 207
4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 5. Comparison of normalized voltage over switch and normalized voltage over output diode for n = 3, n = 5 and n = 7.

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Fig. 6. Cells used on secondary side.
Pr TABLE II
S YNTHESIZED C ONVERTERS U SING C ELLS ON S ECONDARY S IDE
E E
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208 converters [24]. Basically, these cells charge one or more principle of operation when added on secondary. The other 218

209 capacitors in one cycle, transferring the energy to one or more cells, known as voltage tripler (VT), have the same static 219

210 capacitors in next cycle, raising up the equivalent output volt- gain when added on secondary, with exception of VMC 2, 220

211 age. According to [18], all these cells presented in Fig. 6 can but the principle of operation and voltage over elements 221

212 be used as voltage multiplier cells on secondary side. One are different. VD cells have this designation because they 222

213 common problem of this configuration, is the high charge and duplicate a symmetric sinusoidal or square voltage wave. 223

214 discharge currents of capacitors, however, in isolated SEPIC Likewise, VT cells are called like this for the same reason. 224

215 the leakage inductance limits the current slope. However, as aforementioned, this condition is only valid form 225

216 In basic form, Greinacher and Cockcroft-Walton cells, symmetric waveform, that is, when converter has duty cycle 226

217 known as voltage doubler (VD), have the same gain and of 0.5. The difference among these cells is the number of 227
ANDRES et al.: COMPREHENSIVE ANALYSIS OF VOLTAGE STEP-UP TECHNIQUES FOR ISOLATED SEPIC 5

It can be seen that, among VT cells, VMC 1 and VMC 279

2 have the lowest voltage over the capacitor that has the highest 280

voltage stress over it. For values of duty cycle lower than 0.5, 281

the converter with VMC 1 is more attractive, while for values 282

over 0.5, the use of VMC 2 is better. Regarding to the sum of 283

Fig. 7. Generalized structure using cells on secondary side. voltages over the capacitors on secondary, the result for VMC 284

1 is considerable better for low values of duty cycle, while for 285

228 capacitors involved in charge and discharge processes, and values over 0.5, among VT cells, Ladder and VMC 2 are more 286

229 consequently in capacitive energy transfer of one cycle to attractive. In general, for values above 0.4, the converter with 287

230 another. It is important to highlight that the use of these VD cell is more attractive, since it uses one less capacitor. 288

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231 cells on secondary results in a resonant stage with sinusoidal Regarding diodes, for values of duty cycle lower than 0.5, 289

232 waveform. the use of VMC 2 is more attractive because the sum of voltage 290

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233 The VD cell is used in dc-dc converters, isolated [25] and over diodes is lower than others, including VD cell, that has 291

234 non-isolated [26]. Basically, it consists of charging C1 in one one diode less, while for values over than 0.5, VMC 1 (or 292

235 cycle and transferring its energy for output in other cycle. Dickson) is better. The addition of diodes on secondary, when 293

236 More relevant information will be discussed in next section, combined with the addition of capacitors, increases the static 294

237 comparing both techniques, in primary and secondary. Dickson gain of converter and reduces the voltage over the diodes of 295

238 cell is often found in isolated [27] and non-isolated converters each cell, as shown in Fig. 9. 296

239 [24]. In this case, capacitor C2 is charged with a sinusoidal

240 current in one cycle, through D2 , while capacitor C1 is charged
C. Comparison Among Cells Used on Primary and 297
241

242

243

244

245

246

247
Pr
with a trapezoidal current in other cycle, through D1 and Do .
The Ladder is found in [28] and the diodes do not conduct
simultaneously, as occurs with D1 and Do in Dickson. The
sinusoidal current flows through D2 , charging C1 . On other
cycle, diodes D1 and Do conduct the trapezoidal current, but
not simultaneously, as mentioned. For VMC 1, the charge of
capacitors C1 and C2 occurs in parallel when switch is off,
Secondary
In order to define which option is the best to increase the
static gain of isolated dc-dc SEPIC, another concern of this
converter is the voltage spikes over switch and output diode
due to high leakage inductance of coupled inductor, used for
isolation. Due to this issue, the switch has to be selected
298

299

300

301

302

303

248 so, the trapezoidal current on secondary flows through D1 and to withstand high voltage levels, which significantly increase 304

249 D2 , simultaneously, also in parallel. In this case, voltages over the drain source resistance leading to a negative impact on 305

250 C1 and C2 are smaller in comparison with Dickson. Finally, converter’s efficiency. 306
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251 in VMC 2 the opposite of VMC 1 happens, that is, the charge From this, the cells used on primary side prove to be 307

252 of C1 and C2 occurs in parallel through D1 and D2 , when unattractive, since they elevate the voltage stress over switch 308

253 switch is on, with a sinusoidal current on secondary. and consequently over the output, as aforementioned. There- 309

254 Since that theoretical comparison for these converters is fore, the risk of damaging these semiconductors is a serious 310

255 more limited without a detailed analysis, Fig. 8 shows curves problem, besides the decrease of converter’s efficiency. More- 311
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256 of static gain of converters for turn ratio equal to one, three over, these cells add one or more inductors on primary, where, 312

257 and five. As expected, due to low component count, converter in high step-up applications, voltages are low and current 313

258 with VD cell has lower static gain in comparison with others, are high, therefore, conduction losses are significant, further 314

259 without considering isolated SEPIC. For duty cycle under 0.5, reducing converter’s efficiency. Finally, conduction losses on 315

260 the use of VMC 2 is attractive, while for values over 0.5, the diodes are directly proportional to average current and these 316
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261 other VT cells have higher static gain. It can be seen that the elements are also on the primary, so, these losses are also 317

262 influence of turn ratio is considerable, once curves get further relevant. Despite the reverse voltages of diodes on primary are 318

263 apart when n is increased. lower than those of secondary, their forward voltages, directly 319

264 In order to analyze voltage stresses of converters, the proportional to conduction losses, are closer in comparison 320

265 voltages are normalized with respect to output voltage because to the currents on primary and secondary, that are reflected 321

266 cells are added on secondary. Since the number of capacitors according to the turn ratio. Because of that, conduction losses 322

267 are different for VD and VT cells, one of the graphics of of diodes in primary are usually higher than those of diodes 323

268 Fig. 9 compares the normalized voltage over C1 of VD cell on secondary. 324

269 with the highest voltage over one of the capacitors of VT Based on this analysis, the same can be done for converters 325

270 cells. Besides that, the sum of all voltages over capacitors of using cells on secondary. It was explained and showed that 326

271 secondary is shown in Fig. 9. Since the voltage over diodes of these cells can increase static gain without elevating the 327

272 each converter is equal, for example, voltage over D1 is equal voltage over switch, which is important for this case. Besides, 328

273 to D2 for VD cell, in Fig. 9 the normalized voltage individually the increase of converter’s order, that is, the insertion of 329

274 and also the sum of all normalized voltage stresses are shown. more diodes (and consequently of capacitors too) reduces 330

275 These comparisons are interesting since the voltages over these the voltage over its elements, as shown in Fig. 9, reducing 331

276 elements are directly proportional to their volume and cost, the negative impact of conduction losses of these elements 332

277 besides showing best options according to different values of on converter’s efficiency. Moreover, these cells can mitigate 333

278 duty cycle. the voltage spikes over those diodes, clamping their voltages, 334
6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 8. Comparison of static gain of converters using cell on secondary for turn ratio equal to one, three and five.

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Fig. 9. Comparison of the highest normalized voltage over the diode and the capacitor on secondary and the sum of voltages over these elements.

Pr
E
Fig. 10. Expansion and combination of cells used on secondary side in order to increase the static gain.
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335 making spikes no longer a concern. Finally, as these cells are restricted to VD and VT. Based on the performed analysis, 357

336 composed only of diodes and capacitors, without magnetics Fig. 11 shows a block diagram, comparing characteristics of 358

337 elements, the losses on these cells tend to be smaller, and converters using cells on primary and secondary. 359

338 beyond that, volume of converter can be smaller in comparison

339 with cells on primary.

340 From these theoretical analyzes, considering the main prob- D. Analysis of Magnetizing Current Using Cells on 360

341 lems of isolated SEPIC that have to be solved, it is possible Secondary 361

342 to ensure that the cells added on secondary are more attractive The choice of which cell is more suitable for this converter 362

343 than those added on primary. It is important to highlight that must take into account the use of couple inductor or trans- 363

344 both techniques can be combined, however, due to aforemen- former. In order to define this issue, the Cantilever model can 364

345 tioned problems, if static gain has to be increased without be used to represent a transformer [30], composed of a leakage 365

346 elevating turn ratio and duty cycle, it is more interesting to inductance, L lk , and the magnetizing inductance, L m , as shown 366

347 expand the VD and VT cells, resulting in voltage quadrupler in Fig. 12, where the model is applied on isolated SEPIC. 367

348 and quintupler cells [29]. The result is shown in Fig. 10. More In [29] and [13], a simple approach is presented in order 368

349 information about these expansions and combinations of VD to define if a coupled inductor or a transformer is used for 369

350 and VT cells is found in [29]. The advantage of these cells is isolation and is based on dc level of magnetizing current. 370

351 the high voltage gain, mainly for those with more diodes and As shown in Fig. 13, a coupled inductor has a dc level 371

352 capacitors, using a common range of values of duty cycle from on magnetizing current, indicating a continuous flux, storing 372

353 0.4 to 0.6, with low values of turn ratio. However, high step-up energy in L m , while a transformer theoretically has zero dc 373

354 voltage applications with low power require low component level on this current. In fact, according to [30], a coupled 374

355 count and reduced volume to be attractive, therefore, the inductor is characterized by this energy storage, requiring an 375

356 comparison among cells used on secondary in this paper is air gap for this, increasing the leakage inductance and reducing 376
ANDRES et al.: COMPREHENSIVE ANALYSIS OF VOLTAGE STEP-UP TECHNIQUES FOR ISOLATED SEPIC 7

f
Fig. 11. Block diagram for comparison of synthesized converters.
Fig. 13. Comparison between coupled inductor and transformer.

oo
Fig. 12. Isolated SEPIC using Cantilever model.

377 the magnetizing inductance. This is undesirable, since the

378 leakage inductance causes several voltage spikes across the
379

380

381

382

383

384

385
Pr
switch and, besides that, the utilization of BxH curve is only in
one quadrant, which increases the volume in comparison with
a transformer, where the utilization of BxH curve is in two
quadrants. Furthermore, a transformer does not store energy on
air gap and it is designed to have a lowest leakage inductance
and a highest magnetizing inductance, so that the coupling is
almost perfect. Fig. 14. Isolated SEPIC: (a) classical; (b) with VD; (c) with Dickson VT.
386 To perform this analysis, Kirchhoff current law (KCL) is
due to low leakage inductance, since a transformer is used for 415
387 applied on indicated node in Fig. 14, where three converters
isolation. 416
388 are shown, using Cantilever model: traditional isolated SEPIC
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389 without cell, with VD cell and with Dickson VT cell. Since the A. Principle of Operation 417
390 dc current through a capacitor is theoretically null, using KCL
The converter has four operation stages, as shown in Fig. 16. 418
391 in three indicated nodes, only isolated SEPIC with VD cell has
Briefly, the operation is given as follows: 419
392 dc magnetizing current equal to zero, while in two others this
Stage I (t0 – t1 ): Begins when switch is turned on with 420
393 current is equal to average output current reflected to primary.
qZCS. The primary current, i 1 , linearly decreases until it
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421
394 If this analysis is made for other cells, the result is the same,
reaches 0 A, ending the stage, with diode turned off under 422
395 with all VT cells having the same problem of dc level of
ZCS condition. 423
396 magnetizing current. Therefore, isolated SEPIC using VD cell
Stage II (t1 – t2 ): Begins with i 1 changing its direction. 424
397 on secondary is the most suitable choice. Therefore, in next
A resonance occurs among C, L lk and C1 . From the equivalent 425
398 section, a case study is made for this converter, presenting
circuit and the use of Kirchhoff’s voltage law (KVL), and
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426
399 its principle of operation and key waveforms in continuous-
applying Laplace Transform and inverse Laplace Transform, 427
400 conduction-mode (CCM). Furthermore, experimental results
main parameters, as resonance frequency and resonant period 428
401 are shown in order to prove the proposed concept and per-
are obtained, besides that main equations of sinusoidal volt- 429
402 formed theoretical analysis.
ages and currents. According to [31], the equivalent capaci- 430

tance and resonance frequency are given by 431

403 III. T HEORETICAL A NALYSIS OF iSEPIC W ITH VD C1 nC2

Key waveforms of this converter in one switching period, Ceq = , (1) 432
404
C1 + C
n2
405 in CCM, are shown in Fig. 15. Its complete theoretical
406 analysis is found in [31], therefore it will be synthesized here 1 1 1 n 2 L lk
fr = ; = ; Zr = . (2) 433
407 focusing on main information. The circuit of SEPIC with VD 2πωr Tr Ceq
2π Ceq n 2 L lk
408 Greinacher cell has already been shown in Fig. 14(b). It is
409 important to highlight that these waveforms are obtained for This is the most important stage, since the correct analysis 434

410 operation below resonance frequency. As shown in Fig. 15, is a useful tool to design the converter. The stage ends when 435

411 the converter has qZCS turn-on of switch and ZCS turn-off of i 1 reaches 0 A and D1 is turned off under ZCS condition. 436

412 all diodes, besides small current ripple due to input inductor. Stage III (t2 – t3 ): Begins when switch is on, but there is no 437

413 Besides that, it has another advantages, as clamp of voltage current left on transformer and the diodes are off. Ends when 438

414 spikes over diodes and reduced voltage spikes over switch, switch is turned off with losses, without soft-switching. 439
8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

f
oo
Fig. 16. Current flow path in four stages during one switching period in
Pr CCM operation: (a) stage I; (b) stage II; (c) stage III; (d) stage IV.

the terms, static gain is obtained and it is given by

M=
Vo
Vin
=
n
1− D
. (6)
460

461

Fig. 15. Key waveforms of converter in CCM.

C. Voltage and Current Stresses 462

The voltage stress over the switch is given by 463

Stage IV (t3 – t4 ): Begins when is switch is turned off and

E
440
Vin Vo
441 diode is turned on, without current flux on transformer. There VD S = = . (7) 464

442 is no resonance in this stage, that ends when switch is turned 1− D n

443 on, returning to Stage I. For diodes D1 and D2 , the voltage stresses are given by 465

−nVin
V D1 = V D2 = −Vo = . (8) 466
1− D
E

444 B. Voltage Gain

445 To obtain the static gain of this converter, it is necessary Average voltage across capacitors is given by 467

446 to apply the volt-second balance to the input inductor, L in , Vo (1 − D)

447 during the four operation stages, given by VC = Vin = , 468
n
⎛ t ⎞ VC1 = nVin = Vo (1 − D) ,
1 t2 t3 t4
IE

469
1 ⎝
448 vLin dt + vLin dt + vLin dt + vLin dt ⎠ = 0. VC2 = Vo =
nVin
. (9) 470
Ts 1− D
t0 t1 t2 t3
449 (3) As to average currents, on both diodes this is equal to 471

average output current, Io , given by 472

450 Considering that stages I and III are much smaller than
(1 − D)
451 stages II and IV, it is possible to neglect them. So, (3) can be I D1 = I D2 = Io = Iin . (10) 473
452 rewritten as n
⎛ DT ⎞ As to RMS current values, it can be used the theory of
T 474

1 ⎝ general piecewise waveform presented in [31], according to

vLin dt ⎠ = 0.
475
453 vLin dt + (4)
Ts Fig. 17. For diodes, the result is 476
0 DT
1 2 0.5Tr
454 Voltages across L in on stages II and IV are, respectively, 2 i 1( pk) Ts
Vin and Vin − V D S . So, substituting these variables in (4) and iD1(RMS ) = , (11) 477

n
455

solving the integrals, it is obtained

i Lin(min)
456
2 + i Lin(min) i Lin(max) + · · ·
1 (1− D)
457 (DVin + (1 − D)(Vin − V D S )) = 0. (5) 3 +i Lin(max)
2

It is possible to affirm that the Vin − V D S can be substituted iD2(RMS ) = . 478

458 n
459 by −Vo /n + Vin . So, substituting this in (5) and rearranging (12) 479
ANDRES et al.: COMPREHENSIVE ANALYSIS OF VOLTAGE STEP-UP TECHNIQUES FOR ISOLATED SEPIC 9

where 501

1
k= − DTs , (19) 502
2 fr

1
a= i2 − i Lin(min)
2
k, (20) 503
2 fr Lin(min)

2 2 2 1 1 2
b= Vin k D Ts + DTs + , (21) 504
2 fr 2 fr

1
c= L in 3Vin i Lin(min) + DTs k (22) 505

f
2 fr
3 2
1 1
Vin2 Vin i Lin(min)

oo
2 fr 2 fr
d = + 506
3L 2in L in
+ 6Ceq vCeq(0)i Lin(min) , (23) 507
Fig. 17. Key waveforms to calculate RMS currents.
Ceq 21fr vceq(0) 2 32
480 For the primary coil, the RMS current is e= 508
2n 2 L lk

1

− 6Ceq vCeq (0)i Lin(min) cos wr , (24)

1 2 T 2 fr
509

i 1 ( pk) 0, 5 r

=
2 Ts
481

482

483
i 1(RMS )
1
+
3
Pr
+ i Lin(min) i Lin(max) + i Lin(max)
2

It is important to highlight that for secondary coil, the RMS

(1− D) .
(13)
f =
3/2
Ceq vCeq (0)2 32 cos wr 21fr sin wr 21fr

g = 6Ceq

3/2

1
2 fr

2 n 2 L lk

vCeq (0)Vin cos wr

h = 6Ceq n 2 L lk vCeq (0)Vin sin wr
1
2 fr
1

.
, (25)

(26)

(27)
510

511

484 current is 2 fr
512

i 1(RMS )
485 i 2(RMS ) = . (14)
n D. Voltage and Current Ripples 513
E
The same condition occurs for the capacitors, as shown The percentage ripple of i Lin , vC , vC1 and vCo is given by 514

486

487 above. DVin 100

i Lin (%) = i Lin (DTs ) − i Lin (0) = (28) 515
L in f s Iin
i C(RMS ) = ni C1(RMS ) = i 1(RMS )
488 (15) Iin (1 − D) 100
vC (%) = vC (Ts ) − vC (DTs ) = (29)
E

516
C fs V
For the output capacitor, the same methodology is applied, in
489
Iin (1 − D) 100
490 resulting in vC1 (%) = vC1 (DTs ) − vC1 (Ts ) = . 517
nC1 f s nVin
(30)

518
D
i Co(RMS ) = Io (16) D Io 100
IE

491
1− D vCo (%) = vCo (DTs ) − vCo (Ts ) = . (31) 519
Co f s Vo
492 For the input inductor, the same methodology is applied, These equations will be used in next section to determine 520

493 resulting in the minimum values of the inductance and capacitances. 521

1 2 IV. E XPERIMENTAL R ESULTS 522
494 i Lin(RMS ) = i Lin (min) + i Lin(min) i Lin(max) + i Lin 2(max) .
3 In order to validate the theoretical analysis, main waveforms 523

495 (17) and the equations presented in Section II, a 200 W prototype 524

was built and tested. 525

496 Finally, as to switch RMS current, it is necessary to use the

497 RMS classical equation, once its waveform does not have a A. Design Guidelines 526

498 defined equation. The solution of this results in The input voltage is equal to 37.4 V, due to voltage at 527

maximum power point of a Canadian photovoltaic module, 528

1
b+c model CS5A-200M [32], with a maximum power of 200 W,
g + h 529

499 i s(RMS ) = a− 3
+d +e− f − . for an irradiance of 1000 W/m2 , while output voltage is equal 530
Ts L 2in L in to 400 V, an usual value used in grid-tie inverters. Therefore, 531

500 (18) the required static gain is 10.695, while average output current 532
10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

533 is equal to 0.5 A. A duty cycle of 0.44 was chosen, keeping TABLE III
534 balance between efficiency, turn ratio and voltage stress across M AIN PARAMETERS AND C OMPONENT R ATING
535 semiconductors. Similar values are widely used in the con-
536 ception of high static gain converters with similar values of
537 input voltage and output power [33], [34]. Briefly, this occurs
538 since that high values of duty cycle significantly increases the
539 voltage stress over switch. On the other hand, low values of
540 duty cycle increase the required turn ratio, which causes more
541 transformer losses. Therefore, turn ratio has to be equal to
542 six to obtain the specified output voltage. Finally, switching

f
543 frequency is equal to 50 kHz.
544 1) Transformer: The transformer was acquired through a

oo
545 local supplier of magnetic materials, called Magmattec – Tech-
546 nology in Magnetics Materials. The design of this component
547 was made considering a maximum flux density of 0.51 T, using
548 two nanocrystalline cores, model 2xMMT520T40.31.10B [35],
549 in parallel. These cores have positive characteristics that
550 provide low leakage flux and consequently a small leakage
551 inductance. The primary coil is composed of three AWG
552 20 wires in parallel, resulting in a copper wire resistance of
9 m. The secondary coil is composed of one AWG 25 wire,
553

554

555

556

557

558

559
1 mH.
Pr
resulting in a copper wire resistance of 318 m. The leakage
inductance is 500 nH, while the magnetizing inductance is

2) Capacitors: The input capacitor and resonant capacitor

are defined by two conditions: maximum voltage ripple of 5%
and an equivalent capacitance Ceq that guarantee converter
Fig. 18. Experimental waveforms of vGS , Vin and Vo .

WT1600 power meter were used to measure main

parameters.
As aforementioned, the experimental resonant period has a
590

591

592

560 operation below resonance operation, according to (1)-(2). substantial difference to the theoretical due to the effect of 593

561 From (29), the minimum capacitance obtained is equal to winding transformer capacitance. Different from C and C1 , 594

562 32 μF. From (30), the minimum capacitance obtained is that resonate with L lk , this intrinsic capacitance cuts off part 595
E
563 equal to 890 nF. It is important highlight that the winding of the resonant current in the beginning of stage II. Therefore, 596

564 transformer capacitance has a significant impact on resonant the converter was initially tested with the capacitance C equal 597

565 waveforms. Briefly, the discharge of this capacitance directly to 33 μF and the capacitance C1 equal to 1 μF. According 598

566 affects the resonant stage II, therefore, a linear current cuts to (2), considering this capacitances, the leakage inductance, 599

567 off part of resonance, reducing its period. The experimental the switching period and duty cycle, half of the resonant period 600
E

568 results in next section will show this effect. Therefore, the has a closer value to the period that switch is ON, being equal 601

569 solution is to test the converter using capacitance values for to 8.8 μs. However, in the experimental test, half of resonant 602

570 C and C1 close to what was obtained with (29) and (30), period has an approximate value of 7 μs. Taking this into 603

571 and slowly increase these values until converter is operating account, both capacitances were increased until Tr /2 has a 604

572 near the condition Tr /2 = DTs . As to the output capacitor, the close value to DTs . This condition is obtained for C = 50 μF 605
IE

573 maximum voltage ripple defined is equal to 0.1%, therefore, and C1 = 1.4 μF. According to (29) and (30), the ripple of 606

574 according to (31), the minimum capacitance obtained is equal vC is equal to 3.2%, while ripple of vC1 is equal to 3.18%. 607

575 to 11.2 μF. Due to the low availability of capacitors in the laboratory, 608

576 3) Input Inductor: The input inductor was chosen to guaran- to achieve the required capacitances, C is composed of a 609

577 tee a maximum current ripple of 30%. From (28) the minimum parallel association of electrolytic and film capacitors, while 610

578 inductance obtained is 205 μH. Therefore, an inductor was C1 is composed of a parallel association of film capacitors. 611

579 made using a Kool Mu toroidal core, model 77090 [38], with Fig. 18 shows waveforms of vGS , Vin and Vo , in order to 612

580 an AC flux of 0.035 T. A single AWG 18 wire was used with confirm the obtained static gain. The measured value of Vin is 613

581 35 turns, resulting in a DCR equal to 38 m. The obtained 37.4 V, while output voltage is 400.5 V. Therefore, the static 614

582 inductance is equal to 220 μH. gain is equal to 10.7085, while theoretical is 10.714, a very 615

583 4) Semiconductors: The choice of the semiconductors is close value. Fig. 19 shows main waveforms of switch at full- 616

584 based on maximum voltage and current stresses over them. load condition with a zoom on turn-on transition, proving the 617

585 Therefore, the chosen switch is the IPP051N15N5, while the existence of qZCS on turn-on. Substituting values on equation 618

586 chosen diodes are MUR860. presented on Section II, the calculated VDS in steady-state is 619

66.78 V, while measured value is 65 V. 620

587 B. Experimental Results Regarding diodes, Fig. 20 shows waveforms of vGS , i 2 , v D1 621

588 The prototype specification is shown in Table III. and v D2 . It can be seen that voltages over diodes are clamped, 622

589 Tektronix Encore MD03000 oscilloscope and a Yokogawa eliminating the voltage spikes problems, a concern verified in 623
ANDRES et al.: COMPREHENSIVE ANALYSIS OF VOLTAGE STEP-UP TECHNIQUES FOR ISOLATED SEPIC 11

Fig. 19. Experimental waveforms of switch S1 with zoom on turn-on. Fig. 22. Experimental waveforms of vGS , vC and vC1 .

f
oo
Fig. 20. Experimental waveforms of diodes. Fig. 23. Experimental waveforms of vGS , iLin_CC and iLin_CA .

624

625
Fig. 21.
Pr
Experimental waveforms of turn-off transition for diodes.

traditional isolated SEPIC. Moreover, measured steady-state

voltage over diodes is equal to −392 V, while the theoretical
Fig. 24. Experimental waveforms of transformer.

the considerations approached in this paper regarding the 656

626 value is −Vo , so, there is a negligible error (less than 1%),
cell selection for the converter. To understand the efficiency 657
627 proving that equation is correct. The turn-off transition of
behavior, the losses estimation is evaluated. In this sense, the 658
628 D1 and D2 are also shown in Fig. 21, verifying ZCS condition.
losses of each component were calculated. In relation to the 659
629 For the capacitors, waveforms of vC1 and vC2 are shown
E
switch, the losses can be calculated by: 660
630 in Fig. 22. The measured average voltage over C and C1 are
2
631 equal to 38 V and 220 V, respectively, while theoretical value, Ps = R D S(on) i s(RMS ) 661

632 according to (9), is 37.4 V and 224.4 V, therefore, in both

+ 0.5 f s V D S i s(t 3) to f f + ton V D2 S Coss . (32) 662
633 cases, the error is less than 2%, which is acceptable, consider-
634 ing imprecisions on measurement and voltage drops on other where R D S(on) is the static drain-to-source ON-resistance,
E

663
635 elements that are not considered in theoretical analysis. The i s(RMS ) is the rms current of switch, f s is the switching 664
636 current through the input inductor is shown in Fig. 23, with frequency, V D S is the maximum voltage stress over the switch, 665
637 DC and AC coupling. The measured average value is equal to i s(t 3) is the switch current at instant t3 , to f f and ton are the 666
638 5.28 A, while theoretical value is equal to 5.35 A, an error less switching time for turn-on and turn-off and Coss is the output 667
639 than 1.5 %. The peak-to-peak current is 1.58 A, resulting in a capacitance provided by manufacturer [36]. An important issue
IE

668
640 i Lin equal to 29.5%, according to (28). The theoretical value to highlight in this case: 669
641 of peak-to-peak current is equal to 1.496 A, which results in • The switch current on turn-off (t3 ) is equal to the maxi- 670
642 a i Lin equal to 27.96%. Finally, Fig. 24 presents the main mum value of i Lin . This value is obtained considering Iin 671
643 waveforms of the transformer, showing the effect of winding and the current ripple i Lin; 672
644 transformer capacitance in i 1 . There is a voltage spike over
Since there is a qZCS condition, the ton is disregarded on
primary winding (n 1 ), however, it is not a concern, since the
673
645
calculation. 674
646 voltage peak is not high, while voltage over secondary winding
The losses of diodes are given by:
(n 2 ) is clamped because of capacitors, mitigating the voltage
675
647

648 spikes.
2
PD = IDx(avg) v f . (33) 676

x=1
649 C. Efficiency Results and Loss Distribution
where x can be 1 or 2, the I D(avg) is the average current of each 677
650 In Fig. 25, the converter efficiency is presented for different diode and v f is the forward voltage given by the manufacture 678
651 output power levels. The maximum measured efficiency is datasheet [37]. Since both diodes achieve ZCS condition for 679
652 96.85 % at 180 W, while the full-load efficiency is 96.6 %. turn-off transition, these losses can be neglected. 680
653 It is important to highlight that the converter efficiency is The inductor losses can be calculated by 681
654 higher than 96% for most part of the output power range,
2
655 proving that a high efficiency can be achieved when following PLin = DC RLin i Lin(RMS ) + PL Ae le . (34) 682
12 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

TABLE IV
C OMPARISON A MONG P ROPOSED C ONVERTER W ITH O THER C ONVERTERS P RESENTED IN THE L ITERATURE

f
oo
AQ:4

683

684

685

686

687
Pr
where DCRLin is the copper wire resistance and i Lin(RMS ) is the
RMS current of input inductor. The parameter PL is the core
loss density, defined by PL = aBbpk f sc , where a, b and c are
constants given in the datasheet and B pk is the AC magnetic
flux density. The value of PL also can be determined from
688 the chart provided by the manufacture core information [38].
689 Ae is the transversal core area and le is the core medium path
690 length. Both parameters are also available in [38].
691 The transformer losses are the sum of copper losses and
E
692 core losses and can be calculated by Fig. 25. Measured efficiency of the converter.
693 PT = 2
DC Rn1 i 1(RMS ) + 2
DC Rn2 i 2(RMS ) + Pe + Ph (35)
694 where DCRn1 and DCRn2 are the copper wire resistance of
695 primary and secondary coil, respectively, i 1(RMS ) and i 2(RMS )
E

696 are the RMS current of primary and secondary coil, respec-
697 tively. Pe is the eddy current loss and Ph is the hysteresis
698 loss. Usually, the core manufacture datasheet provides a graph
699 relating the power loss density versus peak AC flux density.
700 In this case, the local supplier gives an estimation of core
IE

701 losses based on the peak AC flux density of 0.51 T, considering

702 the graph of power loss density presented in [35].
703 The capacitor losses are given by Fig. 26. Efficiency evaluation: Loss distribution.

3
The result of the loss distribution is shown in Fig. 26. It is 716
704 PC = ESRI2C(RMS ) (36) important to highlight that the use of transformer associated to 717
x=1 a cell on secondary side enable to choose a switch with a low 718

705 In this case, since the input capacitor is composed by some value of R D S(on), which reduces the conduction losses, while 719

706 capacitors connected in parallel, including film capacitors, the the qZCS reduces the switching losses. The ZCS condition 720

707 ESR is significantly reduced so that the losses associated for both diodes associated to a low average current results 721

708 to this element are small. The same occurs for resonant in less than 1 W of losses in these elements. Therefore, 722

709 capacitor, since RMS current on secondary is smaller than on it is expected that the majority of losses are associated to 723

710 primary and only film capacitors were used. Therefore, most the transformer, however, its losses reduces less than 1.5% 724

711 of capacitor losses are due to the output capacitor. of converter efficiency. It is important to mention that losses 725

712 In order to validate the currents of converter components, associated to input inductor are higher than in semiconductors, 726

713 a digital simulation was performed in PSIM® . After that, using which confirms that the insertion of this component on primary 727

714 all the losses equations and MATLAB software, the losses and side is not a suitable choice, since it can degrade converter effi- 728

715 efficiency of converter were calculated for full-load condition. ciency and increase voltage over switch. Finally, the obtained 729
ANDRES et al.: COMPREHENSIVE ANALYSIS OF VOLTAGE STEP-UP TECHNIQUES FOR ISOLATED SEPIC 13

[3] L. Schmitz, D. C. Martins, and R. F. Coelho, “Generalized high step- 773

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oo
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730 theoretical efficiency for 200 W is equal to 96.85%, while the buck-boost converters with integrated interleaved boost converter and 791
731 experimental efficiency is equal to 96.6%, therefore, there is phase-shifted control,” IEEE Trans. Power Electron., vol. 31, no. 2, 792

732 a small difference of 0.25%, which is equivalent to 0.5 W. pp. 987–999, Feb. 2016. 793

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733 Finally, Table IV shows a comparison among the pre- integrated DC–DC converter with nondissipative snubber for solar 795
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735 To perform this, the switching frequency and input and output pp. 3337–3348, Jul. 2014. 797 AQ:5
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voltage levels have to be equal or at least has a close value,
736

737

738

739

740

741

742
Pr
in order to be able to compare the efficiencies. In general,
it can be seen that VDiSEPIC achieve a high static gain
and, in most cases, the maximum and full-load efficiency are
significantly higher than the other converters. Moreover, due to
the low values of leakage inductance, the presented converter
shows attractive results without the need of snubber circuits.
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799
800
801

802
803
804

805
806

743 The converter prototype is shown in Fig. 27. [13] A. F. Witulski, “Introduction to modeling of transformers and coupled 807
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E
M. L. S. Martins, “Comparative evaluation of a family of isolated Ćuk 811
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746 formed in order to increase the static gain of an isolated no. 16, pp. 3637–3650, Dec. 2020. 813

747 SEPIC. To accomplish this goal, several cells were added [15] G. Tibola, E. Lemmen, J. L. Duarte, and I. Barbi, “Passive regenerative 814

748 on primary and secondary side, generating converters that and dissipative snubber cells for isolated SEPIC converters: Analysis, 815
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E

750 account some relevant information, such as voltage stresses, [16] S.-W. Lee and H.-L. Do, “Isolated SEPIC DC–DC converter with ripple- 818

754 for this application, since it can provide high voltage gain inductor cells starting from a simple graph,” IEEE Trans. Circuits Syst. I, 823
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IE

824
755 with high efficiency without increasing voltage stress over
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756 switch and mitigating voltage spikes over diodes. Moreover, “A survey on voltage boosting techniques for step-up DC–DC convert- 826
757 different from other topologies, this synthesized converter ers,” in Proc. IEEE Energy Convers. Congr. Expo. (ECCE), Sep. 2016, 827

758 uses a transformer for galvanic isolation instead of coupled pp. 1–8. 828

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759 inductor. Experimental results show the qZCS condition for switched inductor technique,” Int. J. Eng. Develop. Res., pp. 32–35, 830
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762 over components were measured and their values are close to Proc.-Electr. Power Appl., vol. 151, no. 5, pp. 590–606, Sep. 2004. 833

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763 what was presented in this work. Finally, maximum efficiency Power Converters. Pasadena, CA, USA, 1989. 835 AQ:7
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[23] F. Evran and M. T. Aydemir, “Z-source-based isolated high step-up 839

766 R EFERENCES converter,” IET Power Electron., vol. 6, no. 1, pp. 117–124, Jan. 2013. 840

767 [1] Y. Zheng, W. Xie, and K. M. Smedley, “A family of interleaved high [24] G. Palumbo and D. Pappalardo, “Charge pump circuits: An overview 841

768 step-up converters with diode–capacitor technique,” IEEE J. Emerg. Sel. on design strategies and topologies,” IEEE Circuits Syst. Mag., vol. 10, 842

769 Topics Power Electron., vol. 8, no. 2, pp. 1560–1570, Jun. 2020. no. 1, pp. 31–45, Mar. 2010. 843

770 [2] W. Li and X. He, “Review of nonisolated high-step-up DC/DC con- [25] X. Hu and C. Gong, “A high gain input-parallel output-series DC/DC 844
771 verters in photovoltaic grid-connected applications,” IEEE Trans. Ind. converter with dual coupled inductors,” IEEE Trans. Power Electron., 845
772 Electron., vol. 58, no. 4, pp. 1239–1250, Apr. 2011. vol. 30, no. 3, pp. 1306–1317, Mar. 2015. 846
14 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

847 [26] X. Hu and C. Gong, “A high voltage gain DC–DC converter integrating Leonardo Romitti (Member, IEEE) was born in 909
848 coupled-inductor and diode-capacitor techniques,” IEEE Trans. Power Frederico Westphalen, Brazil, in 1994. He received 910
849 Electron., vol. 29, no. 2, pp. 789–800, Feb. 2014. the B.S. degree in electrical engineering from the 911
850 [27] B. Axelrod, Y. Berkovich, A. Shenkman, and G. Golan, “Diode-capacitor Integrated Regional University of Upper Uruguay 912
851 voltage multipliers combined with boost-converters: Topologies and and Missions, Frederico Westphalen, in 2017, and 913
852 characteristics,” IET, Power Electron., vol. 5, no. 6, pp. 873–884, the M.S. degree in electrical engineering from the 914
853 Jul. 2012. Federal University of Santa Maria, Santa Maria, 915
854 [28] J. C. Rosas-Caro, J. C. Mayo-Maldonado, R. Salas-Cabrera, Brazil, in 2021. His research interests include photo- 916
855 A. Gonzalez-Rodriguez, E. N. Salas-Cabrera, and R. Castillo-Ibarra, voltaic systems, control in power electronics, dc–dc 917
856 “A family of DC–DC multiplier converters,” Eng. Lett., vol. 19, no. 1, converters, maximum power point tracking methods, 918
857 pp. 57–67, Jan. 2011. and microinverters. 919
858 [29] B. Andres, P. F. S. Costa, F. H. Dupont, L. Roggia, and L. Schuch,
859 “Estudo comparativo de celulas elevadoras de tensao aplicadas ao con-

f
860 versor SEPIC isolado,” in Proc. 12th Seminar Power Electron. Control,
861 Oct. 2019, pp. 1–6.
862 [30] R. W. Erickson and D. Maksimovic, “A multiple-winding magnetics António Manuel Santos Spencer Andrade (Mem- 920

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863 model having directly measurable parameters,” in Proc. 29th Annu. IEEE ber, IEEE) was born in Ribeira Grande, Cabo Verde, 921
864 Power Electron. Spec. Conf., May 1998, pp. 1472–1478. in 1989. He received the Bachelor of Science 922
865 [31] B. Andres, L. Romitti, F. H. Dupont, L. Roggia, and L. Schuch, “Analy- degree in automation and control engineering from 923
866 sis and design of isolated SEPIC converter with greinacher voltage the University of Caxias do Sul, Caxias do Sul, 924
867 multiplier cell,” in Proc. 23rd Congresso Brasileiro De Automática, Brazil, in 2012, and the M.S. and Ph.D. degrees in 925
868 Dec. 2020, pp. 1–8. electrical engineering from the Federal University 926
869 [32] CS5A-200 I 205M, document CS5A-200M, Canadian Solar, Guelph, CA, of Santa Maria (UFSM), Santa Maria, Brazil, in 927
870 USA, Dec. 2013. 2015 and 2018, respectively. Since 2018, he has 928
871 [33] L. Schmitz, D. C. Martins, and R. F. Coelho, “Comprehensive con- been a Professor at the UFSM. His research interests 929
872 ception of high step-up DC–DC converters with coupled inductor and include renewable energy, energy storage systems, 930
873 voltage multipliers techniques,” IEEE Trans. Circuits Syst. I, Reg. dc–dc converters, and microinverters. He serves as an Associate Editor for the 931
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875
876
877
878
879
880
881
Pr
Papers, vol. 67, no. 6, pp. 2140–2151, Jun. 2020.
[34] A. M. S. S. Andrade and M. L. D. S. Martins, “Quadratic-boost
with stacked zeta converter for high voltage gain applications,” IEEE
J. Emerg. Sel. Topics Power Electron., vol. 5, no. 4, pp. 1787–1796,
Dec. 2017.
[35] Nanocrystalline Cores Catalog, document MMT520T40.31.10B, Mag-
mattec, 2019.
[36] MOSFET Optimostm 5Power-Transistor, document IPP051N15N5, Infi-
International Journal of Circuit Theory and Applications and Applied Sciences
in the special issue “Renewable and Sustainable Energy Conversion Systems.”
He serves as a frequent Reviewer for several IEEE T RANSACTIONS journals
in the area of power electronics. He was also selected as a Distinguished
Reviewer of 2021 by the IEEE T RANSACTIONS ON P OWER E LECTRONICS .
932
933
934
935
936

882 neon, Neubiberg, Germany, Apr. 2018.

883 [37] SWITCHMODETM Power Rectifiers, document MUR860, Motorola, Leandro Roggia was born in Santa Maria, Brazil, 937
884 Chicago, IL, USA, 1996. in 1985. He received the B.S., M.S., and Ph.D. 938
885 [38] Powder Core Catalog Magnetics, document 77090, Magnetics, 2020. degrees in electrical engineering from the Fed- 939
886 [39] F. Evran and M. T. Aydemir, “Isolated high step-up DC–DC converter eral University of Santa Maria, Santa Maria, 940
E
887 with low voltage stress,” IEEE Trans. Power Electron., vol. 29, no. 7, Brazil, in 2008, 2010, and 2013, respectively. 941
888 pp. 3591–3603, Jul. 2014. From 2010 to 2013, he was a Professor at the 942
889 [40] P. K. Maroti, S. Padmanaban, J. B. Holm-Nielsen, M. S. Bhaskar, Federal Institute of Rio Grande do Sul, Brazil. He is 943
890 M. Meraj, and A. Iqbal, “A new structure of high voltage gain SEPIC currently at the Federal University of Santa Maria, 944
891 converter for renewable energy applications,” IEEE Access, vol. 7, where he has been a Professor at the Tech- 945
892 pp. 89857–89868, 2019. nical Industrial School of Santa Maria and a 946
[41] S.-W. Lee and H.-L. Do, “Zero-ripple input-current high-step-up boost– Researcher with the Power Electronics and Control
E

893 947
894 SEPIC DC–DC converter with reduced switch-voltage stress,” IEEE Group (GEPOC) since 2003 and the Electrical and Computational Systems 948
895 Trans. Power Electron., vol. 32, no. 8, pp. 6170–6177, Aug. 2017. Research and Development Group (GSEC) since 2013. His research interests 949
896 [42] S. A. Ansari and J. S. Moghani, “A novel high voltage gain noncoupled include power electronics, dc–dc converters, energy storage devices, convert- 950
897 inductor SEPIC converter,” IEEE Trans. Ind. Electron., vol. 66, no. 9, ers for photovoltaic systems, LED drivers, and power factor correction. 951
898 pp. 7099–7108, Sep. 2019.
IE

AQ:8 899 Bernardo Andres was born in Cerro Largo, Brazil, Luciano Schuch (Member, IEEE) received the B.S., 952
900 in 1992. He received the B.S. and M.S. degrees in M.S., and Ph.D. degrees in electrical engineering 953
901 electrical engineering (sub-area power electronics) (sub-area power electronics) from the Federal Uni- 954
902 from the Federal University of Santa Maria (UFSM) versity of Santa Maria (UFSM), in 1999, 2001, and 955
903 in 2015 and 2018, respectively, where he is currently 2007, respectively. Since 2009, he has been with 956
904 pursuing the Ph.D. degree in electrical engineering. the Power Electronics and Control Research Group 957
905 Since 2012, he has been with the Power Electronics (GEPOC), UFSM, where he is currently a Professor 958
906 and Control Research Group (GEPOC), UFSM. His and the Current Dean. His research interests include 959
907 research interests include renewable energy, high- PV systems, UPS, and high-performance power 960
908 efficient power converters, and microinverters. converters. 961
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