Analysis and Design of Isolated SEPIC Converter with

Greinacher Voltage Multiplier Cell

Bernardo Andres1. Leonardo Romitti1. Fabrício Hoff Dupont2.
Leandro Roggia1. Luciano Schuch1.


¹Federal University of Santa Maria, Power Electronics and Control Research Group,
Santa Maria, Brazil
e-mail: adoandres, leonardo.romitti, roggia, schuch. prof {@gmail.com}
²Community University of Chapecó Region, Technology Development Group, Chapecó, Brazil
e-mail: [email protected]

Abstract: High step-up converters are required and used in photovoltaic applications, due to low voltage
of photovoltaic modules. In this paper, an isolated dc-dc high step-up SEPIC with a Greinacher voltage
doubler cell is presented. It has the advantage of continuous input current, high efficiency, high voltage
gain, isolation and demands a single switch, being suitable for low power grid-tie photovoltaic systems.
The operating principles and steady-state analysis are presented, including the detailed analysis of
resonant stage, where the value of primary side capacitor is taken into account and plays an important
role in the design of the converter, since it directly affects the resonance frequency and RMS current
values. Simulation results are presented to validate the analysis and design.
Keywords: Isolated SEPIC, Resonant stage, Voltage multiplier cell.

VMCs applied on primary side. These VMCs used on secondary
1. INTRODUCTION
side are based on switched-capacitor techniques and the most
The increase of photovoltaic systems, specifically low power commonly used are known as voltage doubler (VD) and voltage
grid-tie systems with two converters, makes high-step up dc-dc tripler (VT), with the possibility of expansion to raise voltage
converter very important. These systems, as shown in Fig. 1, are gain, although increasing the number of converter components
also known as AC photovoltaic modules (module-integrated- (Forouzesh et al. 2017).
converter – MIC), where a high step-up converter, in first stage,
The goal of this work, besides showing operating principles, is to
provides a high voltage gain and is connected to a grid-tie
deduce the main equations of the selected converter, proving the
inverter. Galvanic isolation is desirable to maintain security of
accuracy of these equations, obtained considering the value of
the whole system, besides mitigating leakage current and
primary side capacitor, instead of Kim et al. (2015), where this
electromagnetic interference (EMI) problems (Kjaer et al. 2005).
element is disregarded, resulting in a contribution that has not
Single-switch converters are more suitable for lower power been reported yet. Section 2 briefly shows the reasons to choose
applications, reducing volume, costs and complexity. Basic the converter topology. In section 3, theoretical analysis is made,
single-switch isolated topologies are: flyback, ZETA, SEPIC including principle of operations and equations of all stages,
and Ćuk. Among these options, isolated SEPIC converter is a besides the equations of current and voltage ripples, rms and the
very good choice, since it provides continuous input current and static gain of converter. Simulation results are presented in
can significantly reduce the dc magnetizing current with the section 4, showing converter operation and the accuracy of the
appropriate choice of voltage multiplier cells (VMCs), allowing equations, comparing theoretical and simulation results. Finally,
to use a transformer instead of coupled inductor (Williams. in section 5, some relevant conclusions about the work are made.
2016).
2. DERIVATION OF CONVERTER
VMCs applied on secondary side provide the advantages of
increased converter static gain and clamped voltage spikes on The isolated SEPIC converter, shown in Fig. 2b is obtained from
diodes without elevating voltage stress over the switch, unlike the classic topology, shown in Fig. 2a. Cantilever model can be
used to represent the magnetic element (transformer or coupled
inductor) (Erickson et al. 1998). Fig. 2c shows the converter
with VMC on secondary side. Greinacher VD cell, Dickson and
Ladder VT cells, shown in Fig. 3, can be used on secondary side.
As mentioned before, an appropriate choice of VMC can
significantly reduce the dc magnetizing current, guaranteeing
that the magnetizing inductance, Lm¸ does not store energy.
Fig 1 MIC converter with emphasis on first stage. Thus, a transformer is used for galvanic isolation instead of a
Fig 2 Isolated SEPIC derivation: (a) Classic SEPIC converter; (b) Isolated SEPIC using cantilever model; (c) Isolated SEPIC with
VMC on secondary side.
assumptions are made:
1) All power devices are ideal;
2) The magnetizing inductor, Lm, is taken into account on
the analysis, however, using a transformer with high
quality material and good design, its impact is
Fig 3 Voltage multiplier cells used on secondary. irrelevant, once its inductance is much higher than
coupled inductor, consequently providing a better utilization of leakage inductance, Llk;
BxH curve, reducing its volume and its leakage inductance, Llk 3) Output voltage is constant, therefore, capacitor Co is not
(Witulski. 1995). This can be achieved by the use of VD, but it taken into account on the analysis.
is not possible with VT cells. Table I summarizes the voltage
gain of cells and the static gain of converters obtained with the Fig. 5 shows the key waveforms of the converter in one
insertion of these VMCs, based on (Alzahrani et al. 2019), switching period, Ts, in continuous-conduction-mode (CCM). It
(Axelrod et al. 2008) and (Yao et al. 2015), where D is duty is important to mention that these waveforms are obtained for
cycle of converter and n is the transformer turn ratio. operation below resonance frequency. This can be better
understood with Fig. 6, where the three operations modes are
Table 1. Voltage and static gain of cells and converters. presented. The best option is the first mode, nearly to second
mode, where total switching losses are smaller. This will receive
Voltage Static Gain more attention during the description of operation stage 2, where
Cell Topology
gain (M) this resonance occurs. The converter has four operation stages in
– – SEPIC D/(1-D) one switching period, as shown in Fig. 7. The converter
operation is given as follows:
Isolated
– – SEPIC nD/(1-D) Stage I (t0 – t1): This stage begins when switch S1 is turned on,
(iSEPIC) and the primary current i1 begins its linear decreasing, as well as
current i2, while switch current, iS, slowly increases also
Greinacher 1/D VDiSEPIC n/(1-D) linearly. This results in a quasi-ZCS turn on of the switch. This
Dickson n(1+D)/(1- stage ends when current i1 reaches 0 A and diode D2 is turned
(1+D)/D VTiSEPIC off under ZCS condition. The duration of this stage is
and Ladder D)
considerably smaller than stage II and, because of this, voltages
across capacitors are constant on this stage. The main equations
of this stage are given by
3. THEORETICAL ANALYSIS OF THE CONVERTER
vC1
The circuit of isolated SEPIC with VD Greinacher cell vC1 (t )  nVin   vC1_ min (1)
2
(VDiSEPIC) is shown in Fig. 4. In order to evaluate the
theoretical performance of this converter, the following features vc
are approached in this section: principle of operation, voltage vC (t )  Vin   vC _ max (2)
gain derivation, voltage stress and current stress. 2

Vin
3.1 Principle of operation iLin  t   iLin  t0   t, (3)
Lin

In order to simplify the steady-state analysis, the following vC1_ min  Vo

vC _ max 
i1  t   ni2 (t )  niD 2  i1 (t0 )  n t, (4)
Llk

vC _ max
iLm  t   iLm  t0   t, (5)
Lm
Fig 4 Topology circuit of VDiSEPIC.
 Fig 6 Converter operation according to variation of resonance:
(a) below resonance operation – first mode: DTs > 0.5Tr; (b)
exactly resonance operation – second mode: DTs = 0.5Tr; (c)
above resonance operation – third mode: DTs < 0.5Tr.
series association of Cs and C1. Therefore, Ceq, resonance
frequency, fr, and resonant impedance, Zr, are given by

C
C1
Ceq  n2 , (7)
C
C1  2
n

Fig 5 Key waveforms of VDiSEPIC in CCM operation.

is (t )  iLin  t   iLm  t   i1  t  . (6)

Stage II (t1 – t2): This stage begins when current i1 changes its
direction, so diode D1 is turned on. At this instant, a resonance
occurs among C, Llk and C1, hence currents and voltages are
sinusoidal, charging the capacitor C and discharging C1. Voltage
across Lin still being equal to Vin, and voltage across Lm is equal Fig 7 Current flow path in four stages during one switching
to vC, so, both currents are increasing linearly. To analyse this period in CCM operation: (a) stage I; (b) stage II; (c) stage III;
resonance, it is necessary to obtain the equivalent circuit for this (d) stage IV.
stage, shown in Fig. 8.
Magnetizing inductance is significantly higher than leakage
inductance, and its ac ripple current is reduced, so, this element
can be neglected in resonance analysis. In Fig. 8, inductance Llk
is referred to secondary multiplying its inductance by square of
turn ratio, n², and C is referred to secondary as CS, dividing its
capacitance by n². The equivalent capacitance is composed by a Fig 8 Converter equivalent circuit of resonant stage.
 This stage ends when current i1 reaches 0 A, and, consequently,
1 1 1 n 2 Llk
fr  ;  ; Zr  . (8) diode D1 is turned off under ZCS condition.
2π r Tr 2π C n 2 L Ceq
eq lk
Stage III (t2 – t3): This stage begins when switch is still on, but
Hence, as mentioned before, there are three possibilities of there is no current left on transformer and diodes are off, so,
operation regarding to resonance frequency, switching period voltage vC1 is constant, equal to the value at the end of stage II.
and duty cycle. The best choice are values of Tr, Ts and D that Once the duration of this stage is considerable smaller than
make converter operate in first mode, near to second mode. In previous stage, and C is in series with Lm, its voltage, vC, also can
this case, ZCS condition is guaranteed to D1, besides root mean be considered constant. This stage ends when S1 is turned off,
square (RMS) and peak value of is and iD1 are the smallest with losses, without soft-switching. Similar to stage 1, this stage
possible. is very small and it happens in first and second modes of
operation, but not in third. The main equations are given by
To solve the circuit, it is necessary to use Kirchhoff’s voltage
law (KVL), obtaining vC1
vC1 (t )  nVin   vC1_ max , (17)
2
di2 1 t2
vn ² Llk  vCeq = 0   n² Llk   iCeq dt  vCeq (0) = 0. (9) vc
dt Ceq t1 vC (t )  Vin   vC _ min , (18)
2
Considering that iCeq = -i2 = -i1/n, and applying Laplace
Transform over (9), yields Vin  TR 
iLin  t   iLin  t2   t  2  =iLin_ max , (19)
Lin  
i1 i i (s ) vCeq (0)
 sn2 Llk (s )  n 2 Llk 1 (0)  1   0, (10)
n n nsCeq s vC _ min  TR 
iLm  t   iLm  t2   t   =iLm_ max , (20)
Lm  2 
where i1(0) and vCeq(0) are the initial conditions of current and
voltage, respectively. Rearranging terms, current i1 can be is (t )  iLin  t   iLm  t  . (21)
obtained, given by
Stage IV (t3 – t4): This stage begins when switch is turned off
i1 (s ) 

n Ceq (+sn 2 Llk i1 (0)  vCeq (0)) . (11)
and diode D2 is turned on, and there is current flux on
s 2 n 2 Llk Ceq  1 transformer. Differently from stage 2, this one occurs without
resonance, and, consequently, currents and voltages are not
Considering i1(0) = 0 A, once its value is null at begin of stage 2, sinusoidal, charging capacitor C and discharging C1. During this
and applying inverse Laplace Transform, i1 is obtained in time stage, the voltage across Lin is the difference between Vin and
domain, given by VDS¸ resulting in a linear decreasing of iLin, while voltage across
Lm is the difference between vC and VDS, also resulting in a linear
Ceq decreasing of iLm. This stage ends when switch is turned on. The
i1 (t )  ni2 (t )   niD1  n vCeq (0)sin(wr t ), (12) main equations are given by
n 2 Llk
 iLin _ max  t  DT   ... 
where vCeq(0) is obtained by the difference between vC1(0) and 1 
nvC(0). Finally, considering that iC = i1, and iC1 = -i1/n, and vC  t   vC _ min    t  DT 2 V  V   (22)
C  DS in
 
applying the equation of capacitor voltage in s domain, the main  2Lin 
equations are given by
 iLin _ max  t  DT   .. 
vC (t ) 

CvC (0)  Ceq nvCeq (0)  Ceq nvCeq (0))cos(wr t )   
C  iLm _ max  t  DT   .. 
(13)  2

vC1 (t ) 

C1vC1 (0)  Ceq vCeq (0)  Ceq vCeq (0)cos(wr t )  vC1  t   vC1_ max 
1   t  DT  VDS  Vin  
  ..  (23)
C1 nC1  2Lin
 
 2 
Vin    t  DT  VDS  Vin  
iLin  t   iLin  t1   t, (14)  2Lm 
Lin  

vC (t ) VDS  Vin 
iLm  t   iLm  t1   t, (15) iLin  t   iLin _ max   t  DT  , (24)
Lm Lin

is (t )  iLin  t   iLm  t   i1  t  (16) VDS  Vin 

iLm  t   iLm _ max   t  DT  , (25)
Lm
 i1  t   iLin  iLm  ni2 (t )  niD 2 . (26)

3.2 Voltage Gain Derivation

To obtain the static gain of this converter, it is necessary to apply

the volt-second balance to the input inductor, Lin, during the four
operation stages, given by

 t1 t2 t3 t4 
1
  vLin dt   vLin dt   vLin dt   vLin dt   0. (27)
Ts  t0 t1 t2 t3 

Considering that stages I and III are much smaller than stages II
and IV, it is possible to neglect them. So, (27) can be rewritten
as

1  DT T 
  vLin dt   vLin dt   0. (28)
Ts  0 DT 

Voltages across Lin on stages II and IV are, respectively, Vin and

Vin - VDS. So, substituting these variables in (28) and solving the Fig 9 Key waveforms to calculate RMS of iD1 and iD2.
integrals, it is obtained where Dk is the duty cycle of segment k, and uk is the
contribution of segment k. The contribution depends on the
 DVin  (1  D)(Vin  VDS )   0. (29) shape of the segment. To better understand this, in Fig. 9 some
waveforms and crucial points to calculate RMS of iD1 and iD2 are
From analysis of stage IV, it is possible to affirm that the Vin – shown.
VDS can be substituted by -Vo/n + Vin. So, substituting this in (29) According to (Erickson et al. 2001), current iD2 has a trapezoidal
and rearranging the terms, static gain is obtained and it is given segment, while iD1 has a sinusoidal segment. From analysis of
by operation stages, it can be affirmed that iD1 is equal to i1 referred
Vo to secondary in stage II. In the same way, iD2 is equal to iLin
n
M   . (30) referred to secondary in stage IV. The portion of iD2 during the
Vin 1  D stage I is neglected, since the duration of this stage is
considerably smaller than the duration of stage IV and, therefore,
3.3 Voltage and Current Stress it does not affect the RMS current evaluation. Dk of segment uk
of iD1 is equal to 0.5Tr/Ts, resulting in a RMS equation given by
The voltage stress over the switch is given by
1 2 0.5Tr
i 1( pk )
V i1( rms ) 2 Ts
VDS  in . (31) iD1( rms )   . (34)
1 D n n
For diodes D1 and D2, the voltage stresses are given by Dk of segment uk of iD2 is equal to (1-D), resulting in a RMS
equation given by
VD1  VD 2  Vo . (32)
uiLin (1  D )
It can be seen that even with the increase in static gain, voltage iD 2( rms )  ;
stress on switch is the same of classical isolated SEPIC, while n
voltage stress on diodes is smaller. 2
1  i Lin (min)  iLin (mi n) iLin (max)  ..  (35)
(1  D)
As to RMS current values on diodes, it can be used the theory of 3  i 2 Lin (max) 
general piecewise waveform, where a periodic waveform,  
iD 2( rms )  .
composed of N piecewise segments has a RMS value of n

Finally, as to switch RMS value, it is necessary to use the

N classical equation of RMS variable, once is waveform does not
RMS   Dk uk , (33) have a defined equation, given by
k 1
   Tr 2    1   1 
   i  i  2 dt   ..  g  6Ceq   vCeq (0)Vin cos  wr , (46)
  0 1 Lin  2 fr   2 fr 
 
1 Ts 2 1   
is  rms    is dt   . (36)  1 
Ts 0 Ts   DT  h  6Ceq 3/2 n 2 Llk vCeq (0)Vin sin  wr
s  . (47)
    iLin 2 dt    2 fr 

  Tr 
 
  2  
3.4 Voltage and current ripples
Substituting i1 and iLin by its equations previously presented in
(36), results in The voltage and current ripples are obtained by the integral of
current on inductor and voltage of capacitor in a switching
  2 
 period, analyzing and rearranging the therms. So, current ripple
 Tr   Ceq (v ( 0 ))sin(w t )n  ..  
 2  n 2 L Ceq r  of iLin is given by
R 
    dt  .. 
1  0  i Vin   1
is  rms     Lin_ min L  t   . (37) iLin  iLin  DT   iLin  0   Vin DT . (48)
Ts   in   Lin
 DTs 2 
  i 
Vin 
t dt  Voltage ripple of vC is given by
    Lin_ min
L

 
 r T in 
 2  I in 1  D 
vc  vc T   vc  DT   . (49)
Cf s
The solution of this equation will give
Voltage ripple of vC1 is given by
 bc 
1    g  h  I in 1  D 
a   3 
is  rms    d e f   , (38) vc1  vc1  DT   vc1 T   . (50)
Ts  Lin 2  Lin   nC1 f s
 
 
4. SIMULATION RESULTS
where
This section presents simulation results of the VDiSEPIC
 1   converter, in order to verify the theoretical analysis approached
k      DTs  , (39) in this paper. The simulation was performed with the parameters
  2 fr   presented in Tab. 2, using a time step of 0.2 ns.

 1  2 2 Table 2. Parameters of simulation.

a  iLin _ min  iLin _ min k , (40)
 2 fr  Parameter Value
Output power 200 W
 2
2  1   1   fs 24 kHz
b  Vin  kD 2Ts 2  DTs    , (41)
 2 fr   2 fr   Ts 16.66 µs
   Vin 37.4 V
Vo 404.3 V
  1  D 0.445
c  Lin  3Vin iLin _ min   DTs   k (42)
  2 fr  n 1:6
Lin 1 mH
 1 
3
 1 
2 Llk 1 µH
2
  Vin   ViniLin _ min Lm 1 mH
2f 2f
d r2  r  6Ceq vCeq (0)iLin _ min , (43) C 33 µF
3Lin Lin C1 9.155 µF
Co 100 µF
 1  2 2 R 821.13 Ω
Ceq   vceq (0) 3
2
 rf  1 
e 2
 6Ceq vCeq (0)iLin _ mín cos  wr  , (44)
2n Llk  2 fr  Input voltage was chosen from the optimum operating voltage
under Standard Test Conditions of PV module CS5A-200, from
 1   1  Canadian Solar, which has a nominal maximum power of 200
Ceq 3/2 vCeq (0)2 32 cos  wr  sin  wr  W. Duty cycle and turn ratio were defined so that the output
f   2 fr   2 fr , (45) voltage is around 400 V, keeping duty cycle at a maximum
2 n 2 Llk value of 0.5 and turn ratio at a maximum value of 6.
 Fig 12 Simulated waveforms of vGS, iD2 and vD2.
Fig 10 (a) Simulated waveforms of vGS, is and iD1; (b)
Simulated waveforms of vGS, iD1 and vD1. Fig. 12 shows waveforms of vGS, iD2 and VD2, with zoom on turn-
off instant of D2. This zoom gives a better view of ZCS
Input inductor, Lin, was chosen for a maximum current ripple of condition. Forward voltage of D2 is equal to VD1, -403.1 V.
15%, while primary capacitor, C¸ and resonant capacitor C1,
were chosen for a maximum voltage ripple of 10% and 1%, Fig. 13 shows waveforms of vGS, is and vDS, with zoom on turn-
respectively. As the transformer was not designed, leakage on instant of S1. This zoom gives a better view of quasi-ZCS
inductor was chosen to guarantee converter operation in first condition. Voltage stress on the switch is 67.2 V, being in
mode, near to second mode. Magnetizing inductor was chosen agreement with theoretical value using (31).
with an inductance thousand times higher than leakage
inductance. Finally, load resistor, R, was chosen in order that
output power is 200 W.
Using (8), the calculated resonance frequency is equal to 29.059
kHz, while in simulation it is equal to 29.036 kHz, resulting in a
small difference of 23 Hz, less than 1% of error. vGS, is and iD1
are shown in Fig. 10a. As can be seen in this figure, converter is
operating in first mode, near to second mode. Considering the
values of duty cycle, and switching period, the total time that
switch is ON is 18.542 µs, while half of resonant period is 17.21
µs. Once converter is operating in first mode, ZCS condition is
obtained in D1, as can be seen in Fig. 10b, where diode forward
voltage is -403.1 V, equal to -Vo.
Fig 13 Simulated waveforms of vGS, vDS and is.
To verify the theoretical static gain of converter, using (30), the
value obtained is 10.811, while in simulation it is equal to 10.78, Finally, Fig. 14a shows waveforms of vGS, iLm, i1 and iLin. Fig.
once that Vo is practically constant, with 403.1 V and Vin is 37.4 14b shows only ac component of iLin, to verify the ripple of this
V. Fig. 11a shows voltages of capacitors C and C1. Fig 11b current. ∆iLin simulated is 0.692 A, while calculated ∆iLin, using
shows only ac component, to verify the ripple of vC and vC1. ∆vC (48), is 0.693 A, also with an error less than 1%.
simulated is 3.723 V, while ∆vC1 simulated is 2.234 V. Using
(49) and (50), calculated ∆vC is 3.73 V, while calculated ∆vC1 is Table 3 shows a comparison of the simulated and calculated
2.241 V, resulting in a small error less than 1%. main parameters of the converter. These results show that all
equations obtained in theoretical analysis have a good accuracy,

Fig 11 (a) Simulated waveforms of vGS, vC and vC1; (b) ripple Fig 14 (a) Simulated waveforms of vGS, iLm and iD1; (b) ripple
of vC and vC1. of iLin.
with a small error, less than 1%, in comparison with simulated Erickson, R.W. and Maksimovic, D. (2001). Fundamentals of
results. power electronics, 2nd ed., Kluwer academics publishers.

Table 3. Comparison of calculated and simulated Forouzesh, M., Siwatoki, Y.P., Gorji, S.A., Blaabjerg, F. and
parameters. Lehman, B. (2017). Step-up dc-dc converters: a
comprehensive review of voltage-boosting techniques,
Parameter Calculated Simulated Error (%) topologies and applications. IEEE Trans. on Pow. Elect.,
fr (kHz) 29.059 29.036 23 (0.08) vol. 32, no. 12, pp. 9143-9178.
M 10.81 10.78 0.03 (0.3)
VD1 = VD2 (V) -404.3 -403.1 1.2 (0.3) Kim, M. and Choi, S. (2015). A fully soft-switched single
VDS (V) 67.388 67.2 0.188 (0.28) switch isolated dc-dc converter. IEEE Trans. Pow.
iD1 (rms) (A) 0.855 0.848 0.007 (0.82) Elect., vol. 30, no. 9, pp. 4883-4890.
iD2 (rms) (A) 0.664 0.66 0.0044 (0.67)
is (rms) (A) 8.406 8.334 0.072 (0.85) Kjaer, S.B, Pedersen, J.K. and Blaabjerg, F. (2005). A review
∆iLin (A) 0.693 0.692 0.001 (0.14) of single-phase grid-connected inverters for photovoltaic
∆vC (V) 3.73 3.723 0.007 (0.188) modules. IEEE Trans. Ind. Appl., vol. 41, no. 5, pp.
∆vC1 (V) 2.241 2.234 0.006 (0.3) 1292-1306.

Williams, B. (2016). Transformer isolated buck-boost

5. CONCLUSIONS converters. Renewable Energy and Sustainable
Development, vol. 2, no. 2, pp. 112-125.
This work presented a dc-dc high step-up SEPIC with a
Greinacher VD cell, used as primary stage of a MIC converter. Witulski, A.F. (1995). Introduction to modeling of
Its derivation was made, showing that VD cell is an appropriate transformers and coupled inductors. IEEE Trans. Pow.
choice. Theoretical analysis was made, showing operating Elect., vol. 10, no. 3, pp. 349-357.
principle of all stages, besides obtaining the equations used for
comparison with simulation results, including the resonant Yao, J., Abramovitz, A. and Smedley, K.M. (2015). Analysis
analysis considering primary capacitor. and design of charge pump-assisted high step-up tapped
inductor SEPIC converter with and “inductorless”
Simulations results were performed and compared with regenerative snubber. IEEE Trans. Pow. Elect., vol. 30,
theoretical values obtained from the equations. These results no. 10, pp. 5565-5580.
show a high static gain, without using a high turn ratio and high
duty cycle. Besides that, all theoretical calculated values show a
good accuracy in comparison with simulated results, proving
that the analysis are correct.

ACKNOWLEDGMENTS
This work was supported by Coordenação de Aperfeiçoamento
de Pessoal de Nível Superior – Brasil (CAPES/PROEX) –
Código de Financiamento 001, INCTGD, CNPq
(465640/2014-1), CAPES (23038.000776/2017- 54),
FAPERGS (17/2551-0000517-1).
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