Z8F80216033

Datasheet Explanation Update

for Infineon’s Automotive MOSFETs

About this document

Scope and purpose
The latest datasheets for Infineon’s mid-voltage (from 40V up to 100V) Automotive MOSFETs are generated with
a new template. Along with the datasheet template update, some parameters are specified with a new format.
This application note explains the definition of parameters and related plots in the datasheet. Together with
published application notes listed in the reference section, this will help engineers who design automotive
applications read and understand the datasheet properly to select the right product for their applications.

Intended audience
Design engineers for automotive applications

Table of contents
About this document ....................................................................................................................... 1
Table of contents ............................................................................................................................ 1
1 Introduction .......................................................................................................................... 2
2 Datasheet Parameters in New Datasheet Template .................................................................... 3
2.1 Power Dissipation ................................................................................................................................... 3
2.2 Drain Current ........................................................................................................................................... 4
2.3 Safe Operating Area ................................................................................................................................ 5
2.4 Thermal characteristics .......................................................................................................................... 6
2.5 Typical Output Characteristics and Maximum Gate-Source Voltage .................................................... 7
2.6 Drain-Source ON-state Resistance as a function of Drain Current ........................................................ 8
2.7 Transfer Characteristics .......................................................................................................................... 9
2.8 Drain-Source ON-state Resistance ......................................................................................................... 9
2.9 Gate Threshold Voltage ......................................................................................................................... 10
2.10 Capacitances ......................................................................................................................................... 11
2.11 Reverse Diode Characteristics .............................................................................................................. 12
2.12 Avalanche Ratings and Characteristics ................................................................................................ 13
2.13 Drain-Source Breakdown Voltage ........................................................................................................ 14
2.14 Gate Charge Characteristics.................................................................................................................. 15
2.15 Leakage Current .................................................................................................................................... 16
2.16 Switching Times .................................................................................................................................... 16
2.17 TJ – Operating temperature .................................................................................................................. 17
2.18 Gate Resistance ..................................................................................................................................... 17
2.19 Packaging Information.......................................................................................................................... 18
3 Summary ............................................................................................................................. 19
4 References ........................................................................................................................... 20
5 Revision History .................................................................................................................... 21

Application Note Please read the Important Notice and Warnings at the end of this document
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for Infineon’s Automotive MOSFETs
Introduction

1 Introduction
Power MOSFETs are widely used for a variety of automotive applications. Infineon offers a broad portfolio of
high power automotive MOSFETs. Application designers can select the device which best meets the
application’s requirements by using product datasheets. The datasheet is one of the most important resources
to help the designer because of the detailed technical product information it contains about the
MOSFET. However, sometimes, the datasheet is deemed to be too complicated because of the great amount of
information it contains in such a condensed format. This application note will help overcome that perception
by providing general guidance to help read and understand the datasheet and its contents. Each
datasheet specification parameter and diagram is explained in detail.

The goal of this application note is to help improve the reader’s comprehension of the parameters and
diagrams in the datasheet. This will result in a more thorough understanding of MOSFETs and their behavior
by application designers and help them better determine operational limits of these devices. This will also help
application designers more effectively compare different MOSFETs and select the best one for their
application.

Infineon’s website contains several other application notes on a variety of topics, including design guidelines
for MOSFETs. [1]

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2 Datasheet Parameters in New Datasheet Template

MOSFET datasheet consists of specifications of electric parameters in table format as well as specific
characteristics in diagrams. In this chapter, each parameter with related plots is explained separately. Format
of the parameters described in this chapter is based on the latest datasheet template. For existing datasheets
with legacy template, please refer to the appropriate application note available on Infineon web site. [2]

2.1 Power Dissipation

This parameter expresses the maximum allowable power dissipation over the case temperature and it can be
calculated by the following equation.
𝑇𝐽 −𝑇𝐶
(1) 𝑃𝑡𝑜𝑡 (𝑇𝐶 ) =
𝑅𝑡ℎ𝐽𝐶

The power dissipation Ptot is related to junction-to-case thermal resistance RthJC which is material and
dimension dependent. With increasing case temperature, the maximum allowable power dissipation decreases
as illustrated in the diagram in the datasheet.

Figure 1 Maximum rating for Ptot

Figure 2 Maximum power dissipation Ptot=f(TC)

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2.2 Drain Current

The continuous Drain current ID is the maximum current which can flow via the device without exceeding any
thermal boundary conditions. There are two limitations for the ID rating – one is maximum allowed junction
temperature and the other is the package current limit coming from Source contact to substrate material or
interconnect. The maximum drain current at a given case temperature can be calculated by the following
formula under the function of TJ (junction temperature), TC (case temperature), RthJC (junction-to-case thermal
resistance) and RDS(on)_TJ(max) (maximum on-state resistance at maximum junction temperature):
𝑇𝐽 −𝑇𝐶
𝑅𝑡ℎ𝐽𝐶
(2) 𝐼𝐷 (𝑇𝐶 ) = √ 𝑅
𝐷𝑆(𝑜𝑛)_𝑇𝐽(𝑚𝑎𝑥)

In the latest MOSFET datasheet with new template, maximum Drain current ID is specified under three different
conditions as shown in Figure 3.

Figure 3 Maximum Drain current (ID and ID,pulse)

First rating is the chip limited current, which is the calculated theoretical maximum rating as described by
equation (2) above. The current is limited by maximum junction temperature at given case temperature (25°C
unless otherwise specified) based on the thermal impedance from junction to case and the maximum RDS(on) at
TJ(max). This would be useful to show device performance of combined on-state resistance RDS(on) and RthJC as
figure of merit, however, it is not practical rating because case temperature TC will not stay constant based on
conditions in the actual applications.
The second rating is the DC current rating which represents the maximum tested current during manufacturing.
This limitation comes from testing process in production, Source contact to substrate due to electromigration
or interconnect such as bond wire or copper clip on Source as described in the beginning. The corresponding
footnote explains which type of limit is relevant for the specific product. It should be noted that if the limit is
related to test capability, then the actual limit in the application can be calculated by equation (2) above, as
long as it is lower than the chip limitation. If the chip limited current rating is lower than this DC current rating,
then the DC current limit will be same as the chip limited current.
The third rating is the called application based current rating based on a standard RthJA from a JEDEC reference
PCB. This suggests more practical rating under the described conditions, however, the RthJA depends on
external environment such as layout design, substrate material, thermal interface material, heatsink design,
etc., and the RthJA in a particular can be lower that the JEDEC standard PCB resulting in a higher current
capability. As stated above, the maximum current in an application can be determined from equation (2). The
application current rating stated in the datasheet is provided as an indication. It is recommended to check the
rating conditions especially when comparing different devices from different suppliers.

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The pulsed Drain current limit ID,pulse, is relevant at pulse width tp which is specified in addition to case
temperature TC. Therefore, the rating can be calculated using equation (2) above by applying thermal
impedance ZthJC extracted from thermal impedance plot on datasheet instead of RthJA. Since thermal impact to
case temperature TC under a short period of time (typically below 1ms) is minimal, TC can be considered
constant for ID,pulse.
The plot for ID over TC in the latest datasheet also follows the new ID rating format as seen in the Figure 4 below.

Figure 4 Maximum Drain current ID = f(TC)

2.3 Safe Operating Area

Figure 5 shows the maximum allowable Drain current ID as a function of the Drain-Source voltage VDS with
different pulse widths. There are several limitations in the diagram as follows:
a) Top line is defined by a maximum pulsed Drain current ID,pulse.
b) This area is limited by maximum on-state resistance RDS(0n) at maximum junction temperature
c) At fixed TC, the device is limited by the constant power line in this region. Depending on the applied
power pulse width, maximum allowable power loss changes are related to thermal impedance. For
a given pulse width, the thermal impedance ZthJC can be obtained from maximum transient thermal
impedance diagram, which will be described in section 2.4
𝑇𝐽 −𝑇𝐶
(3) 𝐼𝐷 (𝑉𝐷𝑆 ) = 𝑉
𝐷𝑆 ∗𝑍𝑡ℎ𝐽𝐶

d) In linear mode operation there is a risk of forming hot spots at low Gate-Source voltage due to the
potential for thermal runaway. This effect is becoming more critical on the latest MOSFET
technologies which have high current densities in the region where the zero temperature coefficient
point of the transfer characteristic is shifted to higher Drain current. In order to consider the hot
spot effect for higher VDS and longer pulse width, derating is applied to the SOA diagram in this
region.
Please refer to additional application note available on Infineon web site that discusses this topic in
detail. [3]

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e) The maximum breakdown voltage V(BR)DSS of the MOSFET defines the max VDS limit in the SOA
diagram

(a)

(c)

(b)

(d)

(e)

Figure 5 Safe Operating Area ID = f(VDS)

2.4 Thermal characteristics

The RthJC is the thermal resistance from the junction of the chip to the outside of the device, normally exposed
pad unless otherwise specified. This is defined by the MOSFET itself (chip, package, and internal interconnects).
The RthJA is the application dependent thermal resistance from junction to the ambient. The RthJA consists of the
RthJC mentioned above and thermal resistance between MOSFET case to ambient which includes all external
components and the environment. Under normal operation, heat is generated by the power loss in the device
and thermal resistance RthJC and RthJA describe how efficiently heat in the MOSFET die is transferred to the
ambient temperature.

Figure 6 Thermal characteristics RthJC and RthJA

In the latest MOSFET datasheet template, RthJA is revised from the legacy 6cm2 cooling area-based specification.
Since the RthJA conditions as stated in footnote is closer to actual use case, it suggests better idea on thermal
performance of the device in the applications when compared to the legacy specification. It should be noted
that the JEDEC PCB is a 4 layer PCB with two 2oz. layers and two 1oz. layers. A well designed PCB for a given
application can achieve a much lower RthJA, but as every design is different it cannot be specified here.

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The transient junction-to-case thermal impedance ZthJC takes the heat capacity CthJC of the device into account.
It can be used to estimate temperature raise caused by transient power losses. Depending on the pulse width tP
and the duty cycle D = tP/T, thermal resistance varies over a wide range and its behavior is specified as a
diagram in the datasheet as seen in Figure 7. The junction temperature increase can be calculated by the
following equation (4). TJ,start is equal to TC at thermal equilibrium before the power pulse is applied.
(4) 𝑇𝐽 = 𝑇𝐽,𝑠𝑡𝑎𝑟𝑡 + 𝑃𝑡𝑜𝑡 ∗ 𝑍𝑡ℎ𝐽𝐶 (𝑡𝑃 , 𝐷)

Figure 7 Maximum transient thermal impedance ZthJC=f(tp)

2.5 Typical Output Characteristics and Maximum Gate-Source Voltage

The typical output characteristic is illustrated by the Drain current ID as a function of the Drain-Source voltage
VDS at given Gate-Source voltages VGS under specified device junction temperature.
The device should be operated in the ohmic region to consider efficiency. There is a region that the drain
current ID saturates beyond the ohmic region at any given VGS. As the operating point goes into the saturation
region, any further ID increase requires a massive VDS rise, which will lead to conduction loss increase. In this
case, the device may fail if the power dissipation is not limited.
As seen in the diagram, VGS determines the output characteristic of the device. The maximum allowable range
for VGS is also specified.

Figure 8 Maximum Rating for VGS

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Ohmic
Region

Figure 9 Typical Output Characteristics ID=f(VDS)

2.6 Drain-Source ON-state Resistance as a function of Drain Current

The Drain-Source ON-state resistance RDS(on) over Drain current ID at given Gate-Source voltage VGS can be
calculated from typical output characteristic diagram shown in Figure 9 using Ohm’s Law.
𝑉𝐷𝑆
(5) 𝑅𝐷𝑆(𝑜𝑛) (𝐼𝐷 ) = 𝐼𝐷

Figure 10 Typical Drain-Source ON-sate Resistance RDS(on)=f(ID)

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2.7 Transfer Characteristics

The typical transfer characteristic of the device is illustrated by the diagram with the Drain current ID as a
function of Gate-Source voltage VGS under the given junction temperature conditions and Drain-Source voltage
VDS. It is observed that all the curves are intersecting at one point, which is called the temperature stable
operating point.

Figure 11 Typical Transfer Characteristics ID = f(VGS)

The device will operate with a positive temperature coefficient until VGS reaches the temperature stable
operating point, which means that ID increases as the junction temperature TJ increases. Extended MOSFET
operation within this region should be avoided because there is potential to fail due to thermal runaway.
Once VGS exceeds the temperature stable operating point, the device will operate with a negative temperature
coefficient. In this region, the device is stable since ID decreases as TJ increases. Operating a MOSFET within this
region is generally recommended as long as TJ is within the maximum allowable temperature.
Minimum or maximum rating of this characteristic can be estimated by shifting the plots in parallel according
to Gate threshold voltage window.

2.8 Drain-Source ON-state Resistance

The Drain-Source ON-state resistance RDS(on) is one of the key parameters for the MOSFET. It specifies the
resistance of the MOSFET when the part is turned on at a defined Gate-Source voltage VGS, Drain current ID and
junction temperature TJ. This parameter is 100% tested in production under the specified conditions.

Figure 12 Drain to Source on-state resistance RDS(ON)

In addition to the table, the data sheet contains a diagram of RDS(on) as a function of TJ. As can be seen in figure
13, the RDS(on) has a positive temperature coefficient and therefore increases with TJ. It is important that this
effect is considered in any power loss calculation.
To calculate the dependency of the junction temperature, the equation (6) below can be used. The parameter 
is a technology related constant which can be approximated as 0.4 for mid voltage Power MOSFETs.

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𝛼
(6) 𝑅𝐷𝑆𝑜𝑛 (𝑇𝐽 ) = 𝑅𝐷𝑆(𝑜𝑛),25°𝐶 ⋅ (1 + 100)𝑇𝐽 −25°𝐶

Figure 13 Typical Drain-Source ON-state Resistance Characteristics RDS(on)=f(Tj)

2.9 Gate Threshold Voltage

The Gate-Source threshold voltage VGS(th) defines the required Gate-Source voltage at the specified Drain
current ID under given junction temperature TJ. This parameter is 100% tested in production under the given
conditions and specified as minimum, typical and maximum ratings.

Figure 14 Gate Threshold Voltage VGS(th)

This parameter has a negative temperature coefficient and its typical behavior is illustrated in a diagram as a
function of TJ at given ID. Two curves are generally provided in this plot, one is plotted with ID specified in the
table and the other one is with 10 times higher ID because Drain-Source leakage current may reach specified
current at TJ.

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Figure 15 Typical Gate Threshold Voltage Characteristics VGS(th) = f(TJ)

2.10 Capacitances
The parasitic capacitances of the MOSFET are specified with typical and maximum rating under given
conditions, and they are defined by design during development. The capacitances between each terminal can’t
be directly measured, however, they can be calculated using input, output and reverse transfer capacitances.
Following equations describe the relationship among them.
(7) 𝐶𝑖𝑠𝑠 = 𝐶𝐺𝑆 + 𝐶𝐺𝐷
𝐶𝑜𝑠𝑠 = 𝐶𝐷𝑆 + 𝐶𝐺𝐷
𝐶𝑟𝑠𝑠 = 𝐶𝐺𝐷

Figure 16 Specifications of Capacitances

Their typical behavior is illustrated as a function of Drain-Source voltage VDS. Wide voltage dependencies are
observed on Coss and Crss due to the change in the space region during the switching transition of the device.

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Figure 17 Typical Characteristics of Capacitances C=f(VDS)

2.11 Reverse Diode Characteristics

The characteristics of body diode in the MOSFET are defined under specified conditions. The following bullets
explains each parameter in detail:

• Diode continuous forward current IS: this parameter determines maximum allowable DC forward
current flowing into body diode under specified conditions and it is normally identical to continuous
Drain current
• Diode pulse current IS,pulse: this parameter defines maximum allowable pulsed current flowing into body
diode under specified conditions and it is normally identical to pulsed Drain current
• Diode forward voltage VSD: this parameter specifies a voltage drop between Source and Drain at diode
ON-state under given conditions and it is 100% tested in production.

• Reverse recovery time trr: this parameter defines the time until reverse recovery charge is removed.
Typical and maximum rating are specified by design during development.
• Reverse recovery charge Qrr: this parameter specifies the charge that accumulates in the PN junction of
a MOSFET's body diode when the diode is forward biased under given conditions. Typical and
maximum rating are specified by design during development.

Figure 18 Reverse Diode Specifications

Figure 19 illustrates generalized reverse recovery waveforms. Diode forward current IF flows when body diode
of the MOSFET is in the forward conducting state. Once the body diode is switched to the reverse bias
condition, IF continues decreasing with a slope of diF/dt which is determined by external circuit conditions. The
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body diode conducts in the reverse direction, from Drain to Source in this case, for a short period of time. After
the carriers have been swept out and the body diode enters reverse blocking mode, the current flow drops to
the leakage level. Reverse recovery time trr is this short period of time when the body diode conducts in a
reverse direction and reverse recovery charge Qrr is the released charge during trr.

ISD, VDS
ISD
VDS
diF/dt
IF
VDD

t
VSD Qrr
Irr

trr

Figure 19 Generalized Reverse Recovery Waveforms

The typical characteristics of the diode forward current IF is also illustrated in a diagram as a function of Source-
Drain voltage VSD with given junction temperatures.

Figure 20 Typical Forward Diode Characteristics IF = f(VSD)

2.12 Avalanche Ratings and Characteristics

The MOSFET datasheet specifies the maximum allowable avalanche energy EAS under given avalanche current ID
and the maximum capability of avalanche current IAS. The IAS is normally the same as Drain DC current ID unless
limited by technology. These rating are not intended to be used in repetitive mode; only a single pulse is
allowed.

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Figure 21 Avalanche Energy EAS and Current IAS

Avalanche characteristics are illustrated with two diagrams. One diagram presents the dependence of the
pulsed avalanche current IAS over the time in avalanche mode tAV. The device allows avalanche operation inside
the curve in terms of maximum junction temperature. This characteristic is bounded by the total energy of a
pulse. The longer tAV, the lower IAV. The avalanche energy can be calculated by the following equation:
1
(8) 𝐸𝐴𝑆 = 2 ∙ 𝑉𝐷𝑆 ∙ 𝐼𝐴𝑉 ∙ 𝑡𝐴𝑉

The second diagram shows the maximum single pulse avalanche energy EAS as a function of junction
temperature TJ at given IAS. As a rule of thumb, allowable EAS is inversely proportional to IAS. The EAS decreases as
TJ increases, and can be calculated with equation (9).
𝑇𝐽_𝑚𝑎𝑥 −𝑇𝐽
(9) 𝐸𝐴𝑆 (𝑇𝐽 ) = (𝑇 )2 ∙ 𝐸𝐴𝑆_25°𝐶
𝐽_𝑚𝑎𝑥 −25°𝐶

Please refer to two application notes available on the Infineon website that describes avalanche characteristics
in detail. [4] [5]

Figure 22 Typical Avalanche Characteristics, Current IAV = f(tAV) (Left) and Energy EAS = f(TJ) (Right)

2.13 Drain-Source Breakdown Voltage

The Drain-Source breakdown voltage V(BR)DSS is defined as the minimum voltage value at a given Drain current ID
and Gate-Source voltage VGS. This parameter is 100% tested in production.

Figure 23 Drain-source breakdown voltage VBR(DSS)

The breakdown voltage V(BR)DSS of a MOSFET is temperature dependent with a positive temperature coefficient.
A diagram is provided in the datasheet to exhibit the characteristic.

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Figure 24 Drain-source breakdown voltage V(BR)DSS=f(Tj)

2.14 Gate Charge Characteristics

The gate charge QG consists of the Gate-Source charge QGS, the charge between Drain and Gate QGD and over-
drive charge on QGS to reach to the desired Gate-Source voltage VGS from the plateau voltage Vplateau. The QGS
represents the charge to charge Gate-Source capacitance CGS up to Vplateau. During this period, Dain current ID
rises up to the load value after Gate-Source voltage VGS reaches threshold voltage. The behavior of Drain-Source
voltage VDS depends on load condition. The VDS falls simultaneously with the rise of ID when switching a resistive
load, or VDS starts falling after ID reaches load level when switching an inductive load. The Gate-Drain
capacitance CGD, also known as the miller capacitance, has to be discharged before the VDS falls to its ON-state
value. (VDS=RDS(on) * ID) This charge component is defined as Gate-Drain Charge QGD. The combined charge
QGS+QGD is not enough to fully turn on the MOSFET because Drain-Source ON-state resistance RDS(on) is not
minimized yet at this VGS level. To optimize conduction loss, VGS needs to be pulled up to typically VGS=10V, until
the devices reaches full ON state. Total gate charge QG is defined as the charge to reach VGS=10V.
Gate charge characteristics are defined with typical and maximum ratings under the given conditions. The
parameters are specified by design during development at the conditions specified. Two diagrams are provided
in the datasheet as seen in figure 26 below. The diagram on the left illustrates the variation of requisite typical
gate charge at given Gate-Source voltage VGS under the specified Drain current ID and Drain-Source supply
voltage VDD. The diagram on the right is the generalized gate charge waveform which graphically explain the
definition of each of the gate charge parameters.

Figure 25 Gate Charge Specifications

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Figure 26 Typical Gate Charge VGS=f(QGate) (Left) and Generalized Gate Charge Waveform (Right)

2.15 Leakage Current

Two types of leakage current are specified in the datasheet.
• Drain-Source leakage current IDSS is defined under given conditions. IDSS at TJ=25°C is 100% tested in
production. Maximum rating of IDSS comes by design during development.

• Gate-Source leakage current IGSS is defined under given conditions. This parameter is 100% tested in
production. Maximum rating of IGSS comes by design during development.

Figure 27 Leakage Current IDSS and IGSS

2.16 Switching Times

The datasheet includes a table that suggests typical rating for switching time related parameters under the
given conditions. Each bullet explains the definition of reach parameter followed by generalized switching
waveforms for graphical support.
• Turn-on delay time td(on): it is measured between 10% value of rising edge on Gate Source voltage VGS
and 90% value of falling edge on Drain-Source voltage VDS.

• Rise time tr: it is measured at falling edge of VDS between 90% value and 10% value
• Turn-off delay time td(off): it is measured between 90% value of falling edge on VGS and 10% value of rising
edge on VDS.
• Fall time tf: it is measured at rising edge of VDS between 10% value and 90% value

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Figure 28 Switching Time Characteristics

VGS, VDS
VDS

90%

10%
VGS
td(on) tr td(off) tf

Figure 29 Generalized Switching Waveforms

2.17 TJ – Operating temperature

The maximum junction temperature specifies the absolute thermal limit in the operation of power MOSFET. It
is one of the most critical limiting factors. For automotive MOSFETs, the limit is typically at 175°C. The junction
temperature is qualified according to AEC-Q101 up to 1000h. It must not be exceeded under any kind of
circumstances; otherwise the lifetime of the device might be considerably reduced and the proper operation of
the device is not guaranteed. The negative temperature limit is typically at -55°C for automotive power
MOSFETs.

Figure 30 Maximum junction temperature

2.18 Gate Resistance

The latest MOSFET datasheet template provides typical rating of internal gate resistance RG. RG is specified
based upon design during development.

Figure 31 Gate Resistance RG

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2.19 Packaging Information

The latest MOSFET datasheet template provides package information which includes package outline,
recommended footprint design and packing with tape and reel. Infineon website also provides the latest
package information, thus it is encouraged to check it periodically.

Figure 32 Package information

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Summary

3 Summary
The parameters and diagrams described on the datasheet are explained in this document. It is very important
for design engineers to read and understand the datasheet contests properly for finding the right product for
their applications.

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References

4 References
[1] Infineon automotive MOSFET web site
https://www.infineon.com/cms/en/product/power/mosfet/automotive-mosfet/#!documents
[2] Application note “Automotive MOSFETs Datasheet Explanation”
https://www.infineon.com/dgdl/20140428_appnote_MOSFET_Datasheet_explanation.pdf?fileId=db3a30431ed
1d7b2011eee736f845470
[3] Application note “MOSFET linear mode operation and SOA power MOSFETs”
https://www.infineon.com/dgdl/Infineon-
ApplicationNote_Linear_Mode_Operation_Safe_Operation_Diagram_MOSFETs-AN-v01_00-
EN.pdf?fileId=db3a30433e30e4bf013e3646e9381200
[4] Application note “Repetitive Avalanche of Automotive MOSFETs”
https://www.infineon.com/dgdl/AN_Repetitive_Avalanche_Rev_1.pdf?fileId=db3a3043430f543101430f7c6aea0
000
[5] Application note “MOSFET some key facts about avalanche”
https://www.infineon.com/dgdl/Infineon-ApplicationNote_Some_key_facts_about_avalanche-AN-v01_00-
EN.pdf?fileId=5546d462584d1d4a0158ba0210977cde

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Revision History

5 Revision History
Document Date of release Description of changes
version
1.0 November 18, 2021 Initial release
1.1 November 29, 2021 Diagram size adjusted

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Application Note 2021-11-29
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