ECE 448

Lecture 16

Fixed-Point Representation
of Real Numbers
in VHDL 2008

ECE 448 – FPGA and ASIC Design with VHDL George Mason University
 Acknowledgments
This set of slides is partially based on course materials
developed by
Dr. David Hwang - Harvard University (formerly GMU)
Mr. Amos Zaslavsky - Technion –
Israel Institute of Technology

ECE 448 – FPGA and ASIC Design with VHDL 2

 Motivation
Topic of Lab 5

ECE 448 – FPGA and ASIC Design with VHDL 3

corresponding pixel has a fractal color, otherwise, it has a background color.

Fig. 1: Julia set for C = -1+0i

Julia Set Fractal for c=-1+0·i

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 Fig. 2: Julia set for C = -0.5+0.5i

Pseudocode:
Julia Set Fractal for c=−0.5+0.5·i
Each value of Z0=z0x+i·z0y, in the pseudocode below, corresponds to one pixel of the display region.
The plotted region should have the following limits 5

-2 ≤ z0x=Re[Z0] < 2 and -1.5 < z0y=Im[Z0] ≤ 1.5

 The Julia Set Fractal
• Checking whether a given pixel belongs to a fractal
involves a sequence of calculations given by the
equation:

zn+1 = zn2 + zn + c

zn+1, zn, and c are complex numbers!

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 Refresher on Complex Numbers
a = ax + ay∙i Square root of -1

Real Part Imaginary Part

ax=Re(a) ay=Im(a) i2 = −1
Examples of operations on complex numbers:

(2.5 + 5.0∙i ) + (4.0 + 0.8∙i) = 6.5 + 5.8∙i

(2.5 + 5.0∙i ) − (4.0 + 0.8∙i) = −1.5 + 4.2∙i
(2.5 + 5.0∙i ) ∙ (4.0 + 0.8∙i) = 2.5∙4.0+2.5∙0.8∙i+ 5.0∙4.0∙i+5.0∙0.8∙i2=
= (10.0-4.0) + (2.0+20.0)∙i = 6.0+22.0∙i
(2.5 + 5.0∙i )2 = 2.52 + 2∙2.5∙5.0∙i + 5.02∙i2 = 6.25 – 25.0 + 25.0∙i =
= -18.75 + 25.0∙i

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 The quadratic recurrence equation
z = z2 + z + c
where
z = zx + zy∙i
c = cx + cy∙i

z = z2 + z + c = (zx + zy∙i)2 + (zx + zy∙i) + (cx + cy∙i) =

= (zx2 – zy2) + 2∙zx∙zy∙i + (zx + cx) + (zy + cy)∙i =
= (zx2 – zy2 + zx + cx) + (2∙zx∙zy + zy + cy)∙i

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 Pseudocode
In the pseudocode below, z0=z0x+i·z0y, corresponds to one
pixel of the display region.
-2 ≤ z0x=Re(z0) < 2
-1.5 < z0y=Im(z0) ≤ 1.5
-2 z0x=-2..2 2-step 2
0 x=0..640 639 640
1.5 0

y=0..479 (x,y) (zx0, zy0)

z0y=1.5..-1.5

-1.5+step 479
-1.5 480 9
Pseudocode (with complex numbers)
for z0y = -1.5+step to 1.5, step 3/480 do
for z0x = -2 to 2-step, step 4/640 do
{
iteration = 0
z = z0x + z0y∙i
while( |z| < 2) && (iteration < MAX_ITER) )
{
z = z2 + z + c // the quadratic recurrence equation
iteration++
}
if |z| < 2
pixel corresponding to z0x, z0y belongs to a fractal
else
pixel corresponding to z0x, z0y does not belong to a fractal
} // next zx0
} // next zy0
}
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 Pseudocode (with real numbers)
for z0y = -1.5+step to 1.5, step 3/480 do
for z0x = -2 to 2-step, step 4/640 do
{
iteration = 0
zx = z0x
zy = z0y
while( (zx2 + zy2 < 4) && (iteration < MAX_ITER) )
{
zxtemp = zx2 – zy2 + zx + cx
zytemp = 2 · zx · zy + zy + cy
zx = zxtemp
zy = zytemp
iteration++
}

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 Recommended Representation
of Real Numbers
• You are expected to use the Q4.28
fixed-point representation
– 4 integer bits
– 28 fractional bits

• Addition/Subtraction performed as usual

• Multiplication of two Q4.28 numbers
results in a Q8.56 number, which should
be converted back to Q4.28
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 Fixed-Point Representation

ECE 448 – FPGA and ASIC Design with VHDL 13

Fixed-Point Number Representations

• Fixed-point number representations can be generally

categorized as unsigned or signed
• Unsigned numbers represent non-negative numbers;
signed numbers represent negative and positive
numbers
• We focus on:
• Unsigned binary
• Two's complement (signed)

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 Unsigned
Fixed-Point Representation

ECE 448 – FPGA and ASIC Design with VHDL 15

Unsigned Binary Representation
N total bits

K -1
X = å
i =- L
xi × 2i X = xK-1 xK-2 … x1 x0 . x-1 x-2 … x-L

K integer bits L fractional bits

• K integer bits, L fractional bits

• More integer bits, the larger the maximum representable value
• Larger the L, the greater the precision
• Notation QK.L
• K = number of integer bits
• L = number of fractional bits

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Unsigned Binary Examples

Q7.0 example : 0100101. = 3710

Q2.3 example : 01.001 = 9/8 = 1.12510

Q1.4 example : 0.1001 = 9/16 = 0.562510

Q0.7 example : .0001001 = 9/128 = 0.070312510

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Maximum Representable Range

• QK.L unsigned number has decimal range:

• Minimum: 0
• Maximum: 2K-2-L = (2K+L-1) / 2L = (2N-1) / 2L
which is obtained when xi=1 for all i
• Exact representable range: 0 ≤ X ≤ 2K-2-L
• Rule of thumb: range of number X in QK.L notation
• 0 ≤ X < 2K
• The number of integer bits K largely determines the
maximum representable range

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Unsigned Binary Maximum Representable Range
Examples
Q7.0 à rule of thumb: 0 ≤ X < 128 (K=7)
min: 0000000 = (0)10
max: 1111111 = (27-1) / 20 = 12710
Q2.3 à rule of thumb: 0 ≤ X < 4 (K=2)
min: 00.000 = (0)10
max: 11.111 = (25-1) / 23 = 3.875
Q1.4 à rule of thumb: 0 ≤ X < 2 (K=1)
min: 0.0000 = (0)10
max: 1.1111 = (25-1) / 24 = 1.9375
Q0.7 à rule of thumb: 0 ≤ X < 1 (K=0)
min: .0000000 = (0)10
max: .1111111 = (27-1) / 27 = 0.9921875
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 Signed
Fixed-Point Representation

ECE 448 – FPGA and ASIC Design with VHDL 20

Two's Complement Notation
N total bits

X = xK-1 xK-2 … x1 x0 . x-1 x-2 … x-L

K integer bits L fractional bits

K -1
K-2

X = xK-1 ･ X =+
(-2K-1) å x ×2
i =- L
i
i

• K integer bits, L fractional bits

• More integer bits, the larger the maximum representable value
• Larger the L, the greater the precision
• Notation QK.L
• K = number of integer bits
• L = number of fractional bits
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Two's Complement Examples

Q7.0 examples:
positive: 0100101. = 3710
negative: 1001011. = -64 + 8 + 2 + 1 = (-53)10
Q2.3 examples:
positive: 01.001 = 9/8 = (1.125)10
negative: 11.100 = (-16+8+4)/8 = (-0.5)10
Q1.4 examples:
positive: 0.1001 = 9/16 = (0.5625)10
negative: 1.1100 = (-16+8+4)/16 = (-0.25)10

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Maximum Representable Range
• QK.L signed number has decimal range:
• Minimum: -2K-1
which is obtained when xi=1 for i=K-1 and xi=0 otherwise
• Minimum value is the largest negative value
• Maximum: 2K-1-2-L = (2N-1-1) / 2L
which is obtained when xi=0 for i=K-1 and xi=1 otherwise
• Maximum value is the largest positive value
• Exact representable range: -2K-1 ≤ X ≤ 2K-1-2-L
• Range is asymmetric
• Rule of thumb: range of number X in QK.L notation
• -2K-1 ≤ X < 2K-1
• The number of integer bits K largely determines the maximum
representable range

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Two's Complement Maximum Representable Range
Examples

Q7.0 à Rule of thumb -64 ≤ X < 64 (K = 7)

minimum: 1000000. = (-64)10
maximum: 0111111. = (63)10
Q2.3 à Rule of thumb -2 ≤ X < 2 (K= 2)
minimum: 10.000 = (-2.0)10
maximum: 01.111 = 15/8 = (1.875)10
Q1.4 à Rule of thumb -1 ≤ X < 1 (K= 1)
minimum : 1.0000 = (-1.0)10
maximum: 0.1111 = 15/16 = (0.9375)10

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Two's Complement in a nutshell
• Values starting with '0' are non-negative
• Values starting with '1' are negative
• To obtain decimal value, invert all bits, add LSB, mod by 2K
• Example Q4.0: i.e. 1110 = -(0001 + 0001) mod 24 = -0010 = (-2)10
• Example Q4.2: i.e. 11.00 = -(00.11 + 00.01) mod 22= (-01.00) = (-1)10
• The decimal value 0 is not redundant
• Can only be represented by all zeros, i.e. 0000
• For a two's complement number QK.L
• Exact representable range: -2K-1 ≤ X ≤ 2K-1-2-L
• Range is asymmetric

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 Fixed-Point Representation
in VHDL-93

ECE 448 – FPGA and ASIC Design with VHDL 26

A Word on Notation in VHDL
N total bits

K -1
X = å x ×2
i =- L
i
i
X = xK-1 xK-2 … x1 x0 . x-1 x-2 … x-L

K integer bits L fractional bits

VHDL: x(N-1) VHDL: x(0)

• In VHDL-93, we use unsigned(N-1 downto 0) to represent

an unsigned QK.L number and signed(N-1 downto 0) to
represent a signed QK.L number, where N=K+L
• So x(N-1) in VHDL refers to the digit xK-1 and
x(0) in VHDL refers to the digit x-L
• The VHDL designer must keep track of the binary point
(via comments usually)
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 Fixed-Point Representation
in VHDL 2008

ECE 448 – FPGA and ASIC Design with VHDL 28

Subsequent versions of VHDL

• IEEE-1076 1987
• IEEE-1076 1993 ← most commonly
supported by CAD tools
• IEEE-1076 2000 (minor changes)
• IEEE-1076 2002 (minor changes)
• IEEE-1076 2008 ← supported by the
new generation of CAD tools, such as
Xilinx Vivado

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Example:

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 Basic Fixed Point Operations
-- Std libraries
library ieee;
use ieee.std_logic_1164.all;

-- Fixed point libraries

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

Because not all features of VHDL 2008

are supported in the standard ieee library

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 Basic Fixed Point Operations
entity Fixed_Test is
Port (
A_F : in sfixed(3 downto -28);
B_F : in sfixed(3 downto -28);
OPCODE : in std_logic_vector(1 downto 0);
S_F : out sfixed(3 downto -28)
);
end Fixed_Test;

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 Basic Fixed Point Operations
architecture Dataflow of Fixed_Test is
signal ADD_F : sfixed(4 downto -28);
signal SUB_F : sfixed(4 downto -28);
signal MUL_F : sfixed(7 downto -56);
begin
-- Addition :
-- Addition between 2 Fixed point number, each Q4.28
will
-- yield a number that is Q5.28
ADD_F <= A_F + B_F;

-- Subtraction
-- Subtraction between 2 Fixed point numbers, each
with
-- Q4.28 gives a Q5.28 number
SUB_F <= A_F - B_F;

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 Basic Fixed Point Operations
-- Multiplication
-- Multiplication between 2 Fixed point numbers, each
with
-- Q4.28 gives Q8.56 number as result
MUL_F <= A_F * B_F;

-- Truncate the results to show the numbers as Q4.28

with OPCODE select
S_F <= ADD_F(3 downto -28) when "01",
SUB_F(3 downto -28) when "10",
MUL_F(3 downto -28) when "11",
to_sfixed(0, 3, -28) when others;

end Dataflow;

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 Setting the Representation
for Display During Simulation

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 Setting the Representation
for Display During Simulation

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Basic Fixed Point Operations
Simulation
Addition

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Basic Fixed Point Operations
Simulation
Subtraction

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Basic Fixed Point Operations
Simulation
Multiplication

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 Important Recommendations!
For Vivado 2019.1, in order to use the types ufixed and sfixed:

• Include in your project special packages to be provided

on the course web page for Lab 5
fixed_float_types_c.vhd
fixed_pkg_c.vhd

• Set the library to which these packages should be compiled

to ieee_proposed

• Set the type of all project files to vhdl 2008

• Include at the top of a VHDL file using ufixed or sfixed

• library ieee_proposed;
• use ieee_proposed.fixed_pkg.all;
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 Single iteration of the Julia fractal set
calculations

• All the fixed-point inputs and the outputs have to

be represented as Q4.28 signed fixed-point
numbers.
• The calculations to implement are as follows
zx_o = zx2 – zy2 + zx + cx
zy_o = 2·zx·zy + zy + cy
overflow = 1 if (zx_o2 + zy_o2 >= 4) else 0

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 Single iteration of the Julia fractal set
calculations

The inputs and outputs of the module can be

defined as follows:
• zx : Signed Fixed-Point input
• zy : Signed Fixed-Point input
• zx_o : Signed Fixed-Point output
• zy_o : Signed Fixed-Point output
• overflow : std_logic output
The Generics of the module can be defined as
• cx : Signed Fixed-Point
• cy : Signed Fixed-Point

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