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Graded channel architecture: the solution for misaligned DG FD SOI n-

MOSFETs

Article  in  Semiconductor Science and Technology · June 2008

DOI: 10.1088/0268-1242/23/7/075041

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Semicond. Sci. Technol. 23 (2008) 075041 (14pp) doi:10.1088/0268-1242/23/7/075041

Graded channel architecture: the solution

for misaligned DG FD SOI n-MOSFETs
Rupendra Kumar Sharma, Ritesh Gupta, Mridula Gupta and R S Gupta1
Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi
South Campus, New Delhi 110021, India
E-mail: [email protected] and [email protected]

Received 22 November 2007, in final form 10 April 2008

Published 4 June 2008
Online at stacks.iop.org/SST/23/075041

Abstract
A double-gate (DG) metal-oxide semiconductor field-effect transistor (MOSFET) is the
leading contender for a deep submicron MOSFET to reduce gate oxide tunneling. One major
issue of concern in a DG-MOSFET is the alignment between the top and bottom gates that
influences the device performance, especially in a subthreshold regime. Use of graded channel
(high–low, low–high and low–high–low doping) architecture somehow reduces this gate
misalignment effect and hence has been analyzed in the present paper through intensive
simulation and analytical analysis. The model uses the conformal mapping transformation
approach to include the fringing field effect that arises at the bottom gate electrode in the
ungated region and is used to predict the surface potential, electric field, threshold voltage,
sub-threshold slope and drain-induced barrier lowering effects. The results so obtained have
been verified with 3D numerical simulation using an ATLAS 3D device simulator.

Introduction channel effects (SCEs), sub-threshold slope, drain-induced

barrier lowering (DIBL), etc. The bottom gate can either
With scaling, process imperfection is becoming a major shift to the source side (DGD) or to the drain side (DGS),
concern in maintaining the reliability of devices [1–14]. As so that part of the channel region is controlled only by one
CMOS scaling approaches the limit imposed by gate oxide gate. The nonideal effects, introduced by gate misalignment,
tunneling, the double-gate (DG) metal-oxide semiconductor can emerge either from the nonoverlap region or from the
field-effect transistor (MOSFET) is becoming the subject of overlap region. The bottom channel of the device under a
intense very large-scale integration (VLSI) research, owing to nonoverlap gate region is weakly controlled by the bottom
its ability to be scaled to the shortest channel length possible gate electrode through a fringing electric field. This weakly
for a given gate oxide thickness [15]. A DG-MOSFET scaled controlled region of the bottom channel introduces large
beyond the 100 nm regime is a promising CMOS device series resistance due to fewer inversion carriers and hence
for analog applications, subjected to an ideal sub-threshold affects device operation. On the other hand, the overlapped
swing (S ≈ 60 mV/decade), lower output conductance region introduces additional gate leakage current through
and higher drive current [16]. In addition, DG structures direct tunneling. The sub-threshold characteristics are seen
with two independent gates allow great functional flexibility to degrade as the misalignment increases. This is because of
[17–20]. One of the major issues with the DG-MOSFET is the reduced total gate capacitance in comparison to the drain
its susceptibility to process variation that affects the eventual capacitance with an increase in misalignment. This degraded
circuit performances [21]. The most significant concern electrostatic control has more influence on Ioff than Ion, thereby
among the various causes that give rise to variation in the showing diminished channel controllability by the gates. In
double gate device performance is the misalignment between terms of short-channel effects, aligned transistors exhibit the
the top and bottom gates. best control, while highly misaligned MOSFETs operate like
The misalignment between the gates would affect several a single gate. Furthermore, ‘laterally asymmetric channel’
device properties of DG-MOSFETs, especially the short devices also known as graded channel (GC) MOSFETs, have
been reported [22–25], in order to overcome problems such
1 Corresponding author. as hot electron degradation, threshold voltage roll-off and

0268-1242/08/075041+14$30.00 1 © 2008 IOP Publishing Ltd Printed in the UK

Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

parasitic bipolar effects, exhibited by uniformly doped (UD) Poisson equation using the Sun and Kuo approach [26], and
devices. The key features behind these enhancements in the are given by
GC architecture is less controllability of the lightly doped   A1i
region in comparison to the highly doped region, and the well- ψbi (y) = U1i exp( A0i y) + U2i exp(− A0i y) − , (3)
A0i
known fact that all the negative effects, i.e. hot carrier effects,  
arise at the drain end. Thus, a lightly doped region toward the ψsi (y) = U3i exp( A0i y) + U4i exp(− A0i y) − Di , (4)
drain end can provide an effective means to eliminate all the where
2κSi
 
negative effects. Misalignment effects have been chosen in t + εεoxsi tsi + tox1
tox2 ox2
the lightly doped region to enhance the device performance. A0i =   (5a)
tsi2 1 + 2εεoxsi ttox1
Intensive simulations and analytical analysis have been si

carried out in the present paper with high–low (H–L), low–      

2
tox2 + εεox tsi +tox1 VG + tox1 + εεox tsi φf 2 +2φf 1
A1i = κSi qN −
tox2
high (L–H) and low–high–low (H–L–H) doping profiles to i si   si
εsi 2
tsi 1+
2εsi tox1
εox tsi
analyze the effect of the graded channel architecture on the
DG FD silicon-on-insulator (SOI) n-MOSFET, considering (5b)
the misalignment of the bottom gate on both source and drain

     φf 1
sides. The model uses a conformal mapping transformation 1
tox2
σ1 1 + 2εsi
εox tsi
ψbi (y) + 1 − ttox2 VG + φf 2 − tox1
approach [26] to include the fringing field effect arising at Di =  1 ox1

+ ε2ε si
the bottom gate electrode in the ungated region. Moreover, to tox1 ox tsi

analyze the effect of the graded channel architecture, analytical (5c)

formulation of the device based on considering the uniformity such that U1i , U2i , U3i and U4i are the coefficients to
of the potential and electric field at the interface has been be determined using the boundary conditions as shown in
adopted. Surface potential, electric field, threshold voltage, figure 1 and are given in the appendix. κ Si is a parameter
sub-threshold slope and DIBL effects have been evaluated, and that relates the derivative of a lateral electric field at any depth
the results so obtained have been verified using the ATLAS in the thin film to the derivative of a lateral electric field at the
3D device simulator [27]. front Si–SiO2 interface [28].
Similarly for region III, the front surface potential (ψ s3)
Theoretical considerations and the back surface potential (ψ b3) are obtained and are given
by the following equations:
γ 
The basic device structure of the GC DG-SOI n-MOSFET, ψb3 (y) = g1 exp (y − Lm )
as shown in figure 1, consists of a silicon film of thickness k
 γ  B
tsi = 60 nm, having p-type channel impurity concentrations in + g2 exp − (y − Lm ) +
1
, (6)
the high- and low-doped regions of N1 and N2 with lengths L1 k B0
and L2 (L1:L2 = 1:1) respectively, with oxide on both sides, of γ 
equal thickness (tox1 = tox2 = 7 nm). Poly-silicon gates, Npoly ψs3 (y) = g3 exp (y − Lm )
(=1.65 × 1019 cm−3), of length L (=200 nm), have been used.  γk 
Misalignment has been considered at the bottom interface of + g4 exp − (y − Lm ) + D3 , (7)
k
length ma. The effects of high–low and low–high doping where
profiles have been analyzed by dividing the channel into three 
γ = −B0 , B0 = 2κS2 k 2 α0 ,
regions, either using a high/low/gate misaligned region or a 
low/high/gate misaligned region. qN2
B1 = κS2 k 2 − 2β0 ,
εsi
ma
Front surface potential and back surface potential k=   t +t  ,
sinh cosh−1 ox2tox2 g2
The 2D potential distribution can be obtained by solving the
  B1  t (y)   φf 1
2D Poisson equation:
1
t (y)
σ2 1 + 2εεsioxtt(y) B
+ 1 − t
VG − φ f 2 + tox1
D3 = si
0 1
ox1
.
∂ 2 ψ(x, y) ∂ 2 ψ(x, y) qNi tox1
+ ε2ε si
ox tsi
2
+ 2
= , (1)
∂x ∂y εSi The coefficients g1 , g2 , g3 and g4 have been evaluated using
where εSi is the silicon permittivity, q is the electronic charge the boundary conditions (figure 1) and are given in the
and ψ(x, y) is the 2D potential distribution in the silicon thin appendix. σ 2 is an empirical correction factor to account
film and for the nonsymmetrical structure in the ungated region [26].

 The analysis as carried out in the present paper is
N1 , for 0
y
L1
Ni = , (2) applicable for uniformly doped architecture (N1 = N2), for
N2 , for L1
y
L1 + L2
high–low-doped architecture (N1 > N2), for low–high-doped
i = 1 for a highly doped and i = 2 for a lightly doped architecture (N2 > N1) and also for low–high–low-doped
region. Using boundary conditions mentioned in figure 1, architecture. The low–high–low-doped architecture can be
the analyses for regions I and II are the same except for the performed by splitting the channel into four different regions:
doping concentration. The front surface potential (ψ si) and three for different doping concentrations and the fourth for an
the back surface potential (ψ bi) are obtained by solving the ungated misalignment region.

2
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

ma ma
(a) DG SOI (b) DGD SOI (c) DGS SOI

Potential
VG & Electric
VS VD flux is
continuous
at the
interfaces
tox tox1
(tsi, 0)
x
L = 0.2 m
N +
N + L1 + L2 = L
I II III
Source
N2 ma Drain tsi L1: L2 = 1:1
N1
Lm = L - ma
(0, 0) y
tox2

Vbi Lm Vbi+Vds
L

VG
L1 L2

−
∂ψ i ( x, y )
∂x
C
[
= ox 2 VG + φ f 2 −ψ bi ( y )
ε si
] −
∂ψ 3 ( x, y )
=
ε ox
[
VG + φ f 2 − ψ b3 ( y ) ]
x =0 ∂x x = 0 ε si t ( y )

−
∂ψ i ( x, y )
∂x
C
[
= ox1 ψ si ( y ) − VG − φ f 1
ε si
] −
∂ψ 3 ( x, y ) C
[
= ox1 ψ s 3 ( y ) − VG − φ f 1 ]
x =t si ∂x x =ti ε si

Figure 1. Schematic structure of a GC DG MOSFET with boundary conditions and gate misalignment of ma for L = 0.2 µm, L1:L2 = 1:1.

Results and discussion IDS by one decade and extracted at VDS = 50 mV. IDS(max) and
gm(max) are defined as the maximum value of the drain current
The analytical results have been proposed only for the and the transconductance at VDS = 50 mV. For a generalized
subthreshold region of device operation, i.e. for calculation analysis, a wide range of gate misalignment (0–50% for UD
of the surface potential, whereas the device characteristics architecture and 0–62.5% for GC architecture) on both sides,
have been simulated for the entire region of operation. The i.e. source and drain sides, has been considered.
drain current curves were obtained from 3D simulations
that include a field-dependent mobility (FLDMOB) model Uniformly doped misaligned DG FD SOI n-MOSFET
and concentration-dependent mobility (CONMOB). The
simulated results for the threshold voltage (Vth), drain-induced For uniformly doped architecture, the variation of threshold
barrier lowering (DIBL), subthreshold slope, maximum voltage with gate misalignment has been explained through
value of drain current (IDS(max)) and maximum value of IDS–VGS curves at different drain voltages, considering the
transconductance (gm(max)) are tabulated in tables 1–4. The gate misalignment on both source and drain sides as shown
threshold voltage is obtained from IDS–VGS characteristics and in figures 2(a) and (b). From figure 2(a), for the zero gate
is considered to be that value of gate voltage for which the drain misalignment case (ma = 0%), the device threshold voltage
current approaches 10−7 A µm−1; DIBL has been calculated is found to be 0.2814 V (table 1). With the increase in
as differences of threshold voltage at VDS = 50 mV and misalignment by 12.5% toward the drain side (DGD), the
1.0 V and the subthreshold slope is defined as the change in threshold voltage increases by 0.8%. This threshold voltage
gate voltage VGS required to reduce the subthreshold current value increases by 11.3% with the increase in misalignment

3
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

Table 1. Device parameters for UD DG devices analyzed in the present work for L = 0.2 µm. Threshold voltage was defined as the gate
voltage at 10−7 A µm−1 drain current. DIBL was calculated by taking the threshold voltage at VDS = 50 mV and 1.0 V.
Subthreshold slope
Channel Vth (V) DIBL (mV/decade) IDS(max) (µA) gm(max) (µS)
doping (cm−3) Misalignment ma DGD DGS DGD DGS DGD DGS DGD DGS DGD DGS
NA = 5 × 1017 0% 0.2814 0.2814 34.11 34.11 64.37 64.37 42.7 42.7 72.2 72.2
12.5% 0.2836 0.2848 37.47 32.53 64.60 64.65 32.2 31.4 53.1 52.1
25% 0.3133 0.3142 57.16 30.74 67.17 66.63 22.3 22.7 37.9 38.3
50% 0.4212 0.4257 98.11 26.0 70.15 70.82 19.4 19.6 41.0 41.5

Table 2. (a–b) Device parameters for GC (high–low doping profile) DG devices analyzed in the present work for L = 0.2 µm, L1:L2 = 1:1.
Subthreshold slope
Channel Vth (V) DIBL (mV/decade) IDS(max) (µA) gm(max) (µS)
doping (cm−3) Misalignment ma DGD DGS DGD DGS DGD DGS DGD DGS DGD DGS
(a)
N1 = 5 × 1017 0% 0.1868 0.1868 29.35 29.35 70.22 70.22 66.5 66.5 109 109
N2 = 5 × 1015 12.5% 0.1868 0.1958 30.09 30.32 70.22 71.24 63.1 46.5 105 74.0
25% 0.1869 0.2335 31.62 33.16 70.18 72.13 58.2 36.7 99.9 60.2
50% 0.200 0.3475 42.95 46.84 70.15 75.85 43.3 31.0 70.8 61.5
62.5% 0.2584 0.3897 52.63 55.47 69.84 81.07 35.3 28.5 59.7 61.1
(b)
N1 = 5 × 1017 0% 0.1918 0.1918 26.95 26.95 69.06 69.06 62.5 62.5 103 103
N2 = 5 × 1016 12.5% 0.1919 0.2027 27.69 30.21 69.06 70.00 58.8 39.5 99.1 64.2
25% 0.1920 0.2379 29.06 30.63 69.00 70.99 52.5 34.4 91.6 56.7
50% 0.2135 0.3540 44.95 46.32 68.96 75.32 36.9 29.1 59.5 58.3
62.5% 0.2707 0.3990 50.22 51.79 68.87 81.06 32.6 26.7 56.1 57.9

Table 3. Device parameters for GC (low–high doping profile) DG devices analyzed in the present work for L = 0.2 µm, L1:L2 = 1:1.
Subthreshold slope
Channel Vth (V) DIBL (mV/decade) IDS(max) (µA) gm(max) (µS)
doping (cm−3) Misalignment ma DGD DGS DGD DGS DGD DGS DGD DGS DGD DGS
N1 = 5×10 15
0% 0.1845 0.1845 101.6 101.6 70.97 70.97 66.6 66.6 109 109
N2 = 5×1017 12.5% 0.1909 0.1845 113.2 101.6 71.87 70.97 47.7 63.0 74.9 105
25% 0.2302 0.1846 152.2 101.5 73.18 70.91 36.4 57.7 59.2 98.7
50% 0.3443 0.1993 169.7 99.27 76.10 70.66 31.0 42.6 61.2 70.0
62.5% 0.3872 0.2574 171.8 98.81 81.59 70.19 28.6 35.7 61.0 60.6

Table 4. (a–b) Device parameters for GC (low–high–low doping profile) DG devices analyzed in the present work for L = 0.2 µm,
L1:L2:L3 = 1:2:1.
Subthreshold slope
Channel Vth (V) DIBL (mV/decade) IDS(max) (µA) gm(max) (µS)
doping (cm−3) Misalignment ma DGD DGS DGD DGS DGD DGS DGD DGS DGD DGS
(a)
N1 = 5 × 1015 0% 0.2279 0.2279 180.8 180.8 71.81 71.81 61.1 61.1 102 102
N2 = 5 × 1017 12.5% 0.2280 0.2280 181.6 181.0 71.82 71.80 57.3 57.1 97.8 97.1
N3 = 5 × 1015 25% 0.2332 0.2335 193.1 184.3 71.83 71.52 45.8 44.9 78.0 76.7
50% 0.3384 0.3488 247.4 240.6 72.06 71.44 30.2 30.1 56.9 57.5
(b)
N1 = 5 × 1016 0% 0.2325 0.2325 41.58 41.58 65.47 65.47 57.9 57.9 96.8 96.8
N2 = 5 × 1017 12.5% 0.2327 0.2327 42.84 41.76 65.55 65.50 54.3 54.2 92.7 92.4
N3 = 5 × 1016 25% 0.2386 0.2394 52.21 42.21 66.08 66.03 41.6 40.8 70.3 69.3
50% 0.3457 0.3557 88.11 42.81 68.94 69.14 28.3 28.3 53.9 54.6

by 25% and further increases by 49.7% with an increase in along the channel (figures 3(a) and (b)), and transmission of
misalignment by 50%. this effect to the upper gate has also been studied through
The cause of this threshold voltage variation has been the variation of the front surface potential along the channel
studied through the variation of the back surface potential (figure 3(c)). Analytical and simulated results are compared

4
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

50
UD DG (a)
UD DGD 70
UD DGS
++ UD SG m a = 0%
40 60

50
m a = 25%
30 m a = 12.5%
I DS ( µ A)

gm (µ S)
40

m a = 50%

20 30

20

10 I DS

L = 200 nm
10
V DS = 50m V
NA = 1017 cm -3
0 0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
V GS (V)

600
UD DG (b)
m a = 0% 600
UD DGD
500 UD DGS
++ UD SG m a = 12.5%
500
L = 200 nm
400 V DS = 1.0 V
m a = 25%
NA = 1017 cm -3 400
g m (µ S )
I D S ( µ A)

300
m a = 50% 300

200
200

100 100

I DS
0 0
0.2 0.4 0.6 0.8 1
V GS (V)

Figure 2. IDS–VGS and gm–VGS curves for UD DG SOI for different gate misalignments at (a) VDS = 50 mV, (b) VDS = 1.0 V.

in figures 3(a)–(c) and are found to be in good agreement of the minimum channel potential and increased threshold
that proves the validity of our model. DIBL effects voltage of the device.
and subthreshold swing studied through 3D simulation are The misalignment at the source side (DGS) increases the
tabulated in table 1. Threshold voltage is usually controlled misalignment effect in comparison to the DGD case; that is,
by minima of the channel potential and for 12.5% gate for ma = 12.5% and 50%, the threshold voltage increases by
misalignment the minimum channel potential is seen to occur 11.52% and 50.67% respectively as can be seen in figures 2(a),
at a normalized channel length of 0.875. However, as we 3(a) and table 1. This is due to the reduction in the fringing
increase the misalignment to 25% the minimum channel field effect that arises at the source side in the absence of drain
potential occurs at a normalized channel length of 0.75, much voltage. The effect of drain voltage can further be explained
closer to the center of the channel. Now, shifting the minimum through figures 2(b) and 3(b). The effect of misalignment
channel potential toward the center results in a decreased value variation decreases in the DGD case with the increase in drain

5
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

0.8
Line - Analytical (a)
m a = 0%
0.6 m a = 12.5% Symbol - simulated
m a = 25% L = 200nm

Back S urface Po tential (V )

0.4 ∗ ∗ m a = 50% NA = 10 17 cm -3
VDS = 50mV
0.2

-0.2

-0.4
DGS DGD
-0.6
Fig. 3(a)
0 0.2 0.4 0.6 0.8 1
Normalized Channel Length (x/L)
2
m a = 0% L = 200nm (b)
Line - Analytical
m a = 12.5% NA = 10 17 cm -3 Symbol - simulated
m a = 25% VDS = 1.0V
1.5
∗ ∗ m a = 50%
Back Surface Potential (V)

0.5

DGS DGD

-0.5
0 0.2 0.4 0.6 0.8 1
Normalized Channel Length (x/L)
0.7
m a = 0% L = 200nm (c)
Line - Analytical
m a = 12.5%
NA = 10 17 cm -3 Symbol - simulated
0.6 m a = 25% VDS = 50mV
∗ ∗ m a = 50%
Front Surface Po tential (V)

0.5

0.4

0.3

0.2

0.1
DGS DGD
0
0 0.2 0.4 0.6 0.8 1
Normalized Channel Length (x/L)

Figure 3. Back surface potential variation with lateral direction for UD DG SOI for VGS = 0 V, (a) VDS = 50 mV, (b) VDS = 1.0 V (c). Front
surface potential variation with lateral direction for UD DG SOI for VDS = 50 mV.

6
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

70
GC DG m a = 0% (a)
∗ ∗ GC DGD 100
GC DGS
60
++ GC SG
m a = 12.5%
m a = 25%
50 80

m a = 50%
40
60
I D S ( µ A)

g m (µ S )
30
m a = 62.5%
40
20

L = 200nm 20
10 V DS = 50m V
I DS
N1 = 1017 cm -3
N2 = 1015 cm -3
0 0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
V GS (V)
70
GC DG (b)
m a = 0%
∗ ∗ GC DGD 100
60 GC DGS
++ GC SG

50 80
m a = 25%
m a = 12.5%

40
I DS ( µ A)

m a = 50% 60 gm (µ S)

30

m a = 62.5%
40

20
I DS
20
10 L = 200nm
V DS = 50m V
N1 = 1017 cm -3
N2 = 1016 cm -3
0 0
0.1 0.3 0.5 0.7 0.9
V GS (V)

Figure 4. IDS–VGS and gm–VGS curves of GC DG SOI using a high–low doping profile for different gate misalignments at VDS = 50 mV,
L = 200 nm, L1:L2 = 1:1. (a) N1 = 5 × 1017 cm−3, N2 = 5 × 1015 cm−3; (b) N1 = 5 × 1017 cm−3, N2 = 5 × 1016 cm−3.

voltage, whereas, in the DGS case, the effect of misalignment ON state characteristics. This is because, in the misalignment
variation remains unaffected by the increase in drain voltage. region, inversion charge emerges as the outcome of the fringing
Figures 2(a) and (b) also show the effect of field and not by the normal gate field action. The effect of
misalignment under ON conditions. The maximum values the normal gate field in creating the inversion charge is more
of transconductance (gm) and drain current (IDS) for ma = 0% significant in comparison to what emerges as a result of the
are obtained to be 72.2 µS and 42.7 µA respectively, and are fringing field. This leads to reduction in inversion charge
tabulated in table 1. With the increase in misalignment toward density in the misaligned region that accounts for reduced gm
the drain side (DGD) by 12.5%, gm and IDS decrease by 26.45% and IDS in the DGD structure. gm and IDS further reduce with an
and 24.59% respectively. This shows that although there is increase in misalignment by 25% due to an increase in the ratio
very little variation in threshold voltage due to misalignment, of misalignment to normal channel length. It is noted from the
the increase in misalignment causes significant variation in figure that a device with a 25% misaligned DG structure acts as

7
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

0.8
L = 200nm Line - Analytical
V DS = 50m V Symbol - simulated
0.6 N1= 1017 cm -3
N2=5 015 cm -3

Back S urface Po tential (V )

0.4

0.2

DGD
0

m a = 0%
-0.2
m a = 12.5%
m a = 25%
-0.4
∗ ∗ ma = 50%
DGS °° m a = 62.5%
-0.6
0 0.2 0.4 0.6 0.8 1
Normalized Channel Length (x/L)
Figure 5. Back surface potential variation with lateral direction for a GC (high–low doping profile, i.e. N1 = 5 × 1017 cm−3, N2 = 5 ×
1015 cm−3) DG SOI for VDS = 50 mV, VGS = 0 V.

a single gate device. Here, also, the misalignment at the source in misalignment by 62.5%. While comparing the effect to
side (DGS) leads to a slight increase in the misalignment effect, a uniformly doped structure, it is found that these values are
as for ma = 12.5% and ma = 25%, gm and IDS are degraded by much less, even for 62.5% misalignment in a retrograde doping
27.83% and 47.51% and 26.46% and 46.84% respectively, and profile. We cannot achieve a 49.7% increase in the threshold
can be seen in figures 2(a) and 3(a) and table 1. Furthermore, voltage as we have obtained with uniformly doped architecture
the effect of drain voltage on gate misalignment has a similar for 50% misalignment. This means that the retrograde doping
effect under the ON condition as with device under the OFF profile having high–low combination is more beneficial than a
condition. uniformly doped profile for the DGD case. However, it is seen
that the higher the difference between high–low doping, i.e.
High on low-doped graded channel misaligned DG FD SOI doping difference between case 1 and case 2, the higher are
n-MOSFET the enhancements offered by it. This is because the threshold
voltage is controlled by minima of the channel potential and,
Drain side misalignment (DGD). High–low-doped graded for this structure, it is totally governed by the highly doped
channel architecture has been studied in the present subsection region and misalignment occurs in the lightly doped region.
to reduce the effect of gate misalignment on the drain side. Figure 5 shows almost negligible variation in potential profiles
This effect has been studied through variation of drain current for 25% misalignment. As misalignment increases up to 50%,
with gate voltage as shown in figures 4(a) and (b) for various the lightly doped region is completely misaligned and leads to
misaligned structures and for different doping concentrations slight variation in the minimum surface potential and threshold
in the low-doped region. The drain current variation is also voltage of the device. For ma > 50%, i.e. 62.5% in the
compared with uniformly doped architecture to predict the highly doped region, abrupt variation in the minimum surface
enhancements in the device performance. From figures 4(a) potential and threshold voltage of the device is seen.
and (b), for the zero misalignment case (ma = 0%), device Figures 4(a) and (b) also show the effect of
threshold voltages for two retrograde doping profiles, i.e. misalignment under ON conditions. The maximum values
case 1: N1 = 5 × 1017 cm−3, N2 = 5 × 1016 cm−3 and case 2: of transconductance (gm) and drain current (IDS) for ma = 0%
N1 = 5 × 1017 cm−3, N2 = 5 × 1015 cm−3, are found to are obtained to be 103 µS, 62.5 µA and 109 µS, 66.5 µA for
be 0.1918 V and 0.1867 V respectively and are tabulated in the two cases of retrograde doping profiles such that case 1:
table 2. With the increase in misalignment by 12.5% toward N1 = 5 × 1017 cm−3, N2 = 5 × 1016 cm−3 and case 2:
the drain side (DGD), the threshold voltage increases by 0.05% N1 = 5 × 1017 cm−3, N2 = 5 × 1015 cm−3 respectively and
in case 1 and 0% in case 2. These values increase by 0.1% and are tabulated in table 2. With the increase in misalignment
0.05% with the increase in misalignment by 25% and increase toward the drain side (DGD) by 12.5%, gm and IDS decrease
by 11.4% and 7.1% with the increase in misalignment by 50% by nearly 3.78%, 5.92% and 3.67%, 5.11% for the two cases
for the two cases, respectively. Further increases of 41.1% and respectively and with an increase in misalignment to 25% they
38.4% for the two cases respectively are seen in the increase decrease by 11.07%, 16.0% and 8.35%, 12.48% respectively.

8
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

70
GC DG m a = 12.5% (a)
m a = 0%
∗ ∗ GC DGD 100
60 GC DGS
m a = 25%
50 80

40 m a = 50%
I D S ( µ A)

60

g m (µ S )
30
40
20
V DS = 50m V
I DS 20
10 N1 = 1015 cm -3
N2 = 1017 cm -3
N3 = 1015 cm -3
0 0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
V GS (V)
70 100
L = 200 nm (b)
m a = 0%
VDS = 50m V
60 N1 = 10 16 cm -3
N2 = 10 17 cm -3 80
N3 = 10 16 cm -3 m a = 12.5%
50

60
40 m a = 25%

g m (µ S )
I D S ( µ A)

30 m a = 50% 40

20

20
10 I DS GC DG
∗ ∗ GC DGD
GC DGS
0 0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
V GS (V)

Figure 6. IDS–VGS and gm–VGS curves of GC DG SOI using a low–high–low doping profile for different gate misalignments at VDS =
50 mV, L = 200 nm, L1:L2:L3 = 1:2:1. (a) N1 = 5 × 1015 cm−3, N2 = 5 × 1017 cm−3, N3 = 5 × 1015 cm−3; (b) N1 = 5 × 1016 cm−3, N2 = 5 ×
1017 cm−3, N3 = 5 × 1016 cm−3.

For a misalignment of 50%, gm and IDS decrease by 42.23%, doped region and thus the misalignment in the low-doped
40.96% and 35.05%, 34.89% respectively for the given cases region will not be able to affect the device characteristics under
and further decreases of 45.53%, 47.84% and 45.22%, 46.92%, ON conditions much. Here, it is to be noted that degradation
respectively, occur with an increase in misalignment to 62.5%. in gm ceases as the gate misalignment touches or enters into
The effect of misalignment in the retrograde profile for the highly doped region, due to the elimination of the barrier
the ON state condition is again less in comparison to the between high and low doping profiles.
uniformly doped profile. However, the greater the difference Source side misalignment (DGS). The misalignment can
between high–low doping concentrations, the greater are occur either toward the source side or toward the drain
the enhancements in the device characteristics. These side. In the previous subsection, the effect of misalignment
enhancements are due to the fact that inversion charge, just like toward the drain side for a high–low doping profile has been
the threshold voltage of the device, is controlled by the highly studied and it is seen that the high–low combination can cause

9
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

N1= 1015 cm -3 GC DG L = 200nm

0.9
N2=5 017 cm -3 ∗ ∗ GC DGD V DS = 50m V
N3 = 1015 cm -3 GC DGS L1 : L2 : L3 = 1 : 2 : 1
0.7

B a c k S urfa c e Po te ntia l (V )
m a = 25%
0.5 m a = 0%
m a = 12.5%
0.3

0.1

-0.1

-0.3
m a = 50%
-0.5
0 0.2 0.4 0.6 0.8 1
Normalized Channel length (mm)
Figure 7. Back surface potential variation with lateral direction for GC (low–high–low doping profile, i.e. N1 = 5 × 1015 cm−3, N2 = 5 ×
1017 cm−3, N3 = 5 × 1015 cm−3) for VDS = 50 mV, VGS = 0 V.

severe degradation in the device performance compared to The effect of misalignment toward the drain side (DGD)
a uniformly doped structure. So, it becomes necessary to for a low–high doping profile has also been studied, and
investigate its effect on the misalignment toward the source the results are summarized in table 3. It is found from
side. Thus, in the present section, analysis has been carried the analysis that a low–high doping profile is the better
out on a high–low-doped graded channel device misaligned alternative for reducing the misalignment effect for the DGS
toward the source side (DGS). Variation of drain current with case, as it produces similar effects as introduced by a high–
gate voltage for various misaligned structures has been studied low doping profile for the DGD case. Although a low–high
in figure 4. From the drain current variation, it is seen that doping profile can aggravate the parasitic bipolar action and
the value of threshold voltage increases by 4.9%, 25.1%, impact ionization-associated phenomena in comparison to a
86.1% and 108.7% for gate misalignments of 12.5%, 25%, high–low doping profile, it is still considered because it can
50% and 62.5% respectively for the DGS case of a high–low produce similar effects as obtained using a uniformly doped
retrograde doping profile, and this has been listed in table 2, structure, with reduced source side gate misalignment effects,
i.e. more negative effects of the misalignment in comparison thereby making a low–high profile a better alternative for the
to a uniformly doped structure. This is because misalignment case of source side misalignment. Another profile, i.e. low–
occurs in the highly doped region, which controls the threshold high–low doping profile, can also be used to reduce the gate
misalignment effect together with improved hot carrier effects
voltage of the device and can be clearly understood from the
and is discussed in the following section of this paper.
variation of the minimum surface potential along the channel
as shown in figure 5.
Figures 4(a) and (b) also show that the effect of Low–high–low-doped graded channel misaligned DG FD
misalignment on gm and IDS occurs on the source side SOI n-MOSFET
(DGS) under ON conditions. The maximum values of gm The analysis shows that using low–high-doped combination
and IDS for ma = 0% are 103 µS, 62.5 µA and 109 µS, can cause enhancement/degradation in the device performance
66.5 µA for the two retrograde doping profiles case 1: in comparison to the uniformly doped architecture, when gate
N1 = 5 × 1017 cm−3, N2 = 5 × 1016 cm−3 and case 2: misalignment occurs toward the source/drain side and vice
N1 = 5 × 1017 cm−3, N2 = 5 × 1015 cm−3 respectively and versa for a high–low doping profile. Considering the fact that
are also listed in table 2. With the increase in misalignment we cannot predict to which side misalignment may occur, we
toward the source side (DGS) to 12.5%, gm and IDS decrease by propose to choose the lightly doped region at both source and
37.67% and 36.8%, and 32.11% and 30.08% respectively for drain sides irrespective of which side the gate misalignment
the two doping cases under consideration. It is seen that the can happen. The effect of gate misalignment on source and
misalignment effect increases, i.e. reduced maximum gm and drain sides has been studied through I–V characteristics, as
IDS in comparison to UD devices, when misalignment toward shown in figure 6, and surface potential profiles, as shown in
the source is considered. figure 7. DIBL effects and subthreshold swing have also been

10
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

0.7
UD DGD (a)
L = 200nm
GC DGD (High - Low ) V DS = 50m V
∗ ∗ GC DGD (Low - High)
+ + GC DGD (Low - High - Low ) m a = 0%
0.5
Back Surface Potential (V)
m a = 50%

0.3

0.1

-0.1
0 0.2 0.4 0.6 0.8 1
Normalized Channel Length (x/L)
0.7
L = 200nm UD DGS (b)
V DS = 50m V GC DGS (High - Low )
0.6 ∗ ∗ GC DGS (Low - High)
m a = 0% + + GC DGS (Low - High - Low )
0.5
Back Surface Potential (V)

m a = 50%
0.4

0.3

0.2

0.1

-0.1
0 0.2 0.4 0.6 0.8 1
Normalized Channel Length (x/L)
Figure 8. Comparison of back surface potential for different structures at constant (VGS–Vth), VDS = 50 mV for (a) DGD structure, (b) DGS
structure.

studied for a low–high–low doping profile and are listed in threshold voltage increases for the two cases by 0.09% and
table 4. 0.04% respectively. The threshold voltage increases by 2.6%
From figures 6(a) and (b), for the zero misalignment and 2.3% with the increase in misalignment to 25% and
case (ma = 0%), the device threshold voltage is found to be further increase by 48.6% and 48.5% respectively with the
0.2325 V and 0.2279 V (table 4) for the two cases of increase in misalignment to 50% for the given cases. It
retrograde doping profiles having L1 = 0.05 µm, L2 = is found that these values are much less up to ma = 25%,
0.1 µm, L3 = 0.05 µm and doping variations such that case 1: but approximately equal for ma = 50% in comparison to a
N1 = 5 × 1016 cm−3, N2 = 5 × 1017 cm−3, N3 = 5 × uniformly doped structure. This is because, in the case of
1016 cm−3 and case 2: N1 = 5 × 1015 cm−3, N2 = 5 × ma = 50% for a low–high–low doping profile, the
1017 cm−3, N3 = 5 × 1015 cm−3 respectively. With the increase misalignment region extends up to the point at which a highly
in misalignment to 12.5% toward the drain side (DGD), the doped region exist. So to reduce the misalignment effect, we

11
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al

have to choose the doping profile such that the misaligned these effects (parasitic bipolar action and impact ionization-
region always exists in the lightly doped region. This associated phenomena) remain unaffected in comparison with
means that the retrograde doping profile having low–high– a uniformly doped structure. Considering the fact that we
low combination is more beneficial than a uniformly doped cannot know on which side misalignment can occur, the low–
profile for both DGS and DGD cases. Moreover, for a low– high–low graded channel profile should be fabricated in order
high–low doping profile all the device characteristics show the to reduce/eliminate the gate misalignment effects in a DG FD
same behavior owing to the uniformity of the structure on both SOI n-MOSFET.
source and drain sides, except the applied drain voltage. For
two retrograde doping profiles, it can be seen that the greater Acknowledgment
the difference between high–low doping concentrations, the
greater are the enhancements in the device characteristics. The authors are grateful to the Defence Research and
These enhancements can be better explained through the back Development Organization (DRDO), Ministry of Defence,
surface potential distribution along the channel as shown in Government of India, for the necessary financial assistance.
figure 7.
Figures 6(a) and (b) also show the effect of misalignment
Appendix
under the ON condition. The maximum values of gm and IDS
for ma = 0% are obtained as 96.8 µS, 57.9 µA and 102 µS, The coefficients for the back surface potential are obtained by
61.1 µA for the two cases of retrograde doping profiles, solving equations (1)–(7) using boundary conditions shown in
case 1: N1 = 5 × 1016 cm−3, N2 = 5 × 1017 cm−3, N3 = 5 × figure 1, and are given as
1016 cm−3 and case 2: N1 = 5 × 1015 cm−3, N2 = 5 × 
√
1017 cm−3, N3 = 5 × 1015 cm−3, respectively, and are given γ A2
U1i = s1i exp(−n1i ) cosh(n2 ) cosh(n3 )
in table 4. With the increase in misalignment toward the drain k
√
side (DGD) to 12.5%, these values decrease by 4.24% and γ A0i
6.22% and 4.11% and 6.06% for the two cases and decrease by + A2 sinh(n2 ) sinh(n3 ) − sinh(n2 ) cosh(n3 )
k 
27.37% and 28.67% and 23.52% and 25.04% respectively with  
the increase in misalignment to 25%. They further decrease − A0i A2 cosh(n2 ) sinh(n3 )
by 44.32% and 51.12% and 44.22% and 50.57% respectively √ 
for the two cases under consideration with an increase in A2 γ
− s2 − F1i DR11 (A.1)
misalignment to 50%. This profile shows enhancements in k
comparison to UD devices in both DGS and DGD cases up to 
√
γ A2
25% gate misalignment. U2i = −s1i exp(n1i ) cosh(n2 ) cosh(n3 )
k
A comparative study between UD, high–low, low–high √
and low–high–low doped structures for both DGS and DGD γ A0i
+ A2 sinh(n2 ) sinh(n3 ) + sinh(n2 ) cosh(n3 )
cases has been studied at constant VGS–Vth in figures 8(a) and k 
(b). Various enhancements and differences among them can  
+ A0i A2 cosh(n2 ) sinh(n3 )
easily be seen through these variations.
√ 
A2 γ
− s2 − F1i DR11 (A.2)
Conclusion k

√
γ A2
A subthreshold analytical model has been proposed using g1 = −s2 cosh(n2 ) sinh(n1 )
the conformal mapping transformation approach, and the k
√
results thus obtained have been compared with ATLAS γ A0
+ A2 sinh(n2 ) sinh(n1 ) + sinh(n2 ) cosh(n1 )
3D device simulation to prove the validity of our model. k 
Intensive simulations and analytical work have been carried  
out in the present paper, using high–low, low–high and low– + A0 A2 cosh(n2 ) cosh(n1 )
high–low graded channel profiles under both OFF and ON   
conditions, to reduce the effect of gate misalignment in a − s1 A2 A0 exp(−n3 ) − h1 DR12 (A.3)
DG FD SOI n-MOSFET. In UD architecture, misalignment
causes degradation in device characteristics, i.e. variation in g2 = exp(n3 )[s2 − g1 exp(n3 )], (A.4)
threshold voltage, drain current and transconductance, while a
high–low doping profile causes reduction/elimination in gate where
misalignment effects on the drain side, it causes an increase A1i A1
in misalignment effects on the source side. To reduce the s1i = φf n + VS + , s1 = φf n + VS + ,
A0i A0
effect of source side misalignment, a low–high doping profile B1
can be used, but this causes an increase in the misalignment s2 = φf n + VD −
B0
effect toward the drain side. In comparison with a high– √ √
low doping profile, this profile aggravates the parasitic bipolar A0i Lm A0 Lm
action and impact ionization-associated phenomena, while n1i = , n1 = ,
2 2

12
Semicond. Sci. Technol. 23 (2008) 075041 R K Sharma et al
√ 
√
A2 Lm γ −γ A2
n2 = , n3 = ma g4 = s 2 cosh(n2 ) sinh(n1 ) + A2 sinh(n2 ) sinh(n1 )
2 k k
 
 √ 
γ A0  
B1 A3 − sinh(n2 ) cosh(n1 ) + A0 A2 cosh(n2 ) cosh(n1 )
h1 = exp(−n3 ) A2 A0 + cosh(n2 ) cosh(n1 ) k
B0 A2 

  
B1 A3 − s1 A2 A0 exp(n3 ) + exp(n3 )F14 DR12 , (A.8)
+ A2 + sinh(n2 ) sinh(n1 )
B0 A2
 
A1 A3

where
+ A2 A0 − cosh(n1 )
A0 A2 si = φf n + VS + Di
 √

F1i =
γ A2 A1i
−
A3
cosh(n2 ) cosh(n3 ) s3 = φf n + VD − D3
k A0i A2  √

 γ A2
A1i A3 = (D1 − D2 ) cosh(n2 ) cosh(n3 )
+ A2 − sinh h(n2 ) sinh(n3 ) F13
k
A0i A2
√
 + A2 (D1 − D2 ) sinh(n2 ) cosh(n3 )
+
γ A2 A3 B1
+ cosh(n3 ) √
k A2 B0 γ A2
+ (D2 + D3 ) cosh(n3 )
 k
γ 
DR11 = −2 cosh(n3 ) A2 sinh(n1 ) cosh(n2 )  
k F14 = A2 A0 (D2 + D3 ) cosh(n2 ) cosh(n1 )
  
+ A0 cosh(n1 ) sinh(n2 ) + A2 sinh(n3 ) + A2 (D2 + D3 ) sinh(n2 ) sinh(n1 )
 
   + A2 A0 (D1 − D2 ) cosh(n1 ) .
× A2 sinh(n1 ) sinh(n2 ) + A0 cosh(n2 ) cosh(n2 )

γ  References
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