Questions - Written Test - Mtech 2013 - 13th July
Questions - Written Test - Mtech 2013 - 13th July
TECH 2013
Entrance Exam
2) In a GaAs sample the electrons are moving under an electric field of 5 kV/cm and the carrier
concentration is uniform at 1016 cm-3. The electron velocity is the saturated velocity of 107 cm/s.
The drift current density is
3) A diode has reverse saturation current Is = 10-10 A and non-ideality factor η=2. If diode voltage is
0.9 V, then diode current is
(A) 11 mA (C) 83 mA
4) In bipolar transistor biased in the forward-active region the base current is IB = 50 µA and the
collector currents is IC = 2.7 mA. The α is
5) The following currents are measured in a uniformly doped npn bipolar transistor:
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M.TECH 2013
Entrance Exam
Determine the region of operation for the transistor shown in circuit in questions 6 and 7.
6)
7)
8) The chemical reaction involved in epitaxial growth in IC chips takes place at a temperature of
about
9) In the question a circuit and a waveform for the input voltage is given. The diode in circuit has
cutin voltage Vγ = 0. Choose the option for the waveform of output voltage vo .
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Entrance Exam
(A) (C)
(B) (D)
10) The circuit inside the box in figure contains only resistor and diodes. The terminal voltage vo is
connected to some point in the circuit inside the box. The largest and smallest possible value of vo
most nearly to is respectively
(A) 15 V, 6 V (C) 24 V, 6 V
(D) 15 V, -9 V
(B) 24 V, 0 V
11) For the circuit shown in figure, diode cutin voltage is Vin = 0. The ripple voltage is to be no more
than vrip = 4 V. The minimum load resistance that can be connected to the output is
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Entrance Exam
12) The common-emitter current gain of the transistor is β =75. The voltage VBE in ON state is 07. V.
IE , RC = ?
13) For the transistor in circuit shown in figure, β = 200. Determine the value of IE and IC for
VB = 0 V.
14) In the circuit, the transistor parameters are VTN = 17. V and Kn = 0.4 mA/ V2. If ID = 0.8 mA and
VD = 1 V, then value of resistor RS and RD are respectively
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Entrance Exam
15) If the transistor parameter are β =180 and Early voltage VA = 140 V and it is biased at
ICQ = 2 mA, the values of hybrid- π parameters gm, rπ and ro are respectively
16) A computer has the following negative numbers stored in binary form as shown. The wrongly
stored number is
(A) X + Y (C) XY
(B) X’ + Y’ (D) X’. Y’
18) The initial contents of the 4-bit serial-in-parallel-out right-shift, register shown in fig. is
0110. After three clock pulses are applied, the contents of the shift register will be
(A) 0 0 0 0 (C) 1 1 1 1
(B) 0 1 0 1 (D) 1 0 1 0
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Entrance Exam
19) A 4 bit modulo–6 ripple counter uses JK flip-flop. If the propagation delay of each FF is
50 ns, the maximum clock frequency that can be used is equal to
(A) 24 (C) 25
(B) 48 (D) 36
(A) 10 Hz (C) 40 Hz
(B) 160 Hz (D) 5 Hz
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Entrance Exam
23) If the contents of memory location 4A00H, 4A01H and 4A02H, are respectively A7H, 98H and
47H, then after the execution of program contents of memory location 4A02H will be respectively
25) x[n] and h[n] are given in the question. Compute the convolution y[n] = x[n] * h[n] and choose
correct option.
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Entrance Exam
27) Determine the time signal x(t) corresponding to given X(s) and choose correct option.
(A) (2e-2t + 2e-t sin2t - 2e-t cos2t) u(t) (C) (2e-2t + 2e-t cos2t - e-t sin2t) u(t)
(B) (2e-2t + 2e-t cos2t - 2e-t sin2t) u(t) (D) (2e-2t + 2e-t sin2t - e-t cos2t) u(t)
(A) (3n + (-1)n 2n+1) u[n] (C) (3n-1 + (-1)n 2n+1) u[n]
30) In a non-pipeline machine F, D, E takes 35 ns, 25 ns, 40 ns respectively. If instruction steps were
pipelined what should be the increase in throughput. Assume 5 ns overhead at each pipelined stage
and ignore the delay.
(A) Greater performance loss (C) Some functional unit is not fully pipelined
(B) Pipeline changes the order of read/write (D) Machine size is limited
access to operands
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M.TECH 2013
Entrance Exam
33) Width of address and data buses for a 512Kx 8 memory chip is _________
(A) To store address of TOS (Top Of Stack) (C) count the number of instructions
(B) To store address of next instruction to be (D) To store base address of the stack
executed
35) _________ makes the instruction execution faster in normal instruction cycle
36)
main ( )
{
static char *s[ ] = {“black”, “white”, “yellow”, “violet”};
char **ptr[ ] = {s+3, s+2, s+1, s}, ***p;
p = ptr;
**++p;
printf(“%s”,*--*++p + 3);
}
A. ak C. Error
B. dk D. ck
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M.TECH 2013
Entrance Exam
37)
int i,j;
for(i=0;i<=10;i++)
{
j+=5;
assert(i<5);
}
A. Compile time error C. 4
B. Runtime error D. 9
38)
main()
{
int i=-1;
+i;
printf("i = %d, +i = %d \n",i,+i);
}
A. error C. i = -2, +i = -1
B. i = 0, +i = 0 D. i = -1, +i = -1
39)
main()
{
char *str1="abcd";
char str2[]="abcd";
printf("%d %d %d",sizeof(str1),sizeof(str2),sizeof("abcd"));
}
A. 2 4 5 C. 1 3 4
B. 2 5 5 D. 2 6 5
40)
main()
{
char not;
not=!2;
printf("%d",not);
}
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M.TECH 2013
Entrance Exam
A. 2 C. 1
B. 0 D. error
41)
main()
{
int k=1;
printf("%d==1 is ""%s",k,k==1?"TRUE":"FALSE");
}
A. 1==1 is TRUE C. Compile error
42)
main()
{
int *j;
{
int i=10;
j=&i;
}
printf("%d",*j);
}
A. 10 C. 11
B. error D. 13
43)
main()
int i=5,j=6,z;
printf("%d",i+++j);
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Entrance Exam
A. 11 C. 20
B. 12 D. 21
A. One C. Three
B. Two D. None
A. Queue C. None
B. Stack D. Array
46) What is the maximum possible number of nodes in a binary tree at level 6?
A. 128 C. 32
B. 64 D. 26
48) When can you tell that a memory leak will occur?
A. When you do not free memory after C. When you declare variable larger then you
allocating needed
49) The searching technique that takes O (1) time to find a data is
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Entrance Exam
51) Which of the following method is most suitable for data-link layer of wireless networks
52) A bit string, 0111101111101111110, needs to be transmitted at the data link layer. What is the
string actually transmitted after bit stuffing? Flag is 01111110
a)011111100111101111100111110001111110
b) 0111111001111011111011111001111110
c) 011111100111101111110111111001111110
d) 011111100111101111100111110000000000
a) 802.11 c) 802.15.1
b) 802.3 d) 802.15
A. 32 bits C. 64 bits
C. To provide a means for the receiver to govern the amount of data sent by the sender.
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M.TECH 2013
Entrance Exam
56) The part of machine level instruction, which tells the central processor what has to be done, is
B) Address D) Flip-flop
58) To avoid the race condition, the number of processes that may be simultaneously inside their
critical section is
A. 8 C. 16
B. 1 D. 0
59) A system program that combines the separately compiled modules of a program into a form
suitable for execution
60) The strategy of allowing processes that are logically runnable to be temporarily suspended is
called
A. preemptive scheduling
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