Introduction: Memory Organization (Memory Hierarchy)

 Memory hierarchy in a computer system : Fig. 12-1

 Main Memory : memory unit that communicates directly with the CPU (RAM)
 Auxiliary Memory : device that provide backup storage (Disk Drives)
 Cache Memory : special very-high-speed memory to increase the processing
speed by making current programs and data available to the CPU at a very fast
rate .
» It is used to compensate the speed difference between main memory access time and
processor logic.
» While the I/O processor manages data transfer between auxiliary memory and main
memory, the cache memory is concerned with the data transfer between main memory
and CPU.

Auxiliary memory
Magnetic
tapes
Main
I/O processor
memory
Magnetic
disks

Cache
CPU
memory
Multiprogramming : Enables the CPU to process a number of independent program
concurrently.
Multiprogramming refers to the existence of two or more programs in different
parts of the memory hierarchy at the same time.
It is possible to keep all parts of CPU busy by working with several programs in
sequence.
In multiprogramming environment when one program is waiting for input or output
transfer there is another program ready to utilize the CPU.
 12-2 Main Memory
 Bootstrap Loader
 A program whose function is to start the computer software operating when
power is turned on Power-ON

 RAM and ROM Chips

FFFF:0000
 Typical RAM chip : Fig. 12-2 (Reset Point)

» 128 X 8 RAM : 27 = 128 (7 bit address lines) POST

Bootstrap Loader
 Typical ROM chip : Fig. 12-3 System Init. Bootstrap ROM
» 512 X 8 ROM : 29 = 512 (9 bit address lines) Boot ROM
INT 19
Chip select 1 CS1
Load Bootstrap Record
Chip select 2 CS2 (Track 0, Sector 0)
128¡¿ 8
Read RD 8 bit data bus
RAM
Load Operating System
Write WR (IO.SYS, MSDOS.SYS, COMMAND.COM)
7 bit address AD7

(a) Block diagram Chip select 1 CS1

CS1 CS2 RD WR Memory function State of data bus Chip select 2 CS2
0 0 ¿
¡ ¿
¡ Inhibit High-impedance
512¡¿ 8
8 bit data bus
0 1 ¿
¡ ¿
¡ Inhibit High-impedance ROM
1 0 0 0 Inhibit High-impedance
1 0 0 1 Write Input data to RAM
1 0 1 ¿
¡ Read Output data from RAM 9 bit address AD9
1 1 ¿
¡ ¿
¡ Inhibit High-impedance

(b) Function table

 Memory Address Map
 Memory Configuration : 512 bytes RAM + 512 bytes ROM
» 1 x 512 byte ROM + 4 x 128 bytes RAM
 Memory Address Map : it is a pictorial representation of assigned address space
for each chip in the system.
» Address line 10 9 8765 4321
 RAM 1 0 0 0x xx xxxx : 0000 - 007F
 RAM 1 0 0 1x xx xxxx : 0080 - 00FF
 RAM 1 0 1 0x xx xxxx : 0100 - 017F
 RAM 1 0 1 1x xx xxxx : 0180 - 01FF
 ROM 1 x xx xx xxxx : 0200 - 03FF
 The small x’s under the address bus lines, designate those lines that must be connected to the
address input in each chip.
 RAM chips have 128 bytes and needs 7 address lines.
 ROM chip have 512 bytes and needs 9 address lines
 Memory Connection to CPU :
 2 x 4 Decoder : RAM select (CS1)
» Address line 10
 RAM select : CS2
 ROM select : CS2 의 Invert

 RD : ROM CS1
 OE(Output Enable)
 Address bus CPU

16 - 11 10 9 8 7 - 1 RD WR Data bus

Decoder
3 2 1 0
CS1
CS2
128¡
¿ 8 Data
RD
RAM 1
WR
AD7

CS1
CS2
128¡
¿ 8 Data
RD
RAM 2
WR
AD7

CS1
CS2
128¡
¿ 8 Data
RD
RAM 3
WR
AD7

CS1
CS2
128¡
¿ 8 Data
RD
RAM 4
WR
AD7

CS1
CS2
1-7 128¡
¿ 8 Data
ROM
8
AD9
9
 Tracks

 12-3 Auxiliary Memory

 Magnetic Disk : FDD, HDD

to r
 Magnetic Tape : Backup or Program

Sec
 Optical Disk : CDR, ODD, DVD
text

 12-4 Associative Memory

 Content Addressable Memory (CAM)
Read/Write
 A memory unit accessed by content head

 Block Diagram : Fig. 12-6 Argument register (A)

이름 주소
Key register (K)

A Register 101 111100 Argument

Match
K Register 111 000000 Key (Mask) register

Memory 내용 Input

Associative memory
Word 1 100 111100 M = 0 array and logic M

Word 2 101 000011 M = 1 Match Logic

Read
m words
Write
n bits per word

M = 1 일때 출력 Output
 m word x n cells per word : Fig. 12-7
Ai Kj
Input
A1 Aj An

Write
K1 Kj Kn

Word 1 C 11 C 1j C 1n M1 R S Match
To M i
F ij logic
Read
Word i C i1 C ij C in Mi

Word m C m1 C mj C mn Mm

Bit 1 Bit j Bit n

Output

 Match Logic
 One cell of associative memory : Fig. 12-8
» Input = 1 or 0 Write F/F
» A 와 K 에 의해 Match Logic 에서 M=1 이면 (M을 READ에 직접 연결 가능함)
» Read 신호에 따라 F/F에서 데이터를 읽는다
 Match Logic : Fig. 12-9 K1 A1 K2 A2 Kn An

» Aj = Argument, Fij = Cell ij bit F'i1 F i1 F'i2 F i2 F'in F in

» j 1 bit match
xj = Aj Fij (1 AND 1)+ Aj’ Fij’ (0 AND 0)
» 1 - n , n bits match Mi = x1x2…..xn
» Key bit Kj : xj + Kj’
 Kj = 0 : Aj 와 Fij 는 no comparison ( Kj : xj + 1 = 1 )
 Kj = 1 : Aj 와 Fij 는 comparison ( Kj : xj + 0 = xj )
» Match Logic for word I :
Mi
Mi = (x1 + K1’) (x2 + K2’)…. (xn + Kn’)
n

=  (xj + Kj’)
j 1

=  (Aj Fij + Aj’ Fij’ + Kj’)

n

j 1
 12-5 Cache Memory
 Locality of Reference
 the references to memory tend to be confined within a few localized areas in
memory. Ex. Program loops or subroutine. It states that over a short interval of
time the addresses generated by a typical program refers to a few localized areas
of memory repeatedly.
 Cache Memory : a fast small memory
 keeping the most frequently accessed instructions and data in the fast cache
memory
 Cache
 cache size : 256 K byte (512 K byte)
 mapping method : 1) associative, 2) direct, 3) set-associative
 replace algorithm : 1) LRU, 2) LFU, 3) FIFO
 write policy : 1) write-through, 2) write-back
 Hit Ratio
 the ratio of the number of hits divided by the total CPU references (hits + misses)
to memory
» hit : the CPU finds the word in the cache
» miss : the word is not found in cache (CPU must read main memory)
 An example where cache memory access time = 100 ns, main memory access
time = 1000 ns, hit ratio = 0.9 produces an average access time of 200 ns.
» 1 * miss : 1 x 1000 ns without the cache memory the time is 1000ns
10
» 9 * hit : 9 x 100 ns
Memory
1900 ns / 10 = 190 ns
 Mapping
 The transformation of data from main memory to cache memory
» 1) Associative mapping
» 2) Direct mapping
» 3) Set-associative mapping
 Example of cache memory :
main memory : 32 K x 12 bit word (15 bit address lines)
cache memory : 512 x 12 bit word
» CPU sends a 15-bit address to cache
 Hit : CPU accepts the 12-bit data from cache
 Miss : CPU reads the data from main memory (then data is written to cache)

Main memory
CPU
32K¡¿ 12 Cache memory
512¡¿ 12
Associative mapping : associative memory stores both address and data of the
memory word.
If the address is found, the corresponding
12-bit data is read and send to the CPU. IF
NO MATCH OCCURS, then main memory
is accessed for the word. The address pair is
then transferred to the associative memory.
If the cache is full, an address-data pair
CPU address(15 bits)
must be displaced to make room for a pair
that is needed and not presently is in cache.
Argument register
This is done with replacement algorithm.
Address Data

0 1 0 0 0 3 4 5 0

0 2 7 7 7 6 7 1 0

2 2 3 4 5 1 2 3 4
Direct mapping : Fig. 12-12
Cache memory 6 bits 9 bits
Tag Index
Tag field (n - k)
Index field (k)
»2k words cache memory and 2n words
main memory 00 000 000
Tag = 6 bit (15 - 9), Index = 9 bit 512¡¿ 12
32K¡¿ 12
Cache memory
Tag (6 bit) Octal
00 - 63 Hex Main memory address
Address = 9 bits
Address
Index (9 bit) Data = 12 bits
1FF
000 - 511 Address = 15 bits
3F 1FF Data = 12 bits

Memory Index
address Memory data address Tag Data
 Direct mapping cache organization : Fig. 12-13 000000 1220 000 00 1220
For address 02000
1) Index 000 cache , tag 00 and data 1220 00777 2340
2) Suppose CPU wants to access the word at 01000 3450

address 02000.
3) The index address is 000 so it is used to 01777 4560 777 02 6710

Access cache. Two tags then compared. 02000 5670

(b) Cache memory
4)Cache tag 00 but address tag 02, not match
5)Main m/m accessed & data word 5670 is 02777 6710

Transferred to CPU.
6)Now 000 is replaced with tag 02 & data 5670.
(a) Main memory
  Direct mapping cache with block size of 8 words : Fig. 12-14
» 64 block x 8 word = 512 cache words size

Index Tag Data 6 6 3

000 01 3450 Tag Block Word
Block 0
007 01 6578
Index
010
Block 1
017

770 02
Block 63
777 02 6710
Set-associative mapping :
Disadvantage of direct mapping: two words with the same index in
their address but with different tag values can not reside in cache
memory at the same time.
Each data word is stored together with its tag and the number of tag-
data item in one word of cache is said to form a set.
Index Tag Data Tag Data
000 01 3450 02 5670

777 02 6710 00 2340

 Replacement Algorithm : cache miss or full
 1) LRU (Least Recently Used) :
 2) LFU (Least Frequently Used)
 3) FIFO (First-In First-Out) :

 Writing to Cache: Cache READ

Write Through: Advantage that main m/m always contain same data as cache.
Write back: only the cache location is updated during a Write operation.
 Cache Initialization
 Cache is initialized :
» 1) when power is applied to the computer
» 2) when main memory is loaded with a complete set of programs from auxiliary memory
 valid bit
» indicate whether or not the word contains valid data
 Assignment
 Explain memory hierarchy with the help of an example.
 Differentiate between cache memory and main memory.