An 370 FT60X Configuration Programmer User Guide
An 370 FT60X Configuration Programmer User Guide
AN_370
Version 1.5
This document provides a guide on how to use the FT60X Chip Configuration
Programmer application for customizing the chip configuration.
Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the
user agrees to defend, indemnify and hold FTDI harmless from any and all damages, claims, suits
or expense resulting from such use.
Table of Contents
1 Introduction .............................................................. 3
1.1 Overview .............................................................................3
1.2 Prerequisite .........................................................................3
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1 Introduction
This document explains how to use the FT60X Series Chip Configuration Programmer, a utility
application for customizing the chip configuration.
1.1 Overview
The FT600 and FT601 are the first USB devices in a brand new SuperSpeed series from FTDI Chip.
The devices provide a USB 3.0 SuperSpeed to FIFO Bridge, with up to 5Gbps of bandwidth.
Delivering the option of 16 bit (FT600) and 32 bit (FT601) wide parallel FIFO interfaces; the FT60X
series enables connectivity for numerous applications including high resolution cameras, displays,
multifunction printers and much more.
During initialization, the FT60X devices read configuration data and initialize the system using
these values. If the chip configuration data read is empty or invalid, the default chip configuration
data will be used. The Chip Configuration Programmer application allows the user to get, set or
update this chip configuration data.
1.2 Prerequisite
A PC running Windows 7 Operating System or greater is required.
The PC should also be installed with D3XX Direct Drivers. FT60X uses D3XX (FTDI’s latest USB
driver targeted for USB 3.0 SuperSpeed devices). They can be obtained here:
http://www.ftdichip.com/Drivers/D3XX.htm
The PC should also be installed with the Microsoft Visual C++ 2013 Redistributable (x86) package.
Please us the following steps to install it:-
1. Go to https://www.microsoft.com/en-us/download/details.aspx?id=40784
2. Click ‘Download’ button
3. Check the ‘vcredist_x86.exe’ and click ‘Next’.
4. After download completes, run ‘vcredist_x86.exe’ to install the package
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2 User Interface
Below is a screenshot of the FT60X Chip Configuration Programmer application.
The application allows the user to reset/clear, write and read the device configuration.
Clicking this button will erase the custom configuration in the device.
After erasing, the chip will automatically reset using its default
Erase Configuration
configuration and the application template values will also change to
reflect the configuration from the chip.
Clicking this button will set the custom configuration that the user has
Write Configuration
selected. The chip will automatically reset using the new configuration.
Clicking this button will show the current settings that the device is
Read Configuration
configured with.
Note: when changing FIFO Clock, or any of the drop-down menus, you must scroll to the selected
item and click on it. Make sure the selection is highlighted in blue before writing the configuration.
If the selection is not highlighted, the chip configuration will not change.
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DCP (11)
Default (00)
Controls the chip behavior when the chip receives less data
than expected from the FIFO Master.
Ignore Session These sub-options are disabled by default and are enabled
Not set when ‘Ignore Session Underrun’ option is checked. A read
Underrun
session is said to underrun, when the FIFO master stops or
pauses writing before the length of data requested in a
corresponding FT_ReadPipe is reached. i.e. If the host
issues FT_ReadPipe (X bytes) and the master pauses or
stops before X bytes are written, the session is said to have
underrun. The FT_ReadPipe will return with the length of
data written by the FIFO master up to the point where it
stopped/paused.
A session underrun may be ignored so that the session
remains open until the requested length of data is reached.
This allows FIFO masters to write as when data is available
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18 ohm
9 Notification Callback and GPIO pin state reads are over the
interrupt endpoint and hence have a minimum latency of
(Available from
2**(bInterval-1) USB frames.
RevB)
Default value of 9, will give a latency of 2**(9-1) USB
Interrupt frames. That is 256 frames. As 1 frame is 125us, this gives
Latency a latency of 32ms.
(bInterval)
FTDI provides a set of APIs to query and set the chip’s configuration. Please refer to the D3XX
Programmer's Guide.
Note: When calculating the maximum string length of a string descriptor the following rules must
be applied:
Each string descriptor requires a 2 byte header therefore of the maximum 128 bytes there is 128-6=122
bytes available.
As the data is sent in Unicode, this then divides down to 122/2=61 bytes.
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High or
GPIO 1 Indicates whether GPIO 1 is set to high or low.
Low
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Below is a sample illustration where the device is detected to be running using the default chip
configuration.
Below is a sample illustration where the device is detected to be running using some custom chip
configuration. If the user wants to go back to the default chip configuration, the user can click on
the Erase Configuration button. This will erase the custom setting in the chip.
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5 Contact Information
Head Office – Glasgow, UK Branch Office – Tigard, Oregon, USA
Future Technology Devices International Limited Future Technology Devices International Limited
Unit 1, 2 Seaward Place, Centurion Business Park (USA)
Glasgow G41 1HH 7130 SW Fir Loop
United Kingdom Tigard, OR 97223-8160
Tel: +44 (0) 141 429 2777 USA
Fax: +44 (0) 141 429 2758 Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-mail (Sales) [email protected]
E-mail (Support) [email protected] E-Mail (Sales) [email protected]
E-mail (General Enquiries) [email protected] E-Mail (Support) [email protected]
E-Mail (General Enquiries) [email protected]
Future Technology Devices International Limited Future Technology Devices International Limited
(Taiwan) (China)
2F, No. 516, Sec. 1, NeiHu Road Room 1103, No. 666 West Huaihai Road,
Taipei 114 Shanghai, 200052
Taiwan , R.O.C. China
Tel: +886 (0) 2 8797 1330 Tel: +86 21 62351596
Fax: +886 (0) 2 8751 9737 Fax: +86 21 62351595
Web Site
http://ftdichip.com
System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology
Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level
performance requirements. All application-related information in this document (including application descriptions, suggested
FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this
information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications
assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the
user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from
such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is
implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product
described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent
of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,
Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640
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Appendix A – References
Document References
FT600Q-FT601Q SuperSpeed USB3.0 IC Datasheet
DS_UMFT60xx module datasheet
D3XX Programmer’s Guide
ID Identification
UI User Interface
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List of Tables
Table 2.1 Description of Main UI Controls ............................................................................... 4
Table 3.1 Description of User Configurable ............................................................................. 8
Table 4.1 Status Information of Chip Configuration Initialization ............................................... 9
List of Figures
Figure 2.1 Application Screenshot ......................................................................................... 4
Figure 4.1 Chip Configuration Status - Default Chip Configuration ........................................... 10
Figure 4.2 Chip Configuration Status - Custom Chip Configuration........................................... 11
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2016-04-05
1.2 Updated Section 1.2 Prerequisites
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