A POWER-ON RESET PULSE GENERATOR FOR LOW VOLTAGE APPLICATIONS

Takeo Yasuda, Masaaki Yamamoto, and Takafumi Nishi

IBM Japan, Yasu Technology Application Laboratory

800 Ichimiyake Yasu-cho Yasu-gun, Shiga 520-2392, Japan
{ taky,ymasa, takafun} @jp.ibm.com

ABSTRACT
The power supply voltage of LSI has been lowered due to
system requirements for low power dissipation. An on-chip
power-on reset pulse generator (POR-PG) is used to de-
termine the initial state of the memory devices of the sys-
tem LSI. This paper describes a POR-PG for low power
voltage supply (I&). Hardware measurement proves im-
Figure 1: Input and output of POR-PG
proved pulse height relative t o various power-on profiles
(slope, rise time etc.) and process fluctuations. Further,
the design provides robust noise immunity against voltage
fluctuations on the power supply line. The circuit is im- in a very short interval between power-down and power-up.
plemented within a small area (115pm x 345pm) in the Such short interval of power-off creates difficult situations
input/output buffer area of a micro-processor and hard- for a POR-PG to work properly. Third, circuits that are
disk controller integrated LSI with 0.25-pm four-layer-metal too sensitive to the voltage fluctuations may sense noise
CMOS technology. on the power line and cause improper initializations a t un-
desired times. Lowering the power-supply voltage is one of
the most efficient ways to implement low power systenis [l],
1. INTRODUCTION but it makes the requirements for a POR pulse generation
circuit more critical because of the above concerns. Fur-
As integration density increases, system LSI has to include ther, utilizing a low voltage bandgap voltage reference [:?]
more complicated functions on each chip. Some of the is not recommended because of the circuit complexitay. Too
special function blocks must be in a known initial state complicated circuit does not work correctly when the power
to start operation correctly at power-on or at recovering supply voltage is very low and unstable. The P O R puke
from power-saving mode. A power-on reset pulse is used generator should work correctly before the power supply
to pre-set or pre-reset the memory devices such as flip- voltage reaches to its target value. This paper describes
flops, latches and registers. At the same time, the on-chip solutions for such problems.
POR-PG is desired for the following reasons. First, inte-
grating the power-on reset (POR) functions into the LSI
reduces the number of electronic parts, which saves space 2. PRIOR ART AND PROBLEMS
and reduces the cost of the final products. Even a small
discrete device occupies much more space than an on-chip Figure 1 shows a POR-PG circuit input (power supply volii-
circuit which consists of several hundred thousand transis- age (I;&+)), output, internal circuit state, and input of th.e
tors. Second, the output of an on-chip POR-PG is free logic circuit. \;&-target is the normal operating voltage of
from inter-chip or inter-module noise which is caused by the system power supply. I)dd stops rising when it reaches
such problems as cross-coupling with other signal lines on I , h d - t a r g e t . The output pulse of POR-PG is supposed to be
a card. Finally, an on-chip circuit is able t o monitor and generated only once with a height of a certain level. This
sense internal voltage, so even a level conversion of power level should be high enough for the POR pulse to initializie
supply voltage can be implemented using an internal volt-
age regulator. The POR-PG is sensitive t o its input, that is
the power line’s behavior. This circuit operation is affected “I
by the rise time of the power supply voltage, the time in-
terval between power-down and power-up, and noise in the
power supply, especially at power-up period. Thus, there
are several points which have t o be taken into consideration
in designing a POR-PG. First, a very long rise time of the
power supply line voltage may cause too low pulse height
to pre-set or pre-reset the internal circuits. Second, a sud-
den surge caused by such problems as lightning can result Figure 2: Conventional POR-PG (I)

IV-598
O-7803-6685-9/0 1/$10.0002001 IEEE
 Figure 5: Conventional POR-PG (111)

backs of this “Charge Clamp” circuit are as follows: First,

Figure 3: Conventional POR-PG Pulse Height Performance the circuit is not able to work reliably when \&target is
low because the threshold voltage of the stacked MOSFETs
fluctuates due to process and temperature variation. Next,
the circuit consumes DC current whenever the device is on,
the internal circuits. Furthermore, the POR pulse should even after the initialization of logic circuit. Another exam-
be generated before any functional operations begin. The ple of prior art is shown in Figure 5 [4]. This circuit uses
rise time of power supply ( T n s e ) is on the order of tens of two diode-connected n-MOSFETs as a “Charge Clamp”.
milh seconds. As there is no input signal except Vdd to the This circuit is also not suited for low power supply volt-
POR-PG, the internal delay of this circuit should be the age applications because of fluctuations of the threshold
same order as Trise. In order to achieve the proper delay voltage and the drain-source resistance of the transistors
time for the rest of the circuits, a C R charge operation with MNI and MN2 caused by process and temperature varia-
a large capacitance and a large resistance is often used. For tion. Figure 6 shows the threshold voltage fluctuations of
on-chip implementations, however, the device values of the n-MOSFET in 0.25-pm CMOS technology against process
capacitance and the resistance are limited by the chip area. and temperature variation. The threshold voltage changes
Figure 2 shows conventional circuit. The circuit consists of more than 0.5 V. Figure 7 shows the I-br characteristic of a
a Delay Generation Portion and a Pulse Generation Por- diode-connected n-MOSFET. Judging from the slope of the
tion. After Vdd starts to raise, Node A starts to charge. curve, the maximum drain-source resistance is 7.72 kR, and
When the voltage of Node A reaches the threshold voltage this is more than twice the minimum resistance of 3.33 kR.
of an inverter I , Node B flips and the Pulse Generation In this circuit, the threshold level may also be affected by
Portion creates a pulse at the output of the POR-PG. As body effect. This is also a drawback of this circuit.
there is no device to limit the capacitance C to be charged
, there is a drawback in this circuit. If Trlseis large com-
pared with the CR time constant (Tcharge), the height of 3. SPECIFICATION FOR LOW POWER SUPPLY
the POR pulse (Vph) is not high enough to initialize the in- POWER ON RESET PULSE GENERATOR
ternal logic circuits. Figure 3 shows the simulation results
of the pulse heights of this conventional POR-PG. There In this paper, LGdfarget is assumed to be 2 . 5 V or 1.8V.
are techniques in prior art to solve this problem. Figure 4 While the voltage of Vdd is increasing at power-on, the op-
shows one of these existing techniques [3]. This circuit uses eration of the entire circuit block is not certain. This is
a “Charge Clamp” circuit composed of several MOSFETs because the device operation is confirmed with simulation
to improve the height of the pulse even if T,,,, is large. The models fitted to the real device within a limited Vdd voltage
“Charge Clamp” circuit determines the voltage at the tim- range. Most of the technology assumes less than f 1 0 % fluc-
ing which the capacitor C starts to be charged by using tuation from the nominal condition voltage. For example,
n times stacked p-MOSFETs (from M P I to MP,,). The the power supply voltage which is supported by the 2.5-V
charge of the capacitor C does not start until Vdd reaches
n times the threshold voltage of p-MOSFET The draw-
..........
..........
-
P
- F.rl .t

..........
Mld T-v

Figure 4: Conventional POR-PG (11) Figure 6: Threshold voltage of n-MOSFET vs. temperature

IV-599
 ................................................................................................

......................................................................................................
D d q G.wruon Ponm

.......................................................................

I
a,
.
I)
.
0,
.
I
.
9,
.
:
.
*I
1
I
Vd NI
...............................................................
pulw C..nnlon P""

Figure 7: I-\,rcharacteristic of diode-connected n-MOSFET

Figure 9: Proposed POR-PG

0.25-pm technology library ranges from 2.3 V to 2.7 V. The

circuit operation is guaranteed as long as the voltage a'dd of the diode-connected n-MOSFET which is shown in Fig-
is within this voltage range. The POR-PG, however, has ure 6, although the voltage at which the p-n diode is c m
t o operate at less than this voltage range because the POR changes by about 0.2 V. This shows the p-n junction diode
pulse is expected t o be generated not during normal oper- is more suitable for the "Charge Clamp" circuit [ 5 , 61. The
ation, but during the power-on period only. Therefore the second improvement is that this circuit has a charge boost-
POR-PG should be simple, robust with respect to noise, ing path P,. This path charges Node .4 once this node
and insensitive t o process and temperature variations. The exceeds the voltage level required t o turn on the inverter
specifications of the POR-PG should be determined taking IL. This path accelerates the second-half of the charge to
these items into consideration. Figure 8 shows the speci- Node A . The simulation result of the output pulse height
fications of the POR-PG which is proposed in this paper. is shown in Figure 11. The final improvement is that this
The maxiniuni Triseis 50 ms. \,interval which is the voltage circuit has the feedback transistor M P 4 to improve noise irn-
at interval period is less than 0.1V. The Vpll and munity. A low threshold transistor MPs discharges Node il
T,,, are set so that the pulse can initialize logic circuits. i\ down to its threshold level, which is low enough to reset
I/& sense voltage.(I.,,,,,,,) has been introduced t o ensure the the half latch composed of I3 and MP4 when the power
minimum height of POR pulse (lil,). The Vi,, should be is off. Resistances R I , Rr and an inverter 11 are included
lower than the functional operation voltage range. Taking for testing the P O R circuit. With the external discharge
the voltage fluctuation into consideration, the l~',,,,, should terminal PAD, the Delay Generation Portion can be dis-
be a t lea3t 1 0 % lower than the lowest, normal operating charged externally. These devices are used to test the T,,,
voltage. .A perforniance parameter Tclelayis introduced to and Tdela). at production test. With these improvements in
prevent noise from triggering the P O R pulse. circuit level, the operation of the proposed circuit is much
more stable even at very low voltage. Thus the proposed
circuit does not require so accurate model at low voltage
4. PR.OPOSED CIR.CUIT AND IMPLEMENTATION
range below 1.OV.
Figure 9 shows the proposed circuit. There are three niajor
improved points in this circuit,. The first improvement is in 5. MEASURED RESULTS
the "Charge Clamp" circuit. In this circuit, the "Charge
Clanip" circuit is composed of two p-n diodes D1 and Dz. Figure 12 shows the output pulse height Vp1, versus T,,,,
Each diode consists of a p'diffusion region inside its own of the proposed circuit. In this measurement, Vddfarget is
11-well region. The two diodes determine the IJ,,,. The 1.8V. The temperature is 0 ° C for "Low Temp" condi-
\1,,,,,, is a value of 1 when Node A starts to charge. The
charge of the capacitor starts through charge path PI when
Vdd exceeds \,Le,,,,. Figure 10 shows 1-1.' characteristic of
the p-n junction diode. The fluctuation of resistance due to
process and temperature variation is much less than that

vwnw

0"DUl
POR-PG

Figure 8: Required specification for POR-PG Figure 10: I-V characteristic of p-n junction diode

IV-600
 Figure 13: POR-PG noise immunity

Figure 11: Simulation result waveform technology also operates correctly.

tion and 90 “C for “High Temp” condition. Effective chan- Acknowledgments

nel length ( L e f f )and ion-implantation for both p- and n- The authors thank I. Tsutamoto, K. Kiyota, K. Ioki, K.
diffusions are biased into fast and slow side to make pro- Enami, and N. Takahashi for their useful suggestions and
cess fast and slow chips. Compared with Figure 3, the pulse support throughout this study. The authors also thank all
height of the improved circuit doesn’t degrade much even of the colleagues in their section and department for their
if T,ise is long, the temperature is high, and \.>&target is helpful encouragement in this work.
low. Figures 13 shows the POR pulse waveform with a
noisy power supply. The POR-PG generates one correct
POR pulse even when there is more than 400-mV of peak- 7. REFERENCES
to-peak noise on b&. Figure 14 shows the layout of this
[1] A. Bellaouar, M.I. Elmasry, Low-Power Digital VLSI
macro. The capacitance C and the resistance R3 which are
Design Circuits, and Systems, Boston / Dordrecht /
implemented to realize large Tdelay (2 1ms) occupy about
London: Kluwer -4cademic Publishers, Chaps. 3 and
1/3 of the total circuit area. The size of the total circuit
is 115 pm x 345 pm. I t is implemented in the input/output 4, 1995.
buffer area with 0.25-pm le^ = 0.18 pin) four-layer-metal [2] H. Banba, H. Shiga, A. Umezawa, T. hiliyaba, T. Tan-
CMOS technology. zawa, S. Atsumi, and K. Sakui, “A CMOS band-gap
reference circuit with sub 1V operation,” Symp. VLSI
Circuits Dig. Tech. Papers, pp. 228-229, June 1998.
6. CONCLUSION
[3] N.bliyake, &I. Kojima, “Initial value decision circuit”,
A Power-on reset pulse generation circuit for low voltage Japan Patent Toku-Kai-Hei 07-312541, Nov. 1995.
application is proposed. This circuit improves pulse height [4] T. Tanizaki, T. Tanigawa, “Power On Reset Circuit”,
and noise immunity compared with prior circuits consid- Japan Patent Toku-Kai-Shou 64-078520, Mar. 1989.
ering process, temperature, and voltage variations. The [5] P. Antognetti, G. Massobrio, Semiconductor Device
circuit is implemented in small area in the input/output* Modeling with SPICE, New York: McGraw-Hill,
buffer area of an integrat,ed LSI of a microprocessor and a Chap. 4, and 6, 1988.
hard-disk controller for the internal power supply voltage
of 2.511 and 1.8V with 0.25-pm CMOS t,echnologp. Ac- [6] S. PI. Sze, Physics of Semiconductor Devices, 2nd ed.,
cording to the simulation, by tuning the “Charge Clamp” New York / Chichester / Brisbane / Toronto / Singa-
circuit, this POR-PG in 0.18-pm, 1.35-V \.&-target CMOS pore: John Wiley & Sons, Chaps. 1, 2, and 8, 1981.

R3

Figure 12: POR-PG performance Figure 14: POR-PG layout

IV-60 I