580 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO.

3, JUNE 2013

Silicon-Embedding Approaches to 3-D

Toroidal Inductor Fabrication
Xuehong Yu, Minsoo Kim, Florian Herrault, Member, IEEE, Chang-Hyeon Ji, Member, IEEE,
Jungkwung Kim, and Mark G. Allen, Fellow, IEEE

Abstract—This paper presents complementary-metal–oxide–

semiconductor-compatible silicon-embedding techniques for on-
chip integration of microelectromechanical-system devices with
3-D complex structures. By taking advantage of the “dead volume”
within the bulk of the silicon wafer, functional devices with large
profile can be embedded into the substrate without consuming
valuable die area on the wafer surface or increasing the packag-
ing complexity. Furthermore, through-wafer interconnects can be
implemented to connect the device to the circuitry on the wafer
surface. The key challenge of embedding structures within the
wafer volume is processing inside deep trenches. To achieve this
Fig. 1. Illustration of a chip-scale integration scheme with a MEMS device
goal in an area-efficient manner, straight-sidewall trenches are de-
embedded in the wafer volume and connected to the circuitry on the wafer front
sired, adding additional difficulty to the embedding process. Two surface using through-wafer interconnects.
approaches to achieve this goal are presented in this paper, i.e., a
lithography-based process and a shadow-mask-based process. The
lithography-based process utilizes a spray-coating technique and
and miniaturization. In many of these approaches, the relatively
proximity lithography in combination with thick epoxy process- large volume of the silicon bulk compared with the active vol-
ing and laminated dry-film lithography. The shadow-mask-based ume of the circuitry, even in thinned wafers, remains untapped.
process employs a specially designed 3-D silicon shadow mask to To take advantage of this “dead volume” in the wafer, silicon-
enable simultaneous metal patterning on both the vertical sidewall embedding approaches can be utilized to enable fabrication
and the bottom surface of the trench during deposition, eliminat-
ing multiple lithography steps and reducing the process time. Both
of functional devices into the silicon bulk, and through-wafer
techniques have been demonstrated through the embedding of the interconnects can be implemented to enable connection from
topologically complex 3-D toroidal inductors into the silicon sub- the embedded device to the circuitry on the wafer surface,
strate for power supply on-chip (PwrSoC) applications. Embedded achieving the ultimate chip-scale integration, as shown in
3-D inductors that possess 25 turns and a diameter of 6 mm in Fig. 1. This silicon-embedding approach, as compared with
a silicon trench of 300-μm depth achieve overall inductances of
45–60 nH, dc resistances of 290–400 mΩ, and quality factors of
other integration schemes of 3-D structures such as surface
16–17.5 at 40–70 MHz. [2012-0187] micromachining of the devices on or beside the circuits [5]–[9],
offers additional system miniaturization, which is particularly
Index Terms—Deep-trench patterning, silicon-embedding,
spray coating, toroidal inductor, 3-D shadow mask.
beneficial when the system profile is a major concern.
The silicon-embedding approach has found application
I. I NTRODUCTION in integrating many microelectromechanical-system (MEMS)
devices and structures such as accelerometers [5], permanent-

A S semiconductor scaling begins to approach ultimate

limits, advanced approaches such as chip stacking and
system-in-package/system-on-package [1]–[4] have been de-
magnet microgenerators [10], interconnects and copper cir-
cuitry [11], [12], magnetic components for power applications
[13]–[17], hall sensor [18], and microfluidic devices [19].
veloped to enable integration of multiple chips or components In [10], the authors proposed a manual drop-in method to
into a single package for continued system multifunctionality embed prefabricated stator windings into a preetched silicon
trench with preelectroplated interconnects folded and threaded
through silicon trenches for realization of a silicon-embedded
Manuscript received June 29, 2012; revised November 15, 2012; accepted
November 20, 2012. Date of publication January 3, 2013; date of current
microgenerator. Although this technique avoided the difficulty
version May 29, 2013. This work was supported in part by the Advanced of processing inside silicon trenches with complex silicon
Research Projects Agency—Energy, U.S. Department of Energy, under Award features, the drop-in approach is a manual serial process.
DE-AR0000123. Subject Editor M. Wong.
X. Yu, M. Kim, F. Herrault, J. Kim, and M. G. Allen are with the School of The creation of devices directly inside the silicon trenches
Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, with batch-fabrication-compatible technology, although chal-
GA 30332 USA (e-mail: [email protected]; [email protected]). lenging, needs to be addressed. To date, most of the published
C.-H. Ji was with the School of Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, GA 30332 USA. He is now with research has focused in embedding 2-D structures into the
the Department of Electronics Engineering, Ewha Women’s University, Seoul silicon substrate due to their less complex geometry and ease
120-750, Korea (e-mail: [email protected]). in fabrication process [11], [12], [16], [17]. Significant chal-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. lenges remain in embedding complex 3-D structures with deep
Digital Object Identifier 10.1109/JMEMS.2012.2233718 profile into the silicon. An additional challenge is introduced
1057-7157/$31.00 © 2013 IEEE
YU et al.: SILICON-EMBEDDING APPROACHES TO 3-D TOROIDAL INDUCTOR FABRICATION 581

when the constraint of vertical, rather than sloped, trench walls nects also demonstrated. Since toroidal inductors constrain the
is imposed to maximize the area efficiency of the embedding magnetic flux within a closed path in contrast to the substrate-
process. penetrating magnetic field that spiral inductors generate, po-
Generally, two techniques have been demonstrated for pat- tentially less magnetic interference will be imposed on other
terning on or within 3-D recessed surfaces, i.e., a spray-coating circuits, and complex shielding techniques can be bypassed.
technique with proximity lithography and a shadow-mask The flux containment offered by toroidal inductors may be
method. The spray coating of photoresist has been well studied particularly important in ultracompact converters, in which the
and reported to generate well-patterned features, for example, physical separation of components is minimized.
in KOH/TMAH etched trenches [14], [22]. The trenches are PCB-embedded toroidal inductors for megahertz operation
formed with slanted sidewalls to enable pattern definition on the [23], [24] and surface-micromachined toroidal inductors that
sidewall, which could lead to a trench opening as much as seven operate in the gigahertz range [25] have been successfully
times the size of the bottom of the trench [14], increasing the demonstrated, yet such structures do not take advantage of
footprint of the device. With vertical sidewalls, patterning typ- the silicon wafer volume. Previous efforts to embed toroidal
ically requires tilting of the structures when using this method inductors within the volume of the silicon wafer [13], [14]
due to the strong vertical directionality of the ultraviolet light. possessed a shallow profile due to fabrication limitations and
Shadow masking can be also used for patterning in trenches. achieved low inductance values that are more suitable for
Traditional shadow masks are usually 2-D planar structures RF application. When considering next-generation integrated
that are aligned and attached to the device wafers to define power converter systems with an operating frequency of 10–
metal patterns during evaporation [12], [18]. This approach is 100 MHz, high inductance and conductor thickness in excess
challenging for deeply recessed surfaces because of the pattern of those achievable by RF inductors are required. In this paper,
blurring introduced due to the gap that exists between the planar the toroidal inductors fabricated by the presented technologies
shadow mask and the recess. Recently, 3-D silicon shadow not only have densely packed electroplated windings but also
masks that possess self-aligning mechanical structures have a deep profile embedded in silicon to achieve high inductances
been demonstrated to enable fine feature patterning in deep and low resistances.
recessed surfaces [19]–[21]. However, the margins between
the drop-in mask and the trench sidewalls do not favor the II. I NDUCTOR FABRICATION
use of conformal deposition methods such as sputtering. The
directional evaporation method required multiple sample tilts A. Lithography-Based Silicon Embedding
during deposition as well when the vertical trench walls needed The lithography-based process combines a spray-coating
to be coated [20]. technique with thick epoxy processing and dry-film lithography
As an example of a technology that could greatly benefit on nonplanar surfaces to enable creation of complex 3-D struc-
from embedded 3-D structures, consider dc–dc power convert- tures in deep silicon trenches. A schematic of the embedded
ers designed for ultracompactness, resulting in an integrated inductor design is shown in Fig. 2. Structures are defined
power supply on chip (PwrSoC) [7]. These converters, com- in the etched trench using spray coating and fine proximity
prising digital control logic, power electronic switchers, and lithography. Patterning on the vertical sidewalls is avoided by
magnetic storage elements, can be utilized not only as small processing thick SU-8 to form a mold for housing the vertical
standalone chargers for portable electronics but also as indis- conductors. An air gap must be maintained between the SU-8
pensible components of compact electronic systems requiring mold and the sidewall to facilitate seed layer removal, which
multiple voltage levels. The requirements of such devices, isolates the windings at the end of the fabrication process. The
in addition to compactness, include reasonably large power complete process flow for realizing the embedded inductor is
handling capability, as well as shielding of stray magnetic fields shown in Fig. 3 [15] with scanning electron microscopy (SEM)
that might influence other portions of the converter or system. images and optical photomicrographs of the partially fabricated
In accordance with Fig. 1, such a PwrSoC could be realized by devices also presented for selected steps. The interconnect
forming the switches and the control logic on the wafer front scheme is temporarily ignored here as it will be introduced later.
surface while forming the 3-D magnetic energy storage element For better illustration, the silicon wafer is drawn upside down
and high power interconnect within the wafer volume. throughout the entire process, and the front and back sides of
In this paper, two approaches for embedding complex 3-D the wafer will be referred to as indicated in Fig. 3.
structures into deep silicon trenches with vertical sidewalls Referring to Fig. 3, fabrication begins with a standard 4-in
are pursued based on the development of the aforementioned silicon wafer in step 1, whose thickness is 500 μm and resistiv-
lithography-based technique and 3-D shadow-mask technique, ity is in the range of 1–10 Ω cm. A silicon trench of 300-μm
respectively. These processes allow for conformal metal deposi- depth and 2-mm width is first etched into the back side of the
tion, as well as patterning along vertical sidewalls. A process for wafer through the Bosch inductively coupled plasma process
incorporating through-wafer interconnects is also presented to as shown in step 2. A cavity-shaping technique is utilized to
enable connection from the device to the circuitry on the wafer form rounded-off edges during the etching to facilitate the uni-
surface. form coverage of spray-coated photoresist on the vertical side-
As a technology demonstration, topologically complex 3-D walls [11]. After deposition of 6-μm-thick plasma-enhanced
toroidal inductors are fabricated and embedded in the silicon chemical vapor deposition (PECVD) oxide as insulation layer
substrate using both approaches, with through-wafer intercon- and metal sputtering, spray coating of photoresist, proximity
582 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 3, JUNE 2013

Fig. 2. Schematic of the embedded 3-D toroidal inductor using lithography-

based approach. (a) Wafer front side with silicon substrate drawn partially
transparent and SU-8 epoxy removed to illustrate the embedded structures; and
(b) wafer back side with cross-sectional cut.

lithography, and wet etching are performed to obtain a patterned

seed layer for radial windings on the recessed bottom surface
of the trench in steps 3 and 4. With a spray-coated photoresist
mold defined again in step 5 to protect the metallized trench
sidewalls and wafer surface, 20-μm-thick radial copper conduc-
tors are electroplated. After hard baking the photoresist, thick Fig. 3. Fabrication process of the toroidal inductor using the lithography-
based silicon-embedding approach with results of partially completed devices
SU-8 is then cast and patterned in the trench, followed by elec- also shown in critical steps. Steps 1 and 2: Silicon etching; 3: proximity
troplating to form the vertical conductors in step 6. To fabricate lithography; 4: seed layer patterning; 5: bottom radial conductor fabrication;
the radial conductors on top of the SU-8 mold, a laminated dry- 6: vertical conductor fabrication; 7: dry-film patterning; 8: seed layer liftoff;
9: top radial conductor fabrication; 10: seed layer etching and device comple-
film technique is employed to generate a patterned seed layer tion. Features are not drawn to scale.
through a liftoff process on the complex 3-D surface, as shown
in steps 7 and 8. The dry film prevents the gap between the
SU-8 mold and the silicon substrate from being sputter coated,
which would be otherwise challenging to remove due to the
narrow gap. An additional patterned photoresist layer under the
dry film facilitates the clean removal of the dry film in acetone,
as shown in step 7. The top radial conductors are then formed
by electroplating in step 9, and the device is completed after
removing the protection photoresist layer using oxygen plasma
and etching away the underlying seed layer in step 10.
Photomicrographs of a fabricated inductor with 25 turns are
shown in Fig. 4 with electrical testing pads located on one radial
conductor that is intentionally separated into two pieces. The
minimum gap between two adjacent copper conductors in the
inner diameter of the inductor is approximately 120 μm, and
the vertical conductors buried in SU-8 at the inner diameter are
125 μm by 160 μm in area. The inductor embedded in the
trench is approximately 100 μm higher than the silicon surface
due to the fact that SU-8 has to be cast thicker to enable Fig. 4. Fabricated inductor embedded in silicon using the lithography-based
reflowing and planarization across the substrate during baking. approach.
YU et al.: SILICON-EMBEDDING APPROACHES TO 3-D TOROIDAL INDUCTOR FABRICATION 583

Fig. 5. Schematic of the embedded 3-D toroidal inductor using the 3-D
shadow-mask-based approach. Bottom view of wafer back side. Some radial
conductors are removed for illustration, and silicon substrate is drawn partially
transparent to show the through-wafer interconnects on the front surface of the
wafer.

B. Shadow-Mask-Based Silicon Embedding

The shadow-mask process utilizes a specially designed 3-D
silicon shadow mask that is formed through multilevel wafer
etching to realize the direct patterning of the metal layer on both
the vertical sidewall and the bottom surface of the deep trench.
Moldless electroplating can then follow to form the 20-μm-
thick copper conductors as required. The benefit of this Fig. 6. Schematic of the designed 3-D shadow mask: (a) Bottom view of
the mask with details of the 3-D spoke structure, (b) top view of the mask
approach is that plating can occur along the entire vertical after insertion into the device wafer with magnified view of the registration
sidewall, as well as the bottom surface of the trench simul- scheme, and (c) fabrication process. The portion of the shadow mask that covers
taneously. The process time of the shadow-mask method is regions 1 and 2 in the magnified view of (b) is drawn partially transparent for
illustration.
significantly reduced compared with the lithography-based ap-
proach due to the elimination of several lithography steps, thick
epoxy processing steps, and use of moldless electroplating. blurring due to the nondirectional characteristic of the sputtered
The inductor resulting from this approach possesses a slightly metals and the intrinsic margins that exist for registering and
different embedding geometry compared with the lithography- inserting the shadow mask into the device wafer. Thus, special
based approach, as shown in Fig. 5. The vertical conductors features on the shadow masks and device wafers are designed
sit directly on the passivated sidewalls of the silicon trench to ensure clean pattern definition after seed layer sputtering.
with no air gap introduced between them and are isolated from The fabrication process of the shadow-mask-based approach
each other automatically by the recesses etched into the vertical proceeds in two parts. First, the shadow mask is designed and
trench sidewalls. Using this approach, the upper surface of the fabricated; then, the shadow mask is applied to the inductor
fabricated inductor can be maintained coplanar with the back fabrication. It should be noted that the shadow mask, once
side of the wafer. fabricated, can be reused.
In the shadow-mask approach, conformal metal deposition The design and registration schematic of the shadow mask, as
(sputtering) is utilized in order to obtain a uniform and thick well as its fabrication process, is presented in Fig. 6. The multi-
seed layer on all exposed areas (bottom and side) of the ple spokelike structures, when looking from the bottom side of
deep trench. However, sputtering could introduce severe pattern the shadow mask, as shown in Fig. 6(a), are designed to fit into
584 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 3, JUNE 2013

Fig. 7. SEM images of the fabricated 3-D silicon shadow mask. (a)–(c) Tilted
view and (d) side view of the spoke structure.

the trench and define the isolation gaps between adjacent copper
conductors. The protruding ends on the spokes, as shown in the
magnified views, are designed to match the recesses etched into
the vertical sidewalls of the trench. The underlying mechanism,
as shown in Fig. 6(b), is that the tortuous path between regions
1 and 2 prevents the sputtered metals from entering the recess,
keeping region 2 free of any metal deposition, and thus ensures
isolation between the to-be-formed vertical conductors on the
trench walls. In addition, the protruding ends on the spokes also
act as alignment marks during registration and insertion of the
shadow mask into the device wafer.
The detailed process for fabricating the 3-D silicon shadow
mask is as follows [see Fig. 6(c)]. Starting with a standard
4-in wafer that is 500 μm thick in step 1, a double-layer mask
consisting of oxide and photoresist are first formed through Fig. 8. Fabrication process of the embedded toroidal inductors using the 3-D
shadow-mask-based approach with results of partially completed devices also
wet etching and photolithography in step 2. The photoresist shown in critical steps. Features are not drawn to scale. Steps 1 and 2: Silicon
acts as a mask for etching 200-μm silicon into the wafer, as etching; 3: shadow-mask registration; 4 and 5: seed layer patterning; 6: bottom
shown in step 4, which defines the thickness of the connection radial and vertical conductor formation; 7: epoxy filling; 8: photoresist mold
for electroplating; 9: top conductor formation.
framework in the shadow mask, and the oxide mask is used to
etch 300-μm silicon to form the spokes, as well as the open
area in the mask that allows metals to be deposited through, Fineplacer Lambda) in step 3. The shadow mask is placed on
as shown in step 5. A shallow Bosch etching step is conducted the bonder stage while the device wafer is positioned on the
in step 3 to compensate for the lower etch rate [due to deep bonder arm. The wafer is aligned with the shadow mask and
reactive-ion etching (DRIE) lag] of the small patterns at the brought into contact with the mask using a force of 3 N. This
inner diameter of the inductor. This is critical as nonuniformity- force was found to allow complete insertion during successful
based overetching of the spokes and the framework may result alignment but not to cause device or mask damage even in the
in overly fragile structures. After stripping the oxide in step 6, case of misalignment and insertion failure. Tape-based adhesive
the silicon shadow mask is ready for use. SEM images of the is temporarily applied after mask insertion to maintain the con-
fabricated 3-D silicon shadow mask are shown in Fig. 7. tact between the mask and the device wafer and is removed once
Once the shadow mask has been completed, inductor fabrica- the metal deposition is completed. The alignment accuracy of
tion can commence. The complete process flow for fabricating the bonder is 0.5 μm, and the registration margins between the
the embedded inductors using the premanufactured shadow shadow mask and the device features are designed to be 10 μm,
mask is illustrated in Fig. 8 with micrographs of partially well within the aligner tolerances. To guarantee a well-defined
completed devices also shown in selected steps. Starting with metal pattern, the height of the spokes in the shadow masks
a standard 4-in wafer that has a thickness of 500 μm and a must match with that of the trench within a maximum error of
resistivity in the range of 1–10 Ω · cm in step 1, a silicon 70 μm, which is achievable since the depth of the Bosch etching
trench with vertical sidewalls and recesses in the sidewalls is can be accurately controlled. A thick layer of Ti/Cu (1 μm) is
first formed using the Bosch process as shown in step 2. After sputtered into the trench, and the subsequent physical removal
deposition of a passivation layer such as PECVD silicon diox- of the shadow mask results in this layer being patterned, as
ide, the prefabricated 3-D shadow mask is then aligned with shown in step 4. To electrically connect the seed layer patterned
and inserted into the trench using a flip-chip bonder (Finetech in individual trenches for subsequent electroplating, a second
YU et al.: SILICON-EMBEDDING APPROACHES TO 3-D TOROIDAL INDUCTOR FABRICATION 585

ing one metal deposition and one 20-μm-thick copper electro-

plating step, eliminating multiple lithography steps, the thick
SU-8 patterning process, and the bottom-to-top filling of the
SU-8 vias. Although the fabrication of the shadow mask does
take time, the shadow mask can be reused to produce many
device wafers. Therefore, the overall processing time of the
shadow-mask approach is greatly reduced compared with that
of the lithography-based approach. The fact that this process
is less complex may also lead to a higher yield of devices
Fig. 9. Fabricated inductor embedded in silicon substrate using the 3-D under nonideal fabrication conditions and less performance
shadow-mask-based approach.
degradation due to fabrication limitations.
While the shadow-mask approach offers great benefit in
thin metal deposition (3000 Å) is conducted by dropping in reducing the process time, care has to be taken to ensure
individual silicon donut structures to mask the trench area in high processing quality in forming the shadow masks. Any
step 5. In step 6, spray-coated photoresist is then defined to dirt or residues that are not removed from the wafer surface
protect the wafer surface, and electroplating is performed to during processing steps prior to DRIE will act as masks in the
obtain the 20-μm-thick copper conductors in the trench, from etching and generate defects that prevent the shadow mask from
sidewalls to the bottom surface. After photoresist stripping and being in intimate contact with the device wafer. In addition,
seed layer removal in step 7, premolded solid epoxy donuts are the number of the devices that can be put in one shadow-
dropped into the silicon trench and melted at a temperature mask wafer is also limited by the fragility of the wafer. Since
of 120 ◦ C to prepare a planarized surface for top conductor the thickness of the silicon framework connecting individual
fabrication. After evaporation of a seed layer and photoresist shadow masks is determined by the wafer thickness and the
patterning in step 8, electroplating follows to form the top radial height of the spokes, the deeper the silicon trench, which is
conductors. The fabrication process concludes by stripping the desirable for higher inductance, the taller the spokes, and thus,
photoresist and etching away the seed layer in step 9. the thinner the silicon framework (the framework is 200 μm
Since there is no gap between the vertical copper conductors thick in this paper). Therefore, the shadow-mask wafer can be-
and the trench walls in the embedding design, no complex come increasingly fragile with an increasing number of devices
dry-film technology is needed for the fabrication of the top incorporated. To address this problem, a reinforcing outer frame
radial conductors as used in the lithography-based process. In can be designed to help strengthen the shadow-mask wafer. For
addition, the uncrosslinked epoxy in the trench can be easily demonstration in this paper, six shadow masks are fabricated in
removed if required [26], resulting in a true air-core inductor. a 100-mm-diameter wafer with a reinforcing outer frame that
Photomicrographs of the fabricated inductors are shown in has the original substrate thickness. The robustness of the outer
Fig. 9 with two circular pads of 500 μm in diameter designed frame greatly facilitates mask handling, insertion, and removal.
for probing and electrical testing. The gap between the top Fabricated shadow-mask wafers have been reused over 30 times
radial conductors gradually widens from the inner and outer without failure. Furthermore, it should be emphasized that
edges of the trench to the middle to facilitate timely and uniform this process is batch-fabrication compatible, as six devices are
etching of the seed layer after electroplating. Well-patterned simultaneously fabricated with a single mask insertion. Denser
radial conductors with a constant gap of 100 μm at the bottom packing, smaller devices, or larger area substrates would lead
surface of the silicon trench can be clearly observed through the to greater batch sizes.
transparent epoxy.

III. I NTERCONNECT I NTEGRATION

C. Process Discussion
In order to electrically connect the embedded toroidal induc-
By using well-established conventional techniques, the tors to circuitry on the front side of the wafer for a PwrSoC
lithography-based approach enables batch fabrication and of- application, through-wafer interconnects can be implemented.
fers great design and fabrication flexibility. In this approach, The interconnect technique proposed here is compatible with
there are no techniques that are specific to the inductor device. both silicon-embedding approaches and can be integrated into
Therefore, the same set of techniques can be potentially applied the inductor fabrication process as shown in Fig. 10.
to fabricate other devices with device-oriented adjustments. The steps from the original inductor process are labeled with
Furthermore, devices with different embedding depths can be the same numbers as before, and the added steps for fabricating
also realized from batch to batch without changing the masks. the through-wafer interconnects are leveled in alphabetical or-
However, due to the processing of thick SU-8 epoxy that is der. After silicon trenches are formed in step 2, through-silicon
needed in forming a mold for the vertical copper conductors, vias and countersunk trenches for embedding the interconnects
the lithography-based approach is more time-consuming. In on the front side of the wafer can be then etched using a
addition, tens of hours are required to fill such a thick mold patterned photoresist mask and an oxide mask, respectively, as
using bottom–up electroplating. shown in steps (a)–(c). After forming the patterned seed layer
In the shadow-mask approach, the vertical conductors are in the trench in step 3, the metallization of the interconnect
simultaneously formed with the bottom radial conductors dur- trenches is completed through sputtering and liftoff of dry-film
586 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 3, JUNE 2013

Fig. 10. Process integration of through-wafer interconnects with

(a) lithography-based approach and (b) shadow-mask-based approach.
Added steps for fabricating the interconnects are labeled in letters with the
original steps labeled in numbers as previously shown.

Fig. 12. Measured L, R, and Q of the embedded toroidal inductors from the
lithography-based approach. The inductors have 25 turns, an inner diameter of
2 mm, an outer diameter of 6 mm, a height of 400 μm, and a 6-μm-thick oxide
insulation layer.

IV. C HARACTERIZATION R ESULTS

The electrical characterization of the embedded inductors
is performed with an impedance analyzer (HP4194) in the
frequency range of 100 kHz to 100 MHz. Results of the
fabricated inductors from the lithography-based approach are
shown in Fig. 12 and compared with an inductor that is partially
released in the trench in order to reduce the capacitive coupling
between the device and the substrate. The partial releasing is
achieved through an abrupt heating and cooling cycle such that
the inductor is still embedded in the silicon trench, yet an air gap
is introduced between some of the bottom radial windings and
the silicon substrate. An inductance of 60 nH, a dc resistance
of 400 mΩ, and a quality factor of 4.5 at 10 MHz is measured
Fig. 11. Through-wafer interconnects. (a) Front and (b) back sides of the for a completed inductor with 25 turns, an inner diameter of
structured silicon prior to electroplating. (c) Front side and (d) cross section 2 mm, an outer diameter of 6 mm, a height of 400 μm, and
of the completed through-wafer interconnects with a partially completed em-
bedded inductor.
a 6-μm-thick oxide insulation layer, as shown in Fig. 12. By
suppressing the capacitive coupling effect using partial release,
the inductor quality factor improves from 4.5 at approximately
photoresist as shown in step (d). With a patterned seed layer 10 MHz to 17.5 at approximately 70 MHz.
obtained in step 4, through-wafer interconnects and testing pads Upon verifying the significant effect of parasitic capacitance,
are simultaneously formed with the radial copper conductors inductors with a 12-μm-thick oxide insulation layer are fab-
as shown in step 5. The remaining steps for fabricating the ricated using the shadow-mask-based approach. The inductor
inductors are the same as discussed before and will not be had a height of 300 μm, and other geometric parameters were
repeated here. Results of the fabricated interconnects are shown maintained the same as for the lithography-based inductors.
in Fig. 11 with SEM images of the etched through-silicon vias The characterization results, as shown in Fig. 13, demonstrate
and microphotographs of the completed interconnects. an overall inductance of 45 nH, a dc resistance of 290 mΩ,
YU et al.: SILICON-EMBEDDING APPROACHES TO 3-D TOROIDAL INDUCTOR FABRICATION 587

with dry-film technique, and a shadow-mask-based approach

that employs a 3-D silicon shadow mask to enable direct metal
patterning on the vertical sidewalls of the trench. The success-
ful fabrication of embedded 3-D toroidal inductors has been
demonstrated with the characterization results that have
been presented. Although these fabrication approaches have
been demonstrated with the application goal of embedding
inductors for ultracompact PwrSoC, these concepts can be
extended to integrating other MEMS devices into the substrate
as well, such as resonators, sensors, RF filters, and microfluidic
devices.

ACKNOWLEDGMENT
Fig. 13. Measured L, R, and Q of the embedded toroidal inductor from the
shadow-mask approach. The inductor has 25 turns, an inner diameter of 2 mm, The authors would like to thank M. Araghchini and
an outer diameter of 6 mm, a height of 300 μm, and a 12-μm-thick oxide Prof. J. H. Lang of Massachusetts Institute of Technology, and
insulation layer. D. V. Harburg and Prof. C. R. Sullivan of Dartmouth College
for helpful technical discussions.
TABLE I
C OMPARISON OF THE M EASURED I NDUCTANCE AND Q UALITY
FACTOR OF VARIOUS S ILICON -E MBEDDED I NDUCTORS R EFERENCES
[1] K. Johguchi, T. Hatanaka, K. Ishida, T. Yasufuku, M. Takamiya,
T. Sakurai, and K. Takeuchi, “Through-silicon via design for a 3-D solid-
state drive system with boost converter in a package,” IEEE Trans. Com-
pon., Packag. Manuf. Technol., vol. 1, no. 2, pp. 269–277, Feb. 2011.
[2] K. Zoschke, T. Fischer, M. Topper, K. Samulewicz, O. Wunsch, J. Roder,
M. Lutz, O. Ehrmann, and H. Reichl, “Wafer level processing of inte-
grated passive components using polyimide or polybenzoxazole/
copper multilayer technology,” IEEE Trans. Adv. Packag., vol. 33, no. 2,
pp. 398–407, May 2010.
[3] H.-H. Lee and J.-Y. Park, “Characterization of fully embedded RF induc-
tors in organic SOP technology,” IEEE Trans. Adv. Packag., vol. 32, no. 2,
pp. 491–496, May 2009.
[4] T. Mori, M. Yamaguchi, S. Kuramochi, and Y. Fukuoka, “Development of
a new interposer including embedded thin film passive elements,” IEEE
Trans. Adv. Packag., vol. 32, no. 2, pp. 503–508, May 2009.
and a quality factor of 16 at 40 MHz. The improved quality [5] C. L. Roozeboom, J. Y. Sim, D. Wickeraad, B. Dura, W. S. Smith,
factor, compared with 4.5 of the unreleased inductor with thin M. A. Hopcroft, P. G. Hartwell, R. S. Williams, and B. L. Pruitt, “Multi-
functional integrated sensors for the environment,” in Proc. 25th IEEE Int.
insulation layer, further demonstrates the importance of para- Conf. MEMS, Paris, France, 2012, pp. 144–147.
sitics minimization. The inductor from the lithography-based [6] P. Galle, X. Wu, L. Milner, S.-H. Kim, P. Johnson, P. Smeys, P. Hopper,
process exhibits a higher inductance because of the taller profile K. Hwang, and M. G. Allen, “Ultra-compact power conversion based on a
CMOS-compatible microfabricated power inductor with minimized core
that was fabricated. Table I compares the measured inductance losses,” in Proc. 57th ECTC, Reno, NV, 2007, pp. 1889–1994.
and quality factor of the fabricated inductors in this paper [7] S. Mathuna, T. ODonnell, N. Wang, and K. Rinne, “Magnetics on silicon:
with the results of silicon-embedded inductors from literature. An enabling technology for power supply on chip,” IEEE Trans. Power
Electron., vol. 20, no. 3, pp. 585–592, May 2005.
Both flux-confined (e.g., toroidal) and nonflux-confined (e.g., [8] N. Chomnawang and J. B. Lee, “On-chip 3D air core microinductor for
solenoidal and planar) geometries are shown. high-frequency applications using deformation of sacrificial polymer,”
The integration of through-wafer interconnects with em- in Proc. SPIE Smart Struct. Mater.—Smart Electron. MEMS, Newport
Beach, CA, Mar. 2001, vol. 4334, pp. 54–62.
bedded inductors is also demonstrated using the lithography- [9] J. Yoon, B. Kim, C. Han, E. Yoon, and C. Kim, “Surface micromachined
based approach as an example. The fabricated device had an solenoid on-Si and on-glass inductors for RF applications,” IEEE Electron
inductance of 110 nH and a dc resistance of 1.3 Ω for an Device Lett., vol. 20, no. 9, pp. 487–489, Sep. 2009.
[10] F. Herrault, B. C. Yen, C.-H. Ji, Z. S. Spakovszky, J. H. Lang, and
inductor with 50 turns and a diameter of 8 mm [15]. M. G. Allen, “Fabrication and performance of silicon-embedded
permanent-magnet microgenerators,” J. Microelectromech. Syst., vol. 19,
pp. 4–13, Feb. 2010.
V. C ONCLUSION [11] C.-H. Ji, F. Herrault, P. Hopper, P. Smeys, P. Johnson, and M. G. Allen,
“Electroplated metal buried interconnect and through-wafer metal-filled
Complementary-metal–oxide–semiconductor-compatiblepro- via technology for high-power integrated electronics,” IEEE Trans. Adv.
cesses for embedding 3-D complex structures in deep silicon Packag., vol. 32, no. 3, pp. 695–702, Aug. 2009.
trenches with vertical walls has been presented, and through- [12] G. J. Burger, E. J. T. Smulders, J. W. Berenschot, T. S. J. Lammerink,
J. H. J. Fluitman, and S. Imai, “High resolution shadow mask patterning
wafer interconnect has been realized to demonstrate the poten- in deep holes and its application to an electrical wafer feed-through,” in
tial to electrically connect the device to circuitry on the wafer Proc. 8th Int. Conf. TRANSDUCERS, 1995, pp. 573–576.
surface. Two approaches have been developed for the silicon- [13] Y. C. Liang, W. Zeng, P. H. Ong, Z. Gao, J. Cai, and N. Balasubrama-
nian, “A concise process technology for 3D suspended radio frequency
embedding process, i.e., a lithography-based approach that micro-inductors on silicon substrate,” IEEE Electron Device Lett., vol. 23,
combines spray coating technique and thick epoxy processing no. 12, pp. 700–703, Dec. 2002.
588 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 3, JUNE 2013

[14] L. Gu and X. Li, “High-Q solenoid inductors with a CMOS-compatible Florian Herrault (M’12) received the B.S. and
concave-suspending MEMS process,” J. Microelectromech. Syst., vol. 16, M.S. degrees in physics and materials science from
pp. 1162–1172, Oct. 2007. the National Institute of Applied Sciences (INSA),
[15] X. Yu, M. Kim, F. Herrault, C.-H. Ji, J. Kim, and M. G. Allen, “Silicon- Toulouse, France, in 2003 and 2005, respectively,
embedded 3D toroidal air-core inductor with through-wafer interconnect and the Ph.D. degree in electrical and electronics en-
for on-chip integration,” in Proc. 25th IEEE Int. Conf. MEMS, Paris, 2012, gineering from the University of Toulouse, Toulouse,
pp. 325–328. in 2009.
[16] R. Wu and J. K. O. Sin, “A novel silicon-embedded coreless inductor for He is currently a Research Engineer with the
high-frequency power management applications,” IEEE Electron Device MicroSensors and MicroActuators Group, Georgia
Lett., vol. 32, no. 1, pp. 60–62, Jan. 2011. Institute of Technology, Atlanta, focusing on inte-
[17] T. Pan, A. Baldi, E. Davies-Venn, R. F. Drayton, and B. Ziaie, “Fabrica- grated magnetics for power supplies on a chip and
tion and modeling of silicon-embedded high-Q inductors,” J. Micromech. MEMS based biomedical implants.
Microeng., vol. 15, no. 4, pp. 849–854, Apr. 2005. Dr. Herrault has been a member of the technical program committee and a
[18] M. Paranjape, F. Giacomozzi, L. Landsberger, M. Kahrizi, B. Margesin, session cochair for the International Workshop on Power Supply on Chip 2010
B. Nikpour, and M. Zen, “A micromachined angled hall magnetic field and 2012, and the International Workshop on Micro and Nanotechnology for
sensor using novel in-cavity patterning,” in Proc. 9th Int. Conf. TRANS- Power Generation and Energy Conversion Applications (PowerMEMS) 2012.
DUCERS, 1997, pp. 397–400.
[19] J. Brugger, C. Andreoli, M. Despont, U. Drechsler, H. Rothuizen, and
P. Vettiger, “Self-aligned 3D shadow mask technique for patterning deeply
recessed surfaces of micro-electro-mechanical systems devices,” Sens.
Actuators A, Phys., vol. 76, no. 1–3, pp. 329–334, Aug. 1999. Chang-Hyeon Ji (M’06) received the B.S. and
[20] S. Morishita, J. H. Kim, F. Marty, Y. Li, A. J. Walton, and Y. Mita, “A M.S. degrees in electrical engineering and the Ph.D.
three-dimensional silicon shadow mask for patterning on trenches with degree in electrical engineering and computer sci-
vertical walls,” in Proc. 15th Int. Conf. TRANSDUCERS, Denver, CO, ence from Seoul National University, Seoul, Ko-
2009, pp. 1608–1611. rea, in 1995, 1997, and 2001, respectively. His
[21] S. Morishita, M. Kubota, and Y. Mita, “Integration of EWOD pumping doctoral dissertation concerned the design, fabrica-
device in deep microfluidic channels using a three-dimensional shadow tion, and testing of electromagnetic micromirrors for
mask,” in Proc. 25th IEEE Int. Conf. MEMS, Paris, France, 2012, microphotonic applications.
pp. 1045–1048. From 2001 to 2006, he was a Senior and Chief
[22] N. P. Pham, E. Boellaard, J. N. Burghartz, and P. M. Sarro, “Photoresist Research Engineer with the LG Electronics Institute
coating methods for the integration of novel 3-D RF microstructures,” J. of Technology, Seoul, where he developed microac-
Microelectromech. Syst., vol. 13, no. 3, pp. 491–499, Jun. 2004. tuators for various types of applications, including optical communication and
[23] S. Orlandi, B. Allongue, G. Blanchot, S. Buso, F. Faccio, C. Fuentes, raster scanning laser display systems. From 2006 to 2011, he was a Postdoctoral
M. Kayal, S. Michelis, and G. Spiazzi, “Optimization of shielded Printed Fellow at Georgia Institute of Technology, Atlanta, where he researched micro
circuit board(PCB) air-core toroids for high efficiency dc-dc converters,” power generators and energy scavengers, micromachined components and
in Proc. ECCE, San Jose, CA, 2009, pp. 2073–2080. through-wafer interconnection technology for integrated power electronics, and
[24] C. R. Sullivan, S. Prabhakaran, W. Li, and S. Lu, “Design and fabrication microfabricated components for wireless power transfer and energy storage.
of low-loss Toroidal air-core inductors,” in Proc. IEEE PESC, Jun. 2007, Since 2011, he has been with the faculty of the Department of Electronics
pp. 1754–1759. Engineering, Ewha Women’s University, Seoul, where he is currently an
[25] J. Kim, D. Weon, J. Jeon, S. Mohammadi, and L. P. B. Katehi, “Design Associate Professor. His current research interests include powerMEMS, bio-
of Toroidal inductors using stressed metal technology,” in MTT-S Int. MEMS, and nanofabrication technology.
Microw. Symp. Dig., 2005, pp. 705–708.
[26] C. Chung and M. G. Allen, “Uncrosslinked SU-8 as a sacrificial material,”
J. Micromech. Microeng, vol. 15, no. 1, pp. N1–N5, Jan. 2005.
Jungkwung Kim received the M.S. and Ph.D.
degrees in electrical engineering from the State
University of New York, Buffalo, in 2008 and
2011, respectively. His dissertation was focused on
Xuehong (Shannon) Yu received the B.S. degree
in electronic engineering from Zhejiang University, 3-D nano/microfabrication by ultraviolet lithography
with related bio, radio frequency, and optical appli-
Hangzhou, China, in 2006, and dual M.S. degrees,
cations.
one in microelectronics from Shanghai Jiaotong
He is currently a Postdoctoral Associate with
University, Shanghai, China, and one in electrical
and computer engineering from Georgia Institute of Georgia Institute of Technology, Atlanta, working on
power magnetic devices.
Technology, Atlanta, in 2009. She is currently work-
ing toward the Ph.D. degree in the MicroSensors
and MicroActuators Laboratory, Georgia Institute of
Technology, Atlanta with Dr. M. G. Allen.
Her research focus is on power microelectrome-
chanical systems, silicon-embedded magnetic components for power supplies
on chip, wireless energy transfer, and energy harvesters. Mark G. Allen (M’88–SM’04–F’11) received the
B.A. degree in chemistry, the B.S.E. degree in chem-
ical engineering, and the B.S.E. degree in electrical
engineering from the University of Pennsylvania,
Philadelphia, and the S.M. and Ph.D. (1989) de-
Minsoo Kim received the B.S. and M.S. degrees grees from Massachusetts Institute of Technology,
in electrical and computer engineering from Seoul Cambridge.
National University, Seoul, Korea, in 2006 and 2008, Since 1989, he has been with the faculty of the
respectively. He is currently working toward the School of Electrical and Computer Engineering,
Ph.D. degree at Georgia Institute of Technology, Georgia Institute of Technology, Atlanta, where he
Atlanta. currently holds the rank of Regents’ Professor and
Until 2009, he was with Korea Institute of In- the J.M. Pettit Professorship in Microelectronics, as well as a joint appointment
dustrial Technology and was involved in research in the School of Chemical and Biomolecular Engineering. His research interests
on inkjet-printed electronics. His current research are in the development and the application of new micro- and nanofabrication
focus is 3-D microfabrication technology based on technologies, as well as MEMS.
multilayer electrodeposition for the realization of a Dr. Allen is the Editor-in-Chief of the Journal of Micromechanics and Micro-
variety of passive and active devices. engineering and the previous cochair of the IEEE/ASME MEMS Conference.