A SIMPLIFIED APPROACH TO THE FIRST ORDER APPROXIMATIONS

OF A CLOSED LOOP, NON ISOLATED DC-DC CONVERTER WITH

SYNCHRONOUS RECTIFIER CIRCUIT BEHAVIOR BY USING THE
ORCAD PSPICE

Chandra Shetty1, Anil Kadle2, A.B.Raju3, Member IEEE

1
Dept. of Electrical Engg.,National Institute of Technology Karnataka
2
Dept. of Electrical Engg., Anjuman Institute of Technology and Management, Bhatkal
3
Dept. of Electrical Engg. B.V.B College of Engg. Hubli
E-mail: [email protected], 2 [email protected], 3
[email protected]

Abstract: In this paper, we present the significance of In some dc-dc converters, the rectifying diodes are
computer simulation program, such as ORCAD replaced by MOSFET’S, known as synchronous
PSPICE, in analyzing, first order approximations of rectifiers, to improve the efficiency of the converter and
circuit behavior, a closed loop, non-isolated dc-dc this paper describes simplified simulation process only
converter with synchronous rectifier circuit. Following for closed loop, non-isolated dc-dc converter with
techniques have been adopted to simplify the process of synchronous rectifier circuits. While the reported work
simulation. They are: (1) Ideal switches are incorporated in [1-5] is claimed to emphasize on circuit simulation of
in the power stage of the converter to eliminate the gate power electronic circuits, little attention has been given
diver requirement which in turn reduces the simulation to the detailed simulation of closed loop dc-dc converter
run time; (2) Diodes are connected in series with circuits. The proposed approach [6] adopts Pspice A/D
switches, which eliminates dead time control circuit, to where the circuit is described by statements and analysis
prevent cross conduction of switches and (3) TL494 commands, which makes simulation a cumbersome
Pspice model, which is readily available in library of process. In this paper, the schematic version of Pspice
most of the versions of the ORCAD PSPICE, is i.e., ORCAD PSPICE is adopted for the simulation.
employed for pulse width modulation. As an example, ORCAD PSPICE is having all the necessary tools
non-inverting synchronous buck boost converter is required for analyzing the power electronic converter
considered for demonstrating the approach. Simulation circuits. The device models of most of power electronic
was carried out for an input voltage range of 6 to 35V devices are readily available in Pspice library, which
and load resistance was varied from 12 to 48 Ohms. makes the simulation an easy process. The device
Output voltage was regulated at 12V for both input models can be used in the schematic capture with the
voltage and load current perturbation. Physical modifications of certain parameters depending on the
prototype was implemented and simulation result was requirement. Model editor tool is also provided along
tested for steady state output. with this software to edit the model of the devices to
meet the design specifications. User defined libraries
Keywords: ORCAD PSPICE, non-inverting can also be created which is an added advantage of this
synchronous buck boost converter, TL494, Sbreak software. The device Pspice models can be downloaded
Switch. from device manufacturer’s website if the required
device model is not provided in the Pspice library of the
INTRODUCTION ORCAD PSPICE as most of the manufacturers provide
Pspice model of their manufactured devices to support
Computer tools cannot replace the traditional methods the consumers for simulation and practical
for mastering the study of electric circuits. They can, implementation of the device. Some of the websites
however, assist in the learning process by providing a such as http://www.orcad.com/, http://www.ema-
visual representation of a circuit’s behavior, validating a eda.com/ e.t.c. have given, provided by the
calculated solution, reducing the computational burden manufacturers, the Pspice models of the certain devices
of more complex circuits, and iterating toward a desired whose Pspice models are not available on the Pspice
solution using parameter variation. This computational library of the few old version of the ORCAD PSPICE.
support is often invaluable in the design process. We can also find information about the application of
ORCAD PSPICE is one of the popular computer tool these device models with OrCAD capture on these
applied in electrical engineering. This software package websites.
includes different device models required for A comprehensive survey of ORCAD PSPICE in
simulation. the analysis, first order approximations of circuit
behavior, of a closed loop, non-isolated DC-DC
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converter with synchronous rectifier circuit presented NON- INVERTING SYNCHRONOUS BUCK
with the example, non-inverting synchronous buck BOOST CONVERTER
boost converter using voltage mode control. For
simulation purpose, Sbreak switch [7] is employed in The non-inverting synchronous buck boost converter
the power stage rather than actual device model for [10, 11] used as a design example to demonstrate the
simplifying the switching and TL494 Pspice model [8] significance of ORCAD PSPICE in analyzing a closed
is used for pulse width modulation. TL494 is one of the loop, non-isolated dc-dc converter with synchronous
most commonly used chips in power electronics rectifier circuit behavior. The circuit diagram of the
engineering for pulse width modulation. Actual device converter is shown in Fig. 1. Converter specification’s
model of TL494 is used for simulation as replacing it are: an input of 6-35V, an output of 12V, a load
with an equivalent ideal model would not give proper resistance of 12-48 Ohms, and f =100 KHz.
information about TL494 chip’s practical
implementation in laboratory. Thus, combining ideal Power Stage Design
model with actual device model for simulation offers
few advantages like elimination of cross conduction Selection of Inductor: The value of inductance is
without the requirement of dead time control circuit, chosen to assure continuous conduction mode and it is
exclusion of gate driver requirement, and reduction in designed for the worst-case input 6V and maximum
simulation time while keeping the simulation result of current of 1A [12].
the converter satisfactory.
The model parameters of all the elements used in ୫ୟ୶ ൌ ቀ౒౒౥శమ౒౩౭ ቁ
శ౒౥
(1)
౟౤
the circuit must be adjusted, if required, to meet the
ୈౣ౗౮
design requirement. The switches and diodes, employed – ୓୒ ൌ (2)
୤
in the power stage of the converter, are idealized by
setting ܴ௢௡ ൌ ͲǤͲͳπ for the switches and ݊ ൌ ͲǤͲͳ for The voltage across the inductor when the switch is ON
the diodes. Transient analysis and parametric sweep is
analysis [9] are adopted for carrying out the simulation
process. The experimental result of the converter’s ୓୒ ൌ ୍୒ െ ʹୗ୛ (3)
steady-state output confirms the simulation result. The So the voltsuseconds is
methodology proposed in this paper can also be adopted
for the simulation of other closed loop, non-isolated dc-
dc converter with synchronous rectifier circuits.

Fig. 1. Non inverting synchronous buck boost converter

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 ‘‘•– ൌ  െ  െ ͻͲ (8)
Ds<୓୒ ൈ – ୓୒ (4)  ൌ ሼ–ƒሾሺ‘‘•–ΤͶሻ ൅ Ͷͷሿሽଶ (9)
Using the ̶‫ ܮ‬ൈ ‫ ̶ܫ‬equation ʹ ൌ ͳȀሺʹɎˆ
ͳሻ (10)
ሺ ൈ ୐ ሻ ൌ –Τ” (5) ͳ ൌ ʹሺ െ ͳሻ (11)
୐ሺ୫ୟ୶ሻ ൌ ୓ሺ୫ୟ୶ሻ Τሺͳ െ ୫ୟ୶ ሻ (6) ʹ ൌ ξȀሺʹɎˆͳሻ (12)
Therefore, ͵ ൌ ͳȀሺ െ ͳሻ (13)
 ൌ –Τሺ” ൈ ୐ሺ୫ୟ୶ሻ ሻ (7) ͵ ൌ ͳȀሺʹɎˆξ͵ሻ (14)
Based on eq. (1) to eq. (7), the values obtained From eq. (8) to eq. (14), the compensating component
are:୫ୟ୶ ൌ ͲǤ͸ͺ,– ୓୒ ൌ ͸Ǥ͹ͺ—•,– ൌ values obtained are: Boost =ͳͳͻǤ͸Ͳ͸ι , choose ܴଵ ൌ
͵ͻǤ͵ʹͶ˜‘Ž–•—•‡…‘†•,  ൈ ୐ ൌ ͻͺǤ͵ͳ—• for the ripple ͳͲ‫ܭ‬π, ʹ ൌ ͳ͵ͷǤͷ’ˆ, ͳ ൌ ͳ͹͵ͶǤͶ’ˆ, ʹ ൌ ͵Ͷπ,
factor of ‫ ݎ‬ൌ ͲǤͶ,୐ሺ୫ୟ୶ሻ ൌ ͵Ǥͳ͵ since ୓ሺ୫ୟ୶ሻ ൌ ͳ , ͵ ൌ ͹ͺͳǤʹͷπ, ͵ ൌ ͷǤͶͺˆ.
 ൌ ͵ͳǤͶ—. 4) Verification of above designed component values
The value of inductor selected is 47uH. for desired phase margin and gain at cross over
Selection of Capacitor: The value of capacitor chosen frequency using PSPICE simulation.
is 220uF. A Pspice simulation of the control loop in Fig. 4 gives
ESR of Filter Components: The measured value of the the desired phase margin of approximately ͻͲι and gain
ESR of the inductor is 0.2ohm. The ESR of the of approximately 0dB as shown in the Fig. 5, verifying
capacitor is assumed as 0.1ohm. the design.
Feedback Compensation: The K-factor approach [13]
has been adopted for designing the compensation Sampling Network
component values. Type-3 error amplifier is used to get
enough phase boost. The following is a design Assume a reference voltage of 2V and choose  ୠ୧ୟୱ ൌ
procedure for the type3 compensated error amplifier ʹπ. Using the voltage divider rule,
[14]. ୭ Τ୰ୣ୤ ൌ  ሺ ୠ୧ୟୱ ൅  ସ ሻΤ ୠ୧ୟୱ (15)
1) Choose the Crossover Frequency. The obtained value of  ସ is ͳͲ‫݄݉݋ܭ‬
The crossover frequency of the total open-loop transfer
function (the frequency where the gain is 1, or 0 dB)
should be well below the switching frequency. Let
݂௖௢ ൌ ͳͲ݇‫ݖܪ‬.

Fig. 2. The ac circuit used to determine the frequency

response
Fig. 3. Gain and phase plot without compensation
2)A Pspice Simulation to determine the Gain and
Phase angle at ܎‫ ܗ܋‬.
The ac circuit used to determine the frequency response
is shown in Fig. 2. AC sweep analysis option from
simulation setting is chosen to obtain the frequency
response by varying the frequency from 10Hz to 100
KHz as shown in Fig. 3. A PSPICE simulation of the
frequency response of the filter with load resistor (Fig.
3) shows that the converter gain at 10 kHz is -11.922dB
and phase angle isെͳͳͻǤ͸Ͳ͸ι. The PWM converter has
a gain of ͳȀܸ௣ ൌ ͳȀ͵ ൌ െͻǤͷ݀‫ܤ‬. The combined gain of
the filter and PWM converter is then -11.922dB - 9.5dB
= -21.5dB.
3) Computation of component values of error
amplifier based on the above information.
G = Amplifier gain at cross-over = 21.5dB
Fig. 4. The ac circuit for determining the frequency
M = Desired Phase Margin (degrees) = ͻͲι
response with compensation
P = Modulator Phase Shift (degrees) = െͳͳͻǤ͸Ͳ͸ι
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 Fig. 5. Gain and phase plot with compensation

DISCUSSION ON ORCAD SCHEMATIC OF THE device model. The Pspice model of this chip is available
CONVERTER AND SIMULATION MODELS OF in controller.olb.
THE DEVICES We have to modify the parameters such as
frequency, reference voltage etc as shown in the
Power Stage schematic of the PWM stage. For the TL494 family
chip’s, the reference voltage is given to inverting
The schematic diagram of power stage of the converter terminal as they are having opposite internal sense [13,
is shown in Fig. 6. The swiches of converter are 15]. The reference voltage for error amplifier obtained
implimented using ‘Sbreak Switch’ model. The diode is using voltage divider circuit from the TL494 internal 5V
connected in series with switch to prevent the reverse reference regulator [15]. Soft start circuit [15] is also
conduction of the switch. The series connected diodes integrated in the PWM stage. The control signals for M1
also prevent simultaneous conduction of switches and M2 are tapped using emitter follower configuration
(OFFPAGELEFT-1). The switching signals for M3 and
without the need of additional dead time control circuit,
M4 are obtained from common emitter configuration
which reduces the complexity of the design as well as
(OFFPAGELEFT-2). The unwanted pins of the chip are
the simulation run time for steady state output. ‘Off connected to ground with high resistances.
page connectors’ [9] are used for connecting the whole
project drawn on different pages. SIMULATION RESULTS
Sbreak Switch: Sbreak switch Pspice model is give by
“.model Sbreak Vswitch Roff=1e6 Ron=0.01 Voff=0.0 Simulation is carried out for input variation of 6V to
Von=1.0”. Here we have to edit the Sbreak switch 35V and load current variation of 0.25A to 1A. The
model to make it an ideal switch. simulation run time given is 10ms to get the steady state
Diode: For simulation purpose, Dbreak is used which output but run time of 5ms would have been enough to
works approximately as an ideal diode [14] with get the steady state output, which would save the time.
emission coefficient n=0.001. The default value of To avoid the convergence problem, following changes
emission coefficient in the vendor model is n=1. has been made to .OPTIONS settings RELTOL=0.001,
Capacitor and Inductor: For capacitor and inductor’s, VNTOL=10u, ABSTOL= 0.001u, CHGTOL=0.01p,
we can use PSPICE model from PSPICE library [7] GMIN=0.1n, ITL1=1000, ITL2=1000, ITL4=1000.
breakout.olb. The Fig. 8 shows simulation result for the input range of
6V to 35V (i.e., 6V, 10V, 15V, 20V, 25V, 30V, and
PWM Stage 35V) and maximum load current of 1A using transient
and parametric sweep analysis. The similar simulation
The schematic of the PWM stage is shown in Fig. 7. results can also be obtained for different load currents
“Off Page Connectors” are used for connecting by changing the load resistance in the schematic of the
compensating elements to the error amplifier of TL494. power stage. Fig. 9 shows load voltage, inductor
We can directly use TL494 Pspice model given by the current, and capacitor current for maximum load current
software vendors without editing the model except few and worst-case input. Switching signals for M1, M2,
required parameters variations on the schematic of the M3, and M4 for worst-case input 6V and maximum
current of 1A is shown in Fig. 10.
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 Fig. 6. Pspice schematic of the power stage

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 Fig. 7. Pspice schematic of the PWM Stage

Fig. 8. Simulation result for input range of 6V to 35V (i.e., 6V, 10V, 15V, 20V, 25V, 30V, and 35V) and maximum
current of 1A using transient and parametric sweep analysis

Fig. 9. Load voltage, inductor current, and capacitor current for maximum load current of 1A and worst-case input of
6V

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HARDWARE IMPLEMENTATION amplitude causes a corresponding linear decrease of
output pulse width. The operating waveform is shown
For hardware implementation, TL494 [15] is employed in Fig. 12.
for pulse width modulation, IR2110 [16] is used as a The converter switching frequency is 100Khz.
gate driver, and IRF150 as a switch. Choose ்ܴ ൌ ͳͲ‫ܭ‬π and substitute in eq. 17 to get
‫ ்ܥ‬ൌ ͳͲͲͲ‫݂݌‬. Soft start circuit [15] is incorporated in
PWM Module the PWM stage to reduce stress on the switching
transistors at start up.
The TL494 is a fixed–frequency pulse width modulation
control circuit, incorporating the primary building Driver Circuit
blocks required for the control of a switching power
supply. The basic circuit diagram is shown in Fig.11. The output of the TL494 can’t be used directly to drive
TL494 has 16 pins. Its operating frequency is the MOSFETS as the outputs are referenced to the
1~300kHz. An internal linear sawtooth oscillator is ground. IR2110 is chosen to drive the MOSFETS. It
frequency–programmable by two external components, can drive the high side MOSFET with the help of
RT and CT. The oscillator frequency is determined by: bootstrap circuit, which creates floating supply for the
high side MOSFET from the ground referenced
݂ைௌ஼ ؆ ͳǤͳΤ்ܴ ‫்ܥ‬ (16) switching signal, the output of TL494.
Each IR2110 gate driver can drive one high side
Output pulse width modulation is accomplished by MOSFET and one low side MOSFET. Consequently,
comparison of the positive saw tooth waveform across two IR2110 gate drivers are required for operating all
capacitor CT to either of two control signals. The NOR the four switches of the converter. Resistor diode
gates, which drive output transistors Q1 and Q2, are network [16], which introduces dead time, employed for
enabled only when the flip–flop clock–input line is in low preventing simultaneous conduction of the low side and
state. This happens only during that portion of time high side MOSFET’S. The full schematic diagram of
when the saw tooth voltage is greater than the control the experimental prototype is shown in Fig. 13.
signals. Therefore, an increase in control–signal

Fig. 10. Switching signals for M1, M2, M3, and M4 for worst-case input 6V and maximum current of 1A

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 Fig. 11. The Basic Circuit Diagram of TL494

Fig.12. Operating Waveforms

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 Fig.13. Full schematic diagram of the converter prototype

TESTING OF SIMULATION RESULTS other closed loop, non-isolated dc-dc converter with
synchronous rectifier circuits. In summary, the
The simulated result was tested, by implementing the development of the converter has been very comfortable
physical prototype converter, for the steady state output. by using the ORCAD PSPICE with the adaptation of
The regulation is satisfactory for full range of input simple simulation teqniques.
voltage with lower load currents. At higher load
currents, regulation is maintained only for higher input ACKNOWLEDGEMENTS
voltages due to practical limitations.
‘National Institute of Technology Karnataka’, India,
CONCLUSION supported this work.

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