5 4 3 2 1

CPU DC/DC
Spears Intel UMA Block Diagram 2008/01/14 ISL6262A 41, 42

INPUTS OUTPUTS
Project code : 91.4W001.001 DCBATOUT VCC_CORE_S0
Intel CPU
D
PCB P/N : 07211 D

CLK GEN Merom 4M SYSTEM DC/DC

ICS9LPRS365 FSB:667MHz/800MHz
Revision : -3 TPS5117 43, 44

4 5,6,7
INPUTS OUTPUTS
RGB CRT CRT 17
1D05V_S0
Host BUS DCBATOUT
1D8V_S3
533/667/800MHz
LVDS LCD 18

DDRII Slot 0 SYSTEM DC/DC

40
14
DDRII 667 Channel A Crestline-GM TPS51120
533/667 S-Vedio
SVIDEO 16
AGTL+ CPU I/F DDR I/F (Upsell) INPUTS OUTPUTS
DDRII Slot 1 INTEGRATED GRAHPICS 5V_AUX_S5
DDR II 667 Channel B 3D3V_AUX_S5
15
533/667 LVDS, CRT I/F 8,9,10,11,12,13
PCIE x 16 SiI 1392 HDMI DCBATOUT 5V_S5
3D3V_S5
SDVO 23 16
(Upsell) (Upsell)
C C
Power SW SYSTEM DC/DC
DMI I/F 28 45
TI TPS2231 TPS51100
100MHz
INPUTS OUTPUTS
1394 DDR_VREF_S0
26
1394 PCIE x 1 & USB 2.0 x 1
1D8V_S3 DDR_VREF_S3
INTEL AZALIA
New Card 28
Ricoh PCI
R5C833 SYSTEM DC/DC
SD/SDIO/MMC 10/100 NIC
MS/MS Pro/xD26 CardReader
25,26
ICH8-M PCIE x 1
Marvell 88E8040 27 RJ45 CONN 28 LDO 45

INPUTS OUTPUTS
10 USB 2.0/1.1 ports Mini-Card X2
PCIE PCIE x 2 & USB 2.0 x 1
802.11a/b/g 29 3D3V_S0 2D5V_S0
6 PCI Express ports 30
BT/UWB/Robson
RJ11 CONN MDC MODEM High Definition Audio 1D8V_S3 1D5V_S0
AZALIA PCIE x 1 & USB 2.0 x 1 Mini-Card X1
28 31 30
(Option) (Option) ATA 66/100
WWAN(Upsell)
1D8V_S4 1D25V_S0

SATA
ACPI 1.1 USB 2.0 USB 2.0 x 1 CAMERA
B MAXIM CHARGER B
18 39
HP2 LPC I/F (Option) MAX8731A
OP AMP INPUTS OUTPUTS
MAX4411 33
PCI/PCI BRIDGE
USB 2.0 x 1 Bluetooth 2.131
AD+
LPC Bus DCBATOUT
19,20,21,22
Lift Side: USB x 38
2 BT+
USB 2.0 x 4
Right Side:
Azalia SPI USB x 1
Digital Mic Array USB x 1(Upsell) 35
CODEC KBC
Winbond WPC8763L
MIC IN Sigmatel
SATA

PATA

34
STAC 9228
32
Internal Analog MIC

HP1
Thermal
Capacity Touch Int. S/W Flash ROM
A HDD ODD & Fan <Core Design> A
Button37 Pad 37 KB37 CIR 31 2MB 35
OP AMP 24 24
G792 36
2CH
MAX9789A Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SPEAKER 33 Taipei Hsien 221, Taiwan, R.O.C.

Title

DS2 System Block Diagram

Size Document Number Rev
A3
Spears-Intel -3
Date: Monday, January 21, 2008 Sheet 1 of 47
5 4 3 2 1
 5 4 3 2 1

TI TPS51120
CPU_CORE 3D3V/5V
ISL6262A 1D5V_S0
Input Signal Output Signal
VID Setting Output Signal 5V_S5
VID0 VCNTL
VID0(I / 3.3V) VRPWRGD 1D5V_S0
VROK(O) 3V/5V_EN FOR VOUT(O)
D VID1 51120_EN2 3.3V 1D8V_S3 D
VID1(I / 3.3V) CLK_EN# CPUCORE_ON(Pull High 3D3V) VIN
CLK_EN#(O) PGOUT1(OD / 5V)
VID2 51120_EN1 FOR
VID2(I / 3.3V) 5.0V PGOUT2(OD / 3D3V) PM_SLP_S3# CPUCORE_ON
EN POK
VID3
VID3(I / 3.3V)
Output Power
VID4 G971
VID4(I / 3.3V) VCC_CORE_S0(Imax=35A)
VCC_CORE_PWR(O)
VID5 DCBATOUT
VID5(I / 3.3V) VIN
VID6
VID6(I / 3.3V) 5V_AUX_S5 2D5V_S0
Input Signal Input Power Output Power
CPUCORE_ON 3D3V_S0 2D5V_S0
EN (I / 3.3V) INPUT OUT
3D3V_AUX_S5
DCBATOUT
Voltage Sense VIN G9131
5V_S5 (6A)
VCC_SENSE 5V(O)
VSEN(I / Vcore) 5V_AUX_S5 1D25V_S0
C
V5FILT(I / 5V) C
VSS_SENSE
RGND(I / Vcore) 3D3V_S5 (5A) 5V_S5
3D3V(O) VCNTL
1D25V_S0
VOUT(O)
Input Power 1D8V_S3
VIN
DCBATOUT
VCC(I)
PM_SLP_S3# CPUCORE_ON
EN POK
5V_S0
VCC(I)
Adapter
3D3V_S0 G966
VCC(I) Input Signal Output Signal Charger_MAX8731A
AD_OFF AD_IN
(I) (O)
Input Signal Output Signal
CHARGE_OFF MAX8731_LDO
CLS (I / 3.3V) LDO (O / 5.4V)
Input Power Output Power
AD_JK AD+ ACAV_IN
VIN(I) VCC(O) (O)
BAT+SENSE
B
5V_AUX_S5 BATT (I / 3.3V) AC_IN# B
VCC(I) (O)
TI TPS51100 BT_SCL
SCL (IO / 5V)
0.9V/DDR_VREF_S3 BT_SDA
SDA (IO / 5V)
TPS51117_1D8V_S3 Output Power
Input Signal DCBATOUT
PM_SLP_S4# VCC (O)
S5
PM_SLP_S3#
S3 Input Signal Output Signal BT+
PM_SLP_S4# VCC (O)
EN_PSV(I / 5V) CPUCORE_ON AC_IN
PGOUT(OD / 5V) PB0/MOSI/AIN0
Output Power

DDR_VREF_S3 5V_S5 Input Power Output Power Input Power

VCC(O) VCC 1D8V_S3 AD+
Input Power 1D8V_PWR DCIN (I)
DCBATOUT
VIN
5V_S5 DDR_VREF_S0
VCC(I) VCC(O) TPS51117_1D05V
1D8V_S3
A VIN(I) <Core Design> A
Input Signal Output Signal
PM_SLP_S3#
EN_PSV(I / 5V) CPUCORE_ON Wistron Corporation
PGOUT(OD / 5V) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

5V_S5 Input Power Output Power Title

VCC 1D05V_S0 (15A) Power Block Diagram
1D05V_PWR Size Document Number Rev
DCBATOUT A3
VIN DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 2 of 47
5 4 3 2 1
 5 4 3 2 1

INTEL ICH8-M STRAP PIN

20,22 +RTCVCC +RTCVCC

5,6,7,8,10,11,12,20,22,34,43,47 1D05V_S0 1D05V_S0

Signal Usage/When Sampled Comment XOR Chain Entrance Strap
ICH_RSVDtp3 8,11,22,45 1D25V_S0 1D25V_S0
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 AZ_DOUT_ICH Description
PCIE Port Config 1 bit1, pulled low at rising edge of PWROK.When TP3 not 0 0 RSVD
27 1D2V_LAN_S5 1D2V_LAN_S5
0 1 Enter XOR Chain
Rising Edge of PWROK pulled low at rising edge of PWROK,sets bit1 of Normal Operation(default)
1 0 28 1D5V_NEW_S0 1D5V_NEW_S0
D RPC.PC(Config Registers:offset 224h) 1 1 Set PCIE port cofig bit1 D
HDA_SYNC PCIE Port Config 1 bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h) 6,11,20,21,22,28,29,30,45 1D5V_S0 1D5V_S0
Rising Edge of PWROK.
8,11,12,14,15,44,45,46,47 1D8V_S3 1D8V_S3
GNT2# PCIE Port Config 2 bit0, Sets bit2 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK. 27,28 2D5V_LAN_S5 2D5V_LAN_S5

GPIO20 Reserved Weak Internal PULL-DOWN.NOTE:This signal should

not be pull HIGH. 20,31,34,35,36,38,39,40,47 3D3V_AUX_S5 3D3V_AUX_S5
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap 27,28 3D3V_LAN_S5 3D3V_LAN_S5
GNT3# Top-Block Swap Override. cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the PCI_GNT#3 low = A16 swap override enable 4,8,10,11,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,40,41,43,45,46,47 3D3V_S0 3D3V_S0
Top-Swap bit until the system is rebooted high = default
19,21,22,27,28,31,35,36,38,40,46,47 3D3V_S5 3D3V_S5
without GNT3# being pulled down. BOOT BIOS Strap
PCI_GNT#0 SPI_CS#1 BOOT BIOS Location 18,39,40,47 5V_AUX_S5 5V_AUX_S5
GNT0# Boot BIOS Destination Controllable via Boot BIOS Destination bit
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). 0 1 SPI
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 0 PCI
1 1 LPC(Default) 16,17,18,22,24,33,35,36,37,41,45,46,47 5V_S0 5V_S0
Integrated VccSus1_05
VccSus1_5 and VccCL1_5 Enables integrated VccSus1_05,VccSus1_5 and integrated VccSus1_05,VccSus1_5,VccCL1_5 22,24,29,30,31,35,38,40,43,44,45,46,47 5V_S5 5V_S5
INTVRMEN VRM Enable/Disable.Always VccCL1_5 VRM when sampled high
SM_INTVRMEN High=Enable Low=Disable 38,39,47 AD+ AD+
sampled.
integrated VccLan1_05VccCL1_05 18,39,40,41,42,43,44,46,47 DCBATOUT DCBATOUT
Integrated VccLAN1_05 Enables integrated VccLAN1_05,VccCL1_05 VRM
C LAN100_SLP VccCL1_05 VRM enable when sampled high LAN100_SLP High=Enable Low=Disable 14,15,45,47 DDR_VREF_S0 DDR_VREF_S0
C

/Disable. Always sampled.

8,14,15,45 DDR_VREF_S3 DDR_VREF_S3
SATALED# PCIE LAN REVERSAL.Rising This signal has weak internal pull-up. DEFAULE HIGH
Edge of PWROK. set bit27 of MPC.LR(Device28:Function0:Offset D8)
18 +LCDVDD +LCDVDD
If sampled high, the system is strapped to the No Reboot Strap
SPKR No Reboot. "No Reboot" mode(ICH8M will disable the TCO Timer SPKR LOW = Defaule 6,7,42 VCC_CORE_S0 VCC_CORE_S0
Rising Edge of PWROK. system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
High=No Reboot

TP3 XOR Chain Entrance. This signal should not be pull low unless using
Rising Edge of PWROK. XOR Chain testing.
Internal Pull-Up.If sampled low,the Flash Descriptor
INTEL ICH8-M INTEGRATED
GPIO33/ Flash Descriptor Security Security will be overidden.if high,the Security
HDA_DOCK_EN# Override Strap
Rising Edge of PWROK.
measures defined in the Flash Descriptor will be in
effect.
8.2K PULL HIGH
PULL-UPS and PULL-DOWNS
This should only be used in manufacturing
environments SIGNAL Resistor Type/Value
HDA_BIT_CLK PULL-DOWN 20K
HDA_RST# NONE
HDA_SDIN[3:0] PULL-DOWN 20K
B B
HDA_SDOUT PULL-DOWN 20K
HDA_SYNC PULL-DOWN 20K
INTEL CRESTLINE STRAP PIN GNT[3:0]
GPIO[20]
PULL-UP 20K
PULL-DOWN 20K
CFG Strap LOW 0 HIGH 1 LDA[3:0]#/FHW[3:0]# PULL-UP 20K
CFG 5
DMI X 2 DMI X 4 ★ LAN_RXD[2:0] PULL-UP 20K
CFG 8
Low Power PCI Express Normal★ Low Power mode LDRQ[0] PULL-UP 20K
CFG 9
PCI Express Graphics Lane Reversal Normal Mode(Lanes★ LDRQ[1]/GPIO23 PULL-UP 20K
Lane Reversal number in order)
CFG 16 PME# PULL-UP 20K
FSB Dynamic ODT Disabled Enabled ★
CFG 19 PWRBTN# PULL-UP 20K
DMI Lane Reserved Normal Operation ★ Reserved Lane
CFG 20 Only PCIE or SDVO PCIE and SDVO are SATALED# PULL-UP 20K
Concurrent SDVO/PCIE is operation ★ operation simultaneous
SPI_CS1# PULL-UP 20K
SDVO_CTRL_DATA NO SDVO Card SDVO Card Present
Present ★ SPI_CLK PULL-UP 20K
SDVO Present
SPI_MOSI PULL-UP 20K
CFG 12 XOR/ALL-Z
A CFG 13 SPI_MISO PULL-UP 20K <Core Design> A
LL(00) Reserved
LH(01) XOR Mode Enabled TACH_[3:0] PULL-UP 20K
HL(10) All Z Mode Enabled
HH(11) Normal Operation SPKR PULL-DOWN 20K Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
TP[3] PULL-UP 20K Taipei Hsien 221, Taiwan, R.O.C.

USB[9:0][P,N] PULL-DOWN 15K Title

CL_RST# TBD Table of Content

Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 3 of 47
5 4 3 2 1
 3D3V_S0 5 3D3V_S0_CK505 4 3 2 1
2 1 3D3V_S0_CK505 3D3V_S0_CK505_IO
R127 0R0603-PAD
1

1
C222 C219 C527 C549 C523 C529 C537
SC1U10V3KX-3GP

SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
X3
CLK_XTAL_IN 1 2 CLK_XTAL_OUT

X-14D31818M-37GP

1
D C214 C211
D
SC15P50V2JN-2-GP SC15P50V2JN-2-GP

2
U24

16

46
62
23

19
27
43
52
33
56
4

9 VDDPCI
VDDREF
VDD48

VDDPLL3

VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDSRC
VDDCPU
3D3V_S0 61 CLK_CPU_BCLK1 RN25 1 4 SRN0J-6-GP CLK_CPU_BCLK 5
3D3V_S0_CK505_IO CPUT0 CLK_CPU_BCLK1#
CPUC0 60 2 3 CLK_CPU_BCLK# 5
CLK_XTAL_IN 3 58 CLK_MCH_BCLK1 RN26 1 4 SRN0J-6-GP CLK_MCH_BCLK 8
C566 SC4D7P50V2CN-1GP CLK_XTAL_OUT X1 CPUT1_F CLK_MCH_BCLK1#
2 1 2 X2 CPUC1_F 57 2 3 CLK_MCH_BCLK# 8
R128 0R0603-PAD
1 2 54 CLK_PCIE_MINI3_1 RN27 1 4 SRN22-3-GP CLK_PCIE_MINI3 30
CPUT2_ITP/SRCT8
1

1
C227 C525 C524 C533 C548 C550 53 CLK_PCIE_MINI3_1# 2 3 CLK_PCIE_MINI3# 30
C231 FSA CPUC2_ITP/SRCC8
21 CLK_48M_ICH 1 2 17 USB_48MHZ/FSLA
SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
SC1U10V3KX-3GP

R383 33R2J-2-GP 51 CLK_PCIE_LAN1 RN28 1 4 SRN0J-6-GP CLK_PCIE_LAN 27

SRCT7/CR#_F CLK_PCIE_LAN1#
DY SRCC7/CR#_E 50 2 3 CLK_PCIE_LAN# 27
21 H_STP_PCI# 45 PCI_STOP#
44 48 CLK_PCIE_MINI1_1 RN29 1 4 SRN22-3-GP CLK_PCIE_MINI1 29
21 H_STP_CPU# CPU_STOP# SRCT6 CLK_PCIE_MINI1_1#
SRCC6 47 2 3 CLK_PCIE_MINI1# 29
41 CLK_PCIE_NEW1 2 3 CLK_PCIE_NEW 28
SRCT10 CLK_PCIE_NEW1#
14,15,21 ICH_SMBCLK 7 SCLK SRCC10 42 1 4 CLK_PCIE_NEW# 28
6 RN30 SRN0J-6-GP
1 2
14,15,21 ICH_SMBDATA SDATA 3D3V_S0
40 R371 10KR2J-3-GP
SRCT11/CR#_H R375 1 NEWCARD_CLKREQ# 28
21 CK_PWRGD 63 CK_PWRGD/PD# SRCC11/CR#_G 39 2
C 37 CLK_PCIE_MINI2_1
RN31
2 3
DY 10KR2J-3-GP
CLK_PCIE_MINI2 30
C
SRCT9 CLK_PCIE_MINI2_1#
SRCC9 38 1 4 CLK_PCIE_MINI2# 30
8 SRN22-3-GP
21 CLKSATAREQ# PCI0/CR#_A CLK_MCH_3GPLL1
8 CLKREQ#_B 10 PCI1/CR#_B SRCT4 34 2 3 CLK_MCH_3GPLL 8
PCI2_TME 11 35 CLK_MCH_3GPLL1# 1 4 CLK_MCH_3GPLL# 8
R370 1 PCI2/TME SRCC4 RN32 SRN0J-6-GP
25 PCLK_PCM 2 33R2J-2-GP PCLK_PCM_R 12
PCI3
34 PCLK_KBC R379 1 2 33R2J-2-GP 27_SEL 13 31 CLK_PCIE_ICH1 2 3 CLK_PCIE_ICH 21
R382 1 PCI4/27_SELECT SRCT3/CR#_C
19 CLK_PCI_ICH 2 33R2J-2-GP ITP_EN 14 PCI_F5/ITP_EN SRCC3/CR#_D 32 CLK_PCIE_ICH1# 1 4 CLK_PCIE_ICH# 21
RN36 SRN0J-6-GP

28 CLK_PCIE_SATA1 2 3 CLK_PCIE_SATA 20
SRCT2/SATAT CLK_PCIE_SATA1#
R355 SRCC2/SATAC 29 1 4 CLK_PCIE_SATA# 20
FSB 64 RN35 SRN0J-6-GP
FSC FSLB/TEST_MODE
21 CLK_14M_ICH 1 2 5 REF0/FSLC/TEST_SEL
24 MCH_SSCDREFCLK1 2 3 MCH_SSCDREFCLK 8
27MHZ_NONSS/SRCT1/SE1
1

1
C540

C545

C552

C526

55 25 MCH_SSCDREFCLK1# 1 4 MCH_SSCDREFCLK# 8
33R2J-2-GP NC#55 27MHZ_SS/SRCC1/SE2 RN34 SRN0J-6-GP
20 CLK_MCH_DREFCLK1 2 3

GNDSRC
GNDSRC
GNDSRC
GNDCPU
CLK_MCH_DREFCLK 8

GNDREF
2

SRCT0/DOTT_96

GNDPCI
3D3V_S0_CK505 Please place R10 near U1 pin5 21 CLK_MCH_DREFCLK1# 1 4

GND48
SRCC0/DOTC_96 RN33 SRN0J-6-GP CLK_MCH_DREFCLK# 8
SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

GND

GND

GND
1

18
15
1

22
30
36
49
59
26

65
R374 ICS9LPRS365BKLFT-GP
10KR2J-3-GP
2

PCI2_TME

B Main source : 71.09365.A03 ICS9LPRS365CKLFT SC:08/11 Add EC165,EC166 on

B
1

2nd source:71.00875.A03 RTM875N-606-LF CLK_MCH_DREFCLK -/+ pair .

R373
10KR2J-3-GP CLK_MCH_DREFCLK
DY
27_SEL NEWCARD_CLKREQ# CLK_MCH_DREFCLK#
2

1
FS_C FS_B FS_A CPU R378 EC119 EC165 EC166
10KR2J-3-GP SC22P50V2JN-4GP

SC47P50V2JN-3GP

SC47P50V2JN-3GP
PCI2_TME Output DY DY

2
1 0 1 100M

2
0 Overclocking of CPU and SRC allowed 0 0 1 133M
0 1 0 200M
0 1 1 166M
1 Overclocking of CPU and SRC not allowed

ITP_EN Output 1 2 FSC 27_SEL strap 0:For 965GM, 1:For 965PM

ITP_EN 6 CPU_BSEL2 R360 2K2R2J-2-GP
1 2 FSB 27_SEL PIN 20 PIN 21 PIN 24 PIN 25
0 SRC8 6 CPU_BSEL1
1

R353 0R0402-PAD
R380 1 CPU_ITP 1 2 FSA
965GM
10KR2J-3-GP 6 CPU_BSEL0 R386 2K2R2J-2-GP 0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100
1 SRCT0 SRCC0 27M_NSS 27M_SS 965PM
R385 1 2 0R0402-PAD MCH_CLKSEL0 8
2

R352 1 2 0R0402-PAD MCH_CLKSEL1 8

<Variant Name>
A R359 1 2 0R0402-PAD MCH_CLKSEL2 8 A
SA:0430 Wistron Corporation
Design Note: 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1. All of Input pin didn't have internal pull up resistor.
Title
2. Clock Request (CR) function are enable by registers.
3. CY28548 integrated serial resistor of differential clock, Clock generator ICS9LPRS365
so put 0 ohm serial resistor in the schematic. Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 4 of 47
 5 4 3 2 1

8 H_A#[3..35]
U45A 1 OF 4

H_A#3 J4 H1 H_ADS# 1D05V_S0

A3# ADS# H_ADS# 8
D H_A#4 L5 E2 H_BNR# D
A4# BNR# H_BNR# 8
H_A#5 L4 G5 H_BPRI#
A5# BPRI# H_BPRI# 8

ADDR GROUP 0
H_A#6 K5 A6#

1
H_A#7 M3 H5 H_DEFER#
A7# DEFER# H_DEFER# 8
H_A#8 N2 F21 H_DRDY# R235

CONTROL
A8# DRDY# H_DRDY# 8 56R2J-4-GP
H_A#9 J1 E1 H_DBSY#
A9# DBSY# H_DBSY# 8
H_A#10 N3
H_A#11 A10# H_BR0#
P5 F1 H_BR0# 8

2
H_A#12 A11# BR0#
P2 A12#
H_A#13 L2 D20 H_IERR#
H_A#14 A13# IERR# H_INIT#
P4 A14# INIT# B3 H_INIT# 20
H_A#15 P1
H_A#16 A15# H_LOCK#
R1 A16# LOCK# H4 H_LOCK# 8
H_ADSTB#0 M1
8 H_ADSTB#0 ADSTB0#
C1 H_RESET#
RESET# H_RESET# 8
H_REQ#0 K3 F3 H_RS#0
8 H_REQ#0 REQ0# RS0# H_RS#0 8
H_REQ#1 H2 F4 H_RS#1
8 H_REQ#1 REQ1# RS1# H_RS#1 8
H_REQ#2 K2 G3 H_RS#2
8 H_REQ#2 REQ2# RS2# H_RS#2 8
H_REQ#3 J3 G2 H_TRDY#
8 H_REQ#3 REQ3# TRDY# H_TRDY# 8
H_REQ#4 L1
8 H_REQ#4 REQ4#
G6 H_HIT#
HIT# H_HIT# 8
H_A#17 Y2 E4 H_HITM#
A17# HITM# H_HITM# 8
H_A#18 U5
H_A#19 A18# XDP_BPM#0 TP15
R3 A19# BPM0# AD4
H_A#20 W6 AD3 XDP_BPM#1 TP13

XDP/ITP SIGNALS
A20# BPM1#
ADDR GROUP 1
H_A#21 U4 AD1 XDP_BPM#2 TP3
H_A#22 A21# BPM2# XDP_BPM#3 TP9
Y5 A22# BPM3# AC4
H_A#23 U1 AC2 XDP_BPM#4 TP7
H_A#24 A23# PRDY# XDP_BPM#5 TP2
R4 A24# PREQ# AC1
C H_A#25 T5 AC5 XDP_TCK C
H_A#26 A25# TCK XDP_TDI
T3 A26# TDI AA6
H_A#27 W2 AB3 XDP_TDO TP8
H_A#28 A27# TDO XDP_TMS
W5 A28# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A29# TRST# XDP_DBRESET# TP19
U2 A30# DBR# C20
H_A#31 V4
H_A#32 A31#
W3 A32#
H_A#33 AA4 THERMAL
H_A#34 A33#
AB2 A34#
H_A#35 AA3 D21 CPU_PROCHOT 1 2 1D05V_S0
H_ADSTB#1 A35# PROCHOT# H_THERMDA R236 56R2J-4-GP
8 H_ADSTB#1 V1 ADSTB1# THRMDA A24 H_THERMDA 36 H_THERMDA, H_THERMDC routing together,
B25 H_THERMDC
H_A20M# A6
THRMDC H_THERMDC 36 Trace width / Spacing = 10 / 10 mil
20 H_A20M# A20M#
H_FERR# A5 C7 H_THERMTRIP#
20 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 8,20,34,46
ICH

H_IGNNE# C4
20 H_IGNNE# IGNNE#

20 H_STPCLK# D5 STPCLK#
C6 HCLK A22 CLK_CPU_BCLK
20 H_INTR LINT0 BCLK0 CLK_CPU_BCLK 4
B4 A21 CLK_CPU_BCLK#
20 H_NMI LINT1 BCLK1 CLK_CPU_BCLK# 4
20 H_SMI# A3 SMI# 1D05V_S0
TPAD28 TP14 CPU_RSVD01 M4
TPAD28 TP16 CPU_RSVD02 RSVD#M4
N5 RSVD#N5
TPAD28 TP6 CPU_RSVD03 T2 XDP_TDI 1 2
RESERVED

TPAD28 TP12 CPU_RSVD04 RSVD#T2 R7 150R2F-1-GP

V3 RSVD#V3
TPAD28 TP4 CPU_RSVD05 B2 layout note:Zo =55 XDP_TMS 1 2
TPAD28 TP10 CPU_RSVD06 RSVD#B2 R5 39R2F-GP
C3
TPAD28 TP5 CPU_RSVD07 D2
RSVD#C3 ohm , 0.5" MAX for
B TPAD28 TP20 CPU_RSVD08 RSVD#D2 B
D22 RSVD#D22 GTLREF
TPAD28 TP11 CPU_RSVD09 D3
TPAD28 TP18 CPU_RSVD10 RSVD#D3
F6 RSVD#F6
B1 KEY_NC
SKT-CPU478P-GP

XDP_TRST# 1 2
R6 649R2F-GP
XDP_TCK 1 2
R4 27D4R2F-L1-GP

CPU_PROCHOT 2 1
R237 0R2J-2-GP CPU_PROCHOT# 41

DY

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Merom(1/3)-AGTL+/XDP
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 5 of 47
5 4 3 2 1
 5 4 3 2 1

8 H_D#[0..63] VCC_CORE_S0 VCC_CORE_S0

U45B 2 OF 4
U45C 3 OF 4
H_D#0 E22 Y22 H_D#32
H_D#1 D0# D32# H_D#33
F24 D1# D33# AB24 A7 VCC VCC AB20
H_D#2 E26 V24 H_D#34 A9 AB7
H_D#3 D2# D34# H_D#35 VCC VCC
G22 D3# D35# V26 A10 VCC VCC AC7
D H_D#4 F23 V23 H_D#36 A12 AC9 D
D4# D36# VCC VCC

DATA GRP0
DATA GRP2
H_D#5 G25 T22 H_D#37 A13 AC12
H_D#6 D5# D37# H_D#38 VCC VCC
E25 D6# D38# U25 A15 VCC VCC AC13
H_D#7 E23 U23 H_D#39 A17 AC15
H_D#8 D7# D39# H_D#40 VCC VCC
K24 D8# D40# Y25 A18 VCC VCC AC17
H_D#9 G24 W22 H_D#41 A20 AC18
H_D#10 D9# D41# H_D#42 VCC VCC
J24 D10# D42# Y23 B7 VCC VCC AD7
H_D#11 J23 W24 H_D#43 B9 AD9
H_D#12 D11# D43# H_D#44 VCC VCC
H22 D12# D44# W25 B10 VCC VCC AD10
H_D#13 F26 AA23 H_D#45 B12 AD12
H_D#14 D13# D45# H_D#46 VCC VCC
K22 D14# D46# AA24 B14 VCC VCC AD14
H_D#15 H23 AB25 H_D#47 B15 AD15
H_DSTBN#0 D15# D47# H_DSTBN#2 VCC VCC
8 H_DSTBN#0 J26 DSTBN0# DSTBN2# Y26 H_DSTBN#2 8 B17 VCC VCC AD17
H_DSTBP#0 H26 AA26 H_DSTBP#2 B18 AD18
8 H_DSTBP#0 DSTBP0# DSTBP2# H_DSTBP#2 8 VCC VCC
H_DINV#0 H25 U22 H_DINV#2 B20 AE9
8 H_DINV#0 DINV0# DINV2# H_DINV#2 8 VCC VCC
C9 VCC VCC AE10
C10 VCC VCC AE12
H_D#16 N22 AE24 H_D#48 C12 AE13
H_D#17 D16# D48# H_D#49 VCC VCC
K25 D17# D49# AD24 C13 VCC VCC AE15
H_D#18 P26 AA21 H_D#50 C15 AE17
H_D#19 D18# D50# H_D#51 VCC VCC
R23 D19# D51# AB22 C17 VCC VCC AE18
H_D#20 L23 AB21 H_D#52 C18 AE20
H_D#21 D20# D52# H_D#53 VCC VCC
M24 D21# D53# AC26 D9 VCC VCC AF9

DATA GRP1
DATA GRP3
H_D#22 L22 AD20 H_D#54 D10 AF10
H_D#23 D22# D54# H_D#55 VCC VCC
M23 D23# D55# AE22 D12 VCC VCC AF12
H_D#24 P25 AF23 H_D#56 D14 AF14
H_D#25 D24# D56# H_D#57 VCC VCC
P23 D25# D57# AC25 D15 VCC VCC AF15
H_D#26 P22 AE21 H_D#58 D17 AF17
H_D#27 D26# D58# H_D#59 VCC VCC
T24 D27# D59# AD21 D18 VCC VCC AF18
C H_D#28 R24 AC22 H_D#60 E7 AF20 1D05V_S0 C
H_D#29 D28# D60# H_D#61 VCC VCC
L25 D29# D61# AD23 E9 VCC
H_D#30 T25 AF22 H_D#62 E10 G21
H_D#31 D30# D62# H_D#63 VCC VCCP
N25 D31# D63# AC23 E12 VCC VCCP V6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E13 J6
8 H_DSTBN#1 DSTBN1# DSTBN3# H_DSTBN#3 8 VCC VCCP
H_DSTBP#1 M26 AF24 H_DSTBP#3 E15 K6
8 H_DSTBP#1 DSTBP1# DSTBP3# H_DSTBP#3 8 VCC VCCP

1
H_DINV#1 N24 AC20 H_DINV#3 E17 M6
8 H_DINV#1 DINV1# DINV3# H_DINV#3 8 VCC VCCP
E18 J21 C20
V_CPU_GTLREF COMP0 VCC VCCP SC10U6D3V5KX-1GP
AD26 R26 1 2 E20 K21

2
TPAD28 TP21 TEST1 GTLREF COMP0 COMP1 R233 VCC VCCP
C23 TEST1 MISC COMP1 U26 1 2 27D4R2F-L1-GP F7 VCC VCCP M21
TPAD28 TP23 TEST2 D25 AA1 COMP2 R234 1 2 54D9R2F-L1-GP F9 N21
SCD1U16V2KX-3GP TPAD28 TP22 TEST3 TEST2 COMP2 COMP3 R3 VCC VCCP
C24 TEST3 COMP3 Y1 1 2 27D4R2F-L1-GP F10 VCC VCCP N6
1 2 C395 TEST4 AF26 TEST4
R2 54D9R2F-L1-GP F12 VCC VCCP R21
TPAD28 TP85 TEST5 AF1 E5 H_DPRSTP# F14 R6
TEST5 DPRSTP# H_DPRSTP# 8,20,41 VCC VCCP
TPAD28 TP87 TEST6 A26 B5 H_DPSLP# F15 T21
DY TEST6 DPSLP#
D24 H_DPWR#
H_DPSLP# 20
F17
VCC VCCP
T6
DPWR# H_DPWR# 8 VCC VCCP
CPU_BSEL0 B22 D6 F18 V21
4 CPU_BSEL0 BSEL0 PWRGOOD H_PWRGOOD 20,46 VCC VCCP 1D5V_S0
CPU_BSEL1 B23 D7 H_CPUSLP# F20 W21 layout note:
4 CPU_BSEL1 BSEL1 SLP# H_CPUSLP# 8 VCC VCCP
CPU_BSEL2 C21 AE6 PSI# AA7
4 CPU_BSEL2 BSEL2 PSI# PSI# 41
AA9
VCC
B26 place C3 near
VCC VCCA
AA10 VCC VCCA C26 PIN B26

1
AA12 C394
VCC CPU_VID[0..6] 41

SCD01U16V2KX-3GP
SKT-CPU478P-GP AA13 AD6 CPU_VID0 C397
VCC VID0 CPU_VID1 SC10U6D3V5KX-1GP
AA15 AF5

2
VCC VID1 CPU_VID2
PLACE C25 close to the TEST4 PIN, AA17 VCC VID2 AE5
AA18 AF4 CPU_VID3
make sure TEST3,TEST4,TEST5 trace AA20
VCC VID3
AE3 CPU_VID4
VCC VID4 CPU_VID5
routing is reference to GND and AB9 VCC VID5 AF3
AC10 AE2 CPU_VID6
B away other noisy signals AB10
VCC VID6 B
VCC
AB12 VCC
Resistor Placed AB14 AF7 VCC_SENSE Length match within
VCC VCCSENSE VCC_SENSE 41
AB15
within 0.5" of CPU AB17
VCC 25 mils . The trace
VCC VSS_SENSE
pin. Trace should AB18 VCC VSSSENSE AE7 VSS_SENSE 41 width/space/other is
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 be at least 25 mils 20/7/25 .
away from any other
SKT-CPU478P-GP
166 0 1 1 toggling signal .
COMP[0,2] trace
width is 18 mils.
200 0 1 0
COMP[1,3] trace
width is 4 mils . VCC_SENSE 1 2 VCC_CORE_S0
R201 100R2F-L1-GP-U

VSS_SENSE 1 2
R199 100R2F-L1-GP-U

1D05V_S0
Close to CPU
pin AD26 Close to CPU pin
Z0=55 ohm within 500mils
2

R239 with in
A <Core Design> A
1KR2F-3-GP 500mils .
1

Wistron Corporation
1 1

C635 V_CPU_GTLREF
SCD1U16V2KX-3GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

R238 Taipei Hsien 221, Taiwan, R.O.C.

Place C635 near 2KR2F-3-GP Title

Merom(2/3)-AGTL+/PWR
2

R238 and R239

Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 6 of 47
5 4 3 2 1
 5 4 3 2 1

VCC_CORE_S0

1
C382 C377 C376 C374 C371 C361 C358 C349

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
U45D 4 OF 4 Place these capacitors on L1

2
D A4 P6 (North side ,Secondary Layer) D
VSS VSS
A8 VSS VSS P21
A11 VSS VSS P24
A14 VSS VSS R2
A16 VSS VSS R5
A19 VSS VSS R22
A23 VSS VSS R25
AF2 T1 VCC_CORE_S0
VSS VSS
B6 VSS VSS T4
B8 VSS VSS T23
B11 VSS VSS T26
B13 VSS VSS U3

1
B16 U6 C34 C33 C36 C17 C35 C24 C25 C23
VSS VSS

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
B19 VSS VSS U21
B21 U24 Place these capacitors on L1

2
VSS VSS
B24 V2
C5
VSS VSS
V5 (North side ,Secondary Layer)
VSS VSS
C8 VSS VSS V22
C11 VSS VSS V25
C14 VSS VSS W1
C16 VSS VSS W4
C19 VSS VSS W23
C2 VSS VSS W26
C22 VSS VSS Y3
C25 VSS VSS Y6
D1 Y21 VCC_CORE_S0
VSS VSS
D4 VSS VSS Y24
D8 VSS VSS AA2
D11 VSS VSS AA5
C D13 AA8 C633 C634 C
VSS VSS

1
D16 VSS VSS AA11

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
D19 AA14
D23
VSS VSS
AA16 Mid Frequencd

2
VSS VSS
D26 VSS VSS AA19
E3
E6
VSS
VSS
VSS
VSS
AA22
AA25 Decoupling
E8 VSS VSS AB1
E11 VSS VSS AB4
E14 VSS VSS AB8
E16 VSS VSS AB11
E19 VSS VSS AB13
E21 VSS VSS AB16
E24 VSS VSS AB19
F5 VSS VSS AB23
F8 VSS VSS AB26
F11 VSS VSS AC3
F13 VSS VSS AC6
F16 VSS VSS AC8
F19 VSS VSS AC11
F2 VSS VSS AC14
F22 VSS VSS AC16
F25 VSS VSS AC19
G4 VSS VSS AC21
G1 VSS VSS AC24
G23 VSS VSS AD2
G26 VSS VSS AD5
H3 VSS VSS AD8
H6 VSS VSS AD11
B B
H21 VSS VSS AD13
H24 VSS VSS AD16
J2 VSS VSS AD19
J5 AD22 1D05V_S0
VSS VSS
J22 VSS VSS AD25
J25 VSS VSS AE1
K1 VSS VSS AE4
K4 VSS VSS AE8
K23 VSS VSS AE11
K26 VSS VSS AE14 Place these
2

2
L3 AE16
L6
VSS VSS
AE19 C16 C12 C10 C39 C45 C37 inside socket
VSS VSS SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
L21 AE23 cavity on L1
1

1
VSS VSS
L24 AE26
M2
VSS VSS
A2
(North side
VSS VSS
M5 VSS VSS AF6 Secondary)
M22 VSS VSS AF8
M25 VSS VSS AF11
N1 VSS VSS AF13
N4 VSS VSS AF16
N23 VSS VSS AF19
N26 VSS VSS AF21
P3 VSS VSS A25
VSS AF25

SKT-CPU478P-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Merom(3/3)-GND&Bypass
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 7 of 47
5 4 3 2 1
 5 4 3 2 1
U50A 1 OF 10
6 H_D#[0..63] H_A#[3..35] 5
H_D#0 E2 J13 H_A#3
H_D#0 H_A#3

SCD01U25V2KX-3GP
H_D#1 G2 B11 H_A#4
H_D#2 H_D#1 H_A#4 H_A#5
G7 H_D#2 H_A#5 C11 FOR Calero: 80.6 ohm
H_D#3 M6 M11 H_A#6 -1:0914 U50B 2 OF 10 Crestline: 20 ohm
H_D#4 H_D#3 H_A#6 H_A#7 1D8V_S3
H7 H_D#4 H_A#7 C15
H_D#5 H3 F16 H_A#8 P36 AV29 M_CLK_DDR0
H_D#6 H_D#5 H_A#8 H_A#9 RSVD#P36 SM_CK0 M_CLK_DDR1 M_CLK_DDR0 14
G4 H_D#6 H_A#9 L13 P37 RSVD#P37 SM_CK1 BB23 M_CLK_DDR1 14

1
H_D#7 F3 G17 H_A#10 C435 R35 BA25 M_CLK_DDR2
H_D#7 H_A#10 RSVD#R35 SM_CK3 M_CLK_DDR2 15

C437
H_D#8 N8 C14 H_A#11 SC2D2U6D3V3KX-GP R268 N35 AV23 M_CLK_DDR3
H_D#9 H_D#8 H_A#11 H_A#12 1KR2F-3-GP RSVD#N35 SM_CK4 M_CLK_DDR3 15
H2 K16 AR12

2
H_D#10 H_D#9 H_A#12 H_A#13 RSVD#AR12
M10 H_D#10 H_A#13 B13 AR13 RSVD#AR13 SM_CK#0 AW30 M_CLK_DDR#0 M_CLK_DDR#0 14
H_D#11 N12 L16 H_A#14 AM12 BA23 M_CLK_DDR#1

2
H_D#12 H_D#11 H_A#14 H_A#15 SM_RCOMP_VOH RSVD#AM12 SM_CK#1 M_CLK_DDR#1 14
N9 H_D#12 H_A#15 J17 AN13 RSVD#AN13 SM_CK#3 AW25 M_CLK_DDR#2 M_CLK_DDR#2 15
H_D#13 H5 B14 H_A#16 J12 AW23 M_CLK_DDR#3
H_D#13 H_A#16 RSVD#J12 SM_CK#4 M_CLK_DDR#3 15

1
D H_D#14 H_A#17 D
P13 H_D#14 H_A#17 K19 AR37 RSVD#AR37
H_D#15 K9 P15 H_A#18 R272 AM36 BE29 DDR_CKE0_DIMMA

DDR MUXING
H_D#16 H_D#15 H_A#18 H_A#19 3K01R2F-3-GP RSVD#AM36 SM_CKE0 DDR_CKE0_DIMMA 14
M2 H_D#16 H_A#19 R17 AL36 RSVD#AL36 SM_CKE1 AY32 DDR_CKE1_DIMMA DDR_CKE1_DIMMA 14
H_D#17 W10 B16 H_A#20 AM37 BD39 DDR_CKE2_DIMMB
H_D#18 H_D#17 H_A#20 H_A#21 RSVD#AM37 SM_CKE3 DDR_CKE2_DIMMB 15
Y8 H20 D20 BG37 DDR_CKE3_DIMMB

2
H_D#19 H_D#18 H_A#21 H_A#22 SM_RCOMP_VOL RSVD#D20 SM_CKE4 DDR_CKE3_DIMMB 15
V4 H_D#19 H_A#22 L19
H_D#20 M3 D17 H_A#23 BG20 DDR_CS0_DIMMA#
H_D#20 H_A#23 SM_CS#0 DDR_CS0_DIMMA# 14

1
H_D#21 J1 M17 H_A#24 -1:0914 BK16 DDR_CS1_DIMMA#
H_D#22 H_D#21 H_A#24 H_A#25 R273 SM_CS#1 DDR_CS1_DIMMA# 14
N5 H_D#22 H_A#25 N16 SM_CS#2 BG16 DDR_CS2_DIMMB# DDR_CS2_DIMMB# 15

SCD01U25V2KX-3GP
H_D#23 N3 J19 H_A#26 C444 1KR2F-3-GP H10 BE13 DDR_CS3_DIMMB#
H_D#23 H_A#26 RSVD#H10 SM_CS#3 DDR_CS3_DIMMB# 15

C442
H_D#24 W6 B18 H_A#27 SC2D2U6D3V3KX-GP B51
H_D#24 H_A#27 RSVD#B51

RSVD
H_D#25 W9 E19 H_A#28 BJ20 BH18 M_ODT0

2
H_D#26 H_D#25 H_A#28 H_A#29 RSVD#BJ20 SM_ODT0 M_ODT1 M_ODT0 14
N2 H_D#26 H_A#29 B17 BK22 RSVD#BK22 SM_ODT1 BJ15 M_ODT1 14
H_D#27 Y7 B15 H_A#30 BF19 BJ14 M_ODT2
H_D#28 H_D#27 H_A#30 H_A#31 RSVD#BF19 SM_ODT2 M_ODT3 M_ODT2 15
Y9 H_D#28 H_A#31 E17 BH20 RSVD#BH20 SM_ODT3 BE16 M_ODT3 15
H_D#29 P4 C18 H_A#32 BK18
H_D#30 H_D#29 H_A#32 H_A#33 RSVD#BK18 SM_RCOMP_VOH
W3 H_D#30 H_A#33 A19 BJ18 RSVD#BJ18 SM_RCOMP_VOH BK31
H_D#31 N1 B19 H_A#34 BF23 BL31 SM_RCOMP_VOL 1D8V_S3
H_D#32 H_D#31 H_A#34 H_A#35 RSVD#BF23 SM_RCOMP_VOL
AD12 H_D#32 H_A#35 N19 BG23 RSVD#BG23
H_D#33 AE3 BC23 BL15 SM_RCOMP 1 2
H_D#34 H_D#33 H_ADS# RSVD#BC23 SM_RCOMP SM_RCOMP# R264 1
AD9 G12 BD24 BK14 2 20R2F-GP

HOST
H_D#34 H_ADS# H_ADS# 5 RSVD#BD24 SM_RCOMP#
H_D#35 AC9 H17 H_ADSTB#0 R261 20R2F-GP
H_D#35 H_ADSTB#0 H_ADSTB#0 5
H_D#36 AC7 G20 H_ADSTB#1 AR49 DDR_VREF_S3
H_D#36 H_ADSTB#1 H_ADSTB#1 5 SM_VREF#AR49
H_D#37 AC14 C8 H_BNR# BH39 AW4 DDR_VREF_S3
H_D#37 H_BNR# H_BNR# 5 RSVD#BH39 SM_VREF#AW4
H_D#38 AD11 E8 H_BPRI# AW20
H_D#39 H_D#38 H_BPRI# H_BR0# H_BPRI# 5 RSVD#AW20
AC11 H_D#39 H_BREQ# F12 H_BR0# 5 BK20 RSVD#BK20
H_D#40 AB2 D6 H_DEFER#
H_D#41 H_D#40 H_DEFER# H_DBSY# H_DEFER# 5 CLK_MCH_DREFCLK
AD7 H_D#41 H_DBSY# C10 H_DBSY# 5 DPLL_REF_CLK B42 CLK_MCH_DREFCLK 4
H_D#42 AB1 AM5 CLK_MCH_BCLK B44 C42 CLK_MCH_DREFCLK#
H_D#42 HPLL_CLK CLK_MCH_BCLK 4 RSVD#B44 DPLL_REF_CLK# CLK_MCH_DREFCLK# 4
H_D#43 Y3 AM7 CLK_MCH_BCLK# C44 H48 MCH_SSCDREFCLK
H_D#43 HPLL_CLK# CLK_MCH_BCLK# 4 RSVD#C44 DPLL_REF_SSCLK MCH_SSCDREFCLK 4
H_D#44 AC6 H8 H_DPWR# A35 H47 MCH_SSCDREFCLK#
H_D#44 H_DPWR# H_DPWR# 6 RSVD#A35 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 4
H_D#45 AE2 K7 H_DRDY# B37
C H_D#45 H_DRDY# H_DRDY# 5 RSVD#B37 C
H_D#46 AC5 E4 H_HIT# B36 K44 CLK_MCH_3GPLL
H_D#46 H_HIT# H_HIT# 5 RSVD#B36 PEG_CLK CLK_MCH_3GPLL 4
H_D#47 AG3 C6 H_HITM# B34 K45 CLK_MCH_3GPLL#

CLK
H_D#47 H_HITM# H_HITM# 5 RSVD#B34 PEG_CLK# CLK_MCH_3GPLL# 4
H_D#48 AJ9 G10 H_LOCK# C34
H_D#48 H_LOCK# H_LOCK# 5 RSVD#C34
H_D#49 AH8 B7 H_TRDY#
H_D#50 H_D#49 H_TRDY# H_TRDY# 5
AJ14 H_D#50
1D05V_S0 H_D#51 AE9
H_D#52 H_D#51 DMI_TXN0
AE11 H_D#52 DMI_RXN0 AN47 DMI_TXN0 21
H_D#53 AH12 AJ38 DMI_TXN1
H_D#53 DMI_RXN1 DMI_TXN1 21
H_D#54 AJ5 K5 H_DINV#0 MCH_CLKSEL0 P27 AN42 DMI_TXN2
H_D#54 H_DINV#0 H_DINV#0 6 4 MCH_CLKSEL0 CFG0 DMI_RXN2 DMI_TXN2 21
H_D#55 AH5 L2 H_DINV#1 MCH_CLKSEL1 N27 AN46 DMI_TXN3
H_D#55 H_DINV#1 H_DINV#1 6 4 MCH_CLKSEL1 CFG1 DMI_RXN3 DMI_TXN3 21
H_D#56 AJ6 AD13 H_DINV#2 MCH_CLKSEL2 N24
H_D#56 H_DINV#2 H_DINV#2 6 4 MCH_CLKSEL2 CFG2
1

R248 R249 H_D#57 AE7 AE13 H_DINV#3 C21 AM47 DMI_TXP0

DMI
H_D#57 H_DINV#3 H_DINV#3 6 CFG3 DMI_RXP0 DMI_TXP0 21
H_D#58 AJ7 C23 AJ39 DMI_TXP1
H_D#58 CFG4 DMI_RXP1 DMI_TXP1 21
H_D#59 AJ2 M7 H_DSTBN#0 TP33 CFG5 F23 AN41 DMI_TXP2
H_D#59 H_DSTBN#0 H_DSTBN#0 6 CFG5 DMI_RXP2 DMI_TXP2 21
54D9R2F-L1-GP

54D9R2F-L1-GP

H_D#60 AE5 K3 H_DSTBN#1 TP29 CFG6 N23 AN45 DMI_TXP3

H_D#60 H_DSTBN#1 H_DSTBN#1 6 CFG6 DMI_RXP3 DMI_TXP3 21
H_D#61 AJ3 AD2 H_DSTBN#2 CFG[17:3] have internal pull up TP32 CFG7 G23
H_DSTBN#2 6
2

H_D#61 H_DSTBN#2 CFG7

CFG
H_D#62 AH2 AH11 H_DSTBN#3 CFG[19:18] have internal pull down TP26 CFG8 J20 AJ46 DMI_RXN0
H_D#62 H_DSTBN#3 H_DSTBN#3 6 CFG8 DMI_TXN0 DMI_RXN0 21
H_D#63 AH13 TP27 CFG9 C20 AJ41 DMI_RXN1
H_D#63 H_DSTBP#0 CFG10 CFG9 DMI_TXN1 DMI_RXN2 DMI_RXN1 21
H_DSTBP#0 L7 H_DSTBP#0 6 TP31 R24 CFG10 DMI_TXN2 AM40 DMI_RXN2 21
K2 H_DSTBP#1 TP34 CFG11 L23 AM44 DMI_RXN3
H_DSTBP#1 H_DSTBP#1 6 CFG11 DMI_TXN3 DMI_RXN3 21
H_SWNG B3 AC2 H_DSTBP#2 TP25 CFG12 J23
H_SWING H_DSTBP#2 H_DSTBP#2 6 CFG12
H_RCOMP C2 AJ10 H_DSTBP#3 TP35 CFG13 E23 AJ47 DMI_RXP0
H_RCOMP H_DSTBP#3 H_DSTBP#3 6 CFG13 DMI_TXP0 DMI_RXP0 21
E20 AJ42 DMI_RXP1
H_SCOMP H_REQ#0 CFG14 DMI_TXP1 DMI_RXP2 DMI_RXP1 21
W1 H_SCOMP H_REQ#0 M14 H_REQ#0 5 K23 CFG15 DMI_TXP2 AM39 DMI_RXP2 21
H_SCOMP# W2 E13 H_REQ#1 TP24 CFG16 M20 AM43 DMI_RXP3
H_SCOMP# H_REQ#1 H_REQ#1 5 CFG16 DMI_TXP3 DMI_RXP3 21
A11 H_REQ#2 M24
H_REQ#2 H_REQ#2 5 CFG17
H_RESET# B6 H13 H_REQ#3 TP39 CFG18 L32
5 H_RESET# H_CPURST# H_REQ#3 H_REQ#3 5 CFG18
H_CPUSLP# E5 B12 H_REQ#4 TP36 CFG19 N33
6 H_CPUSLP# H_CPUSLP# H_REQ#4 H_REQ#4 5 CFG19
TP37 CFG20 L35

GRAPHICS VID
H_RS#0 CFG20
H_RS#0 E12 H_RS#0 5
H_VREF B9 D7 H_RS#1 E35 DFGT_VID0
H_AVREF H_RS#1 H_RS#1 5 GFX_VID0 TP38
A9 D8 H_RS#2 A39 DFGT_VID1
B H_DVREF H_RS#2 H_RS#2 5 GFX_VID1 TP94 B
PM_BMBUSY# G41 C38 DFGT_VID2
21 PM_BMBUSY# PM_BM_BUSY# GFX_VID2 TP92
H_DPRSTP# L39 B39 DFGT_VID3
NB:71.GM965.A0U 6,20,41 H_DPRSTP# PM_EXTTS#0 L36
PM_DPRSTP# GFX_VID3
E36 DFGT_VR_EN
TP93
14 PM_EXTTS#0 PM_EXT_TS#0 GFX_VR_EN TP40 1D25V_S0

PM
PM_EXTTS#1 J36
15 PM_EXTTS#1 PM_POK_R PM_EXT_TS#1
layout note : AW49 PWROK
PLT_RST_R# AV20
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces H_THERMTRIP# N20
RSTIN#
5,20,34,46 H_THERMTRIP# DPRSLPVR THERMTRIP#
21,41 DPRSLPVR G36 DPRSLPVR

2
R84
Layout Note : Spec: H_SWING=0.3125 X AM49 1KR2F-3-GP
CL_CLK CL_CLK0 21
H_RCOMP / H_VREF / H_SWNG VTT +/- 1%
R86
DY BJ51 NC#BJ51 CL_DATA AK50 CL_DATA0 21
1 2 0R2J-2-GP PM_POK_R BK51 AT43 PM_POK_R

ME

1
21,36 PM_PWROK NC#BK51 CL_PWROK
trace width and spacing is 10/20 1D05V_S0
BK50 NC#BK50 CL_RST# AN49 CL_RST# 21
1 2 BL50 AM50 CL_VREF
21,41 VGATE_PWRGD R87 0R2J-2-GP NC#BL50 CL_VREF
BL49 NC#BL49

1
1D05V_S0 BL3 NC#BL3

1
BL2 R85
NC#BL2
1

NC
BK1 C182 392R2F-GP
NC#BK1
1

221R2F-2-GP

R255 BJ1 H35 SDVO_CTRLCLK 23

2
NC#BJ1 SDVO_CTRL_CLK

SCD1U16V2KX-3GP
R263 E1 K36 SDVO_CTRLDATA 23

2
1KR2F-3-GP NC#E1 SDVO_CTRL_DATA
R52 A5 NC#A5 CLKREQ# G39 CLKREQ#_B 4
C51 G40 MCH_ICH_SYNC#
2

PLT_RST_R# NC#C51 ICH_SYNC# MCH_ICH_SYNC# 21

1 2 B50

MISC
2

H_VREF H_RCOMP H_SWNG PLT_RST1# 19,23,24,28,29,30,34 NC#B50

A50 NC#A50
100R2J-2-GP A49 NC#A49 TEST1 A37 TEST1_GMCH 1 R64 2
1

R254 BK2 NC#BK2 TEST2 R32 TEST2_GMCH1 2 0R0402-PAD

1

R262 C426 R250 R65

SCD1U16V2ZY-2GP

2KR2F-3-GP 24D9R2F-L-GP C415 20KR2J-L2-GP

2

SCD1U16V2ZY-2GP
100R2F-L1-GP-U

2
2

3D3V_S0
A A
Layout Note : RN18 NB:71.GM965.A0U
PM_EXTTS#0 1 8 <Core Design>
Layout Note : Place C33 near PM_EXTTS#1 2 7
pin B3 of NB TV_DCONSEL0 3 6
Place C32 within 100 mils of NB 10 TV_DCONSEL0
10 TV_DCONSEL1
TV_DCONSEL1 4 5 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SRN10KJ-6-GP
Title
CLKREQ#_B 1 2
R69 10KR2J-3-GP
CRESTLINE(1/6)-AGTL+/DMI/DDR2
Size Document Number Rev
Custom
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 8 of 47
5 4 3 2 1
 5 4 3 2 1

DDR_A_D[0..63] 14
DDR_B_D[0..63] 15
DDR_A_BS[0..2] 14
DDR_B_BS[0..2] 15
DDR_A_DM[0..7] 14
D DDR_B_DM[0..7] 15 D
DDR_A_DQS[0..7] 14
DDR_B_DQS[0..7] 15
DDR_A_DQS#[0..7] 14
DDR_B_DQS#[0..7] 15
DDR_A_MA[0..14] 14
DDR_B_MA[0..14] 15

U50D 4 OF 10 U50E 5 OF 10

DDR_A_D0 AR43 BB19 DDR_A_BS0 DDR_B_D0 AP49 AY17 DDR_B_BS0

DDR_A_D1 SA_DQ0 SA_BS0 DDR_A_BS1 DDR_B_D1 SB_DQ0 SB_BS0 DDR_B_BS1
AW44 SA_DQ1 SA_BS1 BK19 AR51 SB_DQ1 SB_BS1 BG18
DDR_A_D2 BA45 BF29 DDR_A_BS2 DDR_B_D2 AW50 BG36 DDR_B_BS2
DDR_A_D3 SA_DQ2 SA_BS2 DDR_B_D3 SB_DQ2 SB_BS2
AY46 SA_DQ3 AW51 SB_DQ3
DDR_A_D4 AR41 BL17 DDR_A_CAS# DDR_B_D4 AN51 BE17 DDR_B_CAS#
DDR_A_D5 SA_DQ4 SA_CAS# DDR_A_CAS# 14 DDR_B_D5 SB_DQ4 SB_CAS# DDR_B_CAS# 15
AR45 SA_DQ5 AN50 SB_DQ5
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7 SA_DQ6 SA_DM0 DDR_A_DM1 DDR_B_D7 SB_DQ6 SB_DM0 DDR_B_DM1
AW47 SA_DQ7 SA_DM1 BD44 AV49 SB_DQ7 SB_DM1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
DDR_A_D9 SA_DQ8 SA_DM2 DDR_A_DM3 DDR_B_D9 SB_DQ8 SB_DM2 DDR_B_DM3
BF48 SA_DQ9 SA_DM3 AW38 BB50 SB_DQ9 SB_DM3 BL39
DDR_A_D10 BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
DDR_A_D11 SA_DQ10 SA_DM4 DDR_A_DM5 DDR_B_D11 SB_DQ10 SB_DM4 DDR_B_DM5
BJ45 SA_DQ11 SA_DM5 BG8 BE50 SB_DQ11 SB_DM5 BJ7
DDR_A_D12 BB47 AY5 DDR_A_DM6 DDR_B_D12 BA51 BF3 DDR_B_DM6
DDR_A_D13 SA_DQ12 SA_DM6 DDR_A_DM7 DDR_B_D13 SB_DQ12 SB_DM6 DDR_B_DM7
BG50 SA_DQ13 SA_DM7 AN6 AY49 SB_DQ13 SB_DM7 AW2
DDR_A_D14 BH49 DDR_B_D14 BF50
DDR_A_D15 SA_DQ14 DDR_A_DQS0 DDR_B_D15 SB_DQ14 DDR_B_DQS0
BE45 SA_DQ15 SA_DQS0 AT46 BF49 SB_DQ15 SB_DQS0 AT50
DDR_A_D16 AW43 BE48 DDR_A_DQS1 DDR_B_D16 BJ50 BD50 DDR_B_DQS1
DDR_A_D17 SA_DQ16 SA_DQS1 DDR_A_DQS2 DDR_B_D17 SB_DQ16 SB_DQS1 DDR_B_DQS2
BE44 SA_DQ17 SA_DQS2 BB43 BJ44 SB_DQ17 SB_DQS2 BK46
C DDR_A_D18
DDR_A_D19
BG42
BE40
SA_DQ18 SA_DQS3 BC37
BB16
DDR_A_DQS3
DDR_A_DQS4
DDR_B_D18
DDR_B_D19
BJ43
BL43
SB_DQ18 SB_DQS3 BK39
BJ12
DDR_B_DQS3
DDR_B_DQS4 C
DDR_A_D20 SA_DQ19 SA_DQS4 DDR_A_DQS5 DDR_B_D20 SB_DQ19 SB_DQS4 DDR_B_DQS5
BF44 SA_DQ20 SA_DQS5 BH6 BK47 SB_DQ20 SB_DQS5 BL7
DDR_A_D21 BH45 BB2 DDR_A_DQS6 DDR_B_D21 BK49 BE2 DDR_B_DQS6
DDR_A_D22 SA_DQ21 SA_DQS6 DDR_A_DQS7 DDR_B_D22 SB_DQ21 SB_DQS6 DDR_B_DQS7
BG40 SA_DQ22 SA_DQS7 AP3 BK43 SB_DQ22 SB_DQS7 AV2
DDR_A_D23 BF40 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 AU50 DDR_B_DQS#0
DDR SYSTEM MEMORRY A

DDR_A_D24 SA_DQ23 SA_DQS#0 DDR_A_DQS#1 DDR_B_D24 SB_DQ23 SB_DQS#0 DDR_B_DQS#1

AR40 BD47 BJ41 BC50

DDR SYSTEM MEMORY B

DDR_A_D25 SA_DQ24 SA_DQS#1 DDR_A_DQS#2 DDR_B_D25 SB_DQ24 SB_DQS#1 DDR_B_DQS#2
AW40 SA_DQ25 SA_DQS#2 BC41 BL41 SB_DQ25 SB_DQS#2 BL45
DDR_A_D26 AT39 BA37 DDR_A_DQS#3 DDR_B_D26 BJ37 BK38 DDR_B_DQS#3
DDR_A_D27 SA_DQ26 SA_DQS#3 DDR_A_DQS#4 DDR_B_D27 SB_DQ26 SB_DQS#3 DDR_B_DQS#4
AW36 SA_DQ27 SA_DQS#4 BA16 BJ36 SB_DQ27 SB_DQS#4 BK12
DDR_A_D28 AW41 BH7 DDR_A_DQS#5 DDR_B_D28 BK41 BK7 DDR_B_DQS#5
DDR_A_D29 SA_DQ28 SA_DQS#5 DDR_A_DQS#6 DDR_B_D29 SB_DQ28 SB_DQS#5 DDR_B_DQS#6
AY41 SA_DQ29 SA_DQS#6 BC1 BJ40 SB_DQ29 SB_DQS#6 BF2
DDR_A_D30 AV38 AP2 DDR_A_DQS#7 DDR_B_D30 BL35 AV3 DDR_B_DQS#7
DDR_A_D31 SA_DQ30 SA_DQS#7 DDR_B_D31 SB_DQ30 SB_DQS#7
AT38 SA_DQ31 BK37 SB_DQ31
DDR_A_D32 AV13 BJ19 DDR_A_MA0 DDR_B_D32 BK13 BC18 DDR_B_MA0
DDR_A_D33 SA_DQ32 SA_MA0 DDR_A_MA1 DDR_B_D33 SB_DQ32 SB_MA0 DDR_B_MA1
AT13 SA_DQ33 SA_MA1 BD20 BE11 SB_DQ33 SB_MA1 BG28
DDR_A_D34 AW11 BK27 DDR_A_MA2 DDR_B_D34 BK11 BG25 DDR_B_MA2
DDR_A_D35 SA_DQ34 SA_MA2 DDR_A_MA3 DDR_B_D35 SB_DQ34 SB_MA2 DDR_B_MA3
AV11 SA_DQ35 SA_MA3 BH28 BC11 SB_DQ35 SB_MA3 AW17
DDR_A_D36 AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
DDR_A_D37 SA_DQ36 SA_MA4 DDR_A_MA5 DDR_B_D37 SB_DQ36 SB_MA4 DDR_B_MA5
AT11 SA_DQ37 SA_MA5 BK28 BE12 SB_DQ37 SB_MA5 BE25
DDR_A_D38 BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
DDR_A_D39 SA_DQ38 SA_MA6 DDR_A_MA7 DDR_B_D39 SB_DQ38 SB_MA6 DDR_B_MA7
BA11 SA_DQ39 SA_MA7 BJ25 BG12 SB_DQ39 SB_MA7 BC28
DDR_A_D40 BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
DDR_A_D41 SA_DQ40 SA_MA8 DDR_A_MA9 DDR_B_D41 SB_DQ40 SB_MA8 DDR_B_MA9
BD10 SA_DQ41 SA_MA9 BA28 BL9 SB_DQ41 SB_MA9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
DDR_A_D43 SA_DQ42 SA_MA10 DDR_A_MA11 DDR_B_D43 SB_DQ42 SB_MA10 DDR_B_MA11
AY9 SA_DQ43 SA_MA11 BE28 BL5 SB_DQ43 SB_MA11 BE37
DDR_A_D44 BG10 BG30 DDR_A_MA12 DDR_B_D44 BK9 BA39 DDR_B_MA12
DDR_A_D45 SA_DQ44 SA_MA12 DDR_A_MA13 DDR_B_D45 SB_DQ44 SB_MA12 DDR_B_MA13
AW9 SA_DQ45 SA_MA13 BJ16 BK10 SB_DQ45 SB_MA13 BG13
DDR_A_D46 BD7 BJ29 DDR_A_MA14 DDR_B_D46 BJ8 BE24 DDR_B_MA14
DDR_A_D47 SA_DQ46 SA_MA14 DDR_B_D47 SB_DQ46 SB_MA14
BB9 BJ6
B DDR_A_D48 BB5
SA_DQ47
SA_DQ48 SA_RAS# BE18 DDR_A_RAS#
DDR_A_RAS# 14
DDR_B_D48 BF4
SB_DQ47
SB_DQ48 SB_RAS# AV16 DDR_B_RAS#
DDR_B_RAS# 15
B
DDR_A_D49 AY7 AY20 SA_RCVEN# DDR_B_D49 BH5 AY18 SB_RCVEN#
SA_DQ49 SA_RCVEN# TP30 SB_DQ49 SB_RCVEN# TP28
DDR_A_D50 AT5 DDR_B_D50 BG1
DDR_A_D51 SA_DQ50 DDR_A_WE# DDR_B_D51 SB_DQ50 DDR_B_WE#
AT7 SA_DQ51 SA_WE# BA19 DDR_A_WE# 14 BC2 SB_DQ51 SB_WE# BC17 DDR_B_WE# 15
DDR_A_D52 AY6 DDR_B_D52 BK3
DDR_A_D53 SA_DQ52 DDR_B_D53 SB_DQ52
BB7 SA_DQ53 BE4 SB_DQ53
DDR_A_D54 AR5 DDR_B_D54 BD3
DDR_A_D55 SA_DQ54 DDR_B_D55 SB_DQ54
AR8 SA_DQ55 BJ2 SB_DQ55
DDR_A_D56 AR9 DDR_B_D56 BA3
DDR_A_D57 SA_DQ56 DDR_B_D57 SB_DQ56
AN3 SA_DQ57 BB3 SB_DQ57
DDR_A_D58 AM8 DDR_B_D58 AR1
DDR_A_D59 SA_DQ58 DDR_B_D59 SB_DQ58
AN10 SA_DQ59 AT3 SB_DQ59
DDR_A_D60 AT9 DDR_B_D60 AY2
DDR_A_D61 SA_DQ60 DDR_B_D61 SB_DQ60
AN9 SA_DQ61 AY3 SB_DQ61
DDR_A_D62 AM9 DDR_B_D62 AU2
DDR_A_D63 SA_DQ62 DDR_B_D63 SB_DQ62
AN11 SA_DQ63 AT2 SB_DQ63

NB:71.GM965.A0U NB:71.GM965.A0U

<Core Design>
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CRESTLINE(2/6)-DDR2 A/B CH
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 9 of 47
 5 4 3 2 1

1D05V_S0
For Crestline : 2.4 Kohm 1 2
For Calero : 1.5Kohm U50C 3 OF 10
R74 24D9R2F-L-GP
PEGCOMP trace
Strap Pin Table
J40 N43 PEGCOMP width and spacing 010 = FSB 800MHz
18 LBKLT_CTL RN56 L_BKLT_CTRL PEG_COMPI
34 GMCH_BL_ON H39 L_BKLT_EN PEG_COMPO M43 is 20/25 mils. CFG[2:0] FSB Freq select 011 = FSB 667MHz
3D3V_S0 3 2 E39 L_CTRL_CLK Others = Reserved
4 1 E40 L_CTRL_DATA
18 LDDC_CLK DY C37 L_DDC_CLK PEG_RX#0 J51
SRN10KJ-5-GP D35 L51 SDVOB_INT- 23 CFG5 (DMI select) 0 = DMI x 2
18 LDDC_DATA L_DDC_DATA PEG_RX#1
18 LCDVDD_EN K40 L_VDD_EN PEG_RX#2 N47 1 = DMI x 4 *
PEG_RX#3 T45
D 1 2 LVDS_IBG L41 T50 D
R68 3K3R2F-2-GP LVDS_IBG PEG_RX#4
-1:0908 Chang R68 from TP41 L43 LVDS_VBG PEG_RX#5 U40 CFG6 Reserved
64.24015.6DL to 64.33015.6DL N41 LVDS_VREFH PEG_RX#6 Y44
N40 LVDS_VREFL PEG_RX#7 Y40
18 VGA_TXACLK- D46 LVDSA_CLK# PEG_RX#8 AB51 0 = Reserved
18 VGA_TXACLK+ C45 LVDSA_CLK PEG_RX#9 W49 CFG7 (CPU Strap) 1 = Mobile CPU *

LVDS
18 VGA_TXBCLK- D44 LVDSB_CLK# PEG_RX#10 AD44
18 VGA_TXBCLK+ E42 LVDSB_CLK PEG_RX#11 AD40
PEG_RX#12 AG46 0 = Normal mode
18 VGA_TXAOUT0- G51 LVDSA_DATA#0 PEG_RX#13 AH49 CFG8 (Low power PCIE) 1 = Low Power mode *
18 VGA_TXAOUT1- E51 LVDSA_DATA#1 PEG_RX#14 AG45
18 VGA_TXAOUT2- F49 LVDSA_DATA#2 PEG_RX#15 AG41
C48 LVDSA_DATA#3 CFG9 0 = Reverse Lane
PEG_RX0 J50 (PCIE Graphics Lane Reversal) 1 = Normal Operation *
18 VGA_TXAOUT0+ G50 LVDSA_DATA0 PEG_RX1 L50 SDVOB_INT+ 23
18 VGA_TXAOUT1+ E50 LVDSA_DATA1 PEG_RX2 M47
18 VGA_TXAOUT2+ F48 LVDSA_DATA2 PEG_RX3 U44 CFG[11:10] Reserved
D47 LVDSA_DATA3 PEG_RX4 T49
PEG_RX5 T41
18 VGA_TXBOUT0- G44 LVDSB_DATA#0 PEG_RX6 W45 00 = Reserved
18 VGA_TXBOUT1- B47 LVDSB_DATA#1 PEG_RX7 W41 01 = XOR Mode Enabled
B45 AB50 CFG[13:12] (XOR/ALLZ) 10 = All Z Mode Enabled

PCI_EXPRESS GRAPHICS
18 VGA_TXBOUT2- LVDSB_DATA#2 PEG_RX8
PEG_RX9 Y48 11 = Normal Operation (Default)*
PEG_RX10 AC45
18 VGA_TXBOUT0+ E44 LVDSB_DATA0 PEG_RX11 AC41
18 VGA_TXBOUT1+ A47 LVDSB_DATA1 PEG_RX12 AH47 CFG[15:14] Reserved
18 VGA_TXBOUT2+ A45 LVDSB_DATA2 PEG_RX13 AG49
PEG_RX14 AH45
M_COMP AG42 0 = Disable
C 35 M_COMP M_LUMA PEG_RX15 C
35 M_LUMA CFG16 (FSB Dynamic ODT) 1 = Enable *
M_CRMA N45 NB_SDVOB_R-
35 M_CRMA PEG_TX#0 NB_SDVOB_G-
E27 TVA_DAC PEG_TX#1 U39
1

G27 U47 NB_SDVOB_B- CFG[18:17] Reversed

TVB_DAC PEG_TX#2
150R2F-1-GP

150R2F-1-GP

150R2F-1-GP

K27 N51 NB_SDVOB_C-

TVC_DAC PEG_TX#3
R54

R55

R53

PEG_TX#4 R50

TV
F27 TVA_RTN PEG_TX#5 T42 SDVO_CTRLDATA 0 = No SDVO Device Present *
J27 Y43 1 = SDVO Device Present
2

TVB_RTN PEG_TX#6
L27 TVC_RTN PEG_TX#7 W46
PEG_TX#8 W38
TV_DCONSEL0 M35 AD39 0 = Normal Operation *
8 TV_DCONSEL0 TV_DCONSEL1 TV_DCONSEL0 PEG_TX#9
8 TV_DCONSEL1 P33 TV_DCONSEL1 PEG_TX#10 AC46 CFG19(DMI Lane Reversal) (Lane number in Order)
PEG_TX#11 AC49
PEG_TX#12 AC42 1 = Reverse lane
M_BLUE AH39
17 M_BLUE M_GREEN PEG_TX#13
17 M_GREEN PEG_TX#14 AE49
M_RED AH44 0 = Only PCIE or SDVO is operational *
17 M_RED PEG_TX#15
CFG20(PCIE/SDVO consurrent) 1 = PCIE/SDVO are operating simu.
1

1
150R2F-1-GP

150R2F-1-GP

150R2F-1-GP

M45 NB_SDVOB_R+
PEG_TX0
1

H32 T38 NB_SDVOB_G+

CRT_BLUE PEG_TX1
R57

R61

G32 T46 NB_SDVOB_B+

CRT_BLUE# PEG_TX2
R56

K29 N50 NB_SDVOB_C+

CRT_GREEN PEG_TX3
J29 R51
2

CRT_GREEN# PEG_TX4
F29 U43
2

CRT_RED PEG_TX5
VGA

E29 CRT_RED# PEG_TX6 W42

PEG_TX7 Y47
PEG_TX8 Y39
17 GMCH_DDCCLK K33 CRT_DDC_CLK PEG_TX9 AC38
RN54 G35 AD47
B 17 GMCH_DDCDATA CRT_VSYNC CRT_DDC_DATA PEG_TX10 B
17 GMCH_VSYNC 1 4 E33 CRT_VSYNC PEG_TX11 AC50
17 GMCH_HSYNC 2 3 C32 CRT_TVO_IREF PEG_TX12 AD43
CRT_HSYNC F33 AG39 NB_SDVOB_R- C469 2 1 SCD1U10V2KX-4GP
SRN33J-5-GP-U CRT_HSYNC PEG_TX13 SDVOB_R- 23
PEG_TX14 AE50
1 2 CRTIREF AH43 NB_SDVOB_G- C464 2 1 SCD1U10V2KX-4GP
R60 1K3R2F-1-GP PEG_TX15 SDVOB_G- 23
SA:0428 NB_SDVOB_B- C474 2 1 SCD1U10V2KX-4GP SDVOB_B- 23
FOR Calero: 255 ohm NB_SDVOB_C- C480 2 1 SCD1U10V2KX-4GP SDVOB_C- 23
Crestline: 1.3k ohm
NB:71.GM965.A0U
NB_SDVOB_R+ C470 2 1 SCD1U10V2KX-4GP SDVOB_R+ 23
NB_SDVOB_G+ C468 2 1 SCD1U10V2KX-4GP SDVOB_G+ 23
NB_SDVOB_B+ C478 2 1 SCD1U10V2KX-4GP SDVOB_B+ 23
NB_SDVOB_C+ C484 2 1 SCD1U10V2KX-4GP SDVOB_C+ 23

3D3V_S0

RN55
3 2 LDDC_CLK
4 1 LDDC_DATA

A
SRN10KJ-5-GP <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CRESTLINE(3/6)-VGA/LVDS/TV
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 10 of 47
5 4 3 2 1
 5 4 3 2 1

3D3V_S0_DAC_BG 3D3V_S0
R58
2 1
0R3-0-U-GP 3D3V_S0 1D25V_S0
SCD1U16V2ZY-2GP
1

1D25V_S0_DPLLB
C121

SB:07/01 Change R58,R59 from Place C69,C70

1D05V_S0 1 2
0602 close pad to 1D25V_S0 near Pin
2

1
L26 L-10UH-11-GP -1:0914
63.00000.00L C124 U50H 8 OF 10 B23,B21,A21

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SCD1U16V2ZY-2GP C493 C170 C99

SCD1U16V2ZY-2GP
D U13 C107 D
VTT

SC1U10V3ZY-6GP
J32 U12

2
VCC_SYNC VTT

1
3D3V_S0_DAC_CRT 3D3V_S0

SC10U6D3V5KX-1GP
U11 C106 C83 C168
VTT

SCD1U16V2ZY-2GP
R59

SC4D7U6D3V5KX-3GP
A33 VCCA_CRT_DAC VTT U9
2 1 3D3V_S0_DAC_CRT B33 U8

2
VCCA_CRT_DAC VTT

CRT
VTT U7
SCD1U16V2ZY-2GP

0R3-0-U-GP U5
VTT
1

3D3V_S0_DAC_BG A30 VCCA_DAC_BG VTT U3

C127

VTT U2
B32 U1
2

VSSA_DAC_BG VTT 1D8V_S3

VTT
VTT T13
1D25V_S0_HPLL
Place TC21 near R58 and R59 VTT T11 L16

1
T10 C75 C137 C76

SCD47U16V3ZY-3GP
VTT

SC4D7U6D3V5KX-3GP
1D25V_S0_DPLLA B49 VCCA_DPLLA VTT T9 1 2 1D25V_S0 Place C75,C76 near

SC1U10V3KX-3GP
T7 Pin

2
VTT

1
3D3V_S0

SC10U6D3V5KX-1GP
1D25V_S0_DPLLB H49 T6 C396 C399 BLM18AG121SN-1GP C126 C102
VCCA_DPLLB VTT BK24,BK23,BJ24,BJ23

SCD1U16V2ZY-2GP
PLL
VTT T5

SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP
1D25V_S0_HPLL AL2 T3

2
VCCA_HPLL VTT
T2

2
VTT
1

1D25V_S0_MPLL 150mA AM2 VCCA_MPLL VTT R3

TC21 R2
VTT
SC22U6D3V5MX-2GP

DY R1
1D8V_S0_TXLVDS
POWER

A LVDS
2

VTT 1D25V_S0
A41 VCCA_LVDS
1
C157
SC1KP50V2KX-1GP B41 AT23
3D3V_S0 VSSA_LVDS VCC_AXD
AU28
2

VCC_AXD

SC1U10V3KX-3GP
VCC_AXD AU24

1
400uA K50 AT29 C117 C110 1D25V_S0_PEGPLL 1D5V_S0

AXD
VCCA_PEG_BG VCC_AXD L4
AT25 SC10U6D3V5KX-1GP
VCC_AXD
1

C K49 AT30 1 2 C

A PEG
1D25V_S0

2
C171 VSSA_PEG_BG VCC_AXD

SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP

SCD022U16V2KX-3GP

SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP C176 C119 C125 Place C82,C83
AR29 DY
2

VCC_AXD_NCTF BLM18PG121SN-1GP

1
C181 near Pin
1D25V_S0_PEGPLL 20mil U51 VCCA_PEG_PLL M32,L29
B23 1D25V_S0

2
VCC_AXF 1D25V_S0
SCD1U16V2ZY-2GP

AXF
C167 B21
VCC_AXF
1

AW18 VCCA_SM VCC_AXF A21

AV19 VCCA_SM
1D25V_S0 -1:0909 AU19 AJ50
2

VCCA_SM VCC_DMI
SC10U6D3V5KX-1GP

AU18 VCCA_SM

SCD1U16V2ZY-2GP
AU17 C96
VCCA_SM

1
VCC_SM_CK BK24 1D8V_S3
1

C89 C115 C94 C118 AT22 BK23

A SM

SM CK
VCCA_SM VCC_SM_CK 1D25V_S0_DPLLA 1D25V_S0
SC10U6D3V5KX-1GP

SCD22U10V3KX-2GP

AT21 BJ24 1D8V_S0_TXLVDS

2
VCCA_SM VCC_SM_CK

SC1KP50V2KX-1GP
SC1U10V3KX-3GP

AT19 BJ23
2

VCCA_SM VCC_SM_CK

1
AT18 C153 1 2 1D25V_S0
VCCA_SM L25 L-10UH-11-GP
AT17 VCCA_SM

SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
AR17 C60 Place C96

2
VCCA_SM_NCTF

1
AR16 A43 C490 C492 near Pin
1D25V_S0 VCCA_SM_NCTF VCC_TX_LVDS
3D3V_S0_HV AN2

2
BC29 C40
A CK

VCCA_SM_CK VCC_HV
HV

BB29 VCCA_SM_CK VCC_HV B40

1

1
C82 C101 C104
SC1U10V3KX-3GP

SC10U6D3V5KX-1GP

C25 C139
SCD1U16V2ZY-2GP

3D3V_S0_TVDACA VCCA_TVA_DAC
B25 AD51 1D05V_S0
2

2
VCCA_TVA_DAC VCC_PEG

SCD1U16V2ZY-2GP
3D3V_S0_TVDACB C27 VCCA_TVB_DAC VCC_PEG W50
TV

PEG

B27 VCCA_TVB_DAC VCC_PEG W51

B B
3D3V_S0_TVDACC B28 VCCA_TVC_DAC VCC_PEG V49
A28 V50 1D05V_S0 1D25V_S0_MPLL
VCCA_TVC_DAC VCC_PEG L17
1 2 1D25V_S0
M32 AH50
TV/CRT

3D3V_S0_TVDACC 1D5V_S0 VCCD_CRT VCC_RXR_DMI

SCD1U16V2ZY-2GP
DMI

L29 AH51 Place C407 C411 BLM18AG121SN-1GP

VCCD_TVDAC VCC_RXR_DMI

1
SCD022U16V2KX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
VCCA_TVDAC C169 C180 C179 C95,C99,C112

SC10U6D3V5KX-1GP

SCD1U16V2ZY-2GP
2 R271 1 1D5V_S0 N28 20mil
C446 C445 0R0603-PAD VCCD_QDAC VTTLF1 near Pin
A7
VTTLF

2
VTTLF
1

AD51,W50,W51
SCD1U16V2ZY-2GP

1D25V_S0 AN2 F2 VTTLF2

VCCD_HPLL VTTLF VTTLF3
VTTLF AH1
1D25V_S0_PEGPLL U48
2

VCCD_PEG_PLL
J41 C404 C406 C422
LVDS

VCCD_LVDS
1

1
1D8V_S0_LVDS H42 VCCD_LVDS
SCD47U16V3ZY-3GP

SCD47U16V3ZY-3GP

3D3V_S0_TVDACA
NB:71.GM965.A0U SCD47U16V3ZY-3GP
2

1D05V_S0_D 3D3V_S0 3D3V_S0_HV

SCD022U16V2KX-3GP

VCCA_TVDAC 1D05V_S0 1 D12

2 R267 1 R70
1D5V_S0
SCD1U16V2ZY-2GP

0R0603-PAD 3 2 1 2 R71 1
1

C433 BAS16-1-GP 0R0402-PAD

1
C434

SCD022U16V2KX-3GP

2 10R2J-2-GP
SCD1U16V2ZY-2GP

Place C108,C109 C144

2

C114 C105near SCD1U16V2KX-3GP

Pin N28

2
2

1D8V_S0_TXLVDS

3D3V_S0_TVDACB
A 40mil VCCA_TVDAC <Core Design> A
VCCA_TVDAC 1 R79 2 1D8V_S3 3D3V_S0
SC10U6D3V5KX-1GP

2 R269 1 0R0603-PAD
1

0R0603-PAD C162
Wistron Corporation
1

C440 C439 1D8V_S0_LVDS

SCD022U16V2KX-3GP

SCD1U16V2ZY-2GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

L19
2

1 R82 2 Taipei Hsien 221, Taiwan, R.O.C.

1D8V_S3
2

0R0603-PAD 1 2
1

1
C172 C164 BLM18PG181SN-3GP C447 Title
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP SC1U10V3KX-3GP L85 2nd source CRESTLINE(4/6)-PWR
2

Size Document Number Rev

68.00214.101/68.00217.141 A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 11 of 47
5 4 3 2 1
 5 4 3 2 1

1D05V_S0 LIB C
U50F 6 OF 10 1D05V_S0 U50G 7 OF 10
-1:0909
AT35 T17 1D05V_S0 AB33
VCC VCC_AXG_NCTF VCC_NCTF
AT34 VCC VCC_AXG_NCTF T18 AB36 VCC_NCTF
AH28 VCC VCC_AXG_NCTF T19 AB37 VCC_NCTF
AC32 VCC VCC_AXG_NCTF T21 AC33 VCC_NCTF VSS_NCTF T27
AC31 VCC VCC_AXG_NCTF T22 AC35 VCC_NCTF VSS_NCTF T37

C136

C403

C402

C128

C130

C100
AK32 VCC VCC_AXG_NCTF T23 AC36 VCC_NCTF VSS_NCTF U24

1
AJ31 T25 TC15 AD35 U28

VCC CORE
VCC VCC_AXG_NCTF VCC_NCTF VSS_NCTF
D AJ28 VCC VCC_AXG_NCTF U15 AD36 VCC_NCTF VSS_NCTF V31 D
AH32 U16 AF33 V35

2
VCC VCC_AXG_NCTF C90 C120 C79 VCC_NCTF VSS_NCTF
AH31 VCC VCC_AXG_NCTF U17 DY AF36 VCC_NCTF VSS_NCTF AA19

1
AH29 U19 AH33 AB17

VSS NCTF
VCC VCC_AXG_NCTF VCC_NCTF VSS_NCTF

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

SCD1U16V2ZY-2GP
ST220U2VBM-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AF32 VCC VCC_AXG_NCTF U20 AH35 VCC_NCTF VSS_NCTF AB35
U21 AH36 AD19

2
VCC_AXG_NCTF VCC_NCTF VSS_NCTF
VCC_AXG_NCTF U23 AH37 VCC_NCTF VSS_NCTF AD37
VCC_AXG_NCTF U26 AJ33 VCC_NCTF VSS_NCTF AF17
VCC_AXG_NCTF V16 AJ35 VCC_NCTF VSS_NCTF AF35
R30 VCC VCC_AXG_NCTF V17 AK33 VCC_NCTF VSS_NCTF AK17

SCD22U10V2KX-1GP

SC4D7U6D3V5KX-3GP
V19 AK35 AM17

SCD1U16V2ZY-2GP
VCC_AXG_NCTF VCC_NCTF VSS_NCTF
VCC_AXG_NCTF V20 AK36 VCC_NCTF VSS_NCTF AM24
VCC_AXG_NCTF V21 AK37 VCC_NCTF VSS_NCTF AP26
V23 AD33 AP28

VCC NCTF
VCC_AXG_NCTF VCC_NCTF VSS_NCTF
VCC_AXG_NCTF V24 AJ36 VCC_NCTF VSS_NCTF AR15
VCC_AXG_NCTF Y15 AM35 VCC_NCTF VSS_NCTF AR19
Y16 AL33 AR28
POWER VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
Y17
Y19
AL35
AA33
VCC_NCTF
VCC_NCTF
VCC_NCTF
VSS_NCTF

AU32 VCC_SM VCC_AXG_NCTF Y20 AA35 VCC_NCTF

1D8V_S3 AU33 Y21 AA36
VCC_SM VCC_AXG_NCTF VCC_NCTF
AU35 VCC_SM VCC_AXG_NCTF Y23 AP35 VCC_NCTF
AV33 VCC_SM VCC_AXG_NCTF Y24 AP36 VCC_NCTF
AW33 VCC_SM VCC_AXG_NCTF Y26 AR35 VCC_NCTF
C132

C142

C133

C131

TC17 AW35 Y28 AR36

VCC_SM VCC_AXG_NCTF VCC_NCTF
1

AY35 VCC_SM VCC_AXG_NCTF Y29 Y32 VCC_NCTF

BA32 VCC_SM VCC_AXG_NCTF AA16 Y33 VCC_NCTF
BA33 AA17 Y35
2

VCC_SM VCC_AXG_NCTF VCC_NCTF

DY BA35 AB16 Y36
C BB33
VCC_SM
VCC_SM
VCC_AXG_NCTF
VCC_AXG_NCTF AB19 Y37
VCC_NCTF
VCC_NCTF POWER C
ST220U2VBM-3GP

SC10U6D3V5KX-1GP

SCD01U16V2KX-3GP

BC32 AC16 T30

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

VCC_SM VCC_AXG_NCTF VCC_NCTF NCTF_U56-1 TP89

BC33 AC17 T34 A3

VSS SCB
VCC_SM VCC_AXG_NCTF VCC_NCTF VSS_SCB
BC35 VCC_SM VCC_AXG_NCTF AC19 T35 VCC_NCTF VSS_SCB B2
BD32 AD15 U29 C1
VCC SM

VCC GFX NCTF

VCC_SM VCC_AXG_NCTF VCC_NCTF VSS_SCB NCTF_U56-2 TP88
BD35 VCC_SM VCC_AXG_NCTF AD16 U31 VCC_NCTF VSS_SCB BL1
BE32 AD17 U32 BL51 NCTF_U56-4 TP96
VCC_SM VCC_AXG_NCTF VCC_NCTF VSS_SCB NCTF_U56-3 TP95
BE33 VCC_SM VCC_AXG_NCTF AF16 U33 VCC_NCTF VSS_SCB A51
BE35 VCC_SM VCC_AXG_NCTF AF19 U35 VCC_NCTF
BF33 VCC_SM VCC_AXG_NCTF AH15 U36 VCC_NCTF
BF34 VCC_SM VCC_AXG_NCTF AH16 V32 VCC_NCTF
BG32 VCC_SM VCC_AXG_NCTF AH17 V33 VCC_NCTF
BG33 VCC_SM VCC_AXG_NCTF AH19 V36 VCC_NCTF
BG35 VCC_SM VCC_AXG_NCTF AJ16 V37 VCC_NCTF
BH32 AJ17 AT33 1D05V_S0

VSS AXM
VCC_SM VCC_AXG_NCTF VCC_AXM
BH34 VCC_SM VCC_AXG_NCTF AJ19 VCC_AXM AT31
BH35 VCC_SM VCC_AXG_NCTF AK16 VCC_AXM AK29
BJ32 VCC_SM VCC_AXG_NCTF AK19 VCC_AXM AK24
BJ33 AL16 1D05V_S0 AK23
VCC_SM VCC_AXG_NCTF VCC_AXM
BJ34 VCC_SM VCC_AXG_NCTF AL17 VCC_AXM AJ26
BK32 VCC_SM VCC_AXG_NCTF AL19 VCC_AXM AJ23
BK33 VCC_SM VCC_AXG_NCTF AL20 AL24 VCC_AXM_NCTF
BK34 VCC_SM VCC_AXG_NCTF AL21 AL26 VCC_AXM_NCTF
BK35 VCC_SM VCC_AXG_NCTF AL23 AL28 VCC_AXM_NCTF

1
BL33 AM15 C92 AM26

VSS AXM NCTF

1D05V_S0 VCC_SM VCC_AXG_NCTF SC10U6D3V5KX-1GP VCC_AXM_NCTF
AU30 VCC_SM VCC_AXG_NCTF AM16 AM28 VCC_AXM_NCTF
AM19 AM29

2
VCC_AXG_NCTF VCC_AXM_NCTF
VCC_AXG_NCTF AM20 AM31 VCC_AXM_NCTF
VCC_AXG_NCTF AM21 AM32 VCC_AXM_NCTF
B B
R20 VCC_AXG VCC_AXG_NCTF AM23 AM33 VCC_AXM_NCTF
T14 VCC_AXG VCC_AXG_NCTF AP15 AP29 VCC_AXM_NCTF
C134 C129 W13 AP16 AP31
VCC_AXG VCC_AXG_NCTF VCC_AXM_NCTF
1

C87 C111 W14 AP17 AP32

VCC_AXG VCC_AXG_NCTF VCC_AXM_NCTF
Y12 VCC_AXG VCC_AXG_NCTF AP19 AP33 VCC_AXM_NCTF
AA20 AP20 AL29
2

VCC_AXG VCC_AXG_NCTF VCC_AXM_NCTF

AA23 VCC_AXG VCC_AXG_NCTF AP21 AL31 VCC_AXM_NCTF
AA26 VCC_AXG VCC_AXG_NCTF AP23 AL32 VCC_AXM_NCTF
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

AA28 AP24 AR31

SCD1U16V2ZY-2GP

VCC_AXG VCC_AXG_NCTF VCC_AXM_NCTF

C160

C158

C116

C140

C141
SC1U10V3KX-3GP

AB21 VCC_AXG VCC_AXG_NCTF AR20 AR32 VCC_AXM_NCTF

1
AB24 VCC_AXG VCC_AXG_NCTF AR21 AR33 VCC_AXM_NCTF
AB29 AR23
VCC GFX

VCC_AXG VCC_AXG_NCTF
AC20 AR24

2
VCC_AXG VCC_AXG_NCTF
AC21 VCC_AXG VCC_AXG_NCTF AR26
AC23 VCC_AXG VCC_AXG_NCTF V26
AC24 VCC_AXG VCC_AXG_NCTF V28

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
AC26 VCC_AXG VCC_AXG_NCTF V29
AC28 VCC_AXG VCC_AXG_NCTF Y31
AC29 VCC_AXG
AD20 VCC_AXG
AD23 VCC_AXG
AD24 AW45 VCCSM_LF1
VCC SM LF

VCC_AXG VCC_SM_LF VCCSM_LF2

AD28 VCC_AXG VCC_SM_LF BC39
AF21 BE39 VCCSM_LF3
VCC_AXG VCC_SM_LF VCCSM_LF4
AF26 VCC_AXG VCC_SM_LF BD17
AA31 BD4 VCCSM_LF5
VCC_AXG VCC_SM_LF VCCSM_LF6
AH20 VCC_AXG VCC_SM_LF AW8
C66

C71

C62

C93

C143

C155

C156

AH21 AT6 VCCSM_LF7

VCC_AXG VCC_SM_LF
A AH23 VCC_AXG <Core Design> A
1

AH24 VCC_AXG
AH26 VCC_AXG
AD31
Wistron Corporation
2

VCC_AXG
SC1U10V3KX-3GP
SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

AJ20
SCD47U16V3ZY-3GP
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

VCC_AXG
SC1U10V3KX-3GP

AN14 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

VCC_AXG Taipei Hsien 221, Taiwan, R.O.C.

Title
NB:71.GM965.A0U CRESTLINE(5/6)-PWR/GND
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 12 of 47
5 4 3 2 1
 5 4 3 2 1

U50I 9 OF 10 U50J10 OF 10
U50J10

A13 VSS VSS AW24 C46 VSS VSS W11

A15 VSS VSS AW29 C50 VSS VSS W39
A17 VSS VSS AW32 C7 VSS VSS W43
A24 VSS VSS AW5 D13 VSS VSS W47
AA21 VSS VSS AW7 D24 VSS VSS W5
AA24 VSS VSS AY10 D3 VSS VSS W7
AA29 VSS VSS AY24 D32 VSS VSS Y13
AB20 VSS VSS AY37 D39 VSS VSS Y2
AB23 VSS VSS AY42 D45 VSS VSS Y41
D AB26 VSS VSS AY43 D49 VSS VSS Y45 D
AB28 VSS VSS AY45 E10 VSS VSS Y49
AB31 VSS VSS AY47 E16 VSS VSS Y5
AC10 VSS VSS AY50 E24 VSS VSS Y50
AC13 VSS VSS B10 E28 VSS VSS Y11
AC3 VSS VSS B20 E32 VSS VSS P29
AC39 VSS VSS B24 E47 VSS VSS T29
AC43 VSS VSS B29 F19 VSS VSS T31
AC47 VSS VSS B30 F36 VSS VSS T33
AD1 VSS VSS B35 F4 VSS VSS R28
AD21 VSS VSS B38 F40 VSS
AD26 VSS VSS B43 F50 VSS
AD29 VSS VSS B46 G1 VSS
AD3 VSS VSS B5 G13 VSS
AD41 VSS VSS B8 G16 VSS VSS AA32
AD45 VSS VSS BA1 G19 VSS VSS AB32
AD49 VSS VSS BA17 G24 VSS VSS AD32
AD5 VSS VSS BA18 G28 VSS VSS AF28
AD50 VSS VSS BA2 G29 VSS VSS AF29
AD8 VSS VSS BA24 G33 VSS VSS AT27
AE10 VSS VSS BB12 G42 VSS VSS AV25
AE14 VSS VSS BB25 G45 VSS VSS H50
AE6 VSS VSS BB40 G48 VSS
AF20 VSS VSS BB44 G8 VSS
AF23 VSS VSS BB49 H24 VSS
AF24 VSS VSS BB8 H28 VSS
AF31 VSS VSS BC16 H4 VSS
AG2 BC24 H45
C
AG38
AG43
VSS
VSS
VSS
VSS BC25
BC36
J11
J16
VSS
VSS VSS C
VSS VSS VSS
AG47 VSS VSS BC40 J2 VSS
AG50 VSS VSS BC51 J24 VSS
AH3 VSS VSS BD13 J28 VSS
AH40 BD2 J33
AH41
AH7
VSS
VSS VSS VSS
VSS BD28
BD45
J35
J39
VSS
VSS
VSS VSS VSS
AH9 VSS VSS BD48 K12 VSS
AJ11 VSS VSS BD5 K47 VSS
AJ13 VSS VSS BE1 K8 VSS
AJ21 VSS VSS BE19 L1 VSS
AJ24 VSS VSS BE23 L17 VSS
AJ29 VSS VSS BE30 L20 VSS
AJ32 VSS VSS BE42 L24 VSS
AJ43 VSS VSS BE51 L28 VSS
AJ45 VSS VSS BE8 L3 VSS
AJ49 VSS VSS BF12 L33 VSS
AK20 VSS VSS BF16 L49 VSS
AK21 VSS VSS BF36 M28 VSS
AK26 VSS VSS BG19 M42 VSS
AK28 VSS VSS BG2 M46 VSS
AK31 VSS VSS BG24 M49 VSS
AK51 VSS VSS BG29 M5 VSS
AL1 VSS VSS BG39 M50 VSS
AM11 VSS VSS BG48 M9 VSS
AM13 VSS VSS BG5 N11 VSS
AM3 VSS VSS BG51 N14 VSS
AM4 VSS VSS BH17 N17 VSS
AM41 VSS VSS BH30 N29 VSS
B B
AM45 VSS VSS BH44 N32 VSS
AN1 VSS VSS BH46 N36 VSS
AN38 VSS VSS BH8 N39 VSS
AN39 VSS VSS BJ11 N44 VSS
AN43 VSS VSS BJ13 N49 VSS
AN5 VSS VSS BJ38 N7 VSS
AN7 VSS VSS BJ4 P19 VSS
AP4 VSS VSS BJ42 P2 VSS
AP48 VSS VSS BJ46 P23 VSS
AP50 VSS VSS BK15 P3 VSS
AR11 VSS VSS BK17 P50 VSS
AR2 VSS VSS BK25 R49 VSS
AR39 VSS VSS BK29 T39 VSS
AR44 VSS VSS BK36 T43 VSS
AR47 VSS VSS BK40 T47 VSS
AR7 VSS VSS BK44 U41 VSS
AT10 VSS VSS BK6 U45 VSS
AT14 VSS VSS BK8 U50 VSS
AT41 VSS VSS BL11 V2 VSS
AT49 VSS VSS BL13 V3 VSS
AU1 VSS VSS BL19
AU23 VSS VSS BL22
AU29 VSS VSS BL37
AU3 VSS VSS BL47
AU36
AU49
VSS VSS C12
C16
NB:71.GM965.A0U
VSS VSS
AU51 VSS VSS C19
AV39 VSS VSS C28
A AV48 VSS VSS C29 <Core Design> A
AW1 VSS VSS C33
AW12 VSS VSS C36
AW16 VSS VSS C41
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
NB:71.GM965.A0U
CRESTLINE(6/6)-PWR/GND
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 13 of 47
5 4 3 2 1
 5 4 3 2 1

DM2

MH1 MH2 M_CLK_DDR0

MH1 MH2 M_CLK_DDR#0
9 DDR_A_DQS#[0..7]
DDR_A_MA0 102 13 DDR_A_DQS0
DDR_A_MA1 A0 DQS0 DDR_A_DQS1
9 DDR_A_D[0..63] 101 A1 DQS1 31
DDR_A_MA2 100 51 DDR_A_DQS2
A2 DQS2

1
DDR_A_MA3 99 70 DDR_A_DQS3 C476 C477
9 DDR_A_DM[0..7] A3 DQS3

SC10P50V2JN-4GP

SC10P50V2JN-4GP
DDR_A_MA4 98 131 DDR_A_DQS4
DDR_A_MA5 A4 DQS4 DDR_A_DQS5
9 DDR_A_DQS[0..7] 97 148

2
DDR_A_MA6 A5 DQS5 DDR_A_DQS6
94 A6 DQS6 169
DDR_A_MA7 92 188 DDR_A_DQS7
9 DDR_A_MA[0..14] A7 DQS7
DDR_A_MA8 93 11 DDR_A_DQS#0
D DDR_A_MA9 A8 DQS0# DDR_A_DQS#1 D
91 A9 DQS1# 29
DDR_A_MA10 105 49 DDR_A_DQS#2
9 DDR_A_BS[0..2] A10/AP DQS2#
Layout Note: DDR_A_MA11 90 68 DDR_A_DQS#3 SB:0707 For EMI request
DDR_A_MA12 A11 DQS3# DDR_A_DQS#4
Place near DM1 89 A12 DQS4# 129 put near connector
DDR_A_MA13 116 146 DDR_A_DQS#5
DDR_A_MA14 A13 DQS5# DDR_A_DQS#6 M_CLK_DDR1
86 A14 DQS6# 167
84 186 DDR_A_DQS#7 M_CLK_DDR#1
DDR_A_BS2 A15 DQS7#
85 A16_BA2
10 DDR_A_DM0
DDR_A_BS0 DM0 DDR_A_DM1
107 BA0 DM1 26
1D8V_S3 DDR_A_BS1 106 52 DDR_A_DM2
BA1 DM2 DDR_A_DM3
DM3 67

1
DDR_A_D0 5 130 DDR_A_DM4 C388 C391
DQ0 DM4

SC10P50V2JN-4GP

SC10P50V2JN-4GP
DDR_A_D1 7 147 DDR_A_DM5
DDR_A_D2 DQ1 DM5 DDR_A_DM6
17 170

2
C91 C123 C77 C84 C81 C98 C69 C122 DDR_A_D3 DQ2 DM6 DDR_A_DM7
19 DQ3 DM7 185
1

1
DDR_A_D4 4 DQ4

SC10U6D3V5KX-1GP
DDR_A_D5 6 30 M_CLK_DDR0 M_CLK_DDR0 8
DQ5 CK0
SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
DDR_A_D6 14 32 M_CLK_DDR#0 M_CLK_DDR#0 8
2

2
DDR_A_D7 DQ6 CK0# M_CLK_DDR1
16 DQ7 CK1 164 M_CLK_DDR1 8
DDR_A_D8 23 166 M_CLK_DDR#1 M_CLK_DDR#1 8
DDR_A_D9 DQ8 CK1#
25 DQ9
DDR_A_D10 35 198 SA0 1 R37 2 0R0402-PAD
DDR_A_D11 DQ10 SA0 SA1 R39
37 DQ11 SA1 200 1 2 0R0402-PAD
DDR_A_D12 20 SA:0428
DDR_A_D13 DQ12
22 DQ13 VDD_SPD 199 3D3V_S0
DDR_A_D14 36
DDR_A_D15 DQ14 1D8V_S3
38 DQ15

1
DDR_A_D16 43 81 C41 C46
DDR_A_D17 DQ16 VDD SCD1U16V2ZY-2GP SC2D2U6D3V3KX-GP
45 DQ17 VDD 82
DDR_A_D18 55 87

2
C DDR_A_D19 DQ18 VDD C
DDR_A_D20
57 DQ19 VDD 88 DY
Layout Note: 44 DQ20 VDD 95
DDR_A_D21 46 96
Place one cap close to every 2 pullup DDR_A_D22 DQ21 VDD
56 DQ22 VDD 103
resistors terminated to +0.9VS DDR_A_D23 58 104
DDR_A_D24 DQ23 VDD
61 DQ24 VDD 111
DDR_A_D25 63 112
DDR_A_D26 DQ25 VDD
73 DQ26 VDD 117
DDR_A_D27 75 118
DDR_A_D28 DQ27 VDD
62 DQ28
DDR_A_D29 64 2
DDR_VREF_S0 DDR_A_D30 DQ29 VSS
74 DQ30 VSS 3
DDR_A_D31 76 8
DDR_A_D32 DQ31 VSS
123 DQ32 VSS 9
DDR_A_D33 125 12
DDR_A_D34 DQ33 VSS
135 DQ34 VSS 15
C112 C95 C73 C63 C423 C430 C438 C427 C85 C421 DDR_A_D35 137 18
DQ35 VSS
1

DDR_A_D36 124 21
DDR_A_D37 DQ36 VSS
126 DQ37 VSS 24
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DDR_A_D38 134 27
2

DDR_A_D39 DQ38 VSS

136 DQ39 VSS 28
DY DDR_A_D40 141 33
DDR_A_D41 DQ40 VSS
143 DQ41 VSS 34
DDR_A_D42 151 39
DDR_A_D43 DQ42 VSS
153 DQ43 VSS 40
DDR_A_D44 140 41
DDR_A_D45 DQ44 VSS
142 DQ45 VSS 42
DDR_A_D46 152 47
DDR_A_D47 DQ46 VSS
154 DQ47 VSS 48
DDR_A_D48 157 53
DDR_A_D49 DQ48 VSS
159 DQ49 VSS 54
DDR_A_D50 173 59
B DDR_A_D51 DQ50 VSS B
175 DQ51 VSS 60
DDR_A_D52 158 65
DDR_A_D53 DQ52 VSS
160 DQ53 VSS 66
DDR_A_D54 174 71
change to 8P4R DDR_A_D55
DDR_A_D56
176
179
DQ54
DQ55
DQ56
VSS
VSS
VSS
72
77
DDR_A_D57 181 78
DDR_A_D58 DQ57 VSS
189 DQ58 VSS 121
DDR_A_D59 191 122
DDR_A_D60 DQ59 VSS
180 DQ60 VSS 127
Layout Note: DDR_A_D61 182 128
DDR_VREF_S0 DDR_A_D62 DQ61 VSS
Place these resistors 192 DQ62 VSS 132
DDR_A_D63 194 133
closely DM1,all DQ63 VSS
RN13 RN15 138
DDR_A_MA9 DDR_A_MA12 VSS
1 8 1 8 trace length Max=1.5" 8 PM_EXTTS#0 50 NC#50 VSS 139
DDR_A_MA5 2 7 2 7 DDR_A_BS2 69 144
DDR_A_MA8 DDR_CKE0_DIMMA NC#69 VSS
3 6 3 6 83 NC#83 VSS 145
DDR_A_MA3 4 5 4 5 120 149
NC#120 VSS
163 NC#163/TEST VSS 150
SRN56J-5-GP SRN56J-5-GP 155
DDR_CS0_DIMMA# VSS
8 DDR_CS0_DIMMA# 110 CS0# VSS 156
RN11 RN50 8 DDR_CS1_DIMMA# DDR_CS1_DIMMA# 115 161
DDR_A_MA1 DDR_A_MA0 DDR_CKE0_DIMMA CS1# VSS
1 8 1 8 8 DDR_CKE0_DIMMA 79 CKE0 VSS 162
DDR_A_MA10 2 7 2 7 DDR_A_MA2 8 DDR_CKE1_DIMMA DDR_CKE1_DIMMA 80 165
DDR_A_BS0 DDR_A_MA4 DDR_A_RAS# CKE1 VSS
3 6 3 6 9 DDR_A_RAS# 108 RAS# VSS 168
DDR_A_WE# 4 5 4 5 DDR_A_MA6 9 DDR_A_CAS# DDR_A_CAS# 113 171
DDR_A_WE# CAS# VSS
9 DDR_A_WE# 109 WE# VSS 172
SRN56J-5-GP SRN56J-5-GP 177
ICH_SMBCLK VSS
4,15,21 ICH_SMBCLK 197 SCL VSS 178
RN9 RN48 ICH_SMBDATA 195 183
4,15,21 ICH_SMBDATA SDA VSS
DDR_A_CAS# 1 8 1 8 M_ODT0 184
DDR_A_MA13 DDR_CS0_DIMMA# M_ODT0 VSS
2 7 2 7 8 M_ODT0 114 ODT0 VSS 187
A M_ODT1 DDR_A_RAS# DDR_VREF_S3 M_ODT1 A
3 6 3 6 8 M_ODT1 119 ODT1 VSS 190
DDR_CS1_DIMMA# 4 5 4 5 DDR_A_BS1 193
DDR_VREF_S3 VSS
1 VREF VSS 196
SRN56J-5-GP SRN56J-5-GP
201 GND GND 202
Wistron Corporation
1

RN52 C184 C185

1 8 DDR_A_MA7 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2 7 DDR_A_MA11 Taipei Hsien 221, Taiwan, R.O.C.
SKT-SODIMM200-38GP
2

3 6 DDR_A_MA14
4 5 DDR_CKE1_DIMMA SCD1U16V2ZY-2GP SC2D2U16V5ZY-2GP Title

SRN56J-5-GP Main Source:62.10017.E31 DDRII-SODIMM SLOT1

2nd Source: 62.10017.A41 Size Document Number Rev
Custom
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 14 of 47
5 4 3 2 1
 5 4 3 2 1

M_CLK_DDR2

M_CLK_DDR#2
DM1

DDR_B_MA0 102 108 DDR_B_RAS# DDR_B_RAS# 9 C175 C174

A0 RAS#

1
SC10P50V2JN-4GP

SC10P50V2JN-4GP
DDR_B_MA1 101 109 DDR_B_WE# DDR_B_WE# 9
9 DDR_B_DQS#[0..7] A1 WE#
DDR_B_MA2 100 113 DDR_B_CAS# DDR_B_CAS# 9
DDR_B_MA3 A2 CAS#
9 DDR_B_D[0..63] 99

2
DDR_B_MA4 A3 DDR_CS2_DIMMB#
98 A4 CS0# 110 DDR_CS2_DIMMB# 8
DDR_B_MA5 97 115 DDR_CS3_DIMMB# DDR_CS3_DIMMB# 8
9 DDR_B_DM[0..7] A5 CS1#
DDR_B_MA6 94
DDR_B_MA7 A6 DDR_CKE2_DIMMB
9 DDR_B_DQS[0..7] 92 A7 CKE0 79 DDR_CKE2_DIMMB 8
DDR_B_MA8 93 80 DDR_CKE3_DIMMB DDR_CKE3_DIMMB 8
DDR_B_MA9 A8 CKE1
D 9 DDR_B_MA[0..14] 91 A9 put near connector D
DDR_B_MA10 105 30 M_CLK_DDR2 M_CLK_DDR2 8
DDR_B_MA11 A10/AP CK0 M_CLK_DDR#2
Layout Note: 9 DDR_B_BS[0..2] 90 A11 CK0# 32 M_CLK_DDR#2 8
DDR_B_MA12 89 M_CLK_DDR3
Place near DM2 DDR_B_MA13 A12 M_CLK_DDR3
116 A13 CK1 164 M_CLK_DDR3 8
DDR_B_MA14 86 166 M_CLK_DDR#3 M_CLK_DDR#3 8 M_CLK_DDR#3
A14 CK1#
84 A15
DDR_B_BS2 85 10 DDR_B_DM0 SB:0707 For EMI request
A16/BA2 DM0 DDR_B_DM1
DM1 26

1
DDR_B_BS0 107 52 DDR_B_DM2 C50 C51
BA0 DM2

SC10P50V2JN-4GP

SC10P50V2JN-4GP
DDR_B_BS1 106 67 DDR_B_DM3
1D8V_S3 BA1 DM3 DDR_B_DM4
130

2
DM4 DDR_B_DM5
DM5 147
DDR_B_D0 5 170 DDR_B_DM6
DDR_B_D1 DQ0 DM6 DDR_B_DM7
7 DQ1 DM7 185
DDR_B_D2 17
C88 C109 C67 C70 C103 C78 C72 C108 DDR_B_D3 DQ2
19 DQ3
1

1
DDR_B_D4 4 195 ICH_SMBDATA
DQ4 SDA ICH_SMBDATA 4,14,21

SC10U6D3V5KX-1GP
DDR_B_D5 6 197 ICH_SMBCLK
DQ5 SCL ICH_SMBCLK 4,14,21
SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

SC2D2U16V5ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
DDR_B_D6 14
2

2
DDR_B_D7 DQ6
16 DQ7 VDDSPD 199 3D3V_S0
DDR_B_D8 23
DDR_B_D9 DQ8 R36
25 DQ9 SA0 198 1 2 0R0402-PAD

1
DDR_B_D10 35 200 R38 1 2 10KR2J-3-GP 3D3V_S0 C44 C38
DDR_B_D11 DQ10 SA1 SA:0428 SCD1U16V2ZY-2GP SC2D2U6D3V3KX-GP
37 DQ11
DDR_B_D12 20 50 PM_EXTTS#1 8

2
DDR_B_D13 DQ12 NC#50
DDR_B_D14
22 DQ13 NC#69 69 DY
36 DQ14 NC#83 83
DDR_B_D15 38 120
DDR_B_D16 DQ15 NC#120
43 DQ16 NC#163/TEST 163
DDR_B_D17 45
DDR_B_D18 DQ17 1D8V_S3
55 DQ18
DDR_B_D19 57 81
C DDR_B_D20 DQ19 VDD C
Layout Note: 44 DQ20 VDD 82
DDR_B_D21 46 87
Place one cap close to every 2 pullup DDR_B_D22 DQ21 VDD
56 DQ22 VDD 88
resistors terminated to +0.9VS DDR_B_D23 58 95
DDR_B_D24 DQ23 VDD
61 DQ24 VDD 96
DDR_B_D25 63 103
DDR_B_D26 DQ25 VDD
73 DQ26 VDD 104
DDR_B_D27 75 111
DDR_B_D28 DQ27 VDD
62 DQ28 VDD 112
DDR_B_D29 64 117
DDR_VREF_S0 DDR_B_D30 DQ29 VDD
74 DQ30 VDD 118
DDR_B_D31 76
DDR_B_D32 DQ31
123 DQ32 VSS 3
DDR_B_D33 125 8
DDR_B_D34 DQ33 VSS
135 DQ34 VSS 9
C86 C64 C113 C419 C441 C443 C97 C425 C429 C74 DDR_B_D35 137 12
DQ35 VSS
1

DDR_B_D36 124 15
DDR_B_D37 DQ36 VSS
126 DQ37 VSS 18
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DDR_B_D38 134 21
2

DDR_B_D39 DQ38 VSS

136 DQ39 VSS 24
DY DDR_B_D40 141 27
DDR_B_D41 DQ40 VSS
143 DQ41 VSS 28
DDR_B_D42 151 33
DDR_B_D43 DQ42 VSS
153 DQ43 VSS 34
DDR_B_D44 140 39
DDR_B_D45 DQ44 VSS
142 DQ45 VSS 40
DDR_B_D46 152 41
DDR_B_D47 DQ46 VSS
154 DQ47 VSS 42
DDR_B_D48 157 47
DDR_B_D49 DQ48 VSS
159 DQ49 VSS 48
DDR_B_D50 173 53
DDR_B_D51 DQ50 VSS
175 DQ51 VSS 54
B DDR_B_D52 B
158 DQ52 VSS 59
DDR_B_D53 160 60
DDR_B_D54 DQ53 VSS
Layout Note: 174 DQ54 VSS 65
DDR_VREF_S0 DDR_B_D55 176 66
Place these resistors DDR_B_D56 DQ55 VSS
179 DQ56 VSS 71
RN49 RN14 closely DM2,all DDR_B_D57 181 72
DDR_B_BS0 DDR_B_MA14 DDR_B_D58 DQ57 VSS
1 8 1 8 trace length Max=1.5" 189 DQ58 VSS 77
DDR_B_MA10 2 7 2 7 DDR_B_MA6 DDR_B_D59 191 78
DDR_B_MA1 DDR_B_MA2 DDR_B_D60 DQ59 VSS
3 6 3 6 180 DQ60 VSS 121
DDR_B_MA3 4 5 4 5 DDR_B_MA4 DDR_B_D61 182 122
DDR_B_D62 DQ61 VSS
192 DQ62 VSS 127
SRN56J-5-GP SRN56J-5-GP DDR_B_D63 194 128
DQ63 VSS
VSS 132
RN12 RN51 DDR_B_DQS#0 11 133
DDR_CS2_DIMMB# DDR_B_MA12 DDR_B_DQS#1 DQS0# VSS
1 8 1 8 29 DQS1# VSS 138
DDR_B_BS1 2 7 2 7 DDR_B_MA9 DDR_B_DQS#2 49 139
DDR_B_RAS# DDR_B_MA8 DDR_B_DQS#3 DQS2# VSS
3 6 3 6 68 DQS3# VSS 144
DDR_B_MA0 4 5 4 5 DDR_B_MA5 DDR_B_DQS#4 129 145
DDR_B_DQS#5 DQS4# VSS
146 DQS5# VSS 149
SRN56J-5-GP SRN56J-5-GP DDR_B_DQS#6 167 150
DDR_B_DQS#7 DQS6# VSS
186 DQS7# VSS 155
RN47 RN10 156
M_ODT3 DDR_B_MA13 DDR_B_DQS0 VSS
1 8 1 4 13 DQS0 VSS 161
DDR_CS3_DIMMB# 2 7 2 3 M_ODT2 DDR_B_DQS1 31 162
DDR_B_CAS# DDR_B_DQS2 DQS1 VSS
3 6 51 DQS2 VSS 165
DDR_B_WE# 4 5 SRN56J-4-GP DDR_B_DQS3 70 168
DDR_B_DQS4 DQS3 VSS
131 DQS4 VSS 171
SRN56J-5-GP DDR_B_DQS5 148 172
DDR_B_DQS6 DQS5 VSS
RN16 169 177
DDR_B_DQS7 DQS6 VSS
1 8 188 DQS7 VSS 178
2 7 DDR_CKE3_DIMMB 183
DDR_B_MA7 M_ODT2 VSS
3 6 8 M_ODT2 114 OTD0 VSS 184
A DDR_B_MA11 DDR_VREF_S3 M_ODT3 A
4 5 8 M_ODT3 119 OTD1 VSS 187
VSS 190
SRN56J-5-GP DDR_VREF_S3 1 193
VREF VSS
2 VSS VSS 196
Wistron Corporation
1

C499 C503 202 201

GND GND 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
RN53
1 4 DDR_CKE2_DIMMB SCD1U16V2ZY-2GP MH1 MH2 Taipei Hsien 221, Taiwan, R.O.C.
2

DDR_B_BS2 SC2D2U16V5ZY-2GP MH1 MH2

2 3
Title
SRN56J-4-GP SKT-SODIMM200-37GP DDRII-SODIMM SLOT2
Size Document Number Rev
Main Source:62.10017.E21 Custom
2nd Source: 62.10017.A51
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 15 of 47
5 4 3 2 1
 A B C D E

HDMI I/F & CONNECTOR 5V_S0

3D3V_S0
DY SB:06/23 Add
R444,R445(63.R0034.1DL)
R444

1
2
1 2
R73 RN19
10KR2J-3-GP 0R2J-2-GP
R288 1 SRN2K2J-1-GP
2 0R0603-PAD R278 1 2 0R0603-PAD
DY DY

2
HDMI_TXD#1 HDMI_TXD#1_C HDMI_TXD#0 HDMI_TXD#0_C
23 HDMI_TXD#1 23 HDMI_TXD#0

4
3
4 4
D31 5V_S0
1 2

4
U16 5V_HDMI_C
L23 L21 CH751H-40PT SB:06/21 Add D31 CH751H for HDMI
ACM2012H-900-GP ACM2012H-900-GP HDMI_SCLK 1 6 HDMI_SCLK_C SM bus clock pull up to 5V_S0.
D11
DY DY 2 5 5V_HDMI_D 1 2
HDMI_SDATA_C 3 4 HDMI_SDATA CH751H-40PT

DY SB:06/21 HDMI1 pin18

2

3
2N7002SPT 5V_S0 R445
connect to 5V_S0
directly. 1 2
HDMI_TXD1 HDMI_TXD1_C HDMI_TXD0 HDMI_TXD0_C SB:06/23 Add
23 HDMI_TXD1 23 HDMI_TXD0
0R2J-2-GP R444,R445(63.R0034.1DL)
HDMI CONN

2
1
R292
1 2
0R0603-PAD R285
1 2
0R0603-PAD RN17
DY
SRN1KJ-7-GP
HDMI1
R295 1 2 0R0603-PAD R276 1 2 0R0603-PAD 18 SB:06/22 Change R66,R67 from
HDMI_TXD#0_C +5V_POWER
9 63.R0034.1DL to ZZ.R0402.ZZZ

3
4
HDMI_TXD#2 HDMI_TXD#2_C HDMI_TX#C HDMI_TX#C_C HDMI_TXD0_C TMDS_DATA0-
23 HDMI_TXD#2 23 HDMI_TX#C 7 TMDS_DATA0+
16 HDMI_SDATA_C 1 2 HDMI_SDATA
SDA HDMI_SDATA 23
HDMI_TXD#1_C 6 R67 0R0402-PAD
HDMI_TXD1_C TMDS_DATA1- HDMI_SCLK_C HDMI_SCLK
4 TMDS_DATA1+ SCL 15 1 2 HDMI_SCLK 23
1

4
R66 0R0402-PAD
L24 L20 HDMI_TXD#2_C 3 13 HDMI_CEC TP91 TPAD28
HDMI_TXD2_C TMDS_DATA2- CEC
ACM2012H-900-GP ACM2012H-900-GP 1 TMDS_DATA2+
3 14 HDMI_CNC TP90 TPAD28 3
DY DY HDMI_TX#C_C 12 TMDS_CLOCK-
RESERVED#14
HDMI_TXC_C 10 19 HDMI_DP_C2 1 2 HDMI_HDP
TMDS_CLOCK+ HOT_PLUG_DETECT HDMI_HDP 23
R63 1KR2J-1-GP
DDC/CEC_GROUNG 17

1
20
2

3
GND R62
8 TMDS_DATA0_SHIELD GND 21
5 22 15K4R2F-GP
HDMI_TXD2 HDMI_TXD2_C HDMI_TXC HDMI_TXC_C TMDS_DATA1_SHIELD GND
23 HDMI_TXD2 23 HDMI_TXC 2 TMDS_DATA2_SHIELD GND 23
11

2
TMDS_CLOCK_SHIELD
1 2 1 2 -1:0909
R299 0R0603-PAD R277 0R0603-PAD SKT-USB-169-GP
62.10027.661

TV OUT CONN (Optional) Move to Right I/O Board

2 2

1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI/TV Connector
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 16 of 47
A B C D E
 A B C D E

CRT I/F & CONNECTOR

4 4
-1:12/14 Change D4 from CH751 to
5V_CRT_S0 5V_S0
CH551 for add current rating.
Layout Note:
Place these resistors
D4 2 1 CH551H-30PT-GP

1
close to the CRT-out L3 1 2 BLM18BB470SN1-GP CRT_R C18
10 M_RED
connector SCD01U16V2KX-3GP
CRT1

2
17 5V_CRT_S0
MH1
10 M_GREEN L2 1 2 BLM18BB470SN1-GP CRT_G 6
11

1
2
1 CRT_R
7 RN3

L1 SRN2K2J-1-GP
10 M_BLUE 1 2 BLM18BB470SN1-GP CRT_B 12
CRT_G 2
1

1
C30 C27 C15 C29 C26 C14 8

4
3
SC8P250V2CC-GP

SC8P250V2CC-GP

SC8P250V2CC-GP

SC8P250V2CC-GP

SC8P250V2CC-GP

SC8P250V2CC-GP
R32 R23 R19 JVGA_HS 13
3 CRT_B

2
150R2F-1-GP

150R2F-1-GP

150R2F-1-GP

9
14 JVGA_VS
2

4
10
15
5
3 MH2 3
16
SB:07/09 ChangeC14,C15,C26,C27,C9,C30 DDC_DATA_CON
from 78.3R374.1FL to 78.8R274.1FL VIDEO-15-84-GP-U
20.20735.015 DDC_CLK_CON

1
C347

1
1
C354 C359 C334

SC33P50V2JN-3GP
SC33P50V2JN-3GP DY

SC22P50V2JN-4GP

SC22P50V2JN-4GP
DY

2
2
5V_S0 SB:0630 Change CRT1 from
20.20334.015 to 20.20735.015.
1

C47
Hsync & Vsync level shift SCD1U16V2ZY-2GP
2

D7 5V_S0
14

2
10 GMCH_HSYNC 5 6 HSYNC_5
CRT_R 3
U9B TSAHCT125PW-GP DY
14

1
7
1

2 2
RN6
1 4 JVGA_HS BAV99PT-GP-U
10 GMCH_VSYNC 2 3 VSYNC_5 2 3 JVGA_VS D5

2
U9A TSAHCT125PW-GP SRN33J-5-GP-U
7

CRT_G 3

DY 1
3D3V_S0 BAV99PT-GP-U
RN2
4 1
3 2 D3

3D3V_S0 2
SRN2K2J-1-GP
CRT_B 3

U3 DY 1

BAV99PT-GP-U
4 3 DDC_DATA_CON
10 GMCH_DDCDATA
5 2
DDC_CLK_CON 6 1 GMCH_DDCCLK 10

1 5V @ ext. CRT side <Core Design> 1

2N7002SPT

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT Connector
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 17 of 47
A B C D E
 A B C D E

SC:08/09 Add LCD2 (20.F1093.040) ,please check LCD1 and

LCD 2 layout overlap possibility.
BACKLITEON LCD_TST

LCD1 SC:08/15 Rename "LCD2" to SC:08/05 Change C57 from VBL19 DCBATOUT

1
49 "LCD1" 78.10423.5FL to DY EC59
DY EC60 F2
VBL19 78.10523.5BL SC33P50V2JN-3GP SC33P50V2JN-3GP
47 51 1 2

2
40

2
39 FUSE-3A32V-7-GP
C56 C58

SCD1U10V2KX-4GP
38
37 +LCDVDD SC1KP50V2KX-1GP SCD1U50V3KX-GP

1
3D3V_S0

SC1U10V3KX-3GP
36

1
EC16
35 LCD_CBL_DET#
LCD_CBL_DET# 34 C57
46 34 5V_AUX_S5

1
33 R246 5V_AUX_S5
4 4

2
32 3D3V_S0
31 -1:08/29 Change LCD1 pin 31 from GND to NC 10KR2J-3-GP
30 BAT_SDA
BAT_SDA 34,38,39
29 BAT_SCL DY
BAT_SCL 34,38,39

2
28 BACKLITEON 2 1 LBKLT_CTL 10
INVERTER POWER

1
45 27 LCD_TST R245 0R2J-2-GP
LCD_TST 34
26 LDDC_CLK -1:09/02 Add R460 to DY EC161
LDDC_CLK 10
25 LDDC_DATA 2 1

SCD1U16V2ZY-2GP
LDDC_DATA 10 prevent power short BRIGHTNESS 34

2
24 LCD_DET_G R460 1 2100R2J-2-GP R247 0R2J-2-GP
VGA_TXBOUT0- to GND via
23 VGA_TXBOUT0- 10
VGA_TXBOUT0+ "LCD_CBL_DET#"
22 VGA_TXBOUT0+ 10 DY
21
44 20 VGA_TXBOUT1- VGA_TXBOUT1- 10
19 VGA_TXBOUT1+ VGA_TXBOUT1+ 10 VGA_TXAOUT0+ VGA_TXACLK+ SC:08/09 Add
18 EC161(78.10491.4FL)
17 VGA_TXBOUT2- VGA_TXAOUT0- VGA_TXACLK-
VGA_TXBOUT2- 10 for EMI request
16 VGA_TXBOUT2+
VGA_TXBOUT2+ 10 .Default is DUMMY
15 EC182 EC185

1
14 VGA_TXBCLK- EC169 EC167

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP
VGA_TXBCLK- 10
43 13 VGA_TXBCLK+ SC:08/13 Add

SC5D6P50V2CN-1GP
VGA_TXBCLK+ 10
12 EC167,EC168(78.10034.1FL),

2
11 VGA_TXAOUT0- VGA_TXAOUT0- 10 DY DY
VGA_TXAOUT0+ R460,R461(63.R0034.1DL) place
10 VGA_TXAOUT0+ 10 DY DY cross LVDS CLK A,Bpair.
9
8 VGA_TXAOUT1- VGA_TXAOUT1- 10 Default is DY.This is for RF
7 VGA_TXAOUT1+ VGA_TXAOUT1+ 10 request.
42 6
5 VGA_TXAOUT2- VGA_TXAOUT2- 10
4 VGA_TXAOUT2+ VGA_TXAOUT2+ 10 VGA_TXAOUT1+ VGA_TXBCLK+
3
2 VGA_TXACLK- VGA_TXAOUT1- VGA_TXBCLK-
VGA_TXACLK- 10
3 1 VGA_TXACLK+ EC183 EC186 3
VGA_TXACLK+ 10

1
41 50 EC170 EC168

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP
48

2
IPEX-CONN40-2R-GP DY DY DY DY
20.F1093.040

SC:08/03 Add D32 ,R456 connect to +LCDVDD 3D3V_S0

-1:08/29 Change U49 pin3 and delete R46 that are for
VGA_TXAOUT2+
LVDS channel A and LCD test function.
VGA_TXAOUT2- channel B EMI
solution. this is
EC184 for antena team U49

1
EC171 D32
Mic Power CAMERA Power

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP
request. 1 1 9
10 LCDVDD_EN IN#1 GND
2 8 -1:0914
2

2
ENVDD OUT IN#8
DY DY 3 3 EN IN#7 7

1
3D3V_S0 V_AUD_DMIC +5V_RUN_CARMERA 5V_S0 4 6
GND IN#6

1
2 C61 5 C417

SCD1U16V2ZY-2GP
34 LCD_TST_EN IN#5

1
1 R189 2 1 R186 2 R456

SC1U10V3ZY-6GP
2
0R0603-PAD 0R0603-PAD BAT54CPT-GP

2
1

100KR2J-1-GP
SC:08/13 Add G5281RC1U-GP
600ohm 100MHz EC154 C341 C342 EC153 SC:08/09 Add EC169,EC170,EC171,
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

EC153(78.10491.4FL) R462,R463,R464 on
2

2
200mA 0.5ohm DC
for EMI request LVDS channel A each
.Default is DUMMY AUD_DMIC_CLK_G_R AUD_DMIC_IN0_R data pairs. This is
DY DY
for RF request
.Default is DY.
1

2 SC:08/09 Add 2
EC154(78.10491.4FL) EC151 EC152
for EMI request DY DY
2

2
SC220P50V2KX-3GP

SC220P50V2KX-3GP

.Default is DUMMY
SC:08/09 Add SC:08/09 Add
EC151(78.22124.2FL) EC152(78.22124.2FL)
for EMI request for EMI request
.Default is DUMMY .Default is DUMMY
LCD POWER

-1:0920
+5V_RUN_CARMERA
-1:09/11
V_AUD_DMIC

CAMERA1
11 1 2
1 R193 0R0603-PAD
USB_PN6 21
2 SC:08/13 Change L12
3 AUD_DMIC_CLK_G_R R195 1 2 33R2J-2-GP pin connection.pin
AUD_DMIC_CLK_G 32
1

4 AUD_DMIC_IN0_R R196 1 2 33R2J-2-GP AUD_DMIC_IN0 32 1 connect to

5
"USB_PN6", pin4
6 CAMERA_USB1-
CAMERA_USB1+
DY connect to
7 DLW21SN900SQ2LUGP
1 8 "USB_PP6" . This 1
9 L12
DMIC_DET# 34 change is for
1

10 <Core Design>
4

EC156 EC155 layout request.

1

SC33P50V2JN-3GP SC33P50V2JN-3GP
MLX-CON9-1-GP-U DY DY
2

EC157
DY SC33P50V2JN-3GP 1 2
USB_PP6 21 Wistron Corporation
2

R188 0R0603-PAD 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

SC:08/09 Add EC157(78.33034.1FL) SC:08/09 Add EC156(78.33034.1FL) SC:08/09 Add EC155(78.33034.1FL) Taipei Hsien 221, Taiwan, R.O.C.
for EMI request .Default is DUMMY for EMI request .Default is DUMMY for EMI request .Default is DUMMY -1:09/11
Title

LCD/Inverter Connector
Size Document Number Rev
Custom
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 18 of 47
A B C D E
 5 4 3 2 1

PCI_AD[0..31] U27C 3 OF 6
25 PCI_AD[0..31]
PCI_AD0 D20 A4
3D3V_S0 PCI_AD1 E19
AD0
AD1
PCI REQ0#
GNT0# D7
PCI_REQ#0 25
PCI_GNT#0 25
PCI_AD2 D19 E18 PCI_REQ1#
PCI_AD3 AD2 REQ1#/GPIO50 PCI_GNT1#
RN37 A20 C18 TP129
PCI_GNT1# PCI_AD4 AD3 GNT1#/GPIO51 PCI_REQ2#
1 8 D17 AD4 REQ2#/GPIO52 B19
D 2 7 PCI_REQ1# PCI_AD5 A21 F18 PCI_GNT2# D
AD5 GNT2#/GPIO53 TP125
3 6 PCI_REQ2# PCI_AD6 A19 C10 PCI_GNT3#
PCI_FRAME# PCI_AD7 AD6 GNT3#/GPIO55 PCI_REQ3#
4 5 C19 AD7 REQ3#/GPIO54 A11
PCI_AD8 A18
PCI_AD9 AD8
SRN8K2J-4-GP B16 C17 PCI_C/BE#0 25
PCI_AD10 AD9 C/BE0#
A12 AD10 C/BE1# E15 PCI_C/BE#1 25
RN39 PCI_AD11 E16 F16
AD11 C/BE2# PCI_C/BE#2 25
1 8 PCI_PIRQG# PCI_AD12 A14 E17 Place closely pin B10
AD12 C/BE3# PCI_C/BE#3 25
2 7 PCI_SERR# PCI_AD13 G16
PCI_PIRQA# PCI_AD14 AD13 PCI_IRDY# CLK_PCI_ICH
3 6 A15 AD14 IRDY# C8 PCI_IRDY# 25
4 5 PCI_PIRQE# PCI_AD15 B6 D9 PCI_PAR
AD15 PAR PCI_PAR 25

2
PCI_AD16 C11 G6 PCI_PCIRST#
PCI_AD17 AD16 PCIRST# PCI_DEVSEL# R425
SRN8K2J-4-GP A9 D16 PCI_DEVSEL# 25
PCI_AD18 AD17 DEVSEL# PCI_PERR#
D11 AD18 PERR# A7 PCI_PERR# 25 10R2J-2-GP
RN41 PCI_AD19 PCI_FRAME#
1 8 PCI_IRDY# PCI_AD20
B12
C12
AD19 FRAME# A17
B7 PCI_PLOCK#
PCI_FRAME# 25 DY

1 1
PCI_GNT#0 PCI_AD21 AD20 PLOCK# PCI_SERR#
2 7 D10 AD21 SERR# F10 PCI_SERR# 25
3 6 PCI_PERR# PCI_AD22 C7 C16 PCI_STOP# C599
AD22 STOP# PCI_STOP# 25
4 5 PCI_PLOCK# PCI_AD23 F13 C9 PCI_TRDY# DY
AD23 TRDY# PCI_TRDY# 25
PCI_AD24 E11 SC8P250V2CC-GP

2
PCI_AD25 AD24 PCI_PLTRST#
SRN8K2J-4-GP E13 AG24
PCI_AD26 AD25 PLTRST# CLK_PCI_ICH
RN42 E12 B10 CLK_PCI_ICH 4
PCI_PIRQB# PCI_AD27 AD26 PCICLK
1 8 D8 AD27 PME# G7 ICH_PME# 25
2 7 PCI_PIRQC# PCI_AD28 A6
PCI_REQ#0 PCI_AD29 AD28
3 6 E8 AD29
4 5 PCI_PIRQH# PCI_AD30 D6 R398 1 2 10KR2J-3-GP
3D3V_S5
PCI_AD31 AD30
A3 AD31
SRN8K2J-4-GP -1:0909
RN40 Interrupt I/F
C 1 8 PCI_GNT3# 25 PCI_PIRQA# PCI_PIRQA# F9 F8 PCI_PIRQE# C
PCI_TRDY# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
2 7 B5 PIRQB# PIRQF#/GPIO3 G11
3 6 PCI_REQ3# 25 PCI_PIRQC# PCI_PIRQC# C5 F12 PCI_PIRQG#
PCI_PIRQD# PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
4 5 A10 PIRQD# PIRQH#/GPIO5 B3

SRN8K2J-4-GP
RN38
PCI_GNT2#
1
2
8
7 PCI_DEVSEL#
SB:71.ICH8M.C0U
3 6 PCI_PIRQF#
4 5 PCI_STOP#
PCI_PCIRST# PCIRST1# 25,27
SRN8K2J-4-GP

1
R415
DY 100KR2J-1-GP

2
A16 swap override Strap Boot BIOS Strap
B B
Low= A16 swap override Enable PCI_GNT0# SPI_CS#1 Boot BIOS Location
PCI_GNT3#
High= Default * 3D3V_S5
0 1 SPI
PCI_GNT3# U33B

14
1 0 PCI
1

PCI_PLTRST# 4
R424 6 PLT_RST1# PLT_RST1# 8,23,24,28,29,30,34
1 1 LPC * 5

1
DY 1KR2J-1-GP R416
100KR2J-1-GP
DY SSLVC08APWR-GP
2

2
R419 2 1 33R2J-2-GP

A <Variant Name> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ICH8(1/4)-PCI/INT
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 19 of 47
5 4 3 2 1
 5 4 3 2 1

-1:1120 R356&R365 tolerance

+RTCVCC
change from 5% to 1% for S3
resume issue.

1 2 LAN100_SLP
R365 330KR2F-L-GP

1 2 SM_INTRUDER#
R364 1MR2J-1-GP

1 2 ICH_INTVRMEN +RTCVCC
R356 330KR2F-L-GP U27A1 OF 6
LPC_LAD[0..3] 34
D D
-1:1120 R356&R365 tolerance ICH_RTCX1 AG25 E5 LPC_LAD0
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_LAD1
change from 5% to 1% for S3 AF24 RTCX2 FWH1/LAD1 F5
G8 LPC_LAD2
resume issue. ICH_RTCRST# FWH2/LAD2 LPC_LAD3
1 2 AF23 RTCRST# FWH3/LAD3 F6
R120 20KR2J-L2-GP 1D05V_S0

RTC
2
SM_INTRUDER# AD22 C4 LPC_LFRAME# LPC_LFRAME# 34
INTRUDER# FWH4/LFRAME#

LPC
G26 R124
C205 GAP-OPEN ICH_INTVRMEN AF25 G9 LPC_DRQ0# H_FERR# 2 1
INTVRMEN LDRQ0# TP123
LAN100_SLP AD21 E6 LPC_DRQ1#
TP127

2
SC1U10V3KX-3GP LAN100_SLP LDRQ1#/GPIO23 56R2J-4-GP

1
B24 GLAN_CLK A20GATE AF13 KA20GATE 34
AG26 H_A20M# H_A20M# 5
A20M# H_DPRSTP#
D22 LAN_RSTSYNC
AF26 H_DPRSTP# TP105
DPRSTP# H_DPRSTP# 6,8,41
-2:0920

LAN/GLAN
C21 LAN_RXD0 DPSLP# AE26
B21 H_DPSLP# H_DPSLP# 6
1D5V_S0 LAN_RXD1 H_FERR#
C22 LAN_RXD2 FERR# AD24 H_FERR# 5
H_DPSLP#
1 2 D21 AG29 H_PWRGOOD TP108
32 ICH_AZ_CODEC_BITCLK LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGOOD 6,46

2
R344 33R2J-2-GP E20
R414 LAN_TXD1 H_IGNNE#
C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# 5
23,31 ICH_ACZ_MDC_BITCLK 1 2 24D9R2F-L-GP within 2" from R184
R343 33R2J-2-GP AH21 AE24 H_INIT# H_INIT# 5
GLAN_DOCK#/GPIO13 INIT#
AC20 H_INTR 5

1
GLAN_COMP INTR KBRCIN# 1D05V_S0
D25 GLAN_COMPI RCIN# AH14 KBRCIN# 34
R348 1 233R2J-2-GP C25

CPU
23,31,32 ICH_AZ_CODEC_SYNC GLAN_COMPO

1
AD23 H_NMI H_NMI 5
HDA_BITCLK_R NMI R123
AJ16 HDA_BIT_CLK SMI# AG28 H_SMI# 5
C
31 ICH_AZ_MDC_RST# R368 1 233R2J-2-GP HDA_SYNC AJ15 56R2J-4-GP C
R367 1 HDA_SYNC
23 ICH_AZ_S1392_RST# 233R2J-2-GP STPCLK# AA24 H_STPCLK# H_STPCLK# 5
32 ICH_AZ_CODEC_RST# R366 1 233R2J-2-GP HDA_RST# AE14

2
HDA_RST# THRMTRIP_ICH#
THRMTRIP# AE27 1 2 H_THERMTRIP# 5,8,34,46
31 ICH_SDIN_MDC AJ17 R122 24R2J-GP
HDA_SDIN0
AH17 AA23

IHDA
23 ICH_SDIN_S1392 HDA_SDIN1 TP8
32 ICH_SDIN_CODEC AH15 HDA_SDIN2 IDE_PDD[0..15] 24 placed within 2" from ICH8M
AD13 V1 IDE_PDD0
HDA_SDIN3 DD0 IDE_PDD1
DD1 U2
23,31,32 ICH_SDOUT_CODEC R363 1 233R2J-2-GP HDA_SDOUT AE13 V3 IDE_PDD2
HDA_SDOUT DD2 IDE_PDD3
G62 T1
DD3 IDE_PDD4
1 2 AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
AG14 T5 IDE_PDD5
GAP-OPEN TP101 HDA_DOCK_RST#/GPIO34 DD5 IDE_PDD6
DD6 AB2
35 SATA_LED# AF10 T6 IDE_PDD7
SATALED# DD7 IDE_PDD8
DD8 T3
24 SATA_RXN0_C AF6 R2 IDE_PDD9
SATA0RXN DD9 IDE_PDD10
24 SATA_RXP0_C AF5 SATA0RXP DD10 T4
24 SATA_TXN0 C520 1 2SC3900P50V2KX-2GP SATA_TXN0_C AH5 V6 IDE_PDD11
C521 1 SATA0TXN DD11
24 SATA_TXP0 2SC3900P50V2KX-2GP SATA_TXP0_C AH6 SATA0TXP DD12 V5 IDE_PDD12
-1:0912 U1 IDE_PDD13
DD13 IDE_PDD14

IDE
AG3 SATA1RXN DD14 V2
AG4 U6 IDE_PDD15
SATA1RXP DD15
AJ4

SATA
SATA1TXN
AJ3 SATA1TXP DA0 AA4 IDE_PDA0 24
DA1 AA1 IDE_PDA1 24
1 2 ICH_RTCX2 AF2 AB3 IDE_PDA2 24
C203 SC12P50V2JN-3GP SATA2RXN DA2
AF1 SATA2RXP
AE4 SATA2TXN DCS1# Y6 IDE_PDCS1# 24
B B
CL=12.5pF AE3 SATA2TXP DCS3# Y5 IDE_PDCS3# 24

4 CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 IDE_PDIOR# 24

2

4 CLK_PCIE_SATA AC6 SATA_CLKP DIOW# W3 IDE_PDIOW# 24

1

R119 Y2 IDE_PDDACK# 24
R111 DDACK#
X-32D768KHZ-40GPU 1 2 AG1 SATARBIAS# IDEIRQ Y3 INT_IRQ14 24
10MR2J-L-GP AG2 Y1 IDE_PDIORDY 24
X1 24D9R2F-L-GP SATARBIAS IORDY
DDREQ W5 IDE_PDDREQ 24
Within 500 mils
3

SB:71.ICH8M.C0U
1 2 ICH_RTCX1
C202 SC15P50V2JN-2-GP -1:0920
3D3V_AUX_S5 RTC1
W=20mils
1 PWR
2 GND
ICH_AZ_CODEC_BITCLK ICH_ACZ_MDC_BITCLK +RTCVCC U60 W=20mils BATT1.1 MH1 MH1
2 MH2 MH2
1 2 RTCVCC_R 3 R438
1

R437 100R2J-2-GP W=20mils BAT-CON2-U3-GP

DY EC36 C636 W=20mils 1 BATT_R 1 2
1
SC22P50V2JN-4GP

SC22P50V2JN-4GP
2

DY C625 CH715FPT-GP 1KR2J-1-GP

SC1U10V3ZY-6GP
2

A <Variant Name> A

Wistron Corporation
Please Place C636 near R454 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ICH8(2/4) LAN,HD,IDE,LPC
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 20 of 47
5 4 3 2 1
 5 4 3 2 1

3D3V_S0 3D3V_S5 Place closely pin G5 Place closely pin AG9

RN69
1 8 PM_CLKRUN# CLK_48M_ICH CLK_14M_ICH

4
3
2 7 SATA0_R3
3 6 SATA0_R2 RN63

1
4 5 INT_SERIRQ SRN2K2J-1-GP
R400 R349
SRN10KJ-6-GP U27D 4 OF 6 10R2J-2-GP 10R2J-2-GP
RN62
DY DY

1
2
1 8 SATA0_R0 SMB_CLK AJ26 AJ12 SATA0_R0

1 2

1 2
SMBCLK SATA0GP/GPIO21

GPIO
2 7 SATA0_R1 SMB_DATA AD19 AJ10 SATA0_R1

SATA
SMBDATA SATA1GP/GPIO19

SMB
3 6 THRM# SMB_LINK_ALERT# AG21 AF11 SATA0_R2 C589 C522
CLKSATAREQ# SMLINK0 LINKALERT# SATA2GP/GPIO36 SATA0_R3 SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
4 5 AC17 SMLINK0 GPIO37 AG11
SMLINK1 AE19 DY DY

2
SRN10KJ-6-GP SMLINK1
SB:06/27 Delete RN74, add CLK14 AG9 CLK_14M_ICH 4
3D3V_S0 ICH_RI#

CLOCKS
R449 for "ECSCI#" pull up to AF17 RI# CLK48 G5 CLK_48M_ICH 4
3D3V_S0 PM_SUS_STAT# ICH_SUSCLK
TP124 F4 SUS_STAT#/LPCPD# SUSCLK D3

4
3
D R449 1 ECSCI# DBRESET# D
2 AD15 SYS_RESET#
10KR2J-3-GP RN70 AG23 PM_SLP_S3# 28,34,36,43,45,46
PM_BMBUSY# SLP_S3#
SRN2K2J-1-GP 8 PM_BMBUSY# AG12 BMBUSY#/GPIO0 SLP_S4# AF21 PM_SLP_S4# 28,34,40,44,45
DY OCP# SLP_S5# AD18
AG22 SMBALERT#/GPIO11
3D3V_S5 AH27 GPIO26

1
2
H_STP_PCI# S4_STATE#/GPIO26
4 H_STP_PCI# AE20 STP_PCI#
4 H_STP_CPU# H_STP_CPU# AG18 AE23 PM_PWROK PM_PWROK 8,36 DY
STP_CPU# PWROK
DY 1 2 R347

SYSGPIO
1 2 RSMRST#_KBC 25,34 PM_CLKRUN# AH11 AJ14 DPRSLPVR DPRSLPVR 8,41 10KR2J-3-GP
R96 10KR2J-3-GP CLKRUN# DPRSLPVR/GPIO16
RN64 AE17 AE21 PM_BATLOW#_R

POWER MGT
27,28 PCIE_WAKE# WAKE# BATLOW#
1 8 GPIO26 25,34 INT_SERIRQ INT_SERIRQ AF12
PM_BATLOW#_R THRM# SERIRQ
2 7 36 THRM# AC13 THRM# PWRBTN# C2 PM_PWRBTN# 34
3 6 OCP#
4 5 SMLINK1 8,41 VGATE_PWRGD 1 2 VRMPWRGD AJ20 AH20 1 2
R342 0R2J-2-GP VRMPWRGD LAN_RST# R112 0R0402-PAD
SRN10KJ-6-GP SST_CTL EC_RMRST#
RN65
DY TP67 AJ22 TP7 RSMRST# AG27

1 8 SMB_LINK_ALERT# GPIO1
AJ8 E1 CK_PWRGD 4
TP72 TACH1/GPIO1 CK_PWRGD
2 7 PCIE_WAKE# GPIO6
AJ9 DY
TP71 TACH2/GPIO6
3 6 ICH_RI# 34 ECSCI# ECSCI#AH9 E3 CL_PWRGD_R R411 1 2 0R2J-2-GP VGATE_PWRGD 8,41
USB_OC#0 ECSMI# TACH3/GPIO7 CLPWROK
4 5 SB:06/27 Change RN68 pin1 AE16

GPIO
34 ECSMI# GPIO8
define from"ECSWI#" to 34 ECSWI# AC19 AJ25 SLP_M# 1 2 PM_PWROK
3D3V_S0 GPIO12 SLP_M# TP66
SRN10KJ-6-GP TP98 GPIO17 AG8 R346 0R2J-2-GP
"GPIO22", pin 8 GPIO18 TACH0/GPIO17 CL_CLK0
RN68 TP69 AH12 F23 CL_CLK0 8
GPIO22 connection from 3D3V_S5 GPIO20 GPIO18 CL_CLK0 CL_CLK1
8 1 TP112 AE11 GPIO20 CL_CLK1 AE18 TP110
7 2 USB_OC#6 to 3D3V_S0. GPIO22 AG10
USB_OC#4 SCLOCK/GPIO22 CL_DATA0
6 3 TP63 AH25 F22 CL_DATA0 8

Controller Link
USB_OC#2 QRT_STATE0/GPIO27 CL_DATA0 CL_DATA1
5 4 TP111 AD16 QRT_STATE1/GPIO28 CL_DATA1 AF19 TP103
4 CLKSATAREQ# CLKSATAREQ# AG13 R422
SRN10KJ-6-GP GPIO38 SATACLKREQ#/GPIO35 CL_VREF0_ICH
TP104 AF9 SLOAD/GPIO38 CL_VREF0 D24 1 2 3D3V_S0
RN66 TP70 GPIO39 AJ11 AH23 CL_VREF1_ICH
SDATAOUT0/GPIO39 CL_VREF1

SCD1U16V2KX-3GP
8 1 SMLINK0 TP109 IDE_RESET# AD10 3K24R2F-GP
USB_OC#5 SDATAOUT1/GPIO48
7 2 CL_RST# AJ23 CL_RST# 8

1
6 3 USB_OC#7 32 SB_SPKR SB_SPKR AD9 SPKR

1
5 4 USB_OC#9 AJ27 GPIO24 C598 R423
CLGPIO0/GPIO24 TP73 453R2F-1-GP
8 MCH_ICH_SYNC# MCH_ICH_SYNC# AJ13 AJ24 GPIO10

MISC
C MCH_SYNC# CLGPIO1/GPIO10 TP64 C
SRN10KJ-6-GP AF22 GPIO14
TP99

2
ICH_RSVD CLGPIO2/GPIO14 GPIO9
RN67 TP68 AJ21 AG19 TP100

2
USB_OC#8 TP3 CLGPIO3/GPIO9
8 1
7 2 DBRESET# Low--> default
6 3 ECSMI# R110
USB_OC#1 High--> No boot
5 4 SB:71.ICH8M.C0U 1 2 3D3V_S5

SCD1U16V2KX-3GP
SRN10KJ-6-GP 3K24R2F-GP

1
C201

1
R369 1 2 USB_OC#3 10KR2J-3-GP R107
10KR2J-3-GP 1 2 SB_SPKR 453R2F-1-GP
3D3V_S0
R361 DY

2
R450 1 2 ECSWI#

2
10KR2J-3-GP SB:06/27 Add R450 for
"ECSWI#" pull up to 3D3V_S5

R341 2 1 DPRSLPVR U27B 2 OF 6

100KR2J-1-GP 3D3V_S0
R102 2 1 GPIO9 27 PCIE_RXN1 P27 V27 DMI_RXN0 DMI_RXN0 8
PERN1 DMI0RXN

2
100KR2J-1-GP 27 PCIE_RXP1 P26 V26 DMI_RXP0 DMI_RXP0 8
PCIE_C_TXN1 PERP1 DMI0RXP DMI_TXN0
LAN 27 PCIE_TXN1 2 1C234 N29 PETN1 DMI0TXN U29 DMI_TXN0 8 R116
27 PCIE_TXP1 SCD1U16V2KX-3GP
2 1C232 PCIE_C_TXP1 N28 U28 DMI_TXP0 DMI_TXP0 8 330R2J-3-GP
SCD1U16V2KX-3GP PETP1 DMI0TXP
DMI_RXN1 R117 1
DY CK_PWRGD
M27 Y27 2

Direct Media Interface

29 PCIE_RXN2 DMI_RXN1 8

1
PERN2

PCI-Express
DMI1RXN DMI_RXP1 0R2J-2-GP
29 PCIE_RXP2 M26 PERP2 DMI1RXP Y26 DMI_RXP1 8
1C238 PCIE_C_TXN2 DMI_TXN1 D R118 1 VRMPWRGD
Mini Card 1 29 PCIE_TXN2 2
SCD1U16V2KX-3GP
2 1C236 PCIE_C_TXP2
L29
L28
PETN2 DMI1TXN W29
W28 DMI_TXP1
DMI_TXN1 8
0R2J-2-GP
2
29 PCIE_TXP2 PETP2 DMI1TXP DMI_TXP1 8

3
SCD1U16V2KX-3GP
30 PCIE_RXN3 K27 AB26 DMI_RXN2 DMI_RXN2 8 Q12
3D3V_S0 PERN3 DMI2RXN DMI_RXP2 2N7002PT-U
30 PCIE_RXP3 K26 PERP3 DMI2RXP AB25 DMI_RXP2 8
1C242 PCIE_C_TXN3 DMI_TXN2
Mini Card 2 30 PCIE_TXN3 2
SCD1U16V2KX-3GP
2 1C240 PCIE_C_TXP3
J29
J28
PETN3 DMI2TXN AA29
AA28 DMI_TXP2
DMI_TXN2 8 41 CLK_EN# 1
30 PCIE_TXP3 PETP3 DMI2TXP DMI_TXP2 8 G
SCD1U16V2KX-3GP

2
30 PCIE_RXN4 H27 AD27 DMI_RXN3 DMI_RXN3 8
PERN4 DMI3RXN
4
3

30 PCIE_RXP4 H26 AD26 DMI_RXP3 DMI_RXP3 8 S

RN61 PCIE_C_TXN4 PERP4 DMI3RXP DMI_TXN3
B Mini Card 3 30 PCIE_TXN4 2 1C247 G29 PETN4 DMI3TXN AC29 DMI_TXN3 8 B
SRN2K2J-1-GP 30 PCIE_TXP4 SCD1U16V2KX-3GP
2 1C244 PCIE_C_TXP4 G28 AC28 DMI_TXP3 DMI_TXP3 8
SCD1U16V2KX-3GP PETP4 DMI3TXP
3D3V_S0 F27 T26 CLK_PCIE_ICH#
28 PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# 4
CLK_PCIE_ICH
New Card 28 PCIE_RXP5 F26 T25 CLK_PCIE_ICH 4
1
2

PCIE_C_TXN5 PERP5 DMI_CLKP

28 PCIE_TXN5 2 1C254 E29 PETN5
28 PCIE_TXP5 SCD1U16V2KX-3GP
2 1C251 PCIE_C_TXP5 E28 Y23 Within 500 mils
SCD1U16V2KX-3GP PETP5 DMI_ZCOMP DMI_IRCOMP 1
U55 DMI_IRCOMP Y24 2 1D5V_S0
D27 R376 24D9R2F-L-GP
PERN6/GLAN_RXN
D26 PERP6/GLAN_RXP USBP0N G3 USB_PN0 38
4,14,15 ICH_SMBDATA 1 6
SMB_DATA 28,29,30
C29
C28
PETN6/GLAN_TXN USBP0P G2
H5
USB_PP0 38 USB1
PETP6/GLAN_TXP USBP1N USB_PN1 38
2 5
C23
USBP1P H4
H2
USB_PP1 38 USB2
SPI_CLK USBP2N USB_PN2 35
28,29,30 SMB_CLK 3 4
ICH_SMBCLK 4,14,15 SD SPI_CS1#
B23
E22
SPI_CS0# USBP2P H1
J3
USB_PP2 35 USB3
TP128 SPI_CS1# USBP3N USB_PN3 35
J2 USB4

SPI
USBP3P USB_PP3 35
2N7002SPT D23 SPI_MOSI USBP4N K5 USB_PN4 30
F21 SPI_MISO USBP4P K4
K2
USB_PP4 30 MINICARD2
USBP5N USB_PN5 31
USB_OC#0
3D3V_S5
38 USB_OC#0
USB_OC#1
AJ19
AG16
OC0# USBP5P K1
L3
USB_PP5 31 BlUETOOTH
38 USB_OC#1 OC1#/GPIO40 USBP6N USB_PN6 18
32K suspend clock output USB_OC#2
3D3V_S0
35 USB_OC#2
USB_OC#3
AG15
AE15
OC2#/GPIO41 USBP6P L2
M5 USB_PN7
USB_PP6 18 CAMERA
35 USB_OC#3
USB_OC#4 AF15
OC3#/GPIO42
OC4#/GPIO43
USB USBP7N
USBP7P M4 USB_PP7
TP118
TP117
1

USB_OC#5 AG17 M2
OC5#/GPIO29 USBP8N USB_PN8 28
3D3V_S5 R351 USB_OC#6 AD12 OC6#/GPIO30 USBP8P M1 USB_PP8 28 New Card
1

2K2R2J-2-GP USB_OC#7 AJ18 N3

OC7#/GPIO31 USBP9N USB_PN9 30
DY R91 USB_OC#8
10KR2J-3-GP R327
USB_OC#9
AD14
AH18
OC8# USBP9P N2 USB_PP9 30 MINICARD3
2

U20A OC9# USBRBIAS 1

14

1 2 USBRBIAS# F2 2
F3 R403 20R2F-GP SB:0710 Change R403 from
2

0R2J-2-GP USBRBIAS
1
3 ICH_32KHZ 1 2 D28 22.6 Ohm to 22 Ohm
G792_CLK 36
ICH_SUSCLK 2 R93 10R2J-2-GP EC_RMRST# 1 DY Within 500 mils
TSLVC08APW-1-GP 3
SB:71.ICH8M.C0U
RSMRST#_KBC 34
7

DY
A 2 A
2

BAS16-1-GP
Q35 R350
2N7002PT-U 100KR2J-1-GP
<Core Design>
3 2 SB:06/20 Add 2N7002 Q35 for G792
S

1
D

"G792_CLK"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

Taipei Hsien 221, Taiwan, R.O.C.

G

RUN_POWER_ON Title

ICH8(3/4) PM,USB,GPIO
Size Document Number Rev
Custom
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 21 of 47
5 4 3 2 1
 5 4 3 2 1

+RTCVCC 1D05V_S0 U27F 6 OF 6

20 mils U27E 5 OF 6
AD25 VCCRTC A23 VSS VSS K7
VCC1_05 A13 A5 VSS VSS L1
C530 C532 ICH_V5REF_RUN T7 B13 C580 C576 C573 C551 AA2 L13
V5REF VCC1_05 VSS VSS

1
A16 C13 C196 C195 C272 C273 AA7 L15
V5REF VCC1_05 VSS VSS

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U10V3ZY-6GP

SC1U10V3ZY-6GP
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
VCC1_05 C14 A25 VSS VSS L26
ICH_V5REF_SUS G4 D14 AB1 L27

2
V5REF_SUS VCC1_05 VSS VSS
2 1D5V_S0 E14 AB24 L4

2
VCC1_05 VSS VSS
AA25 VCC1_5_B VCC1_05 F14 AC11 VSS VSS L5
AA26 VCC1_5_B VCC1_05 G14 AC14 VSS VSS M12
AA27 L11 AC25 M13

CORE
VCC1_5_B VCC1_05 VSS VSS

1
C260 C215 C262 C213 AB27 L12 AC26 M14
VCC1_5_B VCC1_05 VSS VSS

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U10V3ZY-6GP

SC1U10V3ZY-6GP
AB28 VCC1_5_B VCC1_05 L14 AC27 VSS VSS M15
D AB29 L16 AD17 M16 D

2
5V_S0 3D3V_S0 VCC1_5_B VCC1_05 VSS VSS
D28 VCC1_5_B VCC1_05 L17 AD20 VSS VSS M17
D29 L18 L5 AD28 M23
VCC1_5_B VCC1_05 1D5V_DMIPLL_S0 VSS VSS
E25 VCC1_5_B VCC1_05 M11 1 2 1D5V_S0 AD29 VSS VSS M28
1

BAS16-1-GP E26 M18 IND-1UH-36-GP AD3 M29

VCC1_5_B VCC1_05 VSS VSS
1

D18 E27 P11 AD4 M3

VCC1_5_B VCC1_05 VSS VSS

1
R387 F24 P18 C228 AD6 N1
VCC1_5_B VCC1_05 C226 SC10U6D3V5KX-1GP VSS VSS
F25 VCC1_5_B VCC1_05 T11 AE1 VSS VSS N11
100R2J-2-GP 20 mils G24 T18 SCD01U16V2KX-3GP AE12 N12

2
VCC1_5_B VCC1_05 VSS VSS
H23 U11 AE2 N13
2

ICH_V5REF_RUN VCC1_5_B VCC1_05 VSS VSS

H24 VCC1_5_B VCC1_05 U18 AE22 VSS VSS N14

VCCA3GP
J23 VCC1_5_B VCC1_05 V11 AD1 VSS VSS N15
1

C555 J24 V12 AE25 N16

SCD1U16V2ZY-2GP VCC1_5_B VCC1_05 VSS VSS
K24 VCC1_5_B VCC1_05 V14 1D25V_S0 AE5 VSS VSS N17
C217 C220 C197 C221 K25 V16 AE6 N18
2

VCC1_5_B VCC1_05 VSS VSS

SC10U6D3V5KX-1GP
L23 VCC1_5_B VCC1_05 V17 AE9 VSS VSS N26
1

1
C208
SC2D2U10V3ZY-1GP

SC2D2U10V3ZY-1GP

SC2D2U10V3ZY-1GP

SC2D2U10V3ZY-1GP
L24 VCC1_5_B VCC1_05 V18 AF14 VSS VSS N27
L25 VCC1_5_B AF16 VSS VSS N4
M24 R29 AF18 N5
2

2
VCC1_5_B VCCDMIPLL VSS VSS
M25 VCC1_5_B AF3 VSS VSS N6
5V_S5 3D3V_S5 N23 AE28 1D05V_S0 AF4 P12
VCC1_5_B VCC_DMI VSS VSS
N24 VCC1_5_B VCC_DMI AE29 AG5 VSS VSS P13
N25 VCC1_5_B AG6 VSS VSS P14
1

BAS16-1-GP P24 AC23 AH10 P15

VCC1_5_B V_CPU_IO VSS VSS
1

P25 VCC1_5_B V_CPU_IO AC24 AH13 VSS VSS P16

R147 D20 R24 AH16 P17
VCC1_5_B VSS VSS

1
R25 AF29 SCD1U16V2ZY-2GP 3D3V_S0 C579 C554 AH19 P23
100R2J-2-GP VCC1_5_B VCC3_3 VSS VSS
20 mils

SCD1U16V2ZY-2GP
R26 VCC1_5_B AH2 VSS VSS P28
R27 AD2 SCD1U16V2ZY-2GP 3D3V_S0 (DMI) AF28 P29
2

2
VCC1_5_B VCC3_3 VSS VSS

1
ICH_V5REF_SUS T23 C595 SCD1U16V2ZY-2GP AH22 R11
C VCC1_5_B VSS VSS C
T24 AC8 (SATA) AH24 R12

VCCP CORE
VCC1_5_B VCC3_3 3D3V_S0 VSS VSS
1

1
C588 T27 AD8 C600 AH26 R13

2
SCD1U16V2ZY-2GP VCC1_5_B VCC3_3 VSS VSS
T28 VCC1_5_B VCC3_3 AE8 AH3 VSS VSS R14
T29 AF8 3D3V_S0 AH4 R15
2

2
VCC1_5_B VCC3_3 VSS VSS
U24 VCC1_5_B AH8 VSS VSS R16
U25 VCC1_5_B VCC3_3 AA3 AJ5 VSS VSS R17
V23 VCC1_5_B VCC3_3 U7 B11 VSS VSS R18

1
V24 V7 C546 B14 R28
VCC1_5_B VCC3_3 SCD1U16V2ZY-2GP VSS VSS
V25 VCC1_5_B VCC3_3 W1 B17 VSS VSS R4
W25 W6 B2 T12

IDE

2
VCC1_5_B VCC3_3 3D3V_S0 VSS VSS
Y25 VCC1_5_B VCC3_3 W7 B20 VSS VSS T13
VCC3_3 Y7 B22 VSS VSS T14
1D5V_S0 AJ6 SCD1U16V2ZY-2GP B8 T15
VCCSATAPLL VSS VSS
VCC3_3 A8 C24 VSS VSS T16
1D5V_S0 AE7 VCC1_5_A VCC3_3 B15 C26 VSS VSS T17
1

1
C198 C200 AF7 B18 C536 C27 T2
VCC1_5_A VCC3_3 VSS VSS
SC10U6D3V5KX-1GP

AG7 B4 C541 C596 SCD1U16V2ZY-2GP C6 U12

VCC1_5_A VCC3_3 VSS VSS
1

C233
ARX
SC1U10V3ZY-6GP

AH7 B9 D12 U13

PCI
2

2
VCC1_5_A VCC3_3 VSS VSS
AJ7 VCC1_5_A VCC3_3 C15 D15 VSS VSS U14
D13 D18 U15
2

SC1U10V3ZY-6GP VCC3_3 SCD1U16V2ZY-2GP VSS VSS

AC1 VCC1_5_A VCC3_3 D5 D2 VSS VSS U16
AC2 VCC1_5_A VCC3_3 E10 D4 VSS VSS U17
ATX

AC3 VCC1_5_A VCC3_3 E7 E21 VSS VSS U23

AC4 VCC1_5_A VCC3_3 F11 E24 VSS VSS U26
AC5 VCC1_5_A E4 VSS VSS U27
AC12 SCD1U16V2ZY-2GP 3D3V_S0 E9 U3
VCCHDA VSS VSS
1D5V_S0 AC10 VCC1_5_A F15 VSS VSS U5
AC9 AD11 SCD1U16V2ZY-2GP 3D3V_S5 E23 V13
VCC1_5_A VCCSUSHDA VSS VSS

1
F28 VSS VSS V15
1

C199 AA5 J6 C583 F29 V28

VCC1_5_A VCCSUS1_05 TP120 VSS VSS

1
B AA6 AF20 F7 V29 B
TP102

2
SC1U10V3ZY-6GP VCC1_5_A VCCSUS1_05 C571 VSS VSS
G1 W2
2

VCCSUS1_5_ICH_1 VSS VSS

G12 AC16 TP113 E2 W26

2
VCC1_5_A VCCSUS1_5 VSS VSS
G17 VCC1_5_A G10 VSS VSS W27
H7 J7 VCCSUS1_5_ICH_2 3D3V_S5 G13 Y28
VCC1_5_A VCCSUS1_5 TP119 VSS VSS
G19 VSS VSS Y29
AC7 C3 SCD1U16V2ZY-2GP G23 Y4
VCC1_5_A VCCSUS3_3 VSS VSS
AD7 VCC1_5_A G25 VSS VSS AB4
VCCSUS3_3 AC18 G26 VSS VSS AB23

1
1D5V_S0 D1 AG20 C567 C558 G27 AB5
VCCUSBPLL VCCSUS3_3 VSS VSS
VCCPSUS

1D5V_S0 AC21 SCD1U16V2ZY-2GP H25 AB6

VCCSUS3_3 VSS VSS
F1 AC22 H28 AD5

2
VCC1_5_A VCCSUS3_3 VSS VSS
1

USB CORE

L6 VCC1_5_A VCCSUS3_3 AH28 H29 VSS VSS U4

C547 C574 L7 H3 W24
VCC1_5_A 3D3V_S5 VSS VSS
M6 P6 H6
2

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP VCC1_5_A VCCSUS3_3 VSS ICHGND1 TP78

M7 VCC1_5_A VCCSUS3_3 P7 J1 VSS VSS_NCTF A1
VCCSUS3_3 N7 J25 VSS VSS_NCTF A2
1D5V_S0 W23 VCC1_5_A VCCSUS3_3 C1 J26 VSS VSS_NCTF A28
1

P1 C224 J27 A29 ICHGND2 TP77

TP126 VCC_LAN1_05_INT_ICH_1 VCCSUS3_3 VSS VSS_NCTF
F17 VCCLAN1_05 VCCSUS3_3 R1 J4 VSS VSS_NCTF AJ28
3D3V_S0
SC4D7U6D3V3KX-GP

TP121 VCC_LAN1_05_INT_ICH_2 G18 P2 J5 AH1

2

VCCLAN1_05 VCCSUS3_3 VSS VSS_NCTF

VCCPUSB

VCCSUS3_3 P3 K23 VSS VSS_NCTF AH29

F19 VCCLAN3_3 VCCSUS3_3 R3 K28 VSS VSS_NCTF AJ1 ICHGND3 TP65
G20 VCCLAN3_3 VCCSUS3_3 P4 K29 VSS VSS_NCTF AJ2
1

VCCSUS3_3 P5 K3 VSS VSS_NCTF AJ29 ICHGND4 TP74

C584 1D5V_S0 A24 R5 K6 B1
VCCGLANPLL VCCSUS3_3 VSS VSS_NCTF
R6 B29
2

SCD1U16V2ZY-2GP VCCSUS3_3 VSS_NCTF

1D5V_S0 A26 VCCGLAN1_5
1

C235 C212 A27 G22 VCCCL1_05_ICH

GLAN POWER

VCCGLAN1_5 VCCCL1_05 TP122

1
SC10U6D3V5KX-1GP

C216 B26
A SC10U6D3V5KX-1GP VCCGLAN1_5 VCCCL1_5_ICH A
SC1U10V3ZY-6GP

B27 A22 TP79 <Variant Name>

2

VCCGLAN1_5 VCCCL1_5
B28
2

VCCGLAN1_5 R399 1 3D3V_S0

VCCCL3_3 F20 2
B25 G21 0R0603-PAD
3D3V_S0 VCCGLAN3_3 VCCCL3_3 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SB:71.ICH8M.C0U Title

ICH8(4/4) POWER&GND
Size Document Number Rev
Custom
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 22 of 47
5 4 3 2 1
 5 4 3 2 1

SB:06/22 Change R279,R280,R281,R282 from 63.30134.1DL

to 63.12134.1DL

16 HDMI_TXD#1 HDMI_TXD#1 HDMI_TXD0

HDMI_TXD0 16
1 2 HDMI_TXD#1_1 1 2 1 2 HDMI_TXD#0_0 1 2
R281 120R2J-2-GP C455 SCD1U10V2KX-4GP R280 120R2J-2-GP C454 SCD1U10V2KX-4GP
16 HDMI_TXD1 HDMI_TXD1 HDMI_TXD#0
HDMI_TXD#0 16

D 16 HDMI_TXD#2 HDMI_TXD#2 HDMI_TXC D

HDMI_TXC 16
1 2 HDMI_TXD#2_2 1 2 1 2 HDMI_TX#C_C1 1 2
R282 120R2J-2-GP C456 SCD1U10V2KX-4GP R279 120R2J-2-GP C453 SCD1U10V2KX-4GP
16 HDMI_TXD2 HDMI_TXD2 HDMI_TX#C
HDMI_TX#C 16

HDMI_HDP 16
EXT_SWING1 1 2 AVCC
R291 560R2F-GP

U52 SB:06/22 Change R291 from 64.75005.6DL to

29
28

26
25

23
22

20
19

42
16
64.56005.6DL

SC100P50V2JN-3GP
TX2+

TX1+

TX0+
TX2-

TX1-

TX0-

TXC+

HTPLG
EXT_SWING
TXC-

SC1KP50V2KX-1GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
550mA R309
2 VCC_PWR 2 1 1D8V_S0
VCC 0R0603-PAD
VCC 43

C471

C472

C485

C466
VCC 9

1
C482 1 2SCD1U10V2KX-4GP S_INT+ 46 48 C481
10 SDVOB_INT+ SDI+ VCC
C487 1 2SCD1U10V2KX-4GP S_INT- 47 38 SC10U6D3V5KX-1GP
10 SDVOB_INT- SDI- VCC
LAYOUT must support

2
10 SDVOB_R+
SDVOB_R+ 51 SDR+ GND 5 connectors from JAE,

SC1KP50V2KX-1GP

SCD1U10V2KX-4GP
10 SDVOB_R-
SDVOB_R- 52 SDR- GND 10
R77 Molex, and Acon
C SDVOB_G+ 54 21 AVCC 2 1 1D8V_S0
C
10 SDVOB_G+ SDG+ AVCC

C151

C150
SDVOB_G- 55 27 0R0603-PAD
10 SDVOB_G- SDG- AVCC

1
C154

SCD1U10V2KX-4GP
SDVOB_B+ 57 18
10 SDVOB_B+ SDB+ AGND

SC1KP50V2KX-1GP SC1KP50V2KX-1GP
SDVOB_B- 58 24 DY 30mA R287
10 SDVOB_B-

2
SDB- AGND AVCC33V
AGND 30 2 1 3D3V_S0

C452

C451
65 SC10U6D3V5KX-1GP 0R0603-PAD
GND

1
SDVOB_C+ 60 R313 C457
10 SDVOB_C+ SDC+

SC1U6D3V2KX-GP
SDVOB_C- 61 64 OVCC 2 1 3D3V_S0 SC10U6D3V5KX-1GP
10 SDVOB_C- SDC- OVCC 0R0603-PAD DY

2
1

1
C489
1 2 EXT_RES 49 EXT_RES
C488
R312 1KR2J-1-GP 17 PVCC1
PVCC1
DY

2
1 31 PVCC2
8,19,24,28,29,30,34 PLT_RST1# RESET# PVCC2
7 32 AVCC33V SC10U6D3V5KX-1GP
8 SDVO_CTRLCLK SDSCL AVCC3.3

SC1U6D3V2KX-GP
6 33 VCC_PWR PVCC1 2 R283 1 1D8V_S0
8 SDVO_CTRLDATA SDSDA VCC

C459
0R0603-PAD

1
SC1KP50V2KX-1GP

C462
SCD1U10V2KX-4GP
1 2 A1 8
R81 1KR2J-1-GP A1 R311
HDMI_SDATA 12 50 SVCC 2 1 1D8V_S0
16 HDMI_SDATA

2
SDADDC SVCC

C496

C495
HDMI_SCLK 11 56 0R0603-PAD
16 HDMI_SCLK SCLDDC SVCC

1
C491

SC10U6D3V5KX-1GP
41

2
GND
14 45
SPDIF/HDASDO

SCLROM GND
LSDA/PREEMP

13 53 R72
SDAROM SGND

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
SC10U10V5KX-2GP

SC1U6D3V2KX-GP
59 R314 PVCC2 2 1
LSCL/DCEN

SGND 1D8V_S0
HDASYNC

SPVCC 0R0603-PAD
HDABCLK

HDARST#

62 2 1 3D3V_S0
HDAVCC

SPVCC

1
HDASDI

C494

C497

C149

C152
0R0603-PAD
1

1
B B
LINT#

SB: 0710 Change R345 from 33 Ohm to 0 44 TEST SPGND 63

Ohm

2
2

2
SII1392CNU-GP-U
39
37

35
36

40

34
4
3
15

1 2 ICH_AZ_S1392_BITCLK
20,31 ICH_ACZ_MDC_BITCLK R345 0R2J-2-GP
1

R80 2 1 3D3V_S0
R306 4K7R2J-2-GP 2D5V_S0
DY 4K7R2J-2-GP
3D3V_S0 DY 2 1 AUD_SPDIF_OUT AUD_SPDIF_OUT 32
2

4
3
R294 22R2J-2-GP
ICH_AZ_S1392_SDOUT RN57
ICH_SDOUT_CODEC 20,31,32
1

R303
R304 2 1
DY ICH_AZ_S1392_SYNC
SRN4K7J-8-GP
ICH_AZ_CODEC_SYNC 20,31,32
0R0603-PAD
4K7R2J-2-GP

1
2
ICH_AZ_S1392_SDIN2_C 2 1 SDVO_CTRLCLK
2

R75 R297 33R2J-2-GP ICH_SDIN_S1392 20 SDVO_CTRLDATA

HDAVCC 2 1
DY ICH_AZ_S1392_RST#
ICH_AZ_S1392_RST# 20
1

4K7R2J-2-GP
C161
SCD1U10V2KX-4GP
2

A -1:09/06 Change EC83 from ASM to DUMMY. <Core Design> A

ICH_AZ_S1392_BITCLK

Wistron Corporation
1

EC83
DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SC22P50V2JN-4GP Taipei Hsien 221, Taiwan, R.O.C.
2

Title
SiI 1392 HDMI
Size Document Number Rev
A3 -3
DS2-Intel
Date: Wednesday, January 23, 2008 Sheet 23 of 47
5 4 3 2 1
 5 4 3 2 1

SATA HD Connector CD-ROM Connector

IDE_PDD[0..15] 20
HDD1
D 23 D
NP1 CDROM1
1 52 3D3V_S0
49 50
20 SATA_TXP0 2 47 48
20 SATA_TXN0 SC3900P50V2KX-2GP 3 IDE_PDD8 45 46 RSTDRV#_5
4 IDE_PDD9 43 44 IDE_PDD7
20 SATA_RXN0_C C564 1 2 SATA_RXN0 5 IDE_PDD10 41 42 IDE_PDD6
20 SATA_RXP0_C C568 1 2 SATA_RXP0 6 IDE_PDD11 39 40 IDE_PDD5

4
3
7 IDE_PDD12 37 38 IDE_PDD4
SC3900P50V2KX-2GP IDE_PDD13 35 36 IDE_PDD3 RN23
IDE_PDD14 33 34 IDE_PDD2 SRN8K2J-3-GP
3D3V_S0 8 IDE_PDD15 31 32 IDE_PDD1
9 20 IDE_PDDREQ 29 30 IDE_PDD0
1

1
C258 C253 10 20 IDE_PDIOR# 27 28

1
2
SC10U6D3V5KX-1GP SCD1U16V2ZY-2GP 11 25 26 IDE_PDIOW# 20
DY DY 12 20 IDE_PDDACK# 23 24 IDE_PDIORDY 20
2

2 13 -1:09/02 Change ODD power 21 22 INT_IRQ14 20

14 net from "5V-S0" to 19 20 IDE_PDA1 IDE_PDA1 20
15 IDE_PDA2 17 18 IDE_PDA0 IDE_PDA0 20
"ODD_5V_S0" for Sniffer 20 IDE_PDA2
HDD_5V_S0 16 20 IDE_PDCS3# 15 16 IDE_PDCS1# 20
17 function circuit. 13 14
1

C264 C268 18 11 12
-1:09/02 Change HDD power SC10U10V5ZY-1GP SCD1U16V2ZY-2GP 19 9 10
ODD_5V_S0 ODD_5V_S0
net from "5V-S0" to 20 7 8
2

1
"ODD_5V_S0" for Sniffer 21 5 6
22 C186 C191 3 4 CSEL -1:09/02 Change ODD power
function circuit. NP2 SC10U10V5ZY-1GP 1 2 net from "5V-S0" to

2
24 SCD1U16V2ZY-2GP 51 GND : Master
C "ODD_5V_S0" for Sniffer C
SYN-CON22-GP-U Open: Slave function circuit.
FOX-CONN50-4R-4GP

5V_S0
Main Source:20.80919.022

3D3V_S0
Close to Connector

14

10
8,19,23,28,29,30,34 PLT_RST1# 9 8 IDE_RST_MOD#1 2 RSTDRV#_5
R100 56R2J-4-GP 1 2 IDE_PDIOW#
R97 4K7R2J-2-GP
U9C TSAHCT125PW-GP

7
5V_S0 ODD_5V_S0

5V_S5
R470 1
DY
2 0R3-0-U-GP
DY

1
R468 1 2 0R3-0-U-GP
R466 DY
100KR2J-1-GP R469 1 2 0R3-0-U-GP
U68 DY
R471 1 2 0R3-0-U-GP

2
B 5V_S0 HDD_5V_S0 B
ODD_5V_EN_R 6 1
5V_S5 5 2 HDD_5V_EN 34

DY 4 3
1

R463 1 2 0R3-0-U-GP
R461 RUN_POWER_ON 5V_S0 ODD_5V_S0
100KR2J-1-GP R464 1 2 0R3-0-U-GP
U67 2N7002SPT
DY
2

1
-1:09/02 Add HDD 5V power control
HDD_5V_EN_R 6 1 circuit for Sniffer function, R467
100KR2J-1-GP
default is DY U35
5 2 HDD_5V_EN 34
8 1

2
D S
4 3 -1:09/02 Add ODD 5V power control 7 D S 2
circuit for Sniffer function, 6 3
RUN_POWER_ON 5V_S0 HDD_5V_S0 5
D S
4
default is DY D G
2N7002SPT SI4800BDY-T1
ODD_PWR_EN
1

R462 Q38 -1:0910

100KR2J-1-GP
-1:0906 Add C639 for

1
1 6 "ODD_5V_EN#".
2

C639
-1:1114 The C639 change

SCD1U25V3KX-GP
A <Core Design> A

2
2 5 from NO-ASM to 0.1uF/25V
for Sniffer issue.
HDD_PWR_EN 3 4 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
FDC655BN-GP
-1:0910 Title

HD/CDROM/USB
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 24 of 47
5 4 3 2 1
 5 4 3 2 1

3D3V_S0

U37B 3D3V_S0

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
1

1
D C325 DY C288 C281 C279 C312 C326 10 67 D
SC10U6D3V5KX-1GP VCC_PCI1 VCC_3V
20 VCC_PCI2
27

2
VCC_PCI3

SCD01U16V2KX-3GP
32 VCC_PCI4

1
41 C283 C290
3D3V_S0 VCC_PCI5 SC10U6D3V5KX-1GP
128 VCC_PCI6

2
61 VCC_RIN
16 VCC_ROUT1
VCC_ROUT 34 VCC_ROUT2
1

64 VCC_ROUT3

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
C282 114

SCD47U16V3ZY-3GP
VCC_ROUT4

1
C297 C319 C278 C280 120
2

SCD1U16V2ZY-2GP VCC_ROUT5
86

2
VCC_MD
SCD47U16V3ZY-3GP
GND1 4
GND2 13
PCI_AD31 125 22
PCI_AD30 AD31 GND3
126 AD30 GND4 28
PCI_AD29 127 54
PCI_AD28 AD29 GND5
1 AD28 GND6 62
PCI_AD27 2 63
19 PCI_AD[0..31] AD27 GND7
PCI_AD26 3 68
PCI_AD25 AD26 GND8
5 AD25 GND9 118
PCI_AD24 6 122
PCI_AD23 AD24 GND10
9 AD23
C PCI_AD22 11 C
PCI_AD21 AD22
12 AD21 AGND1 99
PCI_AD20 14 102
PCI_AD19 AD20 AGND2
15 AD19 AGND3 103
PCI_AD18 17 107 3D3V_S0
PCI_AD17 AD18 AGND4
18 AD17 AGND5 111
PCI_AD16 19 AD16

1
PCI_AD15 36
PCI_AD14 AD15 R177
37 AD14
PCI_AD13 38 4K7R2J-2-GP
PCI_AD12 AD13
39 AD12
PCI_AD11 40 3D3V_S0

2
AD11

PCI / OTHER
PCI_AD10 42 69
PCI_AD9 AD10 HWSPND#
43 AD9
PCI_AD8 44 RN43
PCI_AD7 AD8
46 AD7 1 8
PCI_AD6 47 58 2 7 DY
AD6 MSEN

1
PCI_AD5 48 3 6
PCI_AD4 AD5 EC44
49 AD4 XDEN 55 4 5
PCI_AD3 50 SCD1U16V2ZY-2GP

2
PCI_AD2 AD3
51 SRN10KJ-6-GP
PCI_AD1 AD2
52 AD1 UDIO5 57 1 2 3D3V_S0
PCI_AD0 53 R164 100KR2J-1-GP
AD0
19 PCI_PAR 33 PAR
19 PCI_C/BE#3 PCI_C/BE#3 7 65
PCI_C/BE#2 C/BE3# UDIO3
19 PCI_C/BE#2 21 C/BE2# UDIO4 59
19 PCI_C/BE#1 PCI_C/BE#1 35
PCI_C/BE#0 C/BE1#
19 PCI_C/BE#0 45 C/BE0# UDIO2 56
3D3V_S0 PCI_AD25 1 2 R5C834_IDSEL 8
B R150 10R2J-2-GP IDSEL B
UDIO1 60
19 PCI_REQ#0 124 REQ#
1

19 PCI_GNT#0 123 GNT# UDIO0/SRIRQ# 72 INT_SERIRQ 21,34

R180 19 PCI_FRAME# 23
10KR2J-3-GP FRAME#
19 PCI_IRDY# 24 IRDY#
R179 19 PCI_TRDY# 25 TRDY#
19 PCI_DEVSEL# 26
1 2

DEVSEL#
34 GBRST#_KBC 1 2 19 PCI_STOP# 29 STOP# INTA# 115 PCI_PIRQA# 19
0R2J-2-GP 19 PCI_PERR# 30
C331 PERR#
DY SCD1U16V2ZY-2GP
19 PCI_SERR# 31 SERR# INTB# 116 PCI_PIRQC# 19
2

GBRST# 71 GBRST#
19,27 PCIRST1# 119 PCIRST# 1394 : INTA#
4 PCLK_PCM 121 PCICLK 4in1 : INTB#
DY
SHIELD 19 ICH_PME# 2 1 70 PME# TEST 66
GND R178 0R2J-2-GP
21,34 PM_CLKRUN# 117 CLKRUN#
2

R151 R173
DY 10KR2J-3-GP 100KR2J-1-GP
R5C833-GP
1

1
1

A <Core Design> A
DY C293
SC10P50V2JN-4GP
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

R5C833/PCI
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 25 of 47
5 4 3 2 1
 5 4 3 2 1

3D3V_PHY
3D3V_S0
U37A 2 R174 1 Reserve R547,R548,R550,R551 for co-layout
3D3V_PHY 0R0603-PAD

1
C323 C308 C303 -1:09/11
98 SC10U6D3V5KX-1GP SCD01U16V2KX-3GP 1 2
AVCC_PHY1 R318 0R0402-PAD
106

2
AVCC_PHY2
AVCC_PHY3 110
112 SCD1U16V2ZY-2GP L27
AVCC_PHY4
GUARD GND
TPA0+ 2 1
C329 SC12P50V2JN-3GP SKT-1394-4P-30-GP C190 CLOSE TO CHIP
DY

1
D 1 2 1394_XI 113 TPBIAS0 R90 R89 D
TPBIAS0 TPA0- C189
SB:06/13 Change X4 from GND 6 3 4
82.30023.561 to 82.30023.611 5 DLW21HN900SQ2LGP

2
GND SCD01U16V2KX-3GP
TPA0+ 4
1

94 3 1 2 TPBIAS0

2
X4 XI TPA0- TPB0+ R316 0R0402-PAD SCD33U10V3KX-3GP TPA0P
TPB0+ 2
X-24D576MHZ-70GP 1 TPA0N
TPB0- TPB0P
-1:09/11
2

104 TPB0N 1 2 TPB0N

C330 TPBN0 CN8 R321 0R0402-PAD R95
1 2 1394_XO 95 105 TPB0P 1 2 1 2
XO TPBP0
SC12P50V2JN-3GP 3L28 4 R92 5K1R2F-2-GP
56R2J-4-GP 1394_TPB1_R
DY 1 2 1 2 C192
-1:0920 TPB0- 2 1 R94

IEEE1394/SD
108 TPA0N DLW21HN900SQ2LGP 56R2J-4-GP SC270P50V2JN-2GP
TPAN0
1 2 RICHO_FILO 96 109 TPA0P 1 2
C324 SCD01U16V2KX-3GP FIL0 TPAP0 R319 0R0402-PAD

SC:08/20 Change R95 from

1 2RICHO_REXT 101 REXT
-1:09/11 64.51115.6DL to 64.51015.6DL.
R170 10KR2F-2-GP 3D3V_CARD

RN44
1 2 RICHO_VREF 100 XD_DATA4 8 1 XD_DATA4_1
C315 SCD01U16V2KX-3GP VREF XD_DATA5 XD_DATA5_1 DY DY
7 2

1
XD_DATA6 6 3 XD_DATA6_1 C597 C261 C271 C269
XD_DATA7 5 4 XD_DATA7_1 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC2D2U10V3ZY-1GP
C GUARD GND C

2
SRN47J-5-GP

87 XD_DATA7 RN45
MDIO17 SD/XD/MS_DATA08 1SD/XD/MS_DATA0_1
92 XD_DATA6 SD/XD/MS_DATA17 2SD/XD/MS_DATA1_1
MDIO16 SD/XD/MS_DATA26 3SD/XD/MS_DATA2_1
89 XD_DATA5 SD/XD/MS_DATA35 4SD/XD/MS_DATA3_1 -1:0920
MDIO15
91 XD_DATA4 SRN47J-5-GP
MDIO14
90 SD/XD/MS_DATA3
MDIO13 RN71 3D3V_CARD
93 SD/XD/MS_DATA2 XD_ALE 2 3 XD_ALE_1 CARD1
MDIO12 SD/XD/MS_CMD 1 SD/XD/MS_CMD_1
4
81 SD/XD/MS_DATA1 23 25 SD/XD/MS_DATA0_1
MDIO11 SD_VCC SD_DAT0 SD/XD/MS_DATA1_1
SRN33J-5-GP-U 14 MS_VCC SD_DAT1 29
82 SD/XD/MS_DATA0 33 10 SD/XD/MS_DATA2_1
MDIO10 XD_VCC SD_DAT2 SD/XD/MS_DATA3_1
RN72 SD_DAT3 11

75 XD_WP# XD_CE# 2 3 XD_CE#_1 SD/XD/MS_DATA0_1 8 12 SD/XD/MS_CMD_1

MDIO05 XD_CLE XD_CLE_1 SD/XD/MS_DATA1_1 XD_D0 SD_CMD SD/XD/MS_CLK_1
1 4 9 XD_D1 SD_CLK 24
88 SD/XD/MS_CMD SD/XD/MS_DATA2_1 26 36 SD_CD#
MDIO08 SD/XD/MS_DATA3_1 XD_D2 SD_CD_SW SD_WP#(XDR/B#)
SRN33J-5-GP-U 27 XD_D3 SD_WP_SW 35
83 XD_ALE XD_DATA4_1 28
MDIO19 XD_DATA5_1 XD_D4
30 XD_D5
85 XD_CLE XD_DATA6_1 31 19 SD/XD/MS_DATA0_1
MDIO18 XD_DATA7_1 XD_D6 MS_DATA0 SD/XD/MS_DATA1_1
32 XD_D7 MS_DATA1 20
78 XD_CE# 18 SD/XD/MS_DATA2_1
B MDIO02 SD_WP#(XDR/B#) MS_DATA2 SD/XD/MS_DATA3_1 B
1 XD_R/B MS_DATA3 16
SD/XD/MS_CLK_1 2
SD_WP#(XDR/B#) XD_CE#_1 XD_RE SD/XD/MS_CMD_1
MDIO03 77 3 XD_CE MS_BS 21
D19 XD_CLE_1 4 17 MS_INS#
SD_CD# XD_ALE_1 XD_CLE MS_INS SD/XD/MS_CLK_1
MDIO00 80 5 XD_ALE MS_SCLK 15
SB:06/20 Rename U37 Pin79 MS_INS# 1 SD/XD/MS_CMD_1 6
XD_WP# XD_WE
from"XD/MS_CD#" to "MS_INS#" 7 XD_WP
79 MS_INS# 3 XD_SW# 34 13
MDIO01 XD_CD_SW 4IN1_GND
R175 4IN1_GND 22
SD_CD# 2
84 SD/XD/MS_CLK 1 2 SD/XD/MS_CLK_1 NP2 38
MDIO09 NP2 GROUND
BAT54CPT-GP NP1 37
33R2J-2-GP NP1 GROUND
76 MC_PWR_CTRL_0
MDIO04
1

74 MS_LED# TP82 R176 SB:06/20 Remove U35,R148 and change D19 from CARD-PUSH-36P-1-GP-U2
MDIO06 TPAD30 100KR2J-1-GP 83.R0304.A8H to 83.R2003.E81.
97 RSV
73
2

MDIO07

R5C833-GP

For SD Card Power

3D3V_CARD U57 3D3V_S0 SB:06/20 Remove R427 and change U57
20mil 1 5
pin4 connect to "MC_PWR_CTRL_0"
A OUT IN <Core Design> A
2 GND
3 SET ON# 4 R426
Wistron Corporation
1

SCD1U16V2ZY-2GP RT9711DPBG DY
1

R418 C601 AAT4610AIGV-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
10KR2J-3-GP C609 Taipei Hsien 221, Taiwan, R.O.C.
SC1U10V3ZY-6GP R426 G5240D2T1U DY
2

15KR2J-1-GP -1:08/29 Change R426 Title

2

DY default from ASM to DY, R5C832/IEEE1394/SD

2

because change U57 main AAT4610AIGV 15K Size Document Number Rev
source, it don't need A3
R426. DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 26 of 47
5 4 3 2 1
 5 4 3 2 1

R394 R354 R357 R362 R372 R377 C528 C544

2D5V_LAN_S5 3D3V_LAN_S5
1D2V_LAN_S5 88E8039 DY 1.91K 49.9 49.9 49.9 49.9 0.01u 0.01u
R121 DY
88E8040 4.7K 2K DY DY DY DY DY DY 1 2
10MR2J-L-GP

57
52
51
32
28
22
19

40
45
61

64
23

33
39
44
48
58

13
1
8

2
7
U25 Note:Default is 88E8040 X2
LANX2 1 2 LANX1

AVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL

VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL

VDD25
AVDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1
XTAL-25MHZ-96GP
D C210 C209 D
3D3V_LAN_S5 SC12P50V2JN-3GP SC12P50V2JN-3GP

2
34 NC#34 WAKE# 6 PCIE_WAKE# 21,28
2 1 35 NC#35 PERST# 5 PCIRST1# 19,25
4K7R2J-2-GP R358 55 CLK_PCIE_LAN 4 SB:06/13 Change C209,C210 from 27P to 12P
REFCLKP
36 NC#36 REFCLKN 56 CLK_PCIE_LAN# 4
37 NC#37
50 LAN_RXN1 C230 1 2SCD1U10V2KX-4GP PCIE_RXN1 21
PCIE_TXN LAN_RXP1 C229 1
PCIE_TXP 49 2SCD1U10V2KX-4GP PCIE_RXP1 21

PCIE_RXN 53 PCIE_TXN1 21
3D3V_LAN_S5 LOM_DISABLE# 10 54
LOM_DISABLE# PCIE_RXP PCIE_TXP1 21
12 3D3V_LAN_S5
TPAD30 TP106 1LANSC VAUX_AVLBL 3D3V_LAN_S5
11 SWITCH_VCC
SB:06/13
3D3V_S0 1 R395 2 LANPWR 47 VMAIN_AVLBL LED_LINK# 63 LED_LINK# TP75 TPAD30
0R0402-PAD TP107 1LANSV 9 62 DY DY
SWITCH_VAUX NC#62

1
1

1
1 TPAD30
2 LANRSET 16 60 LAN100M_LED#
R354 2KR2F-3-GP CTRL12 RSET LED_SPEED# R407 R406
DY
3 CTRL12 LED_ACT# 59 ACT_LED# 28 0R2J-2-GP
CTRL25 4 DY 4K7R2J-2-GP 4K7R2J-2-GP
CTRL25
U31

PU_VDDO_TTL#42
PU_VDDO_TTL#43
TPAD30 TP115 1LANHP 24 15 LANX1 1 8 R408

2
2

2
TPAD30 TP114 HSDACP XTALI A0 VCC
1LANHN 25 HSDACN XTALO 14 LANX2 2 A1 WP 7 EEWP EEWP
3 6 VPD_CLK

TESTMODE
VPD_DATA
A2 SCL

1
Marvell recommend: VPD_DATA

VPD_CLK
4 GND SDA 5
2K Ohm(64.20015.6DL) R409

TSTPT
NC#27
NC#31

NC#26
NC#30
AT24C08AN-1-GP 0R2J-2-GP

GND
RXN

RXP
TXN

TXP
-1:0920 DY

2
88E8039-A0-GP
18
21
27
31

17
20
26
30

41
38

29
46

42
43

65
C C

TP116 Pull up for AT24C08 another pull low

28 MDI0- MDI0-
28 MDI1- MDI1- 1 3D3V_LAN_S5 LAN10M_LED#
TPAD30
VPD_CLK R394 1 2 DY
28 MDI0+ MDI0+ VPD_DATA 4K7R2J-2-GP DY

1
28 MDI1+ MDI1+ R393 1 2 MDI0+ 1 2 MDIS0_LAN 1 2 C528
4K7R2J-2-GP DY EC160 R357 DY 49D9R2F-GP

SC1KP50V2JN-2GP
SA:4/30 MDI0- 1 2 SCD01U16V2KX-3GP

2
R362 DY 49D9R2F-GP
MDI1+ 1 2 MDIS1_LAN 1 2 C544
3D3V_LAN_S5 R372 DY 49D9R2F-GP
R397 Q15 R417 Q17 MDI1- 1 2 SCD01U16V2KX-3GP
R377 49D9R2F-GP
DY
1 R50
88E8039 4K7 2SB772PT 4K7 2SB772PT 100KR2J-1-GP
DY
2

3D3V_LAN_S5 -1:0914 2D5V_LAN_S5 1D2V_LAN_S5

88E8040 DY DY DY DY LAN100M_LED# LAN100M_LED# 28
3D3V_LAN_S5 C539 1 2 C543 1 2 C565 1 2
SC1KP50V2KX-1GP -1:0914 SCD1U10V2KX-4GP SC1U6D3V2KX-GP
Q4 1
C R49 C538 1 2 C562 1 2
R1 100KR2J-1-GP C563 1 SC1KP50V2KX-1GP SC1KP50V2KX-1GP
B DY 2
SC1U6D3V2KX-GP
B
E -1:0914 B
R2 C557 1 2 C561 1 2
2

PDTC124EU-1-GP LAN10M_LED# 28 SC1KP50V2KX-1GP SC1U6D3V2KX-GP

C531 1 2
SC1U6D3V2KX-GP C553 1 2 C534 1 2
LED_LINK# SC1U6D3V2KX-GP SC1KP50V2KX-1GP
-1:0914
3D3V_LAN_S5 C542 1 2
SC1U6D3V2KX-GP
R137 1 2
DY 0R3-0-U-GP C535 1 2
PLACE PNP TO CHIP ACAP PLACE PNP TO CHIP ACAP SC1KP50V2KX-1GP
3D3V_S5 CTRL25 PIN TRACE IS 25MIL CTRL12 PIN TRACE IS 25MIL
-1:0914
S 3D3V_LAN_S5
D 3D3V_LAN_S5
1

1
D
SCD1U10V2KX-4GP

C239 DY C593 C256

1

1
G

SCD1U10V2KX-4GP

R139 Q14 C241 C560 C259 DY R417 SC4D7U6D3V5KX-3GP

10KR2J-3-GP SCD1U10V2KX-4GP
SC10U6D3V5KX-1GP

R397 4K7R2J-2-GP
SC4D7U6D3V5KX-3GP
2

2
AO3403-GP 4K7R2J-2-GP
2

3
DY
2

2
3

CTRL12 1 Q17
2

CTRL25 1 Q15 2SB772PT-1-GP 1D2V_LAN_S5

D 2SB772PT-1-GP
DY 2
2
3

2D5V_LAN_S5
1

1
Q16 C592 C255
1

2N7002PT-U C246 C590

SC4D7U6D3V5KX-3GP
SCD1U10V2KX-4GP
SC4D7U6D3V5KX-3GP

1 8053:CTRL25. 8053:2.5V.
2

2
34 PM_LAN_ENABLE
A G 8055:CTRL18. 8055:1.8V. <Core Design> A
2

SCD1U10V2KX-4GP
2

S
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN MARVELL
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 27 of 47
5 4 3 2 1
 5 4 3 2 1

2D5V_LAN_S5
RJ45 Connector 1.route on bottom as differential pairs.
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
CN7
10/100M Lan Transformer 3.No vias, No 90 degree bends. 4
2
4.pairs must be equal lengths.
XF1 5.6mil trace width,12mil separation. 1
27 MDI1+ 1 3
16 RJ45-3 6.36mil between pairs and any other trace.
7.Must not cross ground moat,except MLX-CON2-9-GP-U

RN8 RJ-45 moat. SA:04/23 change CN13 pin3,4 net

RJ45-1 1 8 RJ45-1_L name from "GND" to NC
D RJ45-2 2 7 RJ45-2_L D
RJ45-3 3 6 RJ45-3_L
RJ45-6 4 5 RJ45-6_L 3D3V_LAN_S5
2 15 RJ45-6 RJ1
27 MDI1-
3 14 XFR_RXC SRN0J-5-GP LAN100M_LED# 9
RJ11_1
7 10 RJ45-1 RJ11_2
27 MDI0+

1
DY EC17 A1 LAN10M_LED# 27
SC1KP50V2KX-1GP

2
A2 R47 1 2 330R2J-3-GP
RJ45-7
RJ45-4 A3 LAN100M_LED# 27
RJ45_1 RJ45-1_L
RJ45_2 RJ45-2_L
8 9 RJ45-2 ACT_LED# RJ45_3 RJ45-3_L -1:09/01 Change R43,R47 from
27 MDI0-
6 11 XFR_CMT RJ45_4 RJ45-4 63.47134.1DL to 63.33134.1DL
4 12 RJ45_5

1
5 13 RJ45_6 RJ45-6_L
1

4
3
2
1
DY EC11 RJ45_7 RJ45-7
C401 C392 XFORM-273-GP RN7 SC1KP50V2KX-1GP RJ45_8

2
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SRN75J-1-GP B1 1 2
2

R43 330R2J-3-GP
B2 ACT_LED# 27
10

5
6
7
8
RJ45+RJ11-5GP

C C
LAN_TERMINAL 1 2 Green : Link up
C416 SC1500P2KV8KX-3GP Blinking : TX/RX activity

NEWCARD Connector Place them Near to Connector

Place them Near to Chip 3D3V_NEW_S0 1D5V_NEW_S0 3D3V_NEW_LAN_S5

3D3V_S5 1D5V_S0

1
C613 C610 C620

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
C612 C611 SCD1U16V2ZY-2GP
DY DY NEW1
TP143
2

2
1

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 31
C617 C318 NEWCARD_OC# 1 TPAD30 NP1
1 2
2

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
TPAD30 TP144 1 CPPE# 3 4 PCIE_TXP5 21
4 NEWCARD_CLKREQ# NEWCARD_CLKREQ# 5 6 PCIE_TXN5 21
PM_SLP_S3# 21,34,36,43,45,46 3D3V_NEW_S0 7 8
9 10 PCIE_RXP5 21
PERST# 11 12 PCIE_RXN5 21
21
19
18

13 14
7

U58 15 16 CLK_PCIE_NEW 4
B 3D3V_NEW_LAN_S5 B
17 18
OC#
GND

THERMAL_PAD

STBY#
RCLKEN

21,27 PCIE_WAKE# CLK_PCIE_NEW# 4

1D5V_NEW_S0 19 20
21 22
21,29,30 SMB_DATA 23 24
25 26 CPUSB#
21,29,30 SMB_CLK
16 20 PM_SLP_S4# 21,34,40,44,45 TPAD30 TP137 1CONN_TP2 27 28 USB_PP8 21
NC#16 SHDN# PERST# TPAD30 TP138
1D5V_S0 14 NC#14 PERST# 8 RN73 DY 1CONN_TP3 29 30 USB_PN8 21
13 +1.5VVIN 9 CPUSB# 4 1 NP2
1D5V_NEW_S0 NC#13 +1.5VOUT CPUSB# 3D3V_S5
5 10 CPPE# 3 2 32
3D3V_NEW_S0 NC#5 +3VOUT CPPE#
4 6 NRST
3D3V_S0 NC#4 +3VIN SYSRST# SRN100KJ-6-GP FOX-CONN30A-9GP SB:07/04 For EMI request
AUXOUT

1.5VOUT

3.3VOUT
AUXIN

1.5VIN

3.3VIN

1
2 1 PLTRST# PLT_RST1# 8,19,23,24,29,30,34
R435 0R2J-2-GP EC145 EC144

SC5P50V2CN-2GP

SC5P50V2CN-2GP
Test circuit

2
TPS2231RGP-GP 2 1 DY DY
15
17
11
12
3
2

Use Card and No Card 2nd: 74.02231.A73 SC22P50V2JN-4GP C626

DY 3D3V_S0
3D3V_NEW_LAN_S5 3D3V_S0

3D3V_S5 3D3V_NEW_S0 +1.5V_CARD Max. 650mA, Average 500mA.

1
C621
+3.3V_CARD Max. 1300mA, Average 1000mA C624

SC4D7U6D3V5KX-3GP
1D5V_NEW_S0 1D5V_S0
+3.3V_CARDAUX Max. 275mA

2
A
SCD1U16V2ZY-2GP <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN connector/NEW CARD

Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 28 of 47
5 4 3 2 1
 5 4 3 2 1

Mini Card Connector 1(802.11a/b/g)

D SB:06/22 Change MINI1,2,3 slot from D

62.10043.431 to 62.10043.551(only
modify properties) MINI1
1D5V_S0 3D3V_S0
53

NP1
TP142 1MINI_2_WAKE# 1
TPAD30
2
30,31 WLAN_ACT 3
4
30 BT_ACT 5
6
TP141 1 7
TPAD30 8
9
10
4 CLK_PCIE_MINI1# 11
12
4 CLK_PCIE_MINI1 13
14
15
16

17
18
C 19 C
20 WIFI_RF_EN 34
21
22 PLT_RST1#
PLT_RST1# 8,19,23,24,28,30,34
21 PCIE_RXN2 23
24 3D3V_S0
21 PCIE_RXP2 25
26
27
28
29
30 SMB_CLK
SMB_CLK 21,28,30
21 PCIE_TXN2 31
32 SMB_DATA
SMB_DATA 21,28,30
21 PCIE_TXP2 33
34
35
36
37
38
3D3V_S0 39
40
41
42 1
43 TP131TPAD30
44 WLAN_LED 35
45
46 1
47 TP132TPAD30
B B
48
49
R432 50
5V_S5 1 2 51
DY 0R3-0-U-GP 52
NP2

54

SKT-MINI52P-18-GP

Main Source:62.10043.431
2nd Source: 20.F0992.052

3D3V_S0 3D3V_S0 1D5V_S0

5V_S5
A
WLAN_ACT -1:0909 <Core Design> A
DY
1

C616 C604 C284 SCD1U16V2ZY-2GP C275

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C291 C603 EC175 Wistron Corporation
SC220P50V2KX-3GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY DY DY
2

SCD1U16V2ZY-2GP Taipei Hsien 221, Taiwan, R.O.C.

SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
Title

MINI CARD CONN 1

Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 29 of 47
5 4 3 2 1
 5 4 3 2 1

Mini Card Connector

Mini Card Connector 2(WWAN) Mini Card Connector 3(Robson)
SB:06/22 Change MINI1,2,3 slot from SB:06/22 Change MINI1,2,3 slot from
62.10043.431 to 62.10043.551(only MINI2 62.10043.431 to 62.10043.551(only
1D5V_S0 3D3V_S0
modify properties) modify properties)
53

NP1
D TP80 1 MINI_WAKE# 1 MINI3 D
TPAD30 1D5V_S0 3D3V_S0
2 53
3 3D3V_S0
4 NP1
5 TP140 1 MINI_WAKE# 1
6 TPAD30 SC:08/09 Delete D21,add
TP139 1 7 2 U62(73.01G32.AHH) to replace D21
TPAD30 8 UIM_PWR 29,31 WLAN_ACT 3
UIM_PWR 35
9 4 1 2
10 UIM_DATA BT_ACT_2 5 R155 DY 0R2J-2-GP
UIM_DATA 35
11 6 1 2
4 CLK_PCIE_MINI2#
12 UIM_CLK TP81 1 7 R161 DY 0R2J-2-GP
UIM_CLK 35 TPAD30
4 CLK_PCIE_MINI2 13 8 U62
14 UIM_RESET 9 1 5
UIM_RESET 35 31 BT_ACT_1 B VCC
15 10
16 UIM_VPP 4 CLK_PCIE_MINI3# 11 BT_ACT_2 2
UIM_VPP 35 A
12
4 CLK_PCIE_MINI3 13 3 GND Y 4 BT_ACT 29
17 14
18 SC:07/30 Add "WWAN_RF_EN" GPIO pin 15 74LVC1G32GW-1GP

1
19 connect to MINI2 pin20 16
20 WWAN_RF_EN 34 R160
21 DY 100KR2J-1-GP
22 PLT_RST1# 34 E51_RXD R431 1 2 0R2J-2-GP E51_RXD_R17
PLT_RST1# 8,19,23,24,28,29,34
21 PCIE_RXN3 23 18

2
24 3D3V_S0 34 E51_TXD R428 1 2 0R2J-2-GP E51_TXD_R 19
21 PCIE_RXP3 25 20 BLUETOOTH_EN 31,34
26 21
C 27 22 PLT_RST1# C
PLT_RST1# 8,19,23,24,28,29,34
28 21 PCIE_RXN4 23
29 24 3D3V_S0
30 SMB_CLK 21 PCIE_RXP4 25
SMB_CLK 21,28,29
21 PCIE_TXN3 31 26 BT_ACT_1
32 SMB_DATA 27
SMB_DATA 21,28,29
21 PCIE_TXP3 33 28 BT_ACT_2
34 29

1
35 30 SMB_CLK
SMB_CLK 21,28,29
36 21 PCIE_TXN4 31 R192 R194
USB_PN4 21

100KR2J-1-GP

100KR2J-1-GP
37 32 SMB_DATA
SMB_DATA 21,28,29
38 USB_PP4 21 21 PCIE_TXP4 33
3D3V_S0 39 34

2
40 35
41 36 USB_PN9 21
42 WWAN_LED 1 37
43 TP134TPAD30 38 USB_PP9 21
44 1 3D3V_S0 39
45 TP133TPAD30 40
46 1 41
47 TP130TPAD30 42 1 SC:08/11 Add R192,R194
48 43 TP136TPAD30 pull low resistor for
49 44 1 bluetooth active signal
R430 50 -1:0905 Add C637,C638 for SIM 45 TP135TPAD30
5V_S5 1 2 51 CLK and DATA. 46 BT_ACT_WPAN# 35
to
DY 0R3-0-U-GP 52 47
NP2 48
UIM_DATA 49
54 R429 50
B UIM_CLK B
5V_S5 1 2 51
DY 0R3-0-U-GP 52
NP2
SKT-MINI52P-18-GP
1

54
C637 C638
SC33P50V2JN-3GP

SC33P50V2JN-3GP
2

Main Source:62.10043.431 Main Source:62.10043.431

2nd Source: 20.F0992.052 SKT-MINI52P-18-GP 2nd Source: 20.F0992.052

3D3V_S0 1D5V_S0 3D3V_S0

5V_S5

1
3D3V_S0 1D5V_S0 3D3V_S0 C615 C289 SCD1U16V2ZY-2GP C286 DY C606
SCD1U16V2ZY-2GP C285 C605 SCD1U16V2ZY-2GP
5V_S5
DY DY DY DY

2
SCD1U16V2ZY-2GP DY
SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
1

TC5 C274 C277 C608 Place C606 near MINI 3 pin24

1

C614 C287 C602 C607

SCD1U16V2ZY-2GP
SCD01U16V2KX-3GP

DY DY
SCD1U16V2ZY-2GP

DY ST220U6D3VDM-20GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

2

SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
A Place TC35 near MINI 2 <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MINI CARD CONN 2 & 3

Size Document Number Rev
A3
DS2-Intel -3
Date: Wednesday, January 23, 2008 Sheet 30 of 47
5 4 3 2 1
 5 4 3 2 1

-1:0910

3D3V_S5 3D3V_AUX_S5
3D3V_AUX_S5

CIR

1
DY SC:08/12 Add R458 SC:07/26 Rename
R205 R182 (63.10434.1DL) pull up for "SNIFFER_BD1" to

1
10KR2J-3-GP 10KR2J-3-GP
U61 "WLAN/BT_BTN#. Because R458 "SNIFFER1"
D sniffer is option feaature. 100KR2J-1-GP D

2
FRIEE_CIRRX 4
34 CIRRX OUT

SCD1U10V2KX-4GP
3D3V_S5 2 1 SIO_CIRRX_VS 3 SNIFFER1

2
100R2J-2-GP R181 VS
2 GND 7

1
C333
C332 1 34 WLAN/BT_BTN# 1
GND

SC4D7U6D3V5KX-3GP
2

2
TSOP36136-GP 34 SNIFFER_PWR_SW#
3
34 SNIFFER_YELLOW# 4
34 SNIFFER_BLUE# 5
5V_S5 6

SCD1U10V2KX-4GP
8

C578
1
MLX-CON6-11-GP

2
MDC1
MH1
14 WLAN/BT_BTN# SNIFFER_PWR_SW# SNIFFER_YELLOW# SNIFFER_BLUE#
C 13 15 C
1 2

1
20,23,32 ICH_SDOUT_CODEC 3 4 DY EC114 DY EC115 DY EC111 DY EC110

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP
5 6 3D3V_S5

2
20,23,32 ICH_AZ_CODEC_SYNC 7 8
20 ICH_SDIN_MDC 1 2 ACSDATAIN1_A 9 10
R266 39R2J-L-GP 11 12 ICH_ACZ_MDC_BITCLK
20 ICH_AZ_MDC_RST# ICH_ACZ_MDC_BITCLK 20,23
16 18
1

17
C428 MH2

1
SC22P50V2JN-4GP C432 R265
2

1
SC4D7U6D3V5KX-3GP

100KR2J-1-GP
AMP-CONN12A-1GP C204
2
SC22P50V2JN-4GP

2
DY
Main Source:20.F0677.012 2
2nd Source: 20.F0676.012

B
Bluetooth Module conn. BT1
11
B

21 USB_PP5 2
21 USB_PN5 3
4
30 BT_ACT_1 5
3D3V_S0 6
30,34 BLUETOOTH_EN
29,30 WLAN_ACT 7
8
BT_LED 9
1

C424 10
12
1

SCD1U10V2KX-4GP
2

R259 FOX-CON10-GP
10KR2J-3-GP
20.F0711.010
2

Q28 BT_ACT_1 BLUETOOTH_EN USB_PP5 USB_PN5

35 BT_ACT_K# C
1

R1 B
1

1
E DY DY EC173
1

SC22P50V2JN-4GP

R2 EC172 EC62 EC174

DY DY
2
SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC22P50V2JN-4GP
PDTC124EU-1-GP R258
2

2
10KR2J-3-GP
A <Core Design> A
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SC:08/14 Add Taipei Hsien 221, Taiwan, R.O.C.
EC172(78.22124.2FL) on SC:08/14 Add
SC:08/14 Add EC174(78.22034.1FL) on Title
"BT_ACT1" for
EMI team request. EC173(78.22034.1FL) on "USB_PN5" for MDC/CIR/Bluetooth/Sniffer Conn.
"USB_PP5" for EMI team request. Size Document Number Rev
EMI team request. A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 31 of 47
5 4 3 2 1
 5 4 3 2 1

+VDDA
60ohm 100MHz
3000mA 0.05ohm DC

1
R421
3D3V_S0 +VDDA 5K1R2F-2-GP

2
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP
R420 1 2 AUD_HP1_JD# 33

SC1U10V3KX-3GP
C266

C276

C270

C320

C296
39K2R2F-L-GP

2
D D
U36

1 DVDD_CORE AVDD1 25
9 38 +VDDA
R152 2 DVDD_CORE AVDD2
1+3V_RUN_DVDD_CORE3 40 DVDD
100KR2J-1-GP 13 AUD_SENSE_A
SENSE_A

1
2 1 34 AUD_SENSE_B
C298 SC1KP50V2KX-1GP SENSE_B R154
SB:07/10 Change R344 from 33 Ohm to 0 Ohm
TO Audio OP 5K1R2F-2-GP
ICH_AZ_CODEC_BITCLK 6 39 AUD_HP1_OUT_L
20 ICH_AZ_CODEC_BITCLK BIT_CLK PORT_A_L AUD_HP1_OUT_R AUD_HP1_OUT_L 33
41

2
SB_AZ_CODEC_SDIN0_R 8 PORT_A_R AUD_HP1_OUT_R 33 R158 1
20 ICH_SDIN_CODEC 2 1 SDATA_IN VREFOUT_A 37 2 AUD_HP2_JD# 33
R146 33R2J-2-GP 20KR2J-L2-GP
20,23,31 ICH_SDOUT_CODEC 5 SDATA_OUT PORT_B_L 21
PORT_B_R 22
10 28 R157 1 2 EXT_MIC_JD#
20,23,31 ICH_AZ_CODEC_SYNC SYNC VREFOUT_B C292 1 2SC1U10V3KX-3GP INT_MIC 39K2R2F-L-GP
11 23 AUD_INT_MIC_L
20 ICH_AZ_CODEC_RST# RESET# PORT_C_L
24 AUD_INT_MIC_R C294 1 2SC1U10V3KX-3GP
PORT_C_R AUD_VREFOUT_B R1531
VREFOUT_C 29 2
4K7R2J-2-GP
35 AUD_LINE_OUT_L
PORT_D_L AUD_LINE_OUT_R AUD_LINE_OUT_L 33
36
3D3V_S0 U34 DY PORT_D_R
32
AUD_LINE_OUT_R 33
VREFOUT_D
5 VCC OE# 1 TO Audio OP
2 14 AUD_EXT_MIC_L
AUD_DMIC_CLK_G A PORTE_L AUD_EXT_MIC_R
18 AUD_DMIC_CLK_G 4 Y GND 3 PORTE_R 15
31 AUD_VREFOUT_E
C 74LVC1G125DC-GP VREFOUT_E C

PORTF_L 16 AUD_HP2_OUT_L 33 Port A---> HP1

2 1 AUD_DMIC_CLK 17
R149 33R2J-2-GP PORTF_R AUD_HP2_OUT_R 33 Port E---> Ext Mic
VREFOUT_F 30
Port D---> Speaker
PORTG_L 43 Port F---> HP2
SB: Change R149 from 63.R0034.1DL to 63.33034.1DL PORTG_R 44 Port C--->Int Mic
PORTH_L 45
AUD_DMIC_IN0 2 46
18 AUD_DMIC_IN0 VOLUME UP/DMIC_0/GPIO1 PORTH_R
R455 3 VOLUME DN/DMIC_1/GPIO2

35 SPDIF_D 2 1 200R2F-L-GP CD_L 18

CD_GND 19
PC BEEP
AUD_DMIC_CLK 47 20
AUD_SPDIF_OUT SPDIF_IN/GPIO0/DMIC_CLK CD_R
23 AUD_SPDIF_OUT 48 SPDIF_OUT From SB
R141
12 AUD_PC_BEEP 1AUD_BEEP 2 1 2 SB_SPKR 21
PC_BEEP C267
4 DVSS1
7 33 AUD_CAP2 SCD1U10V2KX-4GP 47KR2F-GP
DVSS2 CAP2 AUD_VREFFLT
VREFFILT 27

1
AUD_DMIC_CLK_G
26 C299 C300 R412 R413
AVSS1

SC10U10V5KX-2GP

SC10U10V5KX-2GP

10KR2J-3-GP
42 1 2 KBC_BEEP 34

1
AVSS2 47KR2F-GP
1

2
EC129 STAC9228X5TAEA2-GP 71.09228.00G From EC
SC22P50V2JN-4GP
2

B SA:0428 B

SB:06/26 Add
Internal Microphone
EC129(78.22034.1FL) by EMI
request

MIC IN
-1:0920

Azalia I/F EMI Azalia I/F EMI CN4

ICH_SDOUT_CODEC -1:0921 Remove R144 and C265 INT_MIC 1 MICROPHONE-40-GP-U1

AUD_VREFOUT_E
EC52

2
1

1
SC1KP50V2KX-1GP
1

C302
SC1U10V3KX-3GP
R162

R163
4K7R2J-2-GP

4K7R2J-2-GP

R145 EXT_MIC_JD#
2

2
47R2J-2-GP MIC1
1
DY
2

2
ICH_AZ_CODEC_SDOUT1

2
AUD_EXT_MIC_L 1 2 C306 MIC_IN_L_2 1 2 MIC_IN_L_C 6
A
SC1U10V3KX-3GP R169 0R3-0-U-GP <Core Design> A
AUD_EXT_MIC_R 1 2 C307 MIC_IN_R_2 1 2 MIC_IN_R_C 3
SC1U10V3KX-3GP R168 0R3-0-U-GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP
4
Wistron Corporation
1

1
EC48

EC49
SB:07/02 Change R168 from 63.R0034.1DL to 63.00000.00L
5 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
7 Taipei Hsien 221, Taiwan, R.O.C.
2

8
600ohm 100MHz 9 Title
1

C263
SCD1U10V2KX-4GP 200mA 0.5ohm DC 10 AUDIO CODEC STAC9228
AUDIO-JK89-GP-U Size Document Number Rev
DY
2

A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 32 of 47
5 4 3 2 1
 5 4 3 2 1

3D3V_S0
Close to U27.18 3D3V_S0
5V_S0 Speaker

SCD1U10V2KX-4GP
SC10U10V5KX-2GP
5V_S0

SC1U10V3KX-3GP

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP
60ohm 100MHz

1
C327

C623

C322

C618
C622
3000mA 0.05ohm DC

SC1U10V3KX-3GP
60ohm 100MHz

1
C328

C627
2

2
3000mA 0.05ohm DC
SC10U6D3V5KX-1GP

5
SPK1

18

17

30
8

9
U59
D Close to U37.8 AUD_SPK_L2 R11 1 2 0R0603-PAD AUD_SPK_L2_R 1 D

PVDD

PVDD

CPVDD

HPVDD

VDD
AUD_SPK_L1 6 2 AUD_LIN_R 1 2 AUD_SPK_L1 R14 1 2 0R0603-PAD AUD_SPK_L1_R 2
3D3V_S0 OUTL+ SPKR_INR AUD_LINE_OUT_R 32
AUD_SPK_L2 7 3 AUD_LIN_L C630 1 2SCD033U16V3KX-GP AUD_SPK_R2 R13 1 2 0R0603-PAD AUD_SPK_R2_R 3
OUTL- SPKR_INL AUD_LINE_OUT_L 32
AUD_SPK_R2 19 C629 SCD033U16V3KX-GP AUD_SPK_R1 R10 1 2 0R0603-PAD AUD_SPK_R1_R 4
AUD_SPK_R1 OUTR-
20 OUTR+
2

C314 R156 2 1 5V_S0 DY DY DY DY

SC1U6D3V2KX-GP 100KR2J-1-GP MLX-CON4-15-GP-U

SC100P50V2JN-3GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP

6
AUD_HP1_JACK_R 15 23 AUD_SPK_ENABLE# From EC
1

HPR SPKR_EN#

1
EC7

EC9

EC6

EC8
AUD_HP1_JACK_L 16 25 AMP_MUTE#_R R171 2 1 0R2J-2-GP
HPL MUTE# AMP_MUTE# 34
22 AUD_HP1_EN DY DY
HP_EN AMP_REGEN R441 2
4 1 5V_S0

2
AUD_AMP_GAIN1 REGEN AMP_C1P +VDDA 100KR2J-1-GP
Close to U30.9 31 GAIN1 C1P 10 1 2

1
AUD_AMP_GAIN2 32 12 AMP_C1N C317
GAIN2 C1N SC1U10V3KX-3GP C628
VOUT 29
24 AUD_BIAS SCD033U16V3KX-GP SC:08/13 Change R441pin1

2
AUD_HP1_OUT_R126 BIAS AUD_SET
32 AUD_HP1_OUT_R 1 2 HP_INR SET 1 connection

SCD033U16V3KX-GP
C309 1 2SC10U10V5KX-2GPAUD_HP1_OUT_L1 27

CPGND

CPVSS
32 AUD_HP1_OUT_L HP_INL from"AMP_MUTE#" to 5V_S0

PGND
PGND

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP
PVSS
C310 SC10U10V5KX-2GP

GND
GND

1
C631

C311

C321

C619
DY

1
MAX9789A-GP R440

21
5

28
33

11

13

14

2
2
Default 0R2J-2-GP

2
TPA6040A MAX9789A
Main source: TPA6040A 74.06040.013
LINE1 OUT
R156 100K No ASM
C 1 2AUD_CPVSS 2nd source: MAX9789A 74.09789.013 C
C316 SC1U10V3KX-3GP
R171 No ASM 0 Ohm AUD_HP2_EN
3D3V_S0 AUD_HP2_JACK_L
AUD_HP2_JACK_R
R440 No ASM 0 Ohm LOUT1
1

1
R441 No ASM 100K C313 AUD_HP1_JD#

10
19

14
18

11
32 AUD_HP1_JD# 2

9
SC1U6D3V2KX-GP U38

2
AUD_HP1_JACK_L 1 2 AUD_HP1_JACK_L1 6

SHDNR#
SHDNL#
SVDD
PVDD

OUTL
OUTR
C631 0.33uF No ASM -1:0909 L10
AUD_HP1_JACK_R 1 2 AUD_HP1_JACK_R1 3
C295 L11
C628 0.33uF No ASM AMP2_C1N AMP2_C1P

SC100P50V2JN-3GP

SC100P50V2JN-3GP
1 2 1 C1P NC#4 4 4

1
EC50

EC51
3 C1N NC#6 6 600ohm 100MHz
8 5
SC2D2U6D3V3KX-GP NC#8
12 200mA 0.5ohm DC 7

2
AUD_HP2_OUT_L AUD_HP2_OUT_L2 NC#12
32 AUD_HP2_OUT_L
AUD_HP2_OUT_R
1
C305 1
2 13 INL NC#16 16 DY DY SA:4/28
8
32 AUD_HP2_OUT_R 2 SC10U10V5KX-2GP AUD_HP2_OUT_R2 15 INR NC#20 20 9
C301 SC10U10V5KX-2GP 10

SGND
PGND
PVSS

SVSS
SB:70213 AUDIO-JK89-GP-U

GND
GAIN SETTING
Main source: TPA4411MRTJ 74.04411.AE3

21

17
2
LINE2 OUT
2nd source: MAX4411EPT+ 74.04411.A13 MAX4411ETP-1-GP
This pin should be FLOAT.
5V_S0 C304
B AUD_PVSS
Do NOT connect to GND. B
1 2
-1:0914

Signal inverter for speaker shutdown

SC2D2U6D3V3KX-GP
1

5V_S0
R434 R439 SC:08/12 Add R459
DY 100KR2J-1-GP 100KR2J-1-GP (63.10434.1DL) pull up

1
DY for U64 pin4 "NB_SPK_EN". R167 LOUT2
2

AUD_AMP_GAIN1 AUD_AMP_GAIN2 100KR2J-1-GP 1

SC:08/11 Delete
1

+VDDA 5V_S0 5V_S0 U63 AUD_HP2_JD# 2

Q19, Add U63,R457

2
R433 R436 32 AUD_HP2_JD#
AUD_HP1_JD circuit for HP1 AUD_HP2_JACK_L AUD_HP2_JACK_L2
100KR2J-1-GP 100KR2J-1-GP 4 3 1 2 6
1

L9
R172 R459 AUD_HP1_JD# 5 2 AMP_MUTE# AUD_HP2_JACK_R 1 2 AUD_HP2_JACK_R2 3
2

100KR2J-1-GP 100KR2J-1-GP L8
R159 AUD_HP1_JD AUD_HP1_EN

SC100P50V2JN-3GP

SC100P50V2JN-3GP
6 1 4

1
EC46

EC47
100KR2J-1-GP 600ohm 100MHz
2

5
200mA 0.5ohm DC
1

D22 U64 2N7002SPT DY DY 7

2

2
R457 5V_S0 8
GAIN1 GAIN2 GAIN AUD_HP1_JD# 1 4 3 AUD_SPK_ENABLE# 10MR2J-L-GP 9

1
SA:4/28 10
0 0 6dB 3AUD_SPK_ENABLE 5 2 AMP_MUTE# R166
2

AUD_HP2_JD# 2 33KR2J-3-GP AUDIO-JK89-GP-U

0 1 10dB NB_SPK_EN# 6 1
U39

2
BAW56PT-U
1 0 15.6dB SC:08/11 Delete Q18, Add
A
2N7002SPT U64 circuit for Speaker 4 3 AUD_HP2_JD <Core Design> A
1 1 21.6dB
AUD_HP2_JD# 5 2 AMP_MUTE#

AUD_HP2_JD 6 1 AUD_HP2_EN Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2N7002SPT 1
R165 Title
10MR2J-L-GP
AUDIO AMP/SPEAKER
Size Document Number Rev
2

A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 33 of 47
5 4 3 2 1
 5 4 3 2 1
VBAT 3D3V_AUX_S5
-1:0914
C194 C193 C518

1
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
SC1U10V3ZY-6GP
-1:0914

SC1U10V3ZY-6GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

1
C513 C515 C505 C512 C504
20 LPC_LAD[0..3] AD_IA 39
TP60 TPAD28

2
LPC_LAD3 TP61 TPAD30 KB_DET# 37
LPC_LAD2 PCB_VER0
PLACE CAP NEAR PIN80 AND PIN102 LPC_LAD1 PCB_VER1
LPC_LAD0
DMIC_DET# 18
PLACE CAP NEAR PIN46,19,115,76,88,104 -1:08/29 Change U22 pin110 define from NC
TP52 TPAD28 SNIFFER_PWR_SW# 31
to"USB_PWR_EN" or USB power control.
3D3V_AUX_S5 ECRST# BLUETOOTH_EN 30,31
USB_PWR_EN#
USB_PWR_EN# 35,38
D WPC8763L STRAP PIN 1 R329
0R0603-PAD
2 VBAT E51_TxD E51_TxD 30
TP97 TPAD28 D
3D3V_S0 PLT_RST1#_1 2 1 R336 PLT_RST1# 8,19,23,24,28,29,30
JEN0 JENK Functionality of Pins Functionality of Pins 0R2J-2-GP
LPC_LFRAME# 20

1
(Pin 24) (Pin 53) 17, 20, 21, 23 25, 27 47, 48, 50, 51, 52 C517 ECSCI#_KBC

SC470P50V2KX-3GP
SC10U6D3V5KX-1GP C514
NO PD RES GPIO Port Keyboard Scan DY

115

102

126
127
128

100

101
105

106
107

110
111
112
U22

46
19

76
88

85

97
98
99

75
83

29

2
4

7
3
10K PD NO PD JTAG signals Keyboard Scan

VCC
VCC
VCC
VCC
VCC

AVCC

VCC_POR#

VDD

LAD0
LAD1
LAD2
LAD3

GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3

GPI94/DA0
GPI95/DA1

GPI96
GPI97

GPO72
GPO76/SHBM
GPO82/HGPO00/TRIS#
GPO83/SOUT_CR/BADDR1
GPO84/HGPO01/BADDR0

LRESET#
LFRAME#
ECSCI#
NO PD 10K PD GPIO Port JTAG signals

TRIS#(Pin 110) TRI-STATE 21,28,36,43,45,46 PM_SLP_S3#

KBC_PWRBTN#
64
95
GPIO01 KBSIN0 54
55
KROW0
KROW1
KROW[0..7] 37
35 KBC_PWRBTN# GPIO03 KBSIN1
Forces the device to float all its output and I/O pins,if an
KBC_THERMTRIP# 96 56 KROW2
GPIO04 KBSIN2 KROW3
18 LCD_CBL_DET# 108 GPIO05 KBSIN3 57
KROW4
external 10 KΩ pull-down resistor is conected. 39 AC_IN# 93 GPIO06/HGPIO06 KBSIN4 58
35 LID_CLOSE# 94 59 KROW5
INSTEAD_BTN# GPIO07/HGPIO07 KBSIN5 KROW6
35 INSTEAD_BTN# 124 GPIO10/HGPIO00/LPCPD# KBSIN6 60
21,25 PM_CLKRUN# 8 61 KROW7
GPIO11/HGPIO02/CLKRUN# KBSIN7 10KR2J-3-GP
38 BAT_IN# 13 GPIO12/PSDAT3
18 BRIGHTNESS 62 R88 2 1
GPIO13/B_PWM0
BADDR1-0 (PIN 111, 112) I/O Base Address. 31 CIRRX 63 53 KCOL0 TP47 TPAD28
GPIO14/HGPIO04/TB1 KBSOUT0/JENK#
10KΩ external pull-down 35 BATFULL_LED 114 52 KCOL1 TP42 TPAD28 DY
GPIO16/HGPIO04 KBSOUT1/TCK KCOL2 TP48 TPAD28
38 ACDC_ID 117 GPIO20/TA2 KBSOUT2/TMS 51
KCOL3 TP43 TPAD28
resistor on BADDR1: Core defined 35 PWRLED 118 GPIO21/A_PWM1 KBSOUT3/TDI 50
21 PM_PWRBTN# 119 49 KCOL4 KCOL[0..16] 37
GPIO23 KBSOUT4 KCOL5 TP44 TPAD28
35 SCRLK_LED 6 GPIO24/HGPIO01 KBSOUT5/TDO 48
-1:08/30 Change Pin10 from NC to be"WWAN_RF_EN" 10 47 KCOL6 TP49 TPAD28
3D3V_S0 30 WWAN_RF_EN GPIO26/PSCLK2 KBSOUT6/RDY# KCOL7
24 HDD_5V_EN 11 GPIO27/PSDAT2 KBSOUT7 43
-1:08/30 Change Pin11 from NC to be"HDD_5V_EN" TPAD30 TP55 12 42 KCOL8
NUM_LED GPIO25/PSCLK3 KBSOUT8 KCOL9
35 NUM_LED 109 GPIO30 KBSOUT9 41 KBC DEBUG POINT
35 CAP_LED CAP_LED 120 40 KCOL10
GPIO31 KBSOUT10
1

35 LED_MASK# 65 39 KCOL11
R105 GPIO32 KBSOUT11 KCOL12
31 SNIFFER_BLUE# 66 GPIO33 KBSOUT12/GPIO64 38
10KR2J-3-GP 18 LCD_TST 14 37 KCOL13
GPIO34 KBSOUT13/GPIO63
DY PIN 111
15 36 KCOL14
46 S5_ENABLE GPIO36 KBSOUT14/GPIO62 KCOL15
16 35
C 21 RSMRST#_KBC
C
2

E51_TxD GPIO40 KBSOUT15/GPIO61/XOR_OUT

38 AD_OFF 17 GPIO42/TCK
27 PM_LAN_ENABLE 20 GPIO43/TMS
2

35 CHARGE_LED CHARGE_LED 21 86 SPIDI 35

GPIO44/TDI F_SDI
SB:06/24 Change R104 from 37 CAPA_INT# 22 GPIO45 F_SDO 87 SPIDO 35
R104 63.10334.1DL to 63.47234.1DL.Base on 23 92 SPICLK 35
4K7R2J-2-GP 35 WLAN_LED_TEST TPAD30 TP57 GPIO46/TRST# F_SCK
Winbond FAE recommend to fix system -1: 08/29 change Pin24 from "WWAN_RF_EN" 24 GPO47/JEN0# F_CS0# 90 SPICS# 35
to NC, because pin24 is H/W straping 38 PSID_DISABLE# 25
1

will hang up after Thermal T8 GPIO50/TDO

pin. it has H/W concern. 31 WLAN/BT_BTN# 26 GPIO51 SDA1 69 BAT_SDA 18,38,39 <-----BATTERY

GPIO57/HGPIO03/KBSOUT17
shutdown 18 LCD_TST_EN LCD_TST_EN 27 70
GPIO52/RDY# SCL1 BAT_SCL 18,38,39
10 GMCH_BL_ON 28 GPIO53
TPAD30 TP50 CLKOUT 30 GPIO55/CLKOUT
25 GBRST#_KBC 31 GPIO56/TA1 PSDAT1 71 TPDATA 37
SHBM PIPN83 Shared Host BIOS Memory.

GPIO60/KBSOUT16

GPIO63/PWUREQ#
PSCLK1 72 TPCLK 37

32KX1/32KCLKIN
SC:08/03 Change Pin27 from"BLON_OUT" to"

GPIO87/SIN_CR
3D3V_S0
HIGH:NO SHARED(internal resistor) LCD_TST_EN", delete TP45 test pad.

GPIO62/SDA2
GPIO61/SCL2

GPIO64/SMI#
GPIO66/SWD
DY

RESERVED
LOW:SHARED BIOS memory. 1 2 E51_RxD

A_PWM0
KBRST#
SERIRQ
GPIO70
GPIO71
GPIO75
GPIO77
GPIO81
R103 10KR2J-3-GP

VCORF

32KX2

AGND
VREF
GA20
R98

LCLK

GND
GND
GND
GND
GND
GND
1 2 BLUETOOTH_EN RN59
4K7R2J-2-GP 1 4 KA20GATE
SB:06/27 Change R98 from 63.10334.1DL to WPC8763LDG-1-GP 2 3 KBRCIN#

33
34
67
68
123
9
81
73
74
82
84
91
113

121
125
122

2
104
44
32
80

79
77

5
18
45
78
89
116

103
63.47234.1DL .
SRN10KJ-5-GP
TPAD30 TP51 KCOL17
TPAD30 TP46 KCOL16 3D3V_AUX_S5

VCORF
KBC_BEEP
VBAT
KBC_SCL1 RN21
KBC_SDA1 1 8 KBC_SCL1
ECSWI#_KBC KBC_XI 2 7 KBC_SDA1
1D05V_S0 TPAD30 TP56 GPIO64 KBC_XO 3 6 BAT_SDA
4 5 BAT_SCL

SCD1U16V2ZY-2GP
21,28,40,44,45 PM_SLP_S4#

1
31 SNIFFER_YELLOW# KBC_BEEP 32 DY EC32
1

TPAD30 TP53 SRN10KJ-6-GP

R442 29 WIFI_RF_EN RN60

2
1
2K2R2J-2-GP ECSMI#_KBC 1 4 KBC_PWRBTN#
33 AMP_MUTE# 2 3 INSTEAD_BTN#
E51_RxD C183
2

2
30 E51_RxD SCD1U16V2ZY-2GP SRN10KJ-5-GP
C632 KA20GATE 3D3V_AUX_S5
20 KA20GATE
1 2 21,25 INT_SERIRQ R106 1 2 SNIFFER_PWR_SW#
KBRCIN# 100KR2J-1-GP

B SCD1U16V2ZY-2GP 20 KBRCIN#
B
B

4 PCLK_KBC R101 1 LID_CLOSE#

2
10KR2J-3-GP
E C KBC_THERMTRIP#
5,8,20,46 H_THERMTRIP#
Q34 R443 1 LCD_CBL_DET#
2
CH3904PT-GP 3D3V_S0 10KR2J-3-GP

ADIA:to Charger R447 1 2 KB_DET#

3D3V_S0 R323 1 2 0R2J-2-GP 10KR2J-3-GP
37 CAP_SDA
ACDC_ID:from Adapter Conn
FOR Thermal AND U54
KBC_PWRBTN#:from power button
R448 1 2 DMIC_DET#
10KR2J-3-GP

MB VERSION ID Capacity Button Module 36 G792_SDA 4 3 KBC_SDA1

1

BAT_IN#:from Battery Conn

R335
10KR2J-3-GP

5 2
R337 DC_BATFULL#:for Battery charge LED 1
10KR2J-3-GP KBC_SCL1 6 1 G792_SCL 36
MB VERSION ID
DY WLAN_TEST:for WKS test WLAN LED
2

PCB_VER0 2N7002SPT 1 2 AD_OFF:enable AC adapter power source

CAP_SCL 37
VER0 VER1
PCB_VER1 R322 0R2J-2-GP R331
CHARGE_LED#:for Battery charge LED 2 S5_ENABLE 1 2
-2 0 0
10KR2J-3-GP
1

WLAN/BT_BTN#:from Wlan on/off button

-3 0 1
R339
R338
10KR2J-3-GP

10KR2J-3-GP DY D30 GMCH_BL_ON:Sense The Backlight On/Off Status from VGA Chip
SC 1 0 21 ECSWI# 1 3D3V_AUX_S5 ECRST#
WIRELESS_EN:Disable/Enable Wireless Module
2

-1 1 1 3 ECSWI#_KBC
BLUETOOTH_EN:Disable/Enable Bluetooth
2 Q30 C516

1
USB_PWR_EN#:to on/off USB power switch RN58

SC1U10V3KX-3GP
BAS16-1-GP 1 4
WPC8763L XTAL KBC CLK EMI CCD_ON:Webcam power on/off 36,46 PURE_HW_SHUTDOWN# 2 3 ECRST#_C B

2
D29
KBC_XO AC_IN#:From Charge SRN10KJ-5-GP

C
PCLK_KBC 21 ECSCI# 1
2

R326 R451 R340 3 ECSCI#_KBC

A 1 2 KBC_XI_R 1 2 KBC_XI DY 0R2J-2-GP

2 A
1

10MR2J-L-GP 10MR2J-L-GP
1

R330
PCLK_KBC_RC

BAS16-1-GP
33KR2J-3-GP
X5
-1:0912 <Core Design>
2

KBC_XO_R 1 4
SC18P50V2JN-1-GP

Wistron Corporation
SC18P50V2JN-1-GP

D16
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

2 3 21 ECSMI# 1 Taipei Hsien 221, Taiwan, R.O.C.

C510 C507 C519
DY SC4D7P50V2CN-1GP 3 ECSMI#_KBC Title
2

X-32D768KHZ-40GPU
2 KBC_Winbond WPC8763L
Size Document Number Rev
-1:0915 BAS16-1-GP A2
-1:0915 DS2-Intel -3
Date: Wednesday, January 23, 2008 Sheet 34 of 47

5 4 3 2 1
 5 4 3 2 1

Power Dash Board to Board CONN

SPI B
Q3

R1
C LED_SCRLK#
-1:09/02 Change
5V_S5
CN2
34 SCRLK_LED
E CN2(Power Dash Board) 9
3D3V_AUX_S5 R2 1
3D3V_AUX_S5 PDTC124EU-1-GP pin assignment.
2
3
SPI FLASH ROM 34 KBC_PWRBTN#
34 INSTEAD_BTN# 4

1
Q1 5

5
6
7
8
D C508 C509 C506 C LED_CAP# LED_SCRLK# 6 D
SC10U6D3V5MX-3GP B R1 LED_CAP# 7

2
SCD1U16V2ZY-2GP 34 CAP_LED LED_NUM#
SRN10KJ-6-GP DY SCD1U16V2ZY-2GP R2
E 8
10
RN24 PDTC124EU-1-GP

1
C5

SPI_HOLD# 4
3
2
1
-1:0920 SCD1U16V2ZY-2GP MLX-CON8-10-GP-U
Q2 20.K0227.008

2
C LED_NUM#
B R1
16M Bits
3D3V_AUX_S5
EMI REQUEST 34 NUM_LED
R2
E
U21 Main Source:20.K0227.008
PDTC124EU-1-GP 2nd Source: 20.K0237.008
34 SPICS# SPICS# SPICS# 1 8
R99 CS# VCC SPI_HOLD#
34 SPIDI 1 2 2 DO HOLD# 7
SPI_WP# 3 6 R334 1 2 SPICLK 34 KBC_PWRBTN# INSTEAD_BTN# LED_SCRLK# LED_CAP# LED_NUM#
WP# CLK
1

150R2J-L1-GP-U 4 5 1 2 SPIDO 34
GND DIO

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP
EC34 R333 150R2J-L1-GP-U

1
SC4D7P50V2CN-1GP 150R2F-1-GP EC98
2

1
W25X16VSSIG-GP SC4D7P50V2CN-1GP EC3 EC2 EC55 EC54 EC53

2
EC97

2
SC4D7P50V2CN-1GP
DY DY DY DY DY

2
C
LED Board to Board CONN
-1:09/02 Change CN3(LED
DY
R446
D13
2 BT_ACT_WPAN# 30
Right I/O Board to Board CONN C

Board) pin assignment. BT_LED# 1 2 BT_LED#_R 3 -1:08/29 Rename CN6

pin2,pin4 power net become
CONN 28PIN
1
EC148 0R2J-2-GP 1 BT_ACT_K# 31 "5V_USB2_S5".

SC220P50V2KX-3GP
CN3 5V_S0 5V_S5 3D3V_S5
13 BAW56PT-U

2
Q36 83.00056.E11 5V_USB2_S5
DY CN6
1 2N7002PT-U NP1
30 UIM_PWR UIM_PWR 1 2
2 3 2 -1:0921

S
LED_PWR# UIM_VPP

D
3 30 UIM_VPP 3 4
4 SC:08/09 Add 5 6 -1:0910
5 LED_BAT# EC148(78.22124.2FL) for EMI 30 UIM_CLK UIM_CLK 7 8 USB_PP2 21

1
6 LED_CHARGE# UIM_DATA 9 10 USB_PN2 21
request, deault is dummy. 30 UIM_DATA
7 -1:0910 11 12 UIM_RESET

G
UIM_RESET 30
8 LED_MASK# 34 13 14
9 LID_CLOSE# LID_CLOSE# 34 10 M_LUMA TV_LUMA 15 16
10 DRVIE_LED# 10 M_COMP TV_COMP 17 18 USB_PP3 21
11 WIFI_LED# D15 10 M_CRMA TV_CRMA 19 20 USB_PN3 21
1

12 BT_LED# DY 21 22
EC163 DRVIE_LED# 1 23 24
SC47P50V2JN-3GP

14 25 26 5V_USB2_S5
2

SC:08/11 Add EC163 on 3 SATA_LED# 20 32 SPDIF_D 27 28 3D3V_S0

MLX-CON12-11GP
"LID_CLOSE" for RF team NP2

1
20.K0227.012 Request. 2 BAS16-1-GP EC149 -1:08/31 Change CN6 pin26

SC220P50V2KX-3GP
Q37 from "5V_S5" to
DY ACES-CONN28A-1-GP

2
2N7002PT-U -3:0114 Change connector "5V_USB2_S5"
20.F1242.028
B for PSE requirment. B
3 2
S
D

SC:08/09 Add -1:08/29 Add U65 power switch to controll

EC149(78.22124.2FL) for EMI "5V_USB2_S5".
1

Q8
request, deault is dummy.
C LED_PWR# LED_MASK#
G

B R1
34 PWRLED 5V_S5 5V_USB2_S5
E
R2 D14
PDTC124EU-1-GP 2 WLAN_LED 29 U65 at least 80 mil
WIFI_LED# 3
WLAN_LED_TEST 34 at least 80 mil 1 GND OC1# 8 USB_OC#2 21
1 2 IN OUT1 7
Q7 3 6
LED_BAT# BAW56PT-U EN1# OUT2
C DY 4 5
B

EN2# OC2# USB_OC#3 21

1
B R1 83.00056.E11 EC128
34 BATFULL_LED Q5 TC8
E

SCD1U50V3ZY-GP
R1

ST100U6D3VBM-9GP
R2 TPS2062D-GP

2
R2

PDTC124EU-1-GP
PDTC124EU-1-GP

Q6 SC:08/09 Add
E
C

C LED_CHARGE# EC150(78.22124.2FL) for EMI

B R1
34 CHARGE_LED request, deault is dummy.
1

E EC150
34,38 USB_PWR_EN#
SC220P50V2KX-3GP

R2
PDTC124EU-1-GP DY
2

A <Core Design> A
LED_PWR# LED_BAT# LED_CHARGE# WIFI_LED#

5V_S5 5V_S0 3D3V_S0

Wistron Corporation
1

EC29 EC31 EC30 EC27 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

C165 C163 C166 Taipei Hsien 221, Taiwan, R.O.C.

DY DY DY DY
2

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

Title
2

FWH and Board to Board CONN

Size Document Number Rev
A3
DS2-Intel -3
Date: Wednesday, January 23, 2008 Sheet 35 of 47
5 4 3 2 1
 5 4 3 2 1

D D

FAN1_VCC
5V_S0 -1:0920
*Layout* 15 mil

1
3
C346 C8 R187
SCD1U16V2ZY-2GP SC10U10V5ZY-1GP D24 10KR2J-3-GP FAN1_VCC

2
BAS16-1-GP FAN1
4

2
1

2
FAN1_FG1 3
3D3V_S0 RN20 2
4 1 G792_SCL *Layout* 15 mil
3 2 G792_SDA 1

1
SRN10KJ-5-GP C337
SC1KP50V2KX-1GP 5

2
SC:08/10 Change C337 MLX-CON3-6-GP-U
from 78.10234.1BL to
-1:1214 78.10224.2FL
5V_S0 U19
*Layout* 30 mil
R308
C 1 2 5V_G792_S0 6 1 C
VCC FAN1
5V_S0 20 DVCC FG1 4
10R2J-2-GP 3D3V_AUX_S5 14
CLK G792_CLK 21
1

1
SA:4/28 16 G792_SDA
SDA G792_SDA 34
1

1
R305 C479 C473 7 18 G792_SCL
30KR2F-GP SCD1U16V2ZY-2GP DXP1 SCL G792_SCL 34
C486 R310 9 19

2
SCD1U50V3ZY-GP SC4D7U6D3V5KX-3GP 100KR2J-1-GP DXP2 NC#19
11
2

DXP3
-1:0909
2

DY 5 H_THERMDA 5

2
DGND

1
21 THRM# R83 1 2 0R2J-2-GP THRM#_R 15 17
ALERT# DGND C173
34,46 PURE_HW_SHUTDOWN# 13 THERM#
V_DEGREE SC2200P50V2KX-2GP
Setting T8 as 3 8 H_THERMDC 5

2
THERM_SET SGND1
2 RESET# SGND2 10
1

85 Degree SGND3 12 Place on reverse side of CPU

R301
47KR2F-GP
V_DEGREE -3:0121 G792SFUF-GP G792_DXP2
=(((Degree-72)*0.02)+0.34)*VCC

C
2

1
C178 B Q25
SC2200P50V2KX-2GP CH3904PT-GP

2
PM_SLP_S3# 21,28,34,43,45,46

E
3D3V_S5 U69 G792_DXN2

2
5 1 G51
R300 VCC A G792_RESET#
B 2
8,21 PM_PWROK 1 2 PWROK 4 3 Place G14 near U36 Place near G792 chip as close
Y GND 1
as possible
33R2J-2-GP R298 GAP-CLOSE

1
B 100KR2J-1-GP B
74AHCT1G08DCKR-1GP

Place near CPU and NB (Orignal Q25

2

G792_DXP3 location)
DXP1:108 Degree

C
DXP2:H/W Setting (85 Degree)

1
B Q33
DXP3:88 Degree C177 CH3904PT-GP
SC2200P50V2KX-2GP

E
2
G792_DXN3

2
G64

Place G15 near U36

GAP-CLOSE

1
A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal/Fan Controllor G792

Size Document Number Rev
A3
DS2-Intel -3
Date: Wednesday, January 23, 2008 Sheet 36 of 47
5 4 3 2 1
 5 4 3 2 1

SB:06/27 Change K/B connector from 20.F0694.025

to 20.K0291.027 .
TouchPad Connector
5V_S0
KB1 KROW[0..7] 34
29
1 KCOL10 5V_S0

1
2 KCOL11 KCOL[0..16] 34
3 KCOL9 C148 C135
4 KCOL14 SCD1U16V2ZY-2GP SC1U10V3ZY-6GP

2
5 KCOL13

2
1
D 6 KCOL15 D
7 KCOL16 RN22
8 KCOL12 SRN10KJ-5-GP
9 KCOL0 Internal KeyBoard Connector SB:06/13 TPAD1
10 KCOL2 5
11 KCOL1 1

3
4
12 KCOL3
13 KCOL8 34 TPCLK 2
14 KCOL6 34 TPDATA 3
15 KCOL7 4
16 KCOL4 6

1
1
17 KCOL5 C187 C188
18 KROW0 SC33P50V2JN-3GP SC33P50V2JN-3GP
19 KROW3 FOX-CON4-12-GP

2
2
20 KROW1
21 KROW5
22 KROW2
23 KROW4
24 KROW6 SA: 04/15 change TPAD conn to 20.K0179.004
25 KROW7
26
27 KB_DET# 34
28

JAE-CON27-GP

-1:12/14 Chage R191 from 0

C
ohm to 0.5A fuse to prevent CAPACITY BUTTON C
VCC short to GND.
for EMI DY
3D3V_S0 R190 1 2 0R3-0-U-GP
CN1
KCOL3 KCOL11 KROW3 KCOL16 7
KCOL2 KCOL10 KROW2 5V_S0 R191 1 2 FUSE-D5A32V-5-GP 1
KCOL1 KCOL9 KROW1 -1:09/02 Change CN1(Capacity
EC72

EC84

EC73

EC85

EC90

EC91

EC89

EC80

EC78

EC75

EC77

EC68

KCOL0 KCOL8 KROW0 EC86 2

CAP_SCL 3 button) pin2 from GND to NC
34 CAP_SCL
CAP_SDA 4
34 CAP_SDA
1

5
34 CAPA_INT# 6
8
2

2
SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

MLX-CON6-11-GP
20.K0227.006
CAP_SCL

CAP_SDA

Main Source:20.K0227.006

1
KCOL7 KCOL15 KROW7 2nd Source: 20.K0228.006
KCOL6 KCOL14 KROW6 EC158 EC159

SC220P50V2KX-3GP

SC220P50V2KX-3GP
KCOL5 KCOL13 KROW5

2
KCOL4 KCOL12 KROW4
EC71

EC79

EC69

EC70

EC87

EC82

EC88

EC81

EC65

EC66

EC76

EC67

DY DY
B B
SC:08/09 Add
1

EC158,EC159(78.22124.2FL)
for EMI request .Default is
2

DUMMY
SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

SC220P50V2KX-3GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

KeyBoard-CONN
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 37 of 47
5 4 3 2 1
 5 4 3 2 1

5V_S5 U66 5V_USB1_S5 5V_S5

at least 80 mil 1 GND OC1# 8 at least 80 mil

2 IN OUT1 7

1
3 EN1# OUT2 6
4 5 R221 D25
34,35 USB_PWR_EN# EN2# OC2#

1
DY DY 15KR2J-1-GP BAV99PT-GP-U

1
R222
DY

E
TPS2062D-GP TC6 EC176 10KR2J-3-GP 5V_S5 3D3V_S5

1
USB_OC#0 21 ST100U6D3VBM-9GP SCD1U16V2ZY-2GP CH3904PT-GP
B

3
Q21

2
USB_OC#1 21

1
C
D R206 D26 R225 D
PSID_DISABLE# 34
100KR2J-1-GP BAV99PT-GP-U 2K2R2J-2-GP

G
1

2
1

3
R220
-1:08/30 Add U66 power switch to PD_ID 3 2 1 2

D
ACDC_ID 34

S
control USB power
33R2J-2-GP
2N7002PT-U
Q20

R207
DY1 2
-1:0915
5V_USB1_S5 CN5 33R2J-2-GP
26 28
NP1 30
1 2

3 4
5 6 AD+_JK AD+

Left I/O Connector 7

9
8
10 1
U47
S
S
D
D
8 -1:0914
11 12 2 7

1
13 14 C3 3 S D 6
21 USB_PP0

1
15 16 SCD1U50V3KX-GP C7 R9 4 G D 5
21 USB_PN0

1
17 18 SC1U25V5KX-1GP 240KR3-GP C409 C410 C408 C398
DY

SC10U25V6KX-1GP
SCD01U50V2ZY-1GP

SCD01U50V2ZY-1GP

SCD01U50V2ZY-1GP
21 USB_PP1 19 20

2
C
21 USB_PN1 21 22 P2003EVG-GP C

2
23 24 Id=17A
NP2 29
25 27 This cap should be used Qg=100~150nC
CONN 24PIN(AC-In+USB) ACES-CONN24A-1-GP
only as last resort for Rdson=5.4~6.5mohm
EMI suppression. Q26
R2
E
B R1
C
Reserved for EMI

2
PDTA124EU-1-GP
Q27 R260
AD+_JK 3 OUT
DY 47KR3J-L-GP
1 R1
-1:0914 34 AD_OFF
IN 2 GND

1
1

R2
C4
SCD01U50V2ZY-1GP DDTC124EUA-7F-GP
2

Place near DCIN1 DY

Left I/O Board to Board CONN 3D3V_AUX_S5

D23
B B
2
BAT_SCL 3

Batt Connecter BAV99PT-GP-U

-1:0920 D1
2
BATT1
BAT_SDA 3
GND 11 SB:07/09 Change R21 from 100K to 470K for
GND 10 power team request 1
GND2 9
GND1 8 BAV99PT-GP-U
7 PBAT_ALARM#
BAT_ALERT TP17
6 R21 1 2 470KR2J-2-GP 3D3V_AUX_S5
SYS_PRES# D6
5 PBAT_PRES1# R22 1 2 100R2J-2-GP RN1 BAT_IN# 34
BATT_PRS# PBAT_SMBDAT1
DAT_SMB 4 1 4 BAT_SDA 18,34,39 2
3 PBAT_SMBCLK1 2 3 BAT_SCL 18,34,39
CLK_SMB BAT_IN#
BATT2+ 2 3
1 SRN100J-3-GP BT+
BATT1+
1
R1 2 1 0R0603-PAD BATT_SENSE 39
SYN-CON9-7-GP BAV99PT-GP-U

A D2 <Core Design> A
Battery CONN. Main source:20.80953.009
2
2nd source:20.80626.009 Wistron Corporation
1

C2 C1 PBAT_ALARM# 3
SCD1U50V3KX-GP SC2200P50V2KX-2GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1 Taipei Hsien 221, Taiwan, R.O.C.
2

Title
BAV99PT-GP-U
AD/BATT CONN
Size Document Number Rev
A3 -3
DS2-Intel
Date: Monday, January 21, 2008 Sheet 38 of 47
5 4 3 2 1
 5 4 3 2 1

MAX8731_LDO SB:06/29 Add

EC130,EC131,EC132,EC133(78.10494.4BL)
for "BT+" by EMI request

1
R44 BT+
10KR2F-2-GP

2
ACAV_IN

1
1 EC130 EC131 EC132 EC133
R45

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP
D D

2
15K4R2F-GP
2

5V_AUX_S5 NEAR
1
R48
100KR2J-1-GP

Adaptor In Soft-Start Circuit

2

AC_IN#
34 AC_IN#
AD+ Layout Trace 250mil
1

C68 U48 Layout Trace 300mil

SC1U10V3KX-3GP D S AD+_TO_SYS DCBATOUT BT+
D
8
D S
1 Layout Trace 300mil
7 2 U5
2

6 D S 3 1 2 1 S D 8
3

5 D G 4 R229 2 S D 7
Q23 D01R2512F-4-GP 3 S D 6
2

2N7002PT-U AD+ 4 G D 5
1 ACAV_IN R240 P2003EVG-GP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
G 10KR2J-3-GP 2nd:A04433(84.04433.A37)
P2003EVG-GP
2

1
1

C S DC_IN_D R18 2nd:A04433(84.04433.A37) C

D 470KR2J-2-GP

G49

G50
1

1
3

DCIN_GATE1 1 2 DCIN_GATE2 1 2
NEAR INPUT AD+

2
Q22 D R241 49K9R2F-L-GP R231 100KR2J-1-GP
2N7002PT-U
3

1
G Q24
2N7002PT-U
2

1
AD+ ACAV_IN 1 C378 C379
S G
SCD1U25V3KX-GP
2

2
MAX8731_CSSN
MAX8731_CSSP
SCD1U25V3KX-GP
S
1 2
R41 0R2J-2-GP CHG_AGNDCHG_AGND CHG_AGND
1

SC10U25V0KX-3GP

SC10U25V0KX-3GP
R40 C43 U46 C380

SCD1U25V3KX-GP
SC1U25V5KX-1GP SC1U10V3KX-3GP
2

C375

C373

C32
365KR3F-GP
ASNS

1
MAX8731_DCIN 22 28 R223
2

DCIN CSSP

5
6
7
8
MAX8731_ACIN 33R2J-2-GP

D
D
D
D
2
NEAR KBC POWER

2
ACIN CHG_AGND
27 DY
SCD01U50V2ZY-1GP

2
CSSN
1

R226 3D3V_AUX_S5 11 26 MAX8731_VCC U8

VDD VCC
1

R42 SI4800BDY-T1
1

0R3-0-U-GP
49K9R2F-L-GP C390 SCD1U25V3KX-GP 25 MAX8731_BST 1 2MAX8731_BST1 1 2 1 2
2

G
S
S
S
BST MAX8731_LDO D8 C48
21
2

4
3
2
1
B LDO B
C383

ACAV_IN 13 1SS400PT SC1U10V3KX-3GP

ACOK
2nd:FDS8884(84.8884.A37) BT+
CHG_AGND 24 MAX8731_DHI
CHG_AGND BAT_SCL DHI R224 CHG_PWR
18,34,38 BAT_SCL 10 SCL L14
1R3F-GP 1 2 Layout Trace 300mil
23 MAX8731_LX 1 2 C42 MAX8731_LX1 1 2 1 2
LX SCD1U25V3KX-GP R204
1 2

SC10U25V0KX-3GP

SC10U25V0KX-3GP

SC10U25V6KX-1GP
BAT_SDA 9 C381 SC220P50V2JN-3GP IND-5D8UH-GP D01R2512F-4-GP
18,34,38 BAT_SDA SDA

C13
20 MAX8731_DLO 68.5R850.101
DLO

5
6
7
8

C336

C335
1

1
D
D
D
D

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
14 BATSEL PGND 19

2
2

2
18 MAX8731_CSIP U7
CHG_AGND CSIP SI4800BDY-T1
17 MAX8731_CSIN DY

G
S
S
S
CSIN

G46

G45
8

4
3
2
1

1
34 AD_IA INP

2nd:FDS8884(84.8884.A37)
1 2 MAX8731_CCV 6 CCV
1MAX8731_CCV1

R227 4K7R2F-GP MAX8731_CCI 5 16

MAX8731_CCS CCI FBSB
4
SCD1U16V2ZY-2GP

CCS
1

MAX8731_REF 3
R230 MAX8731_DAC 7 REF
DAC
1

C393

12 15 BAT_SENSE 1 2 BATT_SENSE
SCD01U50V2ZY-1GP

SCD01U50V2ZY-1GP

SCD01U50V2ZY-1GP

SCD1U16V2ZY-2GP

GND

GND FBSA BATT_SENSE 38

SC1U10V3KX-3GP

10KR2F-2-GP R228 100R2F-L1-GP-U

1

A <Core Design> A
2

1
C387

C385

C384

C49

C389

MAX8731AETI-GP C386
29

74.08731.A73 SCD01U50V2ZY-1GP
2

Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1 2 Taipei Hsien 221, Taiwan, R.O.C.
G48
GAP-CLOSE-PWR Title
CHG_AGND
CHARGER MAX8731
Size Document Number Rev
A3 -3
DS2-Intel
Date: Monday, January 21, 2008 Sheet 39 of 47
5 4 3 2 1
 5 4 3 2 1

DCBATOUT_TPS51120

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
Iout =6A

1
C223

C556

C225
DY

1
DCBATOUT DCBATOUT_TPS51120 5V_AUX_S5 +VCC_TPS51120
G38 C559
OCP < 12A

2
5
6
7
8
1 2 SC2200P50V2KX-2GP +5V_ALWP 5V_S5

2
G28

D
D
D
D
1 2
G33 GAP-CLOSE-PWR R402 5D1R3J-GP 1 2

1
1 2 SA:04/23 Change C746 to DUMMY
C585 for power team request G30 GAP-CLOSE-PWR
G34 GAP-CLOSE-PWR SC1U10V3KX-3GP SI4800BDY-T1
D 1 2 D

2
1 2 U28

G
S
S
S
G31 GAP-CLOSE-PWR

4
3
2
1
G35 GAP-CLOSE-PWR DCBATOUT_TPS51120 +5V_ALWP 1 2
1 2 51120_LL2 1 2 51120_VBST2_11 2 51120_VBST2 51120_DRVH1 L6
C594 R410 0R3-0-U-GP 51120_LL1 1 2 G32 GAP-CLOSE-PWR
G37 GAP-CLOSE-PWR SCD1U50V3KX-GP IND-3D3UH-57GP 1 2

SC18P50V2JN-1-GP
1
1 2

5
6
7
8

SCD1U10V2KX-4GP
C577 R384 G27 GAP-CLOSE-PWR

D
D
D
D
G36 GAP-CLOSE-PWR 51120_LL1 1 2 51120_VBST1_11 2 51120_VBST1 SCD1U50V3KX-GP U26 R392 1 2

1
TC4

C218
1 2 C569 R388 0R3-0-U-GP AO4712-GP 2D2R5F-2-GP
SCD1U50V3KX-GP 30KR3F-GP ST220U6D3VDM-20GP G29 GAP-CLOSE-PWR

C581
SC10U10V5KX-2GP
GAP-CLOSE-PWR DY 1 2

2
+VCC_TPS51120 51120_VFB1
3D3V_AUX_S5

G
S
S
S
GAP-CLOSE-PWR

1
C250
C249

4
3
2
1

1
SC10U10V5KX-2GP C570 R391
DY

2
SC:08/13 Change R129 from 7K5R2F-1-GP

2
U56 3D3V_S0 51120_DRVL1 SC330P50V3KX-GP

19
21

28
13

20
22
63.R0034.1DL to

2
7
2
DY R133 TPS51120RHBR-GPU1
ZZ.R0402.ZZZ

VREG3
VREG5

VBST1
VBST2

V5FILT

COMP2
COMP1
VIN
51120_GND
21,28,34,44,45 PM_SLP_S4# 1 2
0R2J-2-GP
Iout = 5A

1
R129
51120_EN1 51120_LL2 R143 DCBATOUT_TPS51120
OCP < 10A
1 2 29 EN1 LL2 15
0R0402-PAD 12 26 51120_LL1 100KR2J-1-GP +3.3V_ALWP 3D3V_S5
46 3V/5V_EN EN2 LL1

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP
10 EN3
9 G39

2
EN5

C582

C252
C C
PGOOD1 30 DY 1 2

1
C257
R138 1 2 0R2J-2-GP 51120_VFB2 6 11
R136 1
DY 2 0R2J-2-GP 51120_VFB1 3
VFB2 PGOOD2 CPUCORE_ON 41,43,44,45 C587 G44 GAP-CLOSE-PWR
+VCC_TPS51120 DY VFB1

5
6
7
8
25 51120_DRVL1 SC2200P50V2KX-2GP 1 2

2
+5V_ALWP DRVL1 51120_DRVL2

D
D
D
D
1 VO1 DRVL2 16
+3.3V_ALWP 8 G42 GAP-CLOSE-PWR
VO2 51120_DRVH1
DRVH1 27 1 2
51120_VREF2 4 14 51120_DRVH2 SA:04/23 Change C733 to DUMMY
VREF2 DRVH2 SI4800BDY-T1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

G41 GAP-CLOSE-PWR
DY DY for power team request

SKIPSEL
TONSEL
U29
PGND1
PGND2
1 2

G
S
S
S
1

1
C237

C245

GND
GND

4
3
2
1
CS1
CS2
C243 SC:08/13 Change R135 from +3.3V_ALWP G43 GAP-CLOSE-PWR
SC1KP50V2KX-1GP 63.R0034.1DL to 51120_DRVH2 L7 1 2
2

51120_LL2 1 2
24
17
5
33

23
18

32
31
ZZ.R0402.ZZZ

SCD1U10V2KX-4GP
IND-3D3UH-57GP G40 GAP-CLOSE-PWR

C248

C586
51120_GND 1 2

5
6
7
8

1
51120_SKIPSEL

1
D
D
D
D
TI suggest R<=15Kohm U32 R396 R404 GAP-CLOSE-PWR

1
+VCC_TPS51120 1 2 51120_TONSEL 1 2 51120_VREF2 AO4712-GP 30K9R3F-GP TC20

2
C572 SC1KP50V2KX-1GP R135 0R0402-PAD 2D2R5F-2-GP ST220U6D3VDM-20GP

2
51120_GND
DY

2
SC18P-GP
1 2 51120_CS1 1 2 +VCC_TPS51120 DY

2
G
S
S
S
R389 12K1R2F-L1-GP R390 0R2J-2-GP 51120_VFB2
1 2 51120_CS2 DY

4
3
2
1

1
R405 11K3R2F-2-GP 1 2 51120_GND

1
Q32 R134 0R2J-2-GP C575 R401
+VCC_TPS51120 NDS0610-NL-GP 51120_DRVL2 13K3R3F-GP
1
C591
2
SC1KP50V2KX-1GP R125
DY
DY

2
S D 1 2 1 2 51120_VREF2 SC330P50V3KX-GP
DY

2
B R132 0R2J-2-GP B
1 2
1

0R2J-2-GP G63
R381 DY 1
DY 2 +VCC_TPS51120 GAP-CLOSE-PWR 51120_GND
G

Q13 200KR2F-L-GP R131 0R2J-2-GP

2N7002PT-U
DY DY 51120_GND
1 2 51120_GND
2

R130 0R0402-PAD
S

2 3
D

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

51120_GND SC:08/13 Change R130 from Inductor: 3.3UH CYNTEC 11Arms 14.5Apeak
1

63.R0034.1DL to O/P cap: 220U6.3V 6TPE220M 25mOhm 2.4Arms/ 77.22271.17L

R126
G

TPAD30 TP76 RUN_ON ZZ.R0402.ZZZ H/S: AO4468 SO-8/ 30mOhm/ 4.5Vgs

1 2
DY 0R2J-2-GP L/S: AO4712 SO-8/ 7.3mOhm/ 4.5Vgs

Vout=1V*(R1+R2)/R2
GND VREF2 FLOAT V5FILT
AUTOSKIP
SKIPSEL AUTOSKIP /FAULTS PWM PWM
A A
OFF <Core Design>
COMP N/A N/A CURRENT D-Cap
MODE MODE
TONSEL 380k/CH1 280k/CH1 220k/CH1 180k/CH1 Wistron Corporation
580k/CH2 430k/CH2 330k/CH2 2870k/CH2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VFB1 N/A not use ADJ. 5V Taipei Hsien 221, Taiwan, R.O.C.
Fixed Output
VFB2 N/A not use ADJ. 3.3V Title
Fixed Output
EN1,EN2 Switcher OFF not use Swithchr ON Switcher ON DC to DC 3.3V & 5V
EN3,EN5 LDO OFF not use LDO ON VREG3 on Size Document Number Rev
A3 -3
DS2-Intel
Date: Monday, January 21, 2008 Sheet 40 of 47
5 4 3 2 1
 5 4 3 2 1

5V_S0 DCBATOUT 3D3V_S0

1
R25 R30 R202

1
10R3J-3-GP
SCD01U25V2KX-3GP
10R3J-3-GP 10R3J-3-GP

1
SB:06/17 Remove R205,C348,TP86 R203

2
power monitor circuit. 1K91R2F-1-GP

1
-1:0914 C366 6262_3V3

6262_VIN

2
2
VGATE_PWRGD 8,21

2
C9
D SCD01U25V2KX-3GP D

1
6262_AGND -1:0914
6262_VCC
6262_AGND

1
C367

22

20

48

1
SC1U10V3KX-3GP

3V3
VDD

VIN

PGOOD
6262_UGATE1 42

21 GND UGATE1 35 1 2
R200 0R3-0-U-GP
6262_AGND 49 36 6262_BOOT1 1 C345
GND_T BOOT1
SCD22U25V3KX-GP
2
1 2 6262_PSI# 2 34 6262_PHASE1 42
6 PSI# PSI# PHASE1
R12 0R0402-PAD 6262_PMON 3
TPAD30 TP86 6262_RBIAS PMON 6262_LGATE1 42 3K65R3F-GP
Place close to phase 1 chocke 6262_AGND 1
R15
2
147KR2F-GP
4
5
RBIAS LGATE1 32
6262_VSUM 1 R26 2
5 CPU_PROCHOT# VR_TT#
2 1 1 R184 2 6262_NTC 6 NTC PGND1 33
R185 NTC-470K-1-GP 6262_AGND 1 2 6262_SOFT 7 R24
4K02R3F-GP C19 SCD015U25V3KX-GP SOFT 6262_ISEN1
ISEN1 24 1 2 6262_ISENP1 42

1
6262_AGND C11 1 2 SCD01U16V2KX-3GP 6262_VID0 37 5V_S0
6262_VID1 VID0 C362 10KR3F-L-GP
38 VID1
470K /0402 size SB:06/17 Change R12,R16,R17 R198 from 0402 0 6262_VID2 39 31 SCD22U10V3KX-2GP

2
6262_VID3 VID2 PVCC
Ohm to 0402 close pad. 40 VID3 1 2 1 2 6262_ISENN1 42
6262_VID4 C350 SC4D7U6D3V3KX-GP R34 1R3F-GP
If NTC=330Kohm, R10=8.66K 6262_VID5
41
42
VID4
27 R35
C 6262_VID6 VID5 UGATE2 6262_UGATE2 42 6262_ISEN2 C
43 VID6 1 2
R198 1 2 CPUVCORE_ON_R 44 26 6262_BOOT2 1 2
40,43,44,45 CPUCORE_ON VR_ON BOOT2
0R0402-PAD R210 0R3-0-U-GP 1 C356 10KR3F-L-GP
1 2 6262_DPRSLP 45 SCD22U25V3KX-GP
8,21 DPRSLPVR DPRSLPVR
R16 0R0402-PAD 46 2 R219 3K65R3F-GP
DPRSTP# 6262_PHASE2 42
6,8,20 H_DPRSTP# 1 2 6262_DPRSTP# 47 CLK_EN# PHASE2 28 6262_VSUM 1 2
R17 0R0402-PAD 30 6262_LGATE2 42
CPU_VID3 6262_VID3 LGATE2 R217
4 5 21 CLK_EN# PGND2 29
CPU_VID2 3 6 6262_VID2 13 23 6262_ISEN2 1 2
VDIFF ISEN2 6262_ISENP2 42
CPU_VID1 2 7 6262_VID1 R211 SB:06/22 Change R20 from
CPU_VID0 1 8 6262_VID0 1 2 6262_VDIFF ISL6262ACRZ-T-GP-U 64.12725.6DL to 10KR3F-L-GP

1
1KR2F-3-GP 6262_FB212
6 CPU_VID[0..6] SRN0J-5-GP FB2 64.11325.6DL
C360 25 6262_AGND C370
RN4 U43 NC#25 R20
SRN0J-6-GP 2 1 1 2 6262_FB 11 R216

2
FB

SCD22U10V3KX-2GP
RN5 R212 8 6262_OCSET 1 2 1 2
OCSET8 6262_ISENN2 42
CPU_VID4 1 4 6262_VID4 255R2F-L-GP SC1KP50V2KX-1GP 1R3F-GP
CPU_VID5 2 3 6262_VID5 R213 10 19 6262_VSUM 11K3R2F-2-GP R214
COMP VSUM 6262_ISEN1
1 2 1 2

1
CPU_VID6 1 2 6262_VID6 1KR2F-3-GP

1
R197 0R2J-2-GP 9 18 6262_VO R218 10KR3F-L-GP
VW VO

1
2K61R3F-GP

DROOP
1 R208 2 1 2 C368 R215

VSEN
97K6R2F-GP SC470P50V2KX-3GP C372 11KR2F-L-GP

RTN

DFB

SCD22U10V2KX-1GP
C351 C357 SCD068U10V2KX-1GP

1 2
1 2 6262_COMP

2
15

14

16

17
SC220P50V2KX-3GP 1 2 R183
R209 6K81R2F-1-GP NTC-10K-9-GP

6262_VSEN
C355

6262_DROOP
6262_RTN

6262_DFB
1 2 6262_VW

2
B B
SC:08/13 Change R28 from SB:06/23 Change C372 from
63.00000.00L to ZZ.R0603.ZZZ SC1KP50V2KX-1GP 78.47323.2FL to 78.68323.5FL

1 2
Place close to phase 1 chocke
6 VSS_SENSE
R28 0R0603-PAD
1

1
C363 R33 C365
SCD01U25V2KX-3GP 1KR3F-GP SCD22U10V2KX-1GP
2

2
6 VCC_SENSE 1 2

2
R27 0R0603-PAD R29
1 2 6262_AGND
1

C364 -1:0914 SB:06/23 Change R29 from 64.32415.55L

SC:08/13 Change R27 from C369 3K6R2F-GP to 64.36015.6DL
SCD01U25V2KX-3GP

63.00000.00L to ZZ.R0603.ZZZ SCD01U25V2KX-3GP G47

2

1 2 6262_VO 1 2
-1:0914 C28 SC180P50V2JN-1GP GAP-CLOSE-PWR
When test without cpu, 6262_AGND
R483 & R486 change to 0 ohms
6262_AGND 6262_AGND

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DC-DC VCCCPUCORE 1/2

Size Document Number Rev
A3 -3
DS2-Intel
Date: Monday, January 21, 2008 Sheet 41 of 47
5 4 3 2 1
 5 4 3 2 1

DCBATOUT
DCBATOUT SC:08/09 Add EC146,EC147 (78.10492.4BL) for EMI request .
Please place EC146 near C352, EC147 near U1

1
EC120 EC121 EC122 EC123 EC124 EC125 EC126 EC127

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP
SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP
DY

2
1

1
EC147 EC146 C353 C22 C352 C21 TC7

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SE100U25VM-14GP
SCD1U50V3ZY-GP

SCD1U50V3ZY-GP
2

2
SCD1U25V3KX-GP
5
6
7
8

5
6
7
8
D D

D
D
D
D

D
D
D
D
U2 U41
POWERPAK-8P-GP POWERPAK-8P-GP
SB:06/26 Add
EC120~EC127(78.10494.4BL),total 8
Id=13A DY Panasonic ETQP4LR36WFC pcs CAP for EMI team request.

G
S
S
S

G
S
S
S
Qg=10~14nC 10*11.5*4mm Iomax=47A

4
3
2
1

4
3
2
1
Rdson=9.4~12mohm 0.34uH / 24A
VCC_CORE_S0
DCR=1.1mohm
41 6262_UGATE1 L13

41 6262_PHASE1 1 2
IND-D36UH-9-GP
41 6262_LGATE1
-1:0912 -1:0912 DY

1
R8 TC12 TC10 TC9 TC1 C40

ST330U2D5VDM-9GP

ST330U2D5VDM-9GP

ST330U2D5VDM-9GP

ST330U2D5VDM-9GP
2D2R5F-2-GP SCD1U50V3ZY-GP
DY

2
5
6
7
8

5
6
7
8

2
D
D
D
D

D
D
D
D
U40 U1 G2 G1

2
POWERPAK-8P-1-GP POWERPAK-8P-1-GP
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP

1
Id=14.5A

1
Qg=25~35nC
G
S
S
S

G
S
S
S
DY C6
SC330P50V3KX-GP 6262_ISENN1 41
Rdson=5.9~7.25mohm
4
3
2
1

4
3
2
1

2
C 6262_ISENP1 41 C
PANASONIC
330uF / 2V / V size
ESR=6mohm / Iripple=3.7A

DCBATOUT

1
C340 C343 C339 C344 C338

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U25V3KX-GP
2

2
5
6
7
8

5
6
7
8
DY
D
D
D
D

D
D
D
D
U4 U42
POWERPAK-8P-GP POWERPAK-8P-GP

Id=13A
Qg=10~14nC DY
G
S
S
S

G
S
S
S

Rdson=9.4~12mohm Panasonic ETQP4LR36WFC

4
3
2
1

4
3
2
1

10*11.5*4mm
0.34uH / 24A
41 6262_UGATE2 L15 DCR=1.1mohm
B B
41 6262_PHASE2 1 2
IND-D36UH-9-GP
41 6262_LGATE2
-1:0912 -1:0912 DY
1

1
R31 TC11 TC2

ST330U2D5VDM-9GP

ST330U2D5VDM-9GP
2D2R5F-2-GP
DY

2
5
6
7
8

5
6
7
8

2
D
D
D
D

D
D
D
D

Id=14.5A U44 U6 G4 G3
2

Qg=25~35nC POWERPAK-8P-1-GP POWERPAK-8P-1-GP

GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
1

1
1

Rdson=5.9~7.25mohm
DY C31
SC330P50V3KX-GP
G
S
S
S

G
S
S
S

2
4
3
2
1

4
3
2
1

SA: 04/11 Add depend on PW team

If VCC_SENSE and VSS_SENSE pins have pulled

41 6262_ISENP2 resistors to VCC_CORE_S0
41 6262_ISENN2 ==> Remove R44/R45/R46/R47.

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DC-DC VCCCPUCORE 2/2

Size Document Number Rev
A3 -3
DS2-Intel
Date: Monday, January 21, 2008 Sheet 42 of 47
5 4 3 2 1
 5 4 3 2 1

DCBATOUT +1.05V_PWR_SRC

G23
1 2

GAP-CLOSE-PWR
G22
1 2
Iout = 10A
D
GAP-CLOSE-PWR
OCP>20A D

G21
1 2
+1.05V_SUSP 1D05V_S0
GAP-CLOSE-PWR G58
G20 1 2
1 2
+1.05V_PWR_SRC GAP-CLOSE-PWR
GAP-CLOSE-PWR G59
5V_S5 G25 1 2
1 2

2
GAP-CLOSE-PWR

1
GAP-CLOSE-PWR C146 C147 C461 C460 G57
G24 SC10U25V6KX-1GP SCD1U50V3KX-GP DY SC2200P50V2KX-2GP SC10U25V6KX-1GP 1 2

1
1

1 2

2
R293 GAP-CLOSE-PWR

5
6
7
8
3D3R3J-L-GP GAP-CLOSE-PWR G61
1

D
D
D
D
1 2
C159 U15
2

SC1U10V3KX-3GP +1.05V_V5FILT GAP-CLOSE-PWR

2

SI4800BDY-T1 Cyntec 10*10 G60

1

5V_S5 1 2
C138 2 1 +1.05V__LL1 2 1 SB: 06/27 Change U15 from Irating=14A, Isat=16A

G
S
S
S
SC1U10V3KX-3GP R289 0R3-0-U-GP C463 SCD1U16V2KX-3GP DCR=7mohm GAP-CLOSE-PWR
84.08880.037 to
2

4
3
2
1
1

G53
D10 84.04800.D37 SB: 06/27 Change L22 1 2
CH551H-30PT-GP U17 from 68.2R210.20C to
4 13 +1.05V_DRVH +1.05V_SUSP GAP-CLOSE-PWR
C V5FILT DRVH L22 84.04800.D37 G54 C
10
2

V5DRV +1.05V_LL
LL 12 1 2 1 2

SCD1U10V2KX-4GP
+1.05V_VBST 14

SC18P50V2JN-1-GP
VBST

C448
+1.05V_VFB 5 9 +1.05V_DRVL COIL-2D2UH-11-GP GAP-CLOSE-PWR
VFB DRVL

1
C467
3 +1.05V_SUSP R290 G52
VOUT

5
6
7
8

1
1 2 +1.05V_EN 1 6 1.05V_SUS_PWRGD R302 12KR2F-L-GP 1 2
21,28,34,36,45,46 PM_SLP_S3# EN_PSV PGOOD CPUCORE_ON 40,41,44,45 DY

D
D
D
D
R284 0R0402-PAD U18 TC16

2
+1.05V_TON SE220U2D5VDM-6GP
2 1 2 7 DY R78 AO4712-GP 2D2R5F-2-GP GAP-CLOSE-PWR

2
R286 200KR2J-L1-GP +1.05V_TRIP 11 TON GND +1.05V_VFB G56
TRIP PGND 8 1 2 3D3V_S0
100KR2J-1-GP SB: 06/27 Change U18 from DY 1 2

2
TPS51117PWR-GP 84.06676.A37 to
1

1
G
S
S
S
SB:06/17 Change R284 GAP-CLOSE-PWR
R76 84.04800.D37 R296 G55
from 0402 1K Ohm to

4
3
2
1

1
17K4R3F-GP C475 30KR2F-GP 1 2
0402 close pad. SB:06/22 Change R76 from DY GAP-CLOSE-PWR
64.12125.55L to 64.17425.55L
2

2
SC330P50V3KX-GP
Vout=0.75V*(R1+R2)/R2

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 1.5UH M MPL73-1R5 Delta 9Arms 18Apeak / 68.1R510.10I
O/P cap: 220U 4V 4TPE220MF 15mOhm 3.1Arms/ 77.22271.161
H/S & L/S: FDS8884 SO-8/ 30mOhm/ 4.5Vgs/ 84.08884.037
L/S: FDS8896 SO-8/ 7.3mOhm/ 4.5Vgs/ 84.08896.037
B B
Ton = 200KOhm --> 330KHz

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DCDC 1.05V
Size Document Number Rev
A3 -3
DS2-Intel
Date: Monday, January 21, 2008 Sheet 43 of 47
5 4 3 2 1
 5 4 3 2 1

DCBATOUT +1.8V_PWR_SRC

G13
1 2
Iout=7A
GAP-CLOSE-PWR
OCP<14A
G12
1 2 +1.8V_SUSP 1D8V_S3
G18
GAP-CLOSE-PWR 1 2
G11
1 2 GAP-CLOSE-PWR
D
+1.8V_PWR_SRC G14 D
GAP-CLOSE-PWR 1 2
G10
5V_S5 1 2 GAP-CLOSE-PWR
G17

2
GAP-CLOSE-PWR 1 2

1
G65 C59 C65 DY C418 C420
1 2 SC10U25V6KX-1GP SCD1U50V3KX-GP SC2200P50V2KX-2GP SC10U25V6KX-1GP GAP-CLOSE-PWR

1
1

G15

2
R244 GAP-CLOSE-PWR 1 2

5
6
7
8
3D3R3J-L-GP
1

D
D
D
D
U13 GAP-CLOSE-PWR
C52 FDS8880-NL-GP G19
2

SC1U10V3KX-3GP +1.8V_V5FILT 1 2
2

SB: 06/27 Change U13 from

1

5V_S5 84.04800.D37 to 84.08880.037 GAP-CLOSE-PWR

G
S
S
S
C53 2 1 +1.8V_LL1 2 1 G16
SC1U10V3KX-3GP R252 0R3-0-U-GP C405 SCD1U16V2KX-3GP Cyntec 10*10 1 2
2

4
3
2
1
1

D9 Irating=14A, Isat=16A GAP-CLOSE-PWR

CH551H-30PT-GP U10 DCR=7mohm G66
4 13 +1.8V_DRVH +1.8V_SUSP 1 2
V5FILT DRVH L18
10
2

V5DRV +1.8V_LL GAP-CLOSE-PWR

LL 12 1 2

SCD1U10V2KX-4GP
+1.8V_VBST IND-2D2UH-46-GP-U G67

SC33P50V2JN-3GP
14 VBST

C400

C431
+1.8V_VFB 5 9 +1.8V_DRVL 1 2
VFB DRVL

1
VOUT 3 +1.8V_SUSP

5
6
7
8

1
1 2 +1.8V_EN 1 6 R51 R242 TC3 GAP-CLOSE-PWR
21,28,34,40,45 PM_SLP_S4# EN_PSV PGOOD CPUCORE_ON 40,41,43,45

D
D
D
D
R253 0R0402-PAD U12 42K2R2F-L-GP SE220U2D5VDM-6GP

2
C 2 1 +1.8V_TON 2 TON 2D2R5F-2-GP C
GND 7 FDS6676AS-GP

2
R251 200KR2J-L1-GP +1.8V_TRIP 11 TRIP 8 +1.8V_VFB
SB:06/17 Change R253 PGND
from 0402 1K Ohm to 0402 close pad.

2
TPS51117PWR-GP
1

1
G
S
S
S
SB:06/17 Change R253
from 0402 1K Ohm to R243 SB: 06/27 Change U12 from R232

4
3
2
1

1
9K31R3F-GP C80 30KR2F-GP
0402 close pad. 84.04712.037 to 84.06676.A37
SB:06/22 Change R243 from
64.12125.55L to
2

2
SC330P50V3KX-GP
64.17425.55L Vout=0.75V*(R1+R2)/R2
SC:08/13 Change
R51(64.2R205.16L) and
C80(78.33124.2BL) from
No ASM to ASM

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 1.5UH M MPL73-1R5 Delta 9Arms 18Apeak / 68.1R510.10I
O/P cap: 220U 4V 4TPE220MF 15mOhm 3.1Arms/ 77.22271.161
H/S & L/S: FDS8884 SO-8/ 30mOhm/ 4.5Vgs/ 84.08884.037
L/S: FDS8896 SO-8/ 7.3mOhm/ 4.5Vgs/ 84.08896.037
Ton = 200KOhm --> 330KHz

B B

A <Variant Name> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DC/DC 1D8V
Size Document Number Rev
A3 -3
DS2-Intel
Date: Monday, January 21, 2008 Sheet 44 of 47
5 4 3 2 1
 5 4 3 2 1

5V_S0 1D8V_S3

1D5V_SB

1
C498 C500 C501
SC1U10V3ZY-6GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP

2
DY
D D
SB:06/17 Change R315 from 0402 0
Ohm to 0402 close pad. U53

6
1D5V/3A 2D5V/300mA

VCNTL
40,41,43,44 CPUCORE_ON 1 2 7 5 1D5V_S0 3D3V_S0 2D5V_S0
R315 0R0402-PAD POK VIN
VIN 9
U51
21,28,34,36,43,46 PM_SLP_S3# 8 EN VOUT 3
VOUT 4 VOUT 2
Vo=0.8*(1+(R1/R2)) DY 3 VIN

2
C502 1
GND

1
1KR2F-3-GP
2 R320 TC18 TC19 C465

GND
FB

ST100U4VBM-L1-GP
SCD01U16V2KX-3GP
ST100U4VBM-L1-GP C458 SC4D7U6D3V5KX-3GP

1
SCD1U10V2KX-4GP G9131-25T73UF-GP

2
APL5912-KAC-GP

2
SO-8-P -1:0909

1
R317

1K13R2F-1-GP

KEMET

2
100uF, 4V, B2 Size
Iripple=1.1A, ESR=70mohm

C C

SSID = PWR.Plane.Regulator_0.9V
1D8V_S3

G9
SC10U4V3MX-GP

TPS51100_LDOIN 1 2
SCD1U10V2KX-4GP
1

1
C55

C54

GAP-CLOSE-PWR 0.9 Volt +/- 5% 1D8V_S3 5V_S0

Design Current: 1.05A SA:04/23 Change TC24,TC33 P/N for
power team request.
2

Peak current 1.5A

1
SB:06/17 Change R256,R257 from 0402 0 DDR_VREF_S0 C145 C449 C450
G8 SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC1U10V3ZY-6GP 1D25V/2A
Ohm to 0402 close pad.

2
5V_S5 1 2 DY

9
B U14 1D25V_S0 B

10 1 +0.9V_P GAP-CLOSE-PWR

GND
DDR_ON_0.9V VIN VDDQSNS G6
21,28,34,40,44 PM_SLP_S4# 1 2 9 S5 VLDOIN 2 4 VDD NC#5 5
R257 0R0402-PAD 8 3 1 2 3 6
0.9V_DDR_VTT_ON_R GND VTT VIN VOUT
21,28,34,36,43,46 PM_SLP_S3# 1 2 7 S3 PGND 4 21,28,34,36,43,46 PM_SLP_S3# 2 EN ADJ 7 DY
SC10U4V3MX-GP

SC10U4V3MX-GP

R256 0R0402-PAD 6 5 GAP-CLOSE-PWR 1 2 1 8

VTTREF VTTSNS PGOOD GND

1
40,41,43,44 CPUCORE_ON
C412

C413

G7 R275 0R0402-PAD TC13 TC14

GND

DDR_VREF_S3 1 2 R270 C436

ST100U4VBM-L1-GP

ST100U4VBM-L1-GP
SCD01U16V2KX-3GP
U11 RT9018A-25PSP-GP 1K13R2F-1-GP

2
1

TPS51100DGQ-1-GP GAP-CLOSE-PWR SB:06/17 Change R275 from 0402 0 SO-8-P

11

C414 74.51110.B79 G5 Ohm to 0402 close pad.

2
SCD1U10V2KX-4GP 1 2 Vo=0.8*(1+(R1/R2))
2

1
GAP-CLOSE-PWR
R274
2KR2F-3-GP

2
KEMET
100uF, 4V, B2 Size
Iripple=1.1A,
ESR=70mohm

A <Variant Name> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DC/DC 1D8V
Size Document Number Rev
A3 -3
DS2-Intel
Date: Monday, January 21, 2008 Sheet 45 of 47
5 4 3 2 1
 5 4 3 2 1

D D

H_THERMTRIP# 5,8,20,34

DY

E
R328
1 2 H_PWRGD_R B
6,20 H_PWRGOOD 1KR2J-1-GP Q31

1
CHT2222APT-GP

C
DY C511
SCD1U10V2KX-4GP
DY

2
2
D27
BAS16-1-GP 3 PURE_HW_SHUTDOWN# 34,36

40 3V/5V_EN 1

1
1 2 S5_ENABLE 34

R325
200KR2J-L1-GP
R324 1KR2J-1-GP

2
C C

Run Power
-1:1114 The C207 change
5V_S0 5V_S5
from NO-ASM to 0.1uF/25V
for sniffer issue. U23
1 S D 8
C207 2 S D 7
1 2 3 S D 6
4 G D 5
DCBATOUT SCD1U25V3KX-GP
Q11 RUN_POWER_ON AO4468-GP
84.04468.037
1 2 Z_12V S D
R113 10KR2J-3-GP
K
1

NDS0610-NL-GP C206 R108

SCD01U50V3KX-4GP

100KR2J-1-GP

84.S0610.B31 R109 D17

G

B 10KR2J-3-GP 3D3V_S0 3D3V_S5 B

BZX384-C9V1-GP
2

83.9R103.B3F U30
2 1 Z_12V_G3 1 S D 8
A
2

R115 330KR2J-L1-GP 2 S D 7
1

3 S D 6
Z_12V_D4

R114 4 G D 5
-1:0909 100KR2J-1-GP
AO4468-GP
-1:1127 To change C206 84.04468.037
Z_12V_D3 2

D
from 0.1uF to 0.01uF for
S3 resume issue.
3

1D8V_S3 1D8V_S0
Q9
2N7002PT-U Q29
1
G
D -1:1127 To pop Q9 and R109 1 6
2

for power off sequence of

3

S
3D3V_S0/5V_S0.
2 5
Q10
1 2N7002PT-U R307
21,28,34,36,43,45 PM_SLP_S3#
G 1 2 3 4
2

10KR2J-3-GP
S FDC655BN-GP
1

SA:0329 Add for SiI1392 1.8V_S0

C483
A
SCD01U25V2KX-3GP <Core Design> A
2

DY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PWRPLANE&RESETLOGIC
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 46 of 47
5 4 3 2 1
 5 4 3 2 1
-1:0904 Add EC187(78.10422.2BL) for
DCBATOUT decoupling , this is for 1D05V_S0
3D3V_AUX_S5 3D3V_S5 5V_S5 AD+ DCBATOUT EMI request.
-1:0909
-1:0909 DY DY DY DY DY DY

1
DY DY DY DY DY DY DY DY DY DY DY DY DY DY EC64 EC93 EC74 EC102 EC106 EC99
1

1
EC56 EC10 EC94 EC118 EC162 EC108 EC107 EC112 EC105 EC138 EC139 EC140 EC164
EC58 EC57 EC39 EC26 EC1 EC187

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
SC47P50V2JN-3GP

SC47P50V2JN-3GP

SCD1U25V3KX-GP
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
2

2
D D

SC:08/11 Add EC162 on 3D3V_S5 SC:08/11 Add EC164 on 5V_S5 for RF

for RF team Request. team Request.

3D3V_S5 3D3V_S5 3D3V_S5 3D3V_S5 3D3V_S5 3D3V_S5

U33D U33C U33A U20D U20C U20B

14

14

14

14

14

14
12 9 1 12 9 4
11 8 3 11 8 6 DDR_VREF_S0 1D8V_S3
13 10 2 13 10 5
TSLVC08APW-1-GP TSLVC08APW-1-GP TSLVC08APW-1-GP DY DY DY DY DY DY DY DY DY DY DY
7

1
SSLVC08APWR-GP SSLVC08APWR-GP SSLVC08APWR-GP EC13 EC14 EC15 EC20 EC18 EC24 EC21 EC23 EC22 EC19 EC25
DY DY DY DY DY DY

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
5V_S0

C H1 H2 H3 H4 H5 H6 H7 H8 C

14

13
SB:06/29 Add
EC141,EC142,EC143(78.10491.4FL)
12 11 for EMI request
SB:06/22 Change EC1,EC5 from
1

1 U9D TSAHCT125PW-GP 5V_S0 5V_S0

DUMMY to ASM by EMI request.

7
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY

1
EC96 EC12 EC28 EC37 EC38 EC45 EC33 EC117 EC100 EC95 EC63 EC4
H9 H10 H11 H12 H13 H14 H15 H16 DY DY DY

1
EC141 EC142 EC143

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
1

DY DY DY DY DY DY DY DY

H17 H18 H19 H20 H21 H22 H23

3D3V_S0

B 3D3V_S0 B
DY DY DY DY DY DY DY DY DY DY

1
EC41 EC42 EC35 EC43 EC61 EC40 EC103 EC101 EC92 EC116 EC109 EC104
1

DY DY DY DY

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
1

1
EC134 EC135 EC136 EC137
DY SB:06/29 Add

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
EC134,EC135,EC136,EC137(78.10491.4FL)

2
for EMI request

Place this spring near

U40(bottom side) SC:08/15 Add EC177(78.10491.4FL) on 3D3V_S0
-1:0920 ,this is for EMI request. Default is DY
5V_AUX_S5 3D3V_S0

DY DY

1
K2 K5 K6 K7 EC113
SPRING-24-GP

SPRING-58-GP

SPRING-24-GP

SPRING-35-GP

EC177
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP
2

2
1

A <Core Design> A
DY
Wistron Corporation
SC:08/11 Change K7 from 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
34.39S07.001 to
34.41P18.001.This change is for Title
EMI request
-1:11/15 Remove K7 for no used. MISC
Size Document Number Rev
A3
DS2-Intel -3
Date: Monday, January 21, 2008 Sheet 47 of 47
5 4 3 2 1