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LD Answer

1. The circuit adds binary numbers bit-by-bit using a full adder circuit and D flip-flops to store the carry. (A) 2. The sum is shifted into register A while the bits in A are shifted out. This allows addition to be completed by passing each sum bit one at a time into register A. (B) 3. The document describes the operation of a 6-state binary counter that counts from 1 to 6 and then back from 6 to 1 repeatedly over time. The clock period is 100ns. (C)

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19 views

LD Answer

1. The circuit adds binary numbers bit-by-bit using a full adder circuit and D flip-flops to store the carry. (A) 2. The sum is shifted into register A while the bits in A are shifted out. This allows addition to be completed by passing each sum bit one at a time into register A. (B) 3. The document describes the operation of a 6-state binary counter that counts from 1 to 6 and then back from 6 to 1 repeatedly over time. The clock period is 100ns. (C)

Uploaded by

najmaprevia
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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it
b the
e it does not determinetheenablingand sequencing
1 SRAMand DRAM are bothvolatile memory
e

A it is also a function of the input

16k 16 kilobit 8 128kilobit

8 kilobit 4 32kilobit
therefore 128 32 4 1C so we need atleast 4
3

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at
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0 1 1 0 1 0 0 Gtaix
1 1 1 1 0 0
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at
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0 1
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mV 00 01 11 10

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TA X TB ATHEX
00 01 11 10
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II
ABY
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AXTIX

4
multiple of 2 0 2 4106,8
multiple of 3 0 3,60 9

multiple of 2 and not a multiple of 6


IDE 1 3 5
1 7 9 I

ifeng.g LI
next state output
present state 4 0 Xi O XII

IDLE IDLE 0
51 0

0 1
51 51 52

52 52 53 1 0

53 0 1
53 54

54 54 55 1 0

55 55 56 0 0

56 56 51 0 0
9

a b AC 1 1
b 2 C 1 0
C e C 0 1
b d a FC 1 0
e Aa b 0 1
C f e C 0 1
9 E C 0 1
a h Hb Ge 1 1

only 4 States a b c e

next state output


present 0 1 O At
C 7 1
a b
2 C 1 0
b
c e C 0 1
1
e Ja b o
00
It
abeccengeceh
07110011100
11110011100
abecceabecea
1111001170
6
a 11 Beginningwiththe WB thecircuitaddson pairat
atimethroughthe FAcircuit
G Thecarry'oftheoperation is transferredto a D
flipflop whichthen will beused asthecarry
inputforthe nextpairof bits
mgThesumwillbeshifted to Register AwhilethebitsinA
areshiftedout
In Thustheadditionis anomplisted bypassingeach sum
onebit at a time into register A

B4 A B Y 612
01 1 00 11 11 10 1 0 0
11 1 1001 0111 1 1 0 0
2 1 0100 0011 0 1 1 0
3
1 0010 0001 0 1 1 0
4 1001 0000 1 0 1 0

7 7 So
8

a It is counter thatcounts from 1to 6 and


a
then from 6 to 1 and back again

b theclock penodis 100 ns

e the clock starts from high I thus


50

2 50 tE
since initial val 1 400 75
at 1 to 2
Sons 325
at Runs 2to 3 would
Ifthe first 75serondcounts then it
at 250ns 3to4 still be at 31
at 350ns 4to5
hasn'thappenedyet so its still
at goons a falling edge at

5 6
intuisi s n N T

d at 1000nsthe next fallingedge hasn't happened yet so it stillat 1

1000 75 925
then it
If the first 75 selondounte
wouldbe at 2
reset
9
1

Pj targeted pattern
010

ungga

10
PA DB
QA QB Xi Xo Qat Y PA DB
Apt
0 0 0 0 0 0
0 0 0 1 0 1
0 1 0 1 0
0
0 0 1 1 1 1

0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 1 1
0 1 1 1 0 0
1 0 0 0 0
1

1 0 0 1 1 1

1 0 1 0 00
10 11 01
1 1 00 11
11 0 1 00

1 1 1 0 01
11 11 10
air
ijtii

DA AI GA
QTXIXTTQAXTXTTQAGXT QTQBXTXOTQAQBXIX N.ca
b
my best guess
the 4th bit register at cycle 4 will
load 1100
to the register and it will go to state two
where it will shift out the last bit 0

7011070
so now the bit in the register has 0110

however this is only IF Me and Main


cycle 5 k both 0

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