Digital Integrated Circuits

(83-313)
Lecture 7:
Designing Sequential
Logic Circuits
Prof. Adam Teman
27 April 2021

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email [email protected] and I will address this as soon as possible.
 Sequential Logic
• Sequential circuits are a function of both the
current state and the previous state.
• In other words,
they have memory.
• The majority of sequential
circuits are Synchronous,
using a clock to synchronize
the logic paths.

www.tutorialspoint.com

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 Lecture Content

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 Why use Sequential Logic?

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 Explanation through example
• We will look at two examples:
• An accumulator circuit, where sequential
methods are essential to eliminate races.
• A pipelined system, where sequential
methods improve throughput.

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 What would happen if there were no traffic lights?

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 Accumulator Example
• An accumulator is a register that sums a list of numbers.
Therefore, it feeds back the output back to the input.
• Without a register, there would be the possibility that
races would occur, causing erroneous outputs.
• We need to delay the output until the original calculation is finished.

IN

IN 0 1 0 FB + OUT

OUT 0 1 2

FB 0 1 2
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 Accumulator Example
• It is essential to use sequential logic when paths
have different delays but need to converge together.
• We always have to slow our fast paths down so they
arrive along with our slowest path.
• If we could make all paths have equal delays, we wouldn’t need
sequential logic, but this is really hard (almost impossible) to do.

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 Laundry Example
• Small laundry has one washer, one dryer and one operator,
it takes 90 minutes to finish one load:

• Washer takes 30 minutes

• Dryer takes 40 minutes

• “Operator folding” takes 20 minutes

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 Sequential Laundry
• It takes 90 minutes to finish one load.
• The process is sequential.

• Sequential laundry
takes 6 hours
for 4 loads.

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 Pipelined Laundry
• Every 40 minutes a new load starts and a new load ends.

• Pipelined laundry
takes 3.5 hours
for 4 loads

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 Pipelining Data
• If it takes 10 time units to process an instruction, we could perform
one instruction every 10 time units:
Instruction Output

Delay
• But if we divide the process into 5 tasks that take 2 time units each:
Instruction

Output
Delay

• We can start a new instruction every 2 time units.

12 • And after filling the pipe, we finish an instruction every 2 units. © Adam April
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 Pipelining Data
• But some stages may be faster than others, so we need to hold the input to
each stage constant until the previous stage is done.
• We achieve this by adding a register in between the stages.

• So by using a pipeline, we can make our slowest path shorter

and therefore reduce the delay between actions.
• All data paths are built using a pipeline of some sort,
either to eliminate races or to increase throughput.
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 Classic 5-Stage RISC Pipeline

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 Sequential Logic Elements

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 Naming Conventions
• In our course we relate to registers as follows:
• a latch is level sensitive
transparent transparent

opaque opaque

• a flip-flop is edge-triggered
locked locked

sample

sample
• There are many different naming conventions
• For instance, many books call
any bi-stable element a flip-flop (such as an SR Latch)
• However, this leads to confusion,
so we will use the convention above (as used in industry).
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 Latch Vs. Register
• During high clock phases, a latch is transparent,
latching the input on the falling edge.
• However, a Flip Flop only samples the input on the rising edge.

Clock

Input (D)

Latch D Q

D Q
Flip
Flop
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 Latch Vs. Register
• 3 main options for sequential timing:

• Using Flip-Flops

• Using Transparent Latches

• Using Pulsed Latches

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 Static Vs. Dynamic Latch
• A static latch stores its output in a static state
• A dynamic latch uses temporary capacitance to store its state.
• As with logic, this provides a trade-off between area, speed and reliability.

CLK
D Q
S0

MUX
Q
2:1

D S1

CLK
Dynamic Latch
Static Latch
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 Static Vs. Dynamic Latch
• Some basic implementations of static and dynamic latches.

Static Dynamic
CLK

CLK
Q

CLK D Q

D
CLK
CLK

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 Ratioed vs. Non-Ratioed Latch
• A static latch can be made by using a feedback inverter.
• The TG (with the driver before it) CLK
must overcome the feedback
D D
inverter to write into the latch.
CLK

CLK

• But it is usually more robust to create

a mux-based non-ratioed latch. Q

• At the expense of size. CLK

CLK
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 mid

Making a Flip Flop Input D Q D Q out

clk clk
• Conceptually, we can create an edge triggered flip-flop
by combining two opposite polarity latches:

Input

D Q

mid

D Q

out
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 Master-Slave (Edge-Triggered) Register
• Two opposite latches trigger on edge
• Also called master-slave latch pair

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 Master-Slave Register
• Multiplexer-based latch pair

I2 T2 I3 I5 T4 I6 Q

QM
D
I1 T1 I4 T3

CLK

• How many transistors make up this flip-flop?

• What is its clock load?
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 Resettable Flip Flops

Asynchronous Set/Reset Flip-Flop Synchronous Reset Flip-Flop

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 Timing Parameters of
Sequential Elements

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 Timing Definitions Register

D Q

CLK

CLK
t
tsetup thold

D DATA
tcq – propagation delay
STABLE t

tcq
tsetup – setup time
Q DATA thold – hold time
STABLE t

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 Clk-Q Delay - tcq
• tcq is the time from the clock edge until the data
appears at the output.
• The tcq for rising and falling outputs is different.

clk

tcqLH tcqHL tcqLH

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 Mux based FF – tcq Calculation
• During low clock edge, data traverses slave
and “waits” for the clock at pass gate input.
• When clock rises, data has to go through pass gate and inverter.

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK tcq =T3 + I 6

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 Timing Definitions Register

D Q

CLK

CLK
t
tsetup thold

D DATA
tcq – propagation delay
STABLE t

tcq
tsetup – setup time
Q DATA thold – hold time
STABLE t

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 Setup Time - tsetup
• Setup time is the time the data has to arrive before the clock to ensure correct
sampling.
clk

tsetup tsetup tsetup

Good! Good! BAD!

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 Mux based FF – tsetup Calculation
• Before clock edge, data should have propagated to the latching pass gate,
or else data will be restored to the previous state.

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

tsetup = I1 + T1 + I 3 + I 2 = T + 3I
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 Timing Analysis - Setup Time
• To obtain the setup time of the register while using SPICE, we progressively
skew the input with respect to the clock edge until the circuit fails.

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 Timing Definitions Register

D Q

CLK

CLK
t
tsetup thold

D DATA
tcq – propagation delay
STABLE t

tcq
tsetup – setup time
Q DATA thold – hold time
STABLE t

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 Hold Time - thold
• Hold time is the time the data has to be stable after the clock to ensure correct
sampling.
clk

thold thold thold

Good! Good! BAD!

• Often (optimally), Hold Time is negative!

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 Mux based FF – thold Calculation
• When the clock rises, T1 closes, latching the data at the output of I1.
• Therefore, any changes made tpd(I1) before the clock will not traverse.
• The hold time is –tpd(I1)

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK thold = − I1
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 Characterizing Timing

tD - Q

D Q D Q

Clk Clk

tC - Q tC - Q

Register Latch

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 Other Flip Flop
Implementations

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 Problem – Clock Overlap

CLK

CLKb

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

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 C2MOS – clocked CMOS
• Insensitive to clock overlap.
Low Phase Overlap High Phase Overlap

CLK

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CLKb
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 TSPC – True Single-Phase Clocked Register
TSPC enables including
logic inside the latch!

Example:
Positive latch AND latch
(transparent when CLK= 1)

Negative latch
(transparent when CLK= 0)
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 TSPC Flip Flop
VDD VDD VDD

CLK Q
M3 M6 M9
Y
Q
D CLK X CLK
M2 M5 M8

CLK
M1 M4 M7

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 Pulse-Triggered Latches Master-Slave Latches
L1 L2
Data
• Instead of a full set of master-slave latches D Q D Q

• We can emulate an edge with a short clock pulse: Clk Clk

Clk

Pulse-Triggered Latch Design a clock pulse with a “clock chopper”

L
Data
D Q

Clk
Clk

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 Basic Timing Constraints

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 Synchronous Timing

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 Timing Constraints
• There are two main problems that can arise in synchronous logic:
• Max Delay: The data doesn’t have enough time to pass
from one register to the next before the next clock edge.
• Min Delay: The data path is so short that it passes through
several registers during the same clock cycle.

• Max delay violations are a result of a slow data path,

including the registers’ tsetup, therefore it is often called the “Setup” path.

• Min delay violations are a result of a short data path, causing the data to
change before the thold has passed, therefore it is often called the “Hold” path.

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 Setup (Max) Constraint
• Let’s see what makes up our clock cycle:
• After the clock rises, it takes tcq for the data to propagate to point A.
• Then the data goes through the delay of the logic to get to point B.
• The data has to arrive at point B, tsetup before the next clock.
• In general, our timing path is a race:
• Between the Data Arrival, starting with the launching clock edge.
• And the Data Capture, one clock period later.

clk D Q Logic D Q
A B
D tcq

A clk

B tsetup
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 Setup (Max) Constraint

T  tcq + tlogic + tsetup

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 Hold (Min) Constraint
• Hold problems occur due to the logic changing before thold has passed.
• This is not a function of cycle time – it is relative to a single clock edge!
• Let’s see how this can happen:
• The clock rises and the data at A changes after tcq.
• The data at B changes tpd(logic) later.
• Since the data at B had to stay stable for thold after the clock (for the second
register), the change at B has to be at least thold after the clock edge.

clk D Q Logic D Q
A B
D tcq

A clk

B
thold
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 Hold (Min) Constraint

tcq + tlogic  thold

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 Summary
• For Setup constraints, the clock period has to be
longer than the data path delay:
• This sets our maximum frequency. T  tcq + tlogic + tsetup
• If we have setup failures, we can always just
slow down the clock.

• For Hold constrains, the data path delay has to be

longer than the hold time: tcq + tlogic  thold
• This is independent of clock period.
• If there is a hold failure, you can throw your chip away!

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 t DRV_CLK

Clock Nonidealities Ref_Clock

tskew tskew

• Clock skew t− jit t+ jit

tDRVCLK
• Spatial variation in temporally equivalent
Received Clock
clock edges; deterministic + random, tskew tRCV_CLK
T
Clock
uncertainty:
jitter+skew

• Clock jitter
• Temporal variations in consecutive Ref_Clock

edges of the clock signal; tskew tskew

modulation + random noise t+ jit
• Cycle-to-cycle (short-term) tJit,S t− jit
• Long term tJit,L

• Variation of the pulse width Received Clock

• Important for level sensitive clocking T

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 Positive and Negative Skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

CLK tCLK1 tCLK2 tCLK3

delay delay
Positive skew

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

tCLK1 tCLK2 tCLK3

delay delay CLK

Negative skew

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 Setup (Max) Constraint
• The Launch path (still) consists of:
• tcq+tlogic+tsetup
tlaunch = tcq + tlogic + tsetup + t jitter
• But if jitter makes the launch clock later,
we need to add it to the data path delay.
• The Capture path consists of:
• The clock period (T) tcapture = T +  skew − t jitter
• Positive skew means the capture clock path is longer.
• If jitter makes the capture clock earlier, we need to subtract it.
• Our max constraint is:
• So we get: tcapture  tlaunch
T  tcq + tlogic + tsetup + 2t jitter −  skew
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 Setup (Max) Constraint
• Data has to arrive before next clock edge.

T +  skew  tcq + tlogic + tsetup + 2t jitter

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 Hold (Min) Constraint
• The Launch path (still) consists of: tlaunch = tcq + tlogic − t jitter
• tcq+tlogic
• But if jitter makes the launch clock later,
we need to subtract it from the data path delay.
• The Capture path consists of: tcapture =  skew + t jitter + thold
• Skew that makes the clock edge arrive at the
capture register later than at the launch register.
• Actually, since it is a single clock edge, jitter should effect
the capture clock the same as the launch clock.
• But as a worst case, we will add it as spatial jitter. tlaunch  tcapture
• Our min constraint is:
• So we get: tcq + tlogic   skew + thold + 2t jitter
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 Hold (Min) Constraint
• Data has to arrive after the same clock edge has arrived at capture reg.

tcq + tlogic  thold +  skew + 2t jitter

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 Adding in Variation
• As previously discussed, variations in both fabrication and operating
conditions occur and are taken into account through “corner” simulation.
• For global variation we have defined three primary simulation corners:
• Typical Corner: our gates operate under nominal conditions and variation.
• Slow Corner: our gates slower (i.e., high VT, high temperature, low voltage).
• Fast Corner: our gates faster (i.e., low VT, low temperature, high voltage).
• To assume worst-case conditions:
• Calculate max-delay with the slowest possible transitions →Slow Corner.
• Calculate min -delay with the fastest possible transitions →Fast Corner.

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The Computer Hall of Fame
• The machine that made IBM dominate the computer
industry for 20 years

Source: techradar.com
• Announced April 7th, 1964, the first “upgradable”
and fully “compatible” computer.
• Thomas Watson “bet the business” on this machine
with a $5B investment that was to cannibalize all of
IBM’s existing computers.
• Ranked as one of the all-time top 3 business accomplishments
alongside Ford’s Model T and the Boeing 707.
• The machine that pioneered the 8-bit byte and the peripheral
components made by third parties.
Source:computerhistory.org
 Static Timing Analysis
Example

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 STA Example
• We are given a synchronous network with:
tCQ = 150ps, tsetup = 50ps, thold = 100ps, t jitter = 0
• In addition: t = −100ps, t = 50ps
skew1 skew2

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 STA Example
• We’ll find the setup
constraints for each path:
Path 1: T1 + tskew1  tcq1 + tp,max ( CL1 ) + tsetup2
T1  150p + 1.2n + 50p + 100p = 1500p = 1.5ns → 666MHz

Path 2: T2 + ( tskew2 − tskew1 )  tcq2 + tp,max ( CL2 ) + tsetup3

T2  150p + 800p + 50p − 150p = 850p → 1.17GHz

Path 3: T3 + ( 0 − tskew2 )  tcq3 + tp,max ( CL3 ) + tsetup1

T3  150p + 700p + 50p + 50p = 950p → 1.05GHz
• So the critical path is Path 1 and the maximum frequency is 666MHz.
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 STA Example
• Now, we’ll find the hold
constraints for tskew1 and tskew2:
Path 1: tskew1 + thold2  tcq1 + tp,min ( CL1 )
tskew1  150p + 250p − 100p = 300p

Path 2: ( tskew2 − tskew1 ) + thold3  tcq2 + tp,min ( CL2 )

( tskew2 − tskew1 )  150p + 150p − 100p = 200p
Path 3: ( 0 − tskew2 ) + thold1  tcq3 + tp,min ( CL3 )
−tskew2  150p + 200p − 100p = 250p → tskew2  −250p

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 STA Example
• If we could set tskew1 and tskew2,
could we use them to maximize
our frequency?
• If we could equally divide the delay of each path:
ttotal = 3  tcq + tp,max (CL1 + CL2 + CL3 ) + 3  tsetup =
= 450p + 2.7n + 150p = 3.3ns
• So to get the max frequency, set all delays to 1.1ns:

1.1ns + tskew1 = 150p + 1.2n + 50p → tskew1 = 300ps

1.1ns + ( tskew2 − tskew1 ) = 150p + 800p + 50p → tskew2 = 200ps
1.1ns + ( 0 − tskew2 ) = 150p + 700p + 50p → tskew2 = 200ps
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 Further Reading
• J. Rabaey, “Digital Integrated Circuits” 2003, Chapter 7

• Weste, Harris “CMOS VLSI Design” Chapter 7

• E. Alon, Berkeley EE-141, Lectures 23,24 (Fall 2010) http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f10/

• Berkeley CS-150, Lecture 4 http://inst.eecs.berkeley.edu/~cs150/

• Oklobdzija, Stojanovic, Markovic, Nedovic, “Digital System Clocking”

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