Digital Integrated Circuits

(83-313)

Lecture 2:
The Manufacturing Process
23 March 2020

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email [email protected] and I will address this as soon as possible.
 Lecture Content

2
© Adam
March
Teman,
23, 2020
 2 3 4
1
Detailed Process Manufacturing
A Process Primer
Process Flow Variations Issues

A Process Primer
A Quick Introduction to the CMOS Process

3
 Motivation

1~3 Years…

4 © Adam
March
Teman,
23, 2020
 Integrated Circuits…

Source: MIT 6.884

5
© Adam
March
Teman,
23, 2020
 Solution: The Printing Process

Source: Capital Poly

6 © Adam
March
Teman,
23, 2020
 The Photolithographic Process

7 © Adam
March
Teman,
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 CMOS Process/Transistors

8 © Adam
March
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 Basic Process Flow
Lightly Doped Wafer

Grow Field Oxide

Define Wells

Grow Gate Oxide

Deposit Poly Gate

Etch Gates

Implant Source/Drain

Deposit Isolation
Oxide and Contacts

Deposit Metal 1

Deposit Isolation
Oxide and Via 1

Deposit Metal 2
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© Adam
March
Teman,
23, 2020
The Computer Hall of Fame
• Speaking of integrated circuits, the first
IC-based computer was the Texas Instruments
Source: wikipedia Source: Texas Instruments

• A molecular electronic computer

Introduced in 1961
• “It performs exactly the same functions as a conventional
computer but is 150X smaller and 48X lighter.”
• “Three types of semiconductor networks are used in the tiny
computers: RS flip-flop, NOR gates, and logic drivers.”
• 8-16 “networks” were welded together in a stack.
• A total of 47 stacks (587 “networks”) made up the computer.

Source: http://s3data.computerhistory.org/brochures/ti.molecular.1961.102646283.pdf
 2 3 4
1
Detailed Process Process Manufacturing
A Process Primer
Flow Variations Issues

Detailed Process Flow

11
 The Silicon Wafer

Smithsonian (2000)

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
12 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Field Oxide – The LOCOS Process

Photoresist
Nitride (Si3N4)
SiO
Field
2 Oxide (FOX)
Active
Area

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
13 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Field Oxide – The STI Process
• The LOCOS Process has two problems:
• Bird’s Beak makes it hard to make transistors close to each other.
• A parasitic MOSFET can turn on underneath the FOX.
• Solution:
• Shallow Trench Isolation (STI)
• Field Implants
Bird’s
Beak Nitride (Si3N4)
SiO2
Active Active Active
Area Area Area

Parasitic
MOSFET
Lightly Doped Grow Field Transistor Backend
Well Implants Contacts
14 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Well Implantation
• Cover wafer with thin layer of oxide.
Implant wells through photolithographic
process.
• After implant we must Anneal to the
covalent bonds, and Diffuse to get
the wells to the depth we want.
• Annealing: Heating up the wafer to fix
covalent bonds. Done after every ion Source: Ultratech
implantation or similar damaging step.
• Diffusion: Movement of dopants due to heating of the wafer.
Usually this is unwanted, as it changes the doping depth.

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
15 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Well Implantation – Deep N-Wells
• Can we change the body voltage of an nMOS transistor?
• Yes, using a “triple well” process! Deep NWell
Layer
• BUT… it “costs” a lot of area: Don’t forget to NMOS Non-GND
Bulk Contact
connect to VDD!

p (field implant) p (field implant)

Isolated
N-well (n-) P-well (p) P-well (p)

P-sub (p-) Deep N-well (n-)

Regular NWell Layers

around boundary

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
16 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Transistor Fabrication: VT Implant
• The threshold voltage of a transistor is approximately:
2 s qN A ( 2 f ) qQI
VT = VFB + 2 f + +
Cox Cox
• So the first step is to implant QI.

• Random Dopant Fluctuations (RDF) cause a

problematic distribution in VT between devices.

• Native Transistors are transistors that didn’t go

through this step (i.e. VT≈0 → Depletion)
Lightly Doped Grow Field Transistor Backend
Well Implants Contacts
17 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Ion Implantation

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
18 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Transistor Fabrication: Gate Oxide
• Gate Oxide thickness (tox) is one of the most important device parameters.
• 45nm technology has a
1.2nm thick layer (about 5 atoms!).
• Gate oxide growth has to be done
in super-clean conditions to
eliminate traps and defects.
• High-K materials extremely
complicate this process.

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
19 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Transistor Fabrication: Gate Etch
• Originally Aluminum was used as the gate material,
then polysilicon, now metal again.
• The gate is the smallest dimension that is fabricated through photolithography.
• The oxide is self-aligned to the gate through the etching process.

p (field implant) p (field implant)

P-well (p)
P-sub (p-)

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
20 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Photolithography
• From Greek:
• photo – light
• lithos – stone
• graphe – picture
• “carving pictures in stone using light”
• Photomask (reticle): Wavelength


Minimum 193nm
• Chrome covered quartz glass. pitch

• Photoresist: D = k1
• Organic material, sensitive to light.
Material
constant (~0.8)
n sin 
• Developer: Refractive index (nair=1)
Angle of acceptance
• Solvent that dissolves the unexposed (exposed) photoresist. (bigger = larger lens)
Lightly Doped Grow Field Transistor Backend
Well Implants Contacts
21 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Photolithography 
D = k1
• Resolution Enhancement Techniques: n sin 
• Use immersion (wet) lithography (nwater=1.43)
• Use mask and layout techniques
• Use a smaller wavelength (193 nm).
• From 7nm (7+), EUV (13 nm) is used.

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
22 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Photolithography
• “Step and Scan”

• Optical Proximity
Corrections (OPC)

• Phase Shift Masks Source: Wikipedia

• Multiple Exposures,
Multiple Etches

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
23 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Photolithography

Excimer Laser Stepper

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
24 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Transistor Fabrication: Tip Extension
• For various reasons, we need a Lightly Doped Drain (LDD).
• But for source/drain resistance,
we need a heavily doped area away from the channel.
• Therefore, a Tip or Spacer is formed:

n implant n implant
n+ n+ implant
p (field implant) p (field implant)

P-well (p)
P-sub (p-)

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
25 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Contacts – Damascene Process
• The Damascene Process is used to make contacts/vias
• A thick isolation oxide is grown.
• The bumpy oxide is planarized through
Chemical-Mechanical Polishing (CMP)
• Contacts are etched,
lined and plugged.
• The remaining metal
is etched away.
FOX n implant n implant
n+ n+ implant
p (field implant) p (field implant)

P-well (p)
P-sub (p-)

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
26 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Contacts

P858 Process Flow -Intel Confidential 66

Contacts in 28nm Apple A7

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
27 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Misalignment Problems
goal: contact to diffusion problem: misalignment
between process steps

solution: make diffusion larger than contact (overlap)

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
28 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Planarization
• Planarization is achieved with
Chemical-Mechanical Polishing (CMP)

Source: wikipedia
Source: www.businesswire.com

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
29 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Metal Layers (Backend)
• ILD = Inter-layer Dielectric (low-k)
• Passivation protects the final layer
• Al or Cu for Metal layers
• W for Plugs, TiN for barrier layer

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
30 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Copper Interconnect
• Copper cannot be deposited directly on SiO2
• To solve this, the dual-Damascene process was introduced.

FOX n implant n implant

n+ n+ implant
p (field implant) p (field implant)

P-well (p)
P-sub (p-)

Lightly Doped Grow Field Transistor Backend

Well Implants Contacts
31 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 Microfabrication Summary List
• Lithography
• Thermal Oxidation
• Etching
• Ion Implantation
• Epitaxial Growth (PECVD)
• Chemical Mechanical Polishing (CMP)
• Deposition (Physical Vapor Deposition PVD, Chemical Vapor Deposition CVD)
• Diffusion (Furnace Annealing, Rapid Thermal Annealing RTA)
• Metal Plating
• Others…
Lightly Doped Grow Field Transistor Backend
Well Implants Contacts
32 Wafer Oxide Fabrication © (Metals)
AdamMarch
Teman,23, 2020
 2 4
1 3
Detailed Manufacturing
A Process Primer Process Variations
Process Flow Issues

Process Variations

33
 Process Variations
• Variation can occur at different levels:
• Fab to Fab variation
• Lot to Lot variation
• Wafer to Wafer variation
• Die to Die Variation
• Device to Device Variation
• Process Parameters
• Such as impurity concentrations, oxide thickness, diffusion depth.
• Caused during Deposition and Diffusion steps.
• Affect VT and tox.
• Device Dimensions
• Lengths and widths of gates, metals, etc.
• Caused due to photolithographic limitations.
Types of Additional Impact of
RDF LER/LWR WPE
34 Variation Variations © Variation
AdamMarch
Teman,23, 2020
 Types of Process Variation
• Random Variation:
Occurs without regards to the location and patterns of the transistors within the chip (e.g., RDF)
• For example – Random Dopant Fluctuation (RDF)
• Systematic Variation:
Related to the location and patterns
• For example – layout density, well-proximity, distance from center of wafer
• Intra-die (Within-die) Variations
Variations between elements in the same chip
• A.k.a. – “Local Variation”
• Inter-die (Die-to-Die)
Variations between chips in the same wafer or in different wafers
• A.k.a. – “Global Variation”
Types of Additional Impact of
RDF LER/LWR WPE
35 Variation Variations © Variation
AdamMarch
Teman,23, 2020
 Random Doping Fluctuation (RDF)
• The most significant factor in variations of the
threshold voltage is due to the number and
location of dopant atoms in the channel.
• In 1μm technology,
there were many thousands of dopants.
• In 32 nm technology,
there are less than 100 dopants!
• RDF accounts for about 60% of the threshold
variation.

Managing Process Variation in Intel’s 45nm CMOS Technology,

Intel Technology Journal, Volume 12, Issue 2, 2008

Types of Additional Impact of

RDF LER/LWR WPE
36 Variation Variations © Variation
AdamMarch
Teman,23, 2020
 Line Edge/Width Roughness (LER/LWR)
• Line Edge Roughness (LER) and Line Width Roughness (LWR) cause changes
in sub-threshold current and threshold voltage.
• These problems are expected to surpass RDF as the main cause of variations at
deep nanoscale technologies.

Types of Additional Impact of

RDF LER/LWR WPE
37 Variation Variations © Variation
AdamMarch
Teman,23, 2020
 Well Proximity Effects (WPE)
• Threshold voltage depends on
distance to well edge.

http://www.solidodesign.com/

Types of Additional Impact of

RDF LER/LWR WPE
38 Variation Variations © Variation
AdamMarch
Teman,23, 2020
 Additional Variations
• Gate Dielectric Variation
• Oxide Thickness
• Fixed Charge
• Defects and Traps
• CMP Variations
• STI Steps
• Metal Gate height
• ILD (Insulation Layer Dielectric) and Interconnect Thickness
• Strain Variation
• Implant Variation
• Rapid Thermal Anneal (RTA) Variation
Types of Additional Impact of
RDF LER/LWR WPE
39 Variation Variations © Variation
AdamMarch
Teman,23, 2020
 Impact of Process Variations

We will get back to

this next lecture
when we discus
process corners and
Monte Carlo
simulation…

Source: Rabaey, et. al.

Types of Additional Impact of

RDF LER/LWR WPE
40 Variation Variations © Variation
AdamMarch
Teman,23, 2020
 2 3 4
1
Detailed Process Manufacturing
A Process Primer
Process Flow Variations Issues

Manufacturing Issues

41
 Hillocking and Electromigration
• Hillocking:
• The development of small “hills” in the
interconnect due to stress on the Aluminum.
• Can short between metal layers, crack SiO2,
cause bumpiness.
• Adding Cu to Al helps reduce hillocking.
• Electromigration:
• Movement of Aluminum atoms due to high
current densities that can eventually
cause hillocks (shorts) or voids (opens).
• Proper design (keep J [A/cm2] under a limit)
helps prevent electromigration.
• Cu interconnect is very efficient against electromigration.
Electromigration Antennas Density Latchup
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© Adam
March
Teman,
23, 2020
 Antenna Effect
• Charge is built up on interconnect layers during deposition.
• If enough charge is created, this can cause
a high voltage to breakdown the thin gates.
 metal area not tied to diffusion  100  5000
gate area
m4 100 2000
m3
m2
m1
gate diff gate diff

Safe: m3 is too short to Dangerous: lots of m3; will

accumulate very much probably accumulate lots of
charge; won’t kill gate charge and then blow oxide

Electromigration Antennas Density Latchup

43
© Adam
March
Teman,
23, 2020
 Antenna Effect
• “Bridging” or “Antenna Diodes” are used to eliminate the Antenna Effect.

m4
m3
m2
2000
m1
gate diff gate ndiff
psub
Bridging keeps gate away Node diodes are inactive during
from long metals until they chip operation (reverse-biased p/n);
drain through the diffusion let charge leak away harmlessly

Electromigration Antennas Density Latchup

44
© Adam
March
Teman,
23, 2020
 Layer Density
• Metal layers should have between ~30% to ~70% density.
• Maximum metal widths require slotting. Softness of Cu
results in “dishing”
resist This etching step
takes a lot longer
metal
(“microloading”)
ILD

High density Low density

Solution: Add dummy
metal structures here
to maintain minimum
metal density

Electromigration Antennas Density Latchup

45
© Adam
March
Teman,
23, 2020
 Latchup
• The multiple n-type and p-type regions in
the CMOS process create parasitic BJT
transistors.
• Unintentional “Thyristors” can turn on
and short VDD and GND.
• This requires power down at the least, and
sometimes causes chip destruction.

• To reduce the risk of latchup, distribute

well/substrate contacts across the chip.
Electromigration Antennas Density Latchup
46
© Adam
March
Teman,
23, 2020
 Bulk Contacts
• To ensure a constant body voltage across large areas,
Bulk Contacts or Taps have to be added frequently.

N-well P-sub
P-select N-select
VDD VSS

N-select P-select
pMOS nMOS

Electromigration Antennas Density Latchup

47
© Adam
March
Teman,
23, 2020
 Further Reading
• J. Plummer “Silicon VLSI Technology”, 2000 – especially Chapter 2

• J. Rabaey, “Digital Integrated Circuits” 2003, Chapters 2.2-2.3

• C. Hu, “Modern Semiconductor Devices for Integrated Circuits”, 2010, Chapter 3

http://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.html

• E. Alon, Berkeley EE-141, Lectures 2,4 (Fall 2009)

http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/

• Berkeley EE-143 (Lectures – Nguyen 2014, Slides Cheung 2010)

• Tel Aviv University - Yosi Shacham

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© Adam
March
Teman,
23, 2020