Year Venue Architecture / Block Notes

2012 ISSCC Pipelined ADC

2012 JSSC Pipelined ADC
2012 VLSI Pipelined ADC
2013 VLSI Pipelined ADC
2014 ISSCC Pipelined ADC
2015 ISPACS Delta-Sigma ADC
2015 ISSCC Pipelined-SAR ADC
2015 JSSC Pipelined-SAR ADC
2015 JSSC Pipelined ADC
2016 EDSSC Delta-Sigma ADC
2016 ISCAS Pipelined ADC
2016 ISCAS Undefined
2016 ISCAS Delta-Sigma ADC
2017 CICC Pipelined ADC
2017 ICCC Undefined
2017 ISCAS Pipelined-SAR ADC Interleaved
2017 ISCAS Pipelined ADC
2017 MIXDES Delta-Sigma ADC
2017 MWSCAS Undefined
2017 VLSI Pipelined-SAR ADC
2017 VLSI Pipelined ADC
2018 CICC Pipelined ADC
2018 EExPolytech Undefined
2018 ISCAS Pipelined-SAR ADC Interleaved
2018 ISCAS Delta-Sigma ADC
2018 ISCAS Pipelined ADC
2018 ISCAS Undefined
2018 ISCAS Undefined
2018 SSCL Delta-Sigma ADC
2018 TCAS-II Undefined
2018 TCAS-II Pipelined-SAR ADC Interleaved
2019 ASIC Undefined
2019 ASSCC LDO
2019 ESSCIRC Pipelined-SAR ADC
2019 ISCAS PLL
2019 ISCAS Undefined
2019 ISSCC Pipelined-SAR ADC
2019 ISSCC Pipelined ADC Interleaved
2019 ISSCC Pipelined ADC
2019 JSSC Pipelined-SAR ADC
2019 JSSC Pipelined ADC
2019 JSSC Pipelined ADC
2019 JSSC Pipelined ADC
2019 MWSCAS VGA/PGA Bio
2019 TCAS-II Pipelined-SAR ADC
2020 CICC Pipelined-SAR ADC
2020 ICEIC Pipelined ADC
2020 ICSICT Pipelined-SAR ADC
2020 ISSCC LDO
2020 ISSCC NS-SAR ADC Multi-Stage FIA
2020 ISSCC Pipelined-SAR ADC
2020 ITNEC LNA Bio
2020 JSSC NS-SAR ADC Multi-Stage FIA
2020 JSSC Pipelined-SAR ADC
2020 TCAS-I Delta-Sigma ADC
2020 TCAS-II Undefined
2020 VLSI Pipelined ADC
2021 Access Neuromorphic
2021 APCCAS Undefined Multi-Stage FIA
2021 DCIS Pipelined-SAR ADC
2021 ESSCIRC Delta-Sigma ADC
2021 ISPACS Cyclic ADC
2021 ISSCC Pipelined ADC FIA
2021 JSSC Pipelined ADC
2021 JSSC Pipelined ADC Interleaved
2021 MWSCAS Undefined
2021 TCAS-I Pipelined ADC
2021 TCAS-II Delta-Sigma ADC
2021 TCAS-II Delta-Sigma ADC Multi-Stage FIA
2021 TCAS-II Undefined
2021 VLSI Pipelined-SAR ADC
2022 ISSCC Pipelined-SAR ADC
2022 ISSCC Delta-Sigma ADC
2022 ISSCC Pipelined-SAR ADC
2022 JSSC Pipelined-SAR ADC
2022 TCAS-II Pipelined-SAR ADC
2022 ISCAS Pipelined ADC Interleaved
2022 MWSCAS Pipelined ADC
2022 ISCAS SAR ADC VGA/PGA
2022 JSSC Pipelined-SAR ADC
2022 TPEL LDO
2022 JSSC Wireless
2022 ISCAS NS-SAR ADC
2022 JSSC Delta-Sigma ADC
Title
Ring amplifiers for switched-capacitor circuits
Ring Amplifiers for Switched Capacitor Circuits
A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers
A 75.9dB-SNDR 2.96mW 29fJ/conv-step ringamp-only pipelined ADC
A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers
A low-distortion delta-sigma modulator with ring amplifier and passive adder embedded SAR quantizer
A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers
A low-power third-order ΔΣ modulator using ring amplifiers with power-saving technique
A pipeline ADC with latched-based ring amplifiers
An adaptive slew rate and dead zone ring amplifier
Low power DT delta-sigma modulator with ring amplifier SC-integrator
A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier
A highly-linearized ring amplifier with gain offset calibration
A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier
A multi-path ring amplifier with dynamic biasing
A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode
An improved ring amplifier with process- and supply voltage-insensitive dead-zone
A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-
A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
Design of the Ring Amplifier for Low-Power ADC
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation
A Ring Amplifier Architecture for Continuous-Time Applications
An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs
Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers
Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit
34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Ti
A Systematic Design Methodology for Class-AB-Style Ring Amplifiers
A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier
High Linear Ring Amplifier Design with Analysis on Settling Procedures
An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps
Application of Ring-Amplifiers for Low-Power Wide-Bandwidth Digital Subsampling ADC-PLL
Cascoded Ring Amplifiers for High Speed and High Accuracy Settling
A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm
A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting an
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS
A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications
A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching an
A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control
An 11-bit Ring Amplifier Pipeline ADC with Settling-Time Improvement Scheme
A Fast Settling Low Noise Ring Amplifier for High Speed Pipelined SAR ADCs
A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-B
A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined
CMOS Ring Amplifier for Bio-Signal LNA
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level
Design Approach for Ring Amplifiers
Linearity-Enhanced Ring Amplifier Using Adaptive Slew-Rate Feed-Forward Path
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic S
An 8-bit Ring-Amplifier Based Mixed-Signal MAC Circuit With Full Digital Interface and Variable Accumulat
A PVT-Robust Closed-Loop Dynamic Amplifier Using Three-Stage Floating Inverter Amplifier
Design of a Ring-Amplifier Robust Against PVT Variations in Deep-Nanoscale FinFET CMOS
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC
A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating In
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Powe
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs
A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based I
Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers
Slew Rate in Self-Biased Ring Amplifiers
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration
A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp
A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-
A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DAC
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibratio
Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation
A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibratio
A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Orde
A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shiftin
A Fast Droop-Recovery Event-Driven Digital LDO With Adaptive Linear/Binary Two-Step Search for Voltage
Multi-Mode Spatial Signal Processor With Rainbow-Like Fast Beam Training and Wideband Communications
Ultra-Low OSR Calibration Free MASH Noise Shaping SAR ADC
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplif
Authors
Hershberg, Benjamin and Weaver, Skyler and Sobue,
Hershberg, Benjamin and Weaver, Skyler and Sobue,
Hershberg, Benjamin and Weaver, Skyler and Sobue,
Hershberg, Benjamin and Moon, Un-Ku
Lim, Yong and Flynn, Michael P.
Pan, Chunhui and San, Hao
Lim, Yong and Flynn, Michael P.
Lim, Yong and Flynn, Michael P.
Lim, Yong and Flynn, Michael P.
Gryta, Alexis and Suguro, Takuma and Ishikuro, Hiro
Chen, Wen-Tze and Shyu, Ya-Ting and Huang, Chun
Megawer, Karim M. and Hussien, Faisal A. and Abo
Suguro, Takuma and Ishikuro, Hiroki
Leuenberger, Spencer and Muhlestein, Jason and Su
Fan, Aipeng and Jin, Jing
Chen, Yongzhen and Wang, Jingjing and Hu, Hang an
Muhlestein, Jason and Farahbakhshian, Farshad and
Pan, Chunhui and San, Hao and Shibata, Tsugumichi
Cao, Yuefeng and Chen, Yongzhen and Zhang, Tianli
Lim, Yong and Flynn, Michael P.
Lagos, Jorge and Hershberg, Benjamin and Martens,
Lagos, Jorge and Hershberg, Benjamin and Martens,
Sidun, Aleksandr and Gaidukov, Mikhail and Piatak,
Chen, Yongzhen and Ni, Zhekan and Cao, Yuefeng an
Ahmed, Amr S. and Aboudina, Mohamed M. and Hussi
Leuenberger, Spencer and Venkatachala, Praveen Ku
Venkatachala, Praveen Kumar and Leuenberger, Spen
Venkatachala, Praveen Kumar and Leuenberger, Spen
Llimós Muntal, Pere and Jørgensen, Ivan Harald Holg
Megawer, Karim M. and Hussien, Faisal A. and Abo
Chen, Yongzhen and Wang, Jingjing and Hu, Hang an
Chen, Yongzhen and Wu, Jiangfeng
Xiao, Bohui and Venkatachala, Praveen Kumar and
Chen, Yongzhen and Shen, Xingchen and Ni, Zhekan
Lee, Calvin Yoji and ElShater, Ahmed and Venkatac
Lee, Calvin Yoji and Venkatachala, Praveen Kumar
ElShater, Ahmed and Lee, Calvin Yoji and Venkatac
Hershberg, Benjamin and Dermit, Davide and Liempd,
Hershberg, Benjamin and Liempd, Barend van and Mar
ElShater, Ahmed and Venkatachala, Praveen Kumar a
Lagos, Jorge and Hershberg, Benjamin Poris and Mar
Hung, Tsung-Chih and Kuo, Tai-Haur
Lagos, Jorge and Hershberg, Benjamin and Martens,
Wu, Yimin and Lan, Jingchao and Li, Shuai and Ye,
Park, Jun-Sang and An, Tai-Ji and Ahn, Gil-Cho and
Kinyua, Martin and Soenen, Eric
Bae, Chankyu and Shin, Seungwoo and Jung, Jiteck
Fan, Longbo and Ma, Bingbing and Yan, Na and Yin
Park, Jun-Eun and Hwang, Jeongho and Oh, Jonghyu
Tang, Xiyuan and Yang, Xiangxing and Zhao, Wenda a
Hung, Tsung-Chih and Wang, Jia-Ching and Kuo, Ta
Pei, Zhijun and Wang, Yaxin and Han, Lei
Tang, Xiyuan and Yang, Xiangxing and Zhao, Wenda a
Wang, Jia-Ching and Hung, Tsung-Chih and Kuo, Ta
Conrad, Joschua and Vogelmann, Patrick and Mokht
Gadel-Karim, Ahmed Gharib and Mohieldin, Ahmed N
Hershberg, Benjamin and Markulic, Nereo and Lagos,
Kim, Jongho and Seo, Beomkyu and Oh, Young H. and
Cheng, Chiwen and Ohhata, Kenichi
Xavier, João and Barquinha, Pedro and Goes, João
Santana, Lucas Moura and Martens, Ewout and Lagos
Mori, Kenta and Kayama, Eiki and Maebou, Taichi an
Tang, Xiyuan and Yang, Xiangxing and Liu, Jiaxin a
Hershberg, Benjamin and Markulić, Nereo and Lagos,
Hershberg, Benjamin and Dermit, Davide and van Lie
Lan, Jingchao and Zheng, Yan and Wu, Yimin and Ye
Hershberg, Benjamin and van Liempd, Barend and Mar
Lee, Calvin Yoji and Venkatachala, Praveen Kumar
Matsuoka, Akira and Nezuka, Tomohiro and Iizuka,
De Jesus Guzman, Marino and Maghari, Nima
Lagos, J. and Markulic, N. and Hershberg, B. and Der
Zhan, Mingtao and Jie, Lu and Tang, Xiyuan and Sun
Lee, Calvin Yoji and Moon, Un-Ku
Wang, Jia-Ching and Kuo, Tai-Haur
Lagos, Jorge and Markulić, Nereo and Hershberg, Be
Lan, Jingchao and Chen, Yongzhen and Shen, Xingch
Lan, Jingchao and Zhai, Danfeng and Chen, Yongzhe
J. Lan, Y. Zhang, F. Ye and J. Ren
C. -W. Chen, C. -Y. Su and H. -S. Chen
Wang, Jia-Ching and Kuo, Tai-Haur
Song, Yoonho and Oh, Jonghyun and Cho, Sung-Yong
Lin, Chung-Ching and Puglisi, Chase and Boljanovic,
H. Hu, V. Vesely and U. -K. Moon
L. M. Santana, E. Martens, J. Lagos, B. Hershberg,
Abstract
To overcome the challenges that CMOS process scaling has imposed on the design of switched-capacitor amplification circuits
In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient ampl
A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to
A high resolution pipelined ADC that performs precision amplification using only ring amplifiers is presented. Several enab
Pipelined ADCs require accurate amplification; however traditional OTAs limit power efficiency since they require high quiesc
This paper presents a novel multi-bit feedforward ΔΣAD modulator for low power and high signal-to-noise-and-distortion (SND
The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [1]. Consisting of two low-resolution c
This paper presents a 13 bit 50 MS/s fully differential ring amplifier based SAR-assisted pipeline ADC, implemented in 65 nm
The ring amplifier is an energy efficient and high output swing alternative to an OTA for switched-capacitor circuits. However
This paper presents a ΔΣ modulator with ring amplifiers to decrease the power consumption. The proposed ΔΣ modulator empl
In comparison with conventional operational amplifier, ring amplifier can achieve better power efficiency for switched capaci
This paper presents an adaptive ring amplifier that introduces a degree of freedom in speed/stabilization design trade-off in t
This paper presents a low power DT sigma-delta modulator for wide variety of sensor application using a ring amplifier for
Ring amplifiers have emerged as a scalable amplification technique. This work is a ring amplifier built with current-starved
This paper presents a high-accuracy and highly-linearized self-biased ring amplifier for switched capacitor analog and RF ci
This paper presents an 11bit 200MS/s SAR-assisted pipeline ADC with a 2.5bit front end stage and two time-interleaved 9bit s
This paper presents a new method for ring amplifier biasing to improve their stability while maintaining high slew rate. A mu
A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation mode using ring amplifier and SAR quantizer.
Conventional ring amplifier suffers from stability problem, the problem is exacerbated when process, voltage and temperature (
A four-stage fully differential ring amplifier in 40 nm CMOS improves gain to over 90 dB without compromising speed. It is
A pipelined ADC is presented that exploits the low but very constant (over output swing) open-loop gain characteristic o
The design of power-efficient ADCs able to achieve both high linearity and bandwidth in deep nanoscale CMOS processes bec
In this paper two implementations of the ring amplifier for the low-power ADCs are discussed. Requirements for the DC gain o
A SAR assisted pipeline ADC with an inter-stage ring amplifier is an energy efficient structure. The ring amplifier is an al
This paper presents a novel ring amplifier for continuous-time (CT) circuits. The proposed amplifier enables the usage of
This work presents a design example of how ring amplifier settling differs from a traditional operational amplifier. Ringamp
In this paper, passive compensation techniques are proposed: to improve the settling performance of a ring amplifier and to min
In this paper, process invariant biasing is proposed for robust operation of ring amplifiers. The ring amplifier is an efficient
This letter presents two pseudo-differential ring amplifiers (RAs) suitable for a continuous-time (CT) operation as an alterna
This brief introduces a design approach for Class-AB-style ring amplifiers which differs from the design of conventional ampli
This brief presents a time-interleaved SAR assisted pipeline ADC with an inter-stage ring amplifier as an energy efficient st
The ring amplifier is an alternative to an OTA for its low power consumption and large output swing. Since when the ring ampl
This paper presents a capacitor-less low dropout (LDO) regulator that requires no frequency compensation, with the use of an
Ring amplifier has been shown as an alternative to an OTA for its low power consumption and large output swing in low-voltag
A digital subsampling ADC-PLL is simulated using Verilog-A models with ring-amplifier designed in a 65nm CMOS process.
This paper presents a method of biasing high gain ring amplifiers with cascoded output stages while retaining the high slew cap
The two-step SAR architecture has been a popular choice for power-efficient ADCs used in applications such as medical imag
Giga-sample ADCs targeting high performance communication applications such as direct-RF sampling all rely on some form
At the upper end of achievable ADC operating speeds, clocking becomes a critical performance limiter. In “deep” pipelined AD
Low-noise ring amplifiers required for high-precision analog-digital converters (ADCs) greater than 16 b remain unexplored.
Ring amplification has recently been shown capable of simultaneously achieving high linearity and high bandwidth (BW) in low
This paper proposes averaging correlated level shifting (ACLS) and reference swapping (RS) techniques for simultaneously red
Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS proce
This paper presents a novel wideband continuous time (CT) programmable gain amplifier (PGA) with high power and area effi
This brief presents an ultra-low-power two-channel 12b 140 MS/s 28-nm CMOS analog-to-digital converter (ADC) for use in n
Ring amplifiers have emerged as scaling friendly amplification alternatives to conventional OTA-based switched capacitor res
In this paper, an 11-bit ring amplifier (RAMP) pipeline ADC with settling-time improvement scheme is proposed. A RAMP-ba
In this paper, a fast-settling ring amplifier (ringamp) with high linearity and low noise is presented. Implemented in 40 nm
Digital low-dropout regulators (DLDOs) are commonly used in low-power system-on-chips (SoCs) because of their low-voltag
Noise shaping (NS) SAR ADCs combine the merits of SAR and Δσ ADCs, and can simultaneously achieve high power efficien
With the increasing demand for next-generation communication, the trend of developing wide-bandwidth, high-resolution ADC
Low power wireless medical devices have attracted great research interests, which need the low noise amplifier (LNA) to ampl
This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter
This article presents a 14-b 100-MS/s single-channel pipelined-successive-approximation register (SAR) ADC using a weighted
Ring amplifiers are an advantageous new amplifier architecture, but designing them needs to be done in a time consuming proc
This brief presents a novel adaptive slew-rate ring amplifier. The proposed technique enhances the linearity, without stabili
This paper presents an 11 bit fully dynamic pipelined ADC with an integrated reference buffer that consumes only 8% of total
An 8-bit switched-capacitor multiply-and-accumulator (MAC) in 65nm CMOS is presented. Based on a cascaded low-power ri
This paper proposes a closed-loop dynamic amplifier using three-stage floating inverter amplifier (FIA). The closed-loop config
This paper describes the design and the electrical simulation results, at device level, of a proposed ring-amplifier (RINGAMP)
This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring amplifiers to relax critical speed and
This paper presents a non-binary cyclic analog-to-digital converter (ADC) with fully differential ring amplifier in 65nm SOTB
Many applications, such as multi-standard wireless and event-driven IoT devices, demand high-resolution ADCs with scalable
This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s
A 4× interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of
This paper proposed a floating power (FP) technique suitable for the switched-capacitor (SC) circuits. The FP generates an is
An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is show
This brief presents a high-resolution ADC which makes use of the pseudo-pseudo-differential noise filtering technique in an o
This brief proposes a fully dynamic discrete-time ΔΣ ADC using closed-loop two-stage cascoded floating inverter amplifiers (F
This brief presents a more detailed model for the slewing behavior of self-biased ring amplifiers and outlines the factors which
We present a single-channel fully-dynamic pipelined SAR ADC that leverages a novel quantizer and narrowband dither injecti
Pipelined ADCs are widely used for high-speed high-resolution applications, but there are two challenges. First, limited by th
Demands for battery-powered consumer electronics have driven the evolution of power-efficient high-resolution low-bandwidth
To fulfill upcoming communication specifications, it has become popular recently to employ pipelined-SAR architectures, inco
This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use
This brief focuses on the robustness of the ring amplifier (RA), an alternative to the operational transconductance amplif
A 2.5 GS/s12-bit 4-channel time-interleaved SAR-assisted pipelined ADC is proposed. The bias-enhanced ring amplifier serves
This paper proposed a robust ring amplifier (RAMP) with floating power technique for high-speed application. The proposed R
This paper proposes a ring amplifier with a self-stabilization technique (SST) against PVT variation. It can significantly al
This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averag
This letter presents an event-driven digital low-dropout regulator (DLDO) with an adaptive linear/binary two-step search achiev
Initial access in millimeter-wave (mmW) wireless is critical toward successful realization of the fifth-generation (5G) wir
This paper demonstrates a proposed architecture of multi-stage noise-shaping (MASH) structure with noise shaping successive-
This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to rela
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10.1109/TCSII.2021.3068884
10.23919/VLSICircuits52068.2021.949235
10.1109/ISSCC42614.2022.9731599
10.1109/ISSCC42614.2022.9731606
10.1109/ISSCC42614.2022.9731546
10.1109/JSSC.2021.3133829
10.1109/TCSII.2021.3093571
10.1109/ISCAS48785.2022.9937296
10.1109/MWSCAS54063.2022.9859478
10.1109/ISCAS48785.2022.9937223
10.1109/JSSC.2022.3196743
10.1109/TPEL.2021.3103611
10.1109/JSSC.2022.3178798
10.1109/ISCAS48785.2022.9937876
10.1109/JSSC.2022.3163819
Performance Metrics (JSON)
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{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"180",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"180",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"180",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"65","

{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"65",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"65",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"65","

{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"180",

{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"40",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"28","

{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"180"
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"16","
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"16","
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"180"
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"28","
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"90","
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"28","
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"16",

{"class":"ADC","sub_class”":"Oversampling","sub_sub_class":"NS-SAR","performance":{"source":"measured","tech":"40","f
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"28",

{"class":"ADC","sub_class”":"SAR","sub_sub_class":"NS-SAR","performance":{"source":"measured","tech":"40","fs":"10e6"
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"28",

{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"16","

{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"40",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","tech":"16","
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Deep-Pipeline","performance":{"source":"measured","

{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"16",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"28",
{"class":"ADC","sub_class”":"Delta-Sigma","sub_sub_class":"DT Delta-Sigma","performance":{"source":"measured","tech":"
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"28",
{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","

{"class":"ADC","sub_class”":"Pipelined","sub_sub_class":"Pipelined-SAR","performance":{"source":"measured","tech":"28",

{"class":"ADC","sub_class”":"Delta-Sigma","sub_sub_class":"DT Delta-Sigma","performance":{"source":"measured","tech":"
ce":"measured","tech":"180","fs":"20e6","OSR":"1","SNDR_nyq":"76.8","SFDR_nyq":"95.4","P_nyq":"5.1e-3"}}
ce":"measured","tech":"180","fs":"20e6","OSR":"1","SNDR_nyq":"76.8","SFDR_nyq":"95.4","P_nyq":"5.1e-3"}}
ce":"measured","tech":"180","fs":"30e6","OSR":"1","SNDR_nyq":"61.5","SFDR_nyq":"74.2","P_nyq":"2.6e-3"}}
ce":"measured","tech":"180","fs":"20e6","OSR":"1","SNDR_nyq":"75.9","SFDR_nyq":"91.4","P_nyq":"2.96e-3"}}
ce":"measured","tech":"65","fs":"100e6","OSR":"1","SNDR_nyq":"56.3","SFDR_nyq":"67.6","P_nyq":"2.46e-3"}}

rce":"measured","tech":"65","fs":"50e6","OSR":"1","SNDR_nyq":"70.9","SFDR_nyq":"84.6","P_nyq":"1.0e-3"}}
rce":"measured","tech":"65","fs":"50e6","OSR":"1","SNDR_nyq":"70.9","SFDR_nyq":"84.6","P_nyq":"1.0e-3"}}
ce":"measured","tech":"65","fs":"100e6","OSR":"1","SNDR_nyq":"56.6","SFDR_nyq":"64.7","P_nyq":"2.46e-3"}}

ce":"measured","tech":"180","fs":"20e6","OSR":"1","SNDR_nyq":"72.32","SFDR_nyq":"78.13","P_nyq":"2.74e-3"}}

rce":"measured","tech":"40","fs":"100e6","OSR":"1","SNDR_nyq":"73.2","SFDR_nyq":"90.4","P_nyq":"2.3e-3"}}
ce":"measured","tech":"28","fs":"600e6","OSR":"1","SNDR_nyq":"56.3","SFDR_nyq":"69.2","P_nyq":"14.2e-3"}}

rce":"measured","tech":"180","fs":"15e6","OSR":"1","SNDR_nyq":"88.0","SFDR_nyq":"96.5","P_nyq":"9.8e-3", "DR":"93.9"}}
ce":"measured","tech":"16","fs":"3.2e9","OSR":"1","SNDR_nyq":"61.7","SFDR_nyq":"73.3","P_nyq":"61.3e-3"}}
ce":"measured","tech":"16","fs":"600e6","OSR":"1","SNDR_nyq":"60.2","SFDR_nyq":"78.3","P_nyq":"6.0e-3"}}
rce":"measured","tech":"180","fs":"15e6","OSR":"1","SNDR_nyq":"88.0","SFDR_nyq":"96.5","P_nyq":"9.8e-3", "DR":"93.9"}}
ce":"measured","tech":"28","fs":"1e9","OSR":"1","SNDR_nyq":"56.6","SFDR_nyq":"73.1","P_nyq":"24.8e-3"}}
ce":"measured","tech":"90","fs":"24e6","OSR":"1","SNDR_nyq":"74.3","SFDR_nyq":"85.5","P_nyq":"5.1e-3"}}
ce":"measured","tech":"28","fs":"600e6","OSR":"1","SNDR_nyq":"58.7","SFDR_nyq":"72.4","P_nyq":"14.5e-3"}}
rce":"measured","tech":"16","fs":"100e6","OSR":"1","SNDR_nyq":"72.6","SFDR_nyq":"86.5","P_nyq":"2.5e-3"}}

e":"measured","tech":"40","fs":"10e6","OSR":"8","SNDR_nyq":"83.8","SFDR_nyq":"","P_nyq":"107e-6","DR":"85.5"}}
rce":"measured","tech":"28","fs":"100e6","OSR":"1","SNDR_nyq":"71.7","SFDR_nyq":"85.1","P_nyq":"0.7e-3"}}

ured","tech":"40","fs":"10e6","OSR":"8","SNDR_nyq":"83.8","SFDR_nyq":"94.3","P_nyq":"107e-6"}}
rce":"measured","tech":"28","fs":"100e6","OSR":"1","SNDR_nyq":"71.7","SFDR_nyq":"87.2","P_nyq":"0.7e-3"}}

ce":"measured","tech":"16","fs":"1e9","OSR":"1","SNDR_nyq":"59.5","SFDR_nyq":"75.9","P_nyq":"10.9e-3"}}

rce":"measured","tech":"40","fs":"40e6","OSR":"1","SNDR_nyq":"75.7","SFDR_nyq":"81.4","P_nyq":"8.21e-4"}}
ce":"measured","tech":"16","fs":"1e9","OSR":"1","SNDR_nyq":"59.5","SFDR_nyq":"75.9","P_nyq":"10.9e-3"}}
":{"source":"measured","tech":"16","fs":"4e9","OSR":"1","SNDR_nyq":"61.9","SFDR_nyq":"75.2","P_nyq":"75e-3"}}

rce":"measured","tech":"16","fs":"500e6","OSR":"1","SNDR_nyq":"62.9","SFDR_nyq":"75.5","P_nyq":"2.8e-3"}}
rce":"measured","tech":"28","fs":"200e6","OSR":"1","SNDR_nyq":"66.7","SFDR_nyq":"87.2","P_nyq":"1.30e-3"}}
"source":"measured","tech":"180","fs":"5.8e6","OSR":"145","SNDR_nyq":"105.4","SFDR_nyq":"","P_nyq":"2.04e-4","DR":"108.8"}}
rce":"measured","tech":"28","fs":"130e6","OSR":"1","SNDR_nyq":"72.5","SFDR_nyq":"87.5","P_nyq":"820e-6"}}
e":{"source":"measured","tech":"16","fs":"500e6","OSR":"1","SNDR_nyq":"62.3","SFDR_nyq":"75.5","P_nyq":"3.3e-3"}}

rce":"measured","tech":"28","fs":"130e6","OSR":"1","SNDR_nyq":"72.5","SFDR_nyq":"87.5","P_nyq":"820e-6"}}

"source":"measured","tech":"28","fs":"950e6","OSR":"10","SNDR_nyq":"67","SFDR_nyq":"","P_nyq":"4.7e-3","DR":"70"}}
"2.96e-3"}}
"2.46e-3"}}

"2.46e-3"}}

q":"2.74e-3"}}

"14.2e-3"}}

:"9.8e-3", "DR":"93.9"}}

:"9.8e-3", "DR":"93.9"}}

"14.5e-3"}}
6","DR":"85.5"}}

":"75.2","P_nyq":"75e-3"}}

:"1.30e-3"}}
nyq":"2.04e-4","DR":"108.8"}}
:"820e-6"}}
yq":"75.5","P_nyq":"3.3e-3"}}

:"820e-6"}}

"4.7e-3","DR":"70"}}
Year # Publications
2012 3 Ringamp Publications on IEEE Xplore by Year
2013 1 16
2014 1
14
2015 4
2016 4 12
2017 8

# of Publications
10
2018 10
2019 14 8

2020 12 6
2021 14
4
2022 13
(2022 still incomplete) 2

0
2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

Category # Publications
Pipelined ADC 25
Pipelined-SAR ADC 21 Type of Circuit or System where Ringamp is
Delta-Sigma ADC 12 Used
NS-SAR ADC 3 30
Cyclic ADC 1 25
LDO 3 20
PLL 1
15
# of Publications

LNA 1
10
VGA/PGA 2
Neuromorphic 1 5
Wireless 1 0
C C C C C O L A A ic ss ned
Undefined 13 AD AD AD AD c AD LD PL LN /PG rph ele
ed R a R li A o i r efi
lin S A igm -S A Cyc VG urom W Und
pe e d- - S N S
a quick sanity check here… Pi lin elta Ne
i pe D
P
total found: 84
total publications: 84

Venue # Publications
JSSC 15
ISSCC 13 Publication Venue of Ringamp Papers
VLSI 6 20
CICC 3 18
ESSCIRC 2 16
ASSCC 1 14
ISCAS 15
# of Publications

12
TCAS-I 2
10
TCAS-II 8
8
6
4
2
 14

# of Publications
12
10
8
Other 19
6
4
2
0
JSSC ISSCC VLSI CICC ESSCIRC ASSCC ISCAS TCAS-I TCAS-II Other
EEE Xplore by Year

17 2018 2019 2020 2021 2022

where Ringamp is

L A A ic ss ned
PL LN /PG rph ele
A o i r efi
VG urom W Und
Ne

Ringamp Papers
ASSCC ISCAS TCAS-I TCAS-II Other