Date :- 04/05/015 – 09/05/015

Encoding Schemes for Multipliers

Hardware multiplication is performed in the same way multiplication done by

hand, first step is to partialized the products are computed then shifted
appropriately and summed.
Normal multiplication Process:
The simplest multiplication operation is to directly calculate the product of two
numbers by hand. This procedure can be divided into three steps:
1. Partial product generation
2. Partial product reduction
3. Addition.
Let us calculate the product of 2’s complement of two numbers 1101(-3) and 5
(0101), when computing the two binary numbers product we get the result
1 1 0 1 Multiplicand
x 0 1 0 1 Multiplier
------------------------
1 1 1 1 1 1 0 1 PP1
0 0 0 0 0 0 0 PP2
1 1 1 1 0 1 PP3
+ 0 0 0 0 0 PP4
------------------------------------
1 1 1 1 1 0 0 0 1 = −15 Product

Discard this bit

From the above we say that 1101 is multiplicand and 0101 is multiplier. The
intermediate products are partial products. The final result is product (-15). When
this method is processed in hardware, the operation is to take one of the multiplier
bits at a time from right to left, multiplying the multiplicand by the single bit of
the multiplier and shifting the intermediate product one position to the left of the
earlier intermediate products. All the bits of the partial products in each column
are added to obtain two bits: sum and carry. Finally, the sum and carry bits in
each column have to be summed. The two rows before the product are called sum
and carry bits.

1 1 0 1 Multiplicand
x 0 1 0 1 Multiplier
 ------------------------
1 1 1 1 1 1 0 1 PP1
0 0 0 0 0 0 0 PP2
1 1 1 1 0 1 PP3
+ 0 0 0 0 0 PP4
------------------------------------
0 0 0 0 1 0 0 1 Sum bit
1 1 1 1 0 1 0 0 0 Carry bit
______________________________
1 1 1 1 1 0 0 0 1 = −15 Product

Advantage:
In this method the partial product circuit is simple and easy to implement.
Therefore, is is suitable for the implementation of small multipliers.
Disadvantage:
This method is not able to efficiently handle the sign extension and it generates a
number of partial products as many as the number of bits of the multiplier, which
results in many adders needed so that the area and power consumption increase.
This method is not applicable for large multipliers.
Booths algorithm:-
This algorithm will be slow if there are many partial products because the output
must wait until each sum is calculated and performed. As speed is main important
aspect while calculating the multiplication. By using the Booths algorithm, we
can maximize the speed. In Booths algorithm, speed can be maximized by
reducing the partial products to half. The adder circuits in Booth algorithm
provide the advantage in maximizing the speed.

ALU implements Booth algorithm to multiply binary number. ALU cannot

simply multiply binary number as it can do only addition, subtraction and
shifting.

Working Principle:-
Accumulator Multiplier Q-1 Multiplicand Action
Q
0000 0010 0 0110 2’s Shifting
Step1 complement of
0000 0001 0 0110

1010
 0000 Step 2 0001 0 0110 2’s Subtraction
+1010 complement of
1010 0110
1101 Step 3 0000 1 shifting
1010
1101 Step 4 0000 1 0110 Addition
+0110
0011
0001 Step 5 1000 0 Shifting
Shifting
0000 Step 6 1100 0

The operation of Booth encoding consists of two major steps: the first one is to
take one bit of the multiplier, and then to decide whether to add the multiplicand
according to the current and previous bits of the multiplier.
Initially accumulator start with 0000 and we will perform shift that is arthimetic
shift then we get first bit of A and the copy of first bit A and for the remaining
positions we get from the second position of A. The left bit in A is shifted to Q
and bits of Q is placed after it. The bit in Q is shifted to Q-1 . Initially Q-1 will be
0. Then we will compare LSB Multiplier, based on this comparision we will
perform the addition, subtraction and shifting.

Q0 Q-1 Action on A and

multiplicand
0 0 Shifting
0 1 Adding
1 0 Subtracting
1 1 Shifting

Based on this comparision we will perform the action on Accumulator and

multiplicand.
In the above table we multiplied 0010 and 0110 as an example and the result will
be combination of both Accumulator and multiplier i.e 0000 1100(12).

Modified Booth Algorithm:

The encoding method is widely used to generate the partial products for the
implementation of large multipliers. It adopts parallel encoding scheme.
Modified Booth Algorithm can be realized by using circuits consists of Booth
Encoder and multiplier array of partial product generator (Multiplexer) and
adders.
Booth Encoder:
It implements Booth Algorithm encoding.
Basic Principle:-
The basic principle in modified Booth Algorithm is, consider X and Y are two
fixed-point two’s complement numbers, where X is multiplier and Y is
multiplicand both having same n bits.

X can be represented as
�−
X = − �− 2�− + ∑�= �2
�

�/ − �
= ∑�= − �− + � + �− .2

�/ −
= ∑�= −2 �+ + � + �− . 4�

By multiplying the X with Y, results

�/ −
XY = ∑�= −2 �+ + � + �− . 4� .

From the above equation we portioned the bits of multipliers into substrings of
3 adjacent bits and each substring consists of �+ , � , �− ), each
corresponds to the value {−2, −1, 0, +1, +2}
The grouping of bits of multiplies can be done as
1 1 0 1 1 0 1 0 1 1
 �+ � �− Possible values
0 0 0 0
0 0 1 +1
0 1 0 +1
0 1 1 +2
1 0 0 -2
1 0 1 -1
1 1 0 -1
1 1 1 0

Each three adjacent bits of the multiplier can generate a single encoding digit
having the possible values
{−2, −1, 0, +1, +2}. For the n × n multiplication, the number of bits for the
multiplier X is n, using the modified Booth encoding n/2 partial products are
produced.

Multiplication:
The partial product should be shifted two positions to the left of the partial product
due to the is multiplied by
Add a Zero to get 3 bit as a group
1 1 0 1 0

+1
-1
0 1 0 1 +1Y

1 0 1 1 -1Y
-------------------------------------------
1 1 0 0 0 1 (-15)
The operation is summerized as

Possible values Operation on Y

0 0*Y: Y => 0 => Product is zero
+1 +1*Y: Y => Product (Y is the product)
+2 +2*Y: One Shift Y to the left => Product
-1 -1*Y: Invert Y and add 1 to the LSB of Y => Product
 -2 -2*Y: One Shift to the left for Y, then inverted Y & added 1 to
the LSB

Architecture: Booth Multiplier

Multiplier cell
Modified Booth Algorithm can be realized by using circuits consists of Booth
Encoder and multiplier array of partial product generator (Multiplexer) and
adders.
Booth Encoder:
On the left-hand side are the Booth encoders, one for each partial product.
They each have three bits of as input (with “0” to the right of the LSB).They are
also responsible for decoding and propagating the sign extension logic to the
next encoder. The array cells then generate the appropriate bit and add it to the
accumulated sum with their internal adders. In two’s complement format
inverting a number consists of flipping all bits and adding one. The “ADD” cell
generates the 1 if required.
Multiplier cell:
The cell consists of two components, a multiplexer to generate the partial product
bit (PP-MUX) and a full adder (FA) or half adder (HA) to add this bit with the
previous sum.
The multiplier cell represents one bit in a partial product and is responsible for:
1) Generating a bit of the correct partial product in response to the signals from
the Booth encoder;
2) Adding this bit to the cumulative sum propagated from the row above.

Adders:
In Booth Algorithm we use Half Adder and Full Adders along with the
Multiplexer. The FA is the most critical circuit in the multiplier as it ultimately
determines the speed and power dissipation of the array.
The Boolean Expression for Half Adder is
� = A XOR B
� = AB
The Boolean Expression for Full Adder is
� = A XOR B XOR ���
� = A (~B) ��� + ÃB��� +AB.
 Date :- 10/05/015 – 16/05/015

COMPARISON OF GDI BOOTH MULTIPLIER AND CMOS BOOTH MULTIPLIER

In this project we compare GDI Booth Multiplier and CMOS Booth Multiplier in
terms of power dissipation. The power dissipation in a
multiplier is a very important issue as it reflects the total
power dissipated by the circuit and hence affects the
performance for the device. We will conclude that GDI Booth Multiplier is better
than CMOS Booth Multiplier. We calculate the power dissipation of basic blocks
(Booth Encoder, Adder) of both GDI Booth Multiplier and CMOS Booth
Multiplier. We calculate the power dissipation of each block at channel length of
45nm, by varying the width of the channel we calculate the power of each block,
in GDI Booth Multiplier at channel width of PMOS = 49nm and NMOS = 45nm
and in CMOS Booth Multiplier, the channel width of PMOS is 900nm and NMOS
is 450nm.
Calculation of power dissipation of GDI based Booth Encoder:
The booth Encoder Circuit is shown in the Figure. The Y2i-1, Y2i, Y2i+1 are the
three adjacent bits of the multiplier and its output generates five possible values
which are encoded.
The output of the Booth Encoder circuit is shown in figure.

Power Dissipation of the input Source is

Source Power in GDI
VDD 5.8902e-006
Y2i+1 2.5952e-008
Y2i 6.9726e-008
Y2i-1 1.3979e-007
PP n , j 9.6417e-013
Fj 1.6801e-006
TOTAL POWER 7.805768e-6

Time Delay of the outbus w.r.t input Voltage Sources is:

Delay in GDI
Outbus<0> w.r.t Y2i-1 7.6990e-009
Outbus<1> w.r.t Y2i-1 2.5674e-008
Outbus<2> w.r.t Y2i-1 5.9361e-009
Outbus<3> w.r.t Y2i-1 1.8549e-010
Outbus<4> w.r.t Y2i-1 4.3784e-011

Outbus<0> w.r.t Y2i 2.3010e-009

Outbus<1> w.r.t Y2i 4.3835e-010
Outbus<2> w.r.t Y2i 4.0639e-009
Outbus<3> w.r.t Y2i 1.8549e-010
Outbus<4> w.r.t Y2i 3.8965e-010

Outbus<0> w.r.t Y2i+1 2.7699e-008

Outbus<1> w.r.t Y2i+1 1.4326e-008
Outbus<2> w.r.t Y2i+1 2.5936e-008
Outbus<3> w.r.t Y2i+1 1.8549e-010
Outbus<4> w.r.t Y2i+1 9.6104e-009
Calculation of power of Half Adder:-

We calculate the power of Half Adder for different input patterns taken in such
Pattern Power
Source 1 (1v) 0011 6.0470e-008
Source 2(1v) 0101 1.6233e-009
TOTAL POWER 1.596313e-7
a way that satisfies the all the conditions or having all the possible cases. The
power of VDD Voltage Source is 9.7538e-008

The circuit of the Half Adder in the GDI Multiplier is

Calculation of Power Dissipation of Full Adder of GDI Multiplier:

We calculate the power of Half Adder for different input patterns taken in such a
way that satisfies the all the conditions or having all the possible cases. The power
of VDD Voltage Source is -2.1139e-008 watts.
Pattern Power
Source1(1v) 00001111 4.1456e-006
Source2(1v) 00110011 9.5822e-007
Source3(1v) 01010101 1.1155e-007
TOTAL POWER 5.194231e-6
Calculation of Power Dissipation in Booth Encoder of CMOS Multiplier:
The booth Encoder Circuit is shown in the Figure. The Y2i-1, Y2i, Y2i+1 are the
three adjacent bits of the multiplier and its output generates five possible values
which are encoded. The output of the Booth Encoder is Outbus<0, 1, 2, 3, 4 >.The
power dissipated from the input Voltage Sources is
Source Power in CMOS
VDD 8.2437e-006
Y2i+1 4.5346e-008
Y2i 6.6163e-008
Y2i-1 1.1919e-007
PP n , j 2.3175e-008
Fj 4.5286e-008
TOTAL POWER 8.54286e-6

The circuit Diagram of Booth Encoder of CMOS Multiplier is

Calculation of Time Delay of output of the Booth Encoder
The output of the Booth Encoder is

Comparison of Time Delay of output w.r.t input:

Delay in CMOS
Outbus<0> w.r.t Y2i-1 6.8460e-011
Outbus<1> w.r.t Y2i-1 1.1024e-010
Outbus<2> w.r.t Y2i-1 1.1285e-010
Outbus<3> w.r.t Y2i-1 1.2418e-010
Outbus<4> w.r.t Y2i-1 8.3383e-011

Outbus<0> w.r.t Y2i 9.9315e-009

Outbus<1> w.r.t Y2i 1.0110e-008
Outbus<2> w.r.t Y2i 9.8871e-009
Outbus<3> w.r.t Y2i 1.2418e-010
Outbus<4> w.r.t Y2i 3.9185e-011

Outbus<0> w.r.t Y2i+1 2.9932e-008

Outbus<1> w.r.t Y2i+1 1.0110e-008
Outbus<2> w.r.t Y2i+1 1.9929e-008
Outbus<3> w.r.t Y2i+1 1.2418e-010
Outbus<4> w.r.t Y2i+1 3.9185e-011
Calculation of Power Dissipation of Adder Circuit of CMOS Multiplier:
The Circuit diagram of Adder circuit is

Pattern Power
Source1(1v) 0000000011111111 8.7274e-008
Source2(1v) 0000111100001111 5.8733e-008
Source3(1v) 0011001100110011 1.0371e-007
Source4(1v) 0101010101010101 2.4736e-007
TOTAL POWER 0.0004295371

We calculate the power of Half Adder for different input patterns taken in such
a way that satisfies the all the conditions or having all the possible cases. The
power of VDD Voltage Source is 4.2904e-004.
Comparison of time delay of both GDI & CMOS Multiplier:
Delay in CMOS Delay in GDI
Outbus<0> w.r.t Y2i-1 6.8460e-011 7.6990e-009
Outbus<1> w.r.t Y2i-1 1.1024e-010 2.5674e-008
Outbus<2> w.r.t Y2i-1 1.1285e-010 5.9361e-009
Outbus<3> w.r.t Y2i-1 1.2418e-010 1.8549e-010
Outbus<4> w.r.t Y2i-1 8.3383e-011 4.3784e-011

Outbus<0> w.r.t Y2i 9.9315e-009 2.3010e-009

Outbus<1> w.r.t Y2i 1.0110e-008 4.3835e-010
Outbus<2> w.r.t Y2i 9.8871e-009 4.0639e-009
Outbus<3> w.r.t Y2i 1.2418e-010 1.8549e-010
Outbus<4> w.r.t Y2i 3.9185e-011 3.8965e-010
 Outbus<0> w.r.t Y2i+1 2.9932e-008 2.7699e-008
Outbus<1> w.r.t Y2i+1 1.0110e-008 1.4326e-008
Outbus<2> w.r.t Y2i+1 1.9929e-008 2.5936e-008
Outbus<3> w.r.t Y2i+1 1.2418e-010 1.8549e-010
Outbus<4> w.r.t Y2i+1 3.9185e-011 9.6104e-009

From the above table we say that the delay is more in GDI Multiplier compared
to CMOS Multiplier.

Comparison of power dissipated in both GDI Multiplier and CMOS Multiplier:

Source Power in CMOS Power in GDI
VDD 8.2437e-006 5.8902e-006
Y2i+1 4.5346e-008 2.5952e-008
Y2i 6.6163e-008 6.9726e-008
Y2i-1 1.1919e-007 1.3979e-007
PP n , j 2.3175e-008 9.6417e-013
Fj 4.5286e-008 1.6801e-006
TOTAL POWER 8.54286e-6 7.805768e-6

From the above table we say that the power dissipation is more in CMOS
Multiplier compared to GDI Multiplier by 8%. This is due to less transistors are
used GDI Multiplier when compared to CMOS Multiplier. So that the power is
less in GDI Multiplier when compared to CMOS Multiplier.