Lecture 37
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Problem-2: Write the software program for the same problem as in
problem-1 if the largest natural number exceeds 22.
In this case the sum shall exceed 8-bits; therefore, 16-bit
operations are involved. Therefore, let us take the sum to be in (H, L)
register pair (16-bits). If the sum is in (H, L) pair, the constraint on the
sum is
SUM ≤ 65535.
This shall give the largest value for N ≤ 361. Thus the largest number
also needs 16-bit register for 16 bit arithmetic operation.
START
(H,L) 0
(B,C) N
(D,E) 0
(D,E) (D,E) + 1
(H,L) (H,L) + (D,E)
(B,C) (B,C) - 1
(A) (B)
(A) (A) U (C)
IS No
Z =1 ?
Yes
STOP
Fig.6.6 ALP for SUM of N Natural Numbers
Therefore, both counter and next natural numbers be placed in 16-bit
registers
COUNTER (B, C)
Next Natural Number, I (D, E)
Therefore the macro RTL flow chart will be as shown in fig.6.6 and
the ALP is given in fig.6.7
; This programme / sum of N natural numbers for N greater than 22.
ORG 2000H
LNN EQU 360 D
NSUM: LXI H, 0000 H ; Initialize SUM
LXI B, LNN ; Initialize COUNTER
LXI D, 0000H ; Initialize current natural no.
NEXT: INX D ; Generate next natural no.
DAD D ; Obtain running sum in (H,L)
DCX B ; Decrement counter
MOV A,B ; Is counter zero?
ORA C
JNZ NEXT ;No, go to generate natural number
HLT ; Yes, SUM is in (H,L)
Fig.6.7 ALP of SUM of N Natural Numbers
Problem-3: Write a program me to introduce 1msec delay in the
main programme. Assume 4MHz crystal is used in 𝜇𝑝 .
The philosophy of software delay is to ask the microprocessor
to do some irrelevant job for the requested delay duration. In general,
the irrelevant job is to load an internal register with a pre-calculated
number ‘N’, ask the microprocessor to decrement it repeatedly till the
register or counter becomes zero, and came out of the loop when the
counter becomes zero. In this process the processor must have spent
the required time delay duration. The two points to be noted in this
connection are:
i) Number ‘N’ to be loaded is to be recalculated
ii) The register used for initial loading the number should not
contain any useful data of main programme.
The necessary macro RTL flow chart for introducing the necessary
1msec delay is shown in fig.6.7.
(D) N
(D) (D) - 1
IS No
(D) =0 ?
Yes
Fig.6.7 Flow Chart to Introduce 1 ms Delay
The corresponding ALP is shown in fig.6.8.
:
MVI D, N 7 states
LP: DCR D 4 x N states
JNZ LP 10 x (N-1) + 7
:
Fig.6.8 Assembly Language Program to Introduce 1 ms Delay
The fig.6.7 also shows the number of states elapsed in executing
each instruction.
Total number of states elapsed = 7 + 4N + 10 (N-1) +7
= 14N + 4
If T secs is the duration of a state then time delay introduced is
≈td =(K N + 4)×T. This must be equal to 1msec. For 4MHz clock, the
time period T=0.5μsec.
On substitution, we get,
(14N + 4) x 0.5 x 10-6 =1 x 103
7 x 10-6 x N = 1 x 10-3 – 2 x 10-6
≈ 1x 10-3
Therefore, N = 142.88 143D = 8FH.
Therefore, in fig.11 the number ‘N’ to be loaded in to the (D) register
is 8FH to introduce 1msec delay in the main pregame.
Problem-4: Modify problem-3 to introduce K msec delay
K ms Delay
Fig.6.9 Flow Chart to Introduce K ms Delay
In this problem we have to introduce a variable time delay from 1
msec up to K msec. The register pair (B, C) can be used for loading,
the constant K. K shall be 1 for 1msec delay and K shall be 60000D
for 1min delay. The corresponding macro RTL flow chart in given in
flg-14
(B,C) K
(D) N
(D) (D) - 1
IS No
Z =1 ?
Yes
(B,C) (B,C) - 1
(A) (B)
(A) (A) U (C)
IS No
Z=1?
Yes
Fig.6.10 Macro RTL Flow Chart to Introduce K ms Delay
While drawing the macro RTL flow chart of fig-14 it is assumed that
register pain (B, C), the register (D) and the accumulator (A) are
available to the user. The corresponding ALP for fig- 14 is shown in
fig.6.11.
: Number of states
: required for K=1
LXI B, K 10
LP2: MVI D, N 7
LP1: DCR D 4N
JNZ LP1 10(N-1)+7
DCX B 6
MOV A,B 4
ORA C 4
JNZ LP2 7
:
Fig.6.11 ALP to Introduce K ms Delay
The constant N can be calculated again to introduce 1msec delay.
The constant so calculated shall not differ from 8FH calculated in
problem -3 because only few extra instructions are involved in this
problem. However we shall calculate the value of N?
For K = 1, the delay is given by
Td = [10 + 7 + 4N + 10(N-1) + 7 + 6 + 4 + 4 + 7] T
= [14N + 35] T
In this case, outer loop will not be traversed at all.
Assuming T=0.5 μsec, i.e., 2MHz external clock
1x 10-3 = [14N + 35] x 0.5 x 106
or, 14N + 35 = 2 x 103
or, N = 140D = 8CH
8CH can be taken as 1msec constant for introducing 1mesc delay
using ALP of fig.15. This constant shall not change even if some
more instructions are added to fig.15.
Consider now that of we have to implement Kmsec delay, K
variable at different points in the main programme as shown in
fig.6.12.
K1 ms Delay
K2 ms Delay
K3 ms Delay
Fig.6.12 Flow Chart to Introduce K ms Delay at Different Points
One way to solve the problem of fig.6.12 is to repeat the flow
chart of fig.6.10 every time loading the (B, C) pair in the appropriate
constant K. This is clumsy and occupies tremendous amount of
memory space unnecessarily. We can, therefore, write a subroutine
program for Kmsec time delay starting from the symbolic address
KDELAY. While writing the subroutine, it is assumed that the value of
K is available in the (B, C) register pair. This means that the value of
K must be loaded in to the (B, C) pair in the main programme before
calling the subroutine. This is known as the input to subroutine or
parameter passing from the main programme to subroutine
programme. The second point has to be noted while writing the
subroutine. Contents of all the registers made use of in the subroutine
programme should not be destroyed. They should be saved on the
top of stack using PUSH instructions. Further, the contents of these
registers should be restored by POP operations before returning to
the main programme. These extra instructions increases the delay
introduced by the subroutine. The subroutine incorporating the above
details is shown in fig6.13.
KDELAY: PUSH B
PUSH D
PUSH PSW
LP2: MVI D, 8CH
LP1: DCR D
JNZ LP1
DCX B
MOV A,B
ORA C
JNZ LP2
POP PSW
POP D
POP B
RET
