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COA Module2

The document discusses instruction set architecture (ISA). It defines ISA as the interface between software and hardware that specifies how the CPU is controlled. ISAs differ based on where operands are stored, such as in registers or on a stack. Features to consider when designing an ISA include instruction types, operand sizes, addressing modes, and encoding. Common ISA types include RISC, which aims for simple instructions executed in one clock cycle, and CISC, which uses more complex instructions to minimize program size.

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Aditya Dhanaraj Kundu
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20 views

COA Module2

The document discusses instruction set architecture (ISA). It defines ISA as the interface between software and hardware that specifies how the CPU is controlled. ISAs differ based on where operands are stored, such as in registers or on a stack. Features to consider when designing an ISA include instruction types, operand sizes, addressing modes, and encoding. Common ISA types include RISC, which aims for simple instructions executed in one clock cycle, and CISC, which uses more complex instructions to minimize program size.

Uploaded by

Aditya Dhanaraj Kundu
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture & Organization (YCS4001)

Module 2: Basic Operation of Computer

Soumya Majumdar
Instruction Set Architecture

● Part of the abstract model of a computer that defines how the CPU is controlled by the software
● ISA acts as an interface between hardware and software, specifying both what the processor is
capable of doing as well as how it gets done
● Only way that you can talk to your machine is through the ISA
● Suppose we have a high-level program written in C which is independent of the architecture on
which we want to work- has to be translated into an assembly language program which is
specific to a particular architecture- consists of a number of instructions like LOAD, STORE,
ADD, etc.
● All these instructions are part of the instruction set architecture of the MIPS architecture
●
Instruction Set Architecture

● ISAs differ based on the internal storage in a processor.


● ISA can be classified as follows, based on where operands are stored and whether they are
named explicitly or implicitly: 1. Single accumulator organization, 2. General register
organization, 3. Stack organization
● Single accumulator organization: one of the general purpose registers as the accumulator and uses it to
necessarily store one of the operands and indicates that one of the operands is implied to be in accumulator and
it is enough if other operand is specified along with instruction.
● General register organization: specifies all the operands explicitly. Depending on whether the operands are
available in memory or registers, it can be further classified as
● – Register – register : registers are used for storing operands
● – Register – memory: one operand is in a register and the other one in memory
● – Memory – memory: all the operands are specified as memory operands
● Stack organization: operands are put into the stack and the operations are carried out on the top of the stack
Features need to be considered during design of ISA

● Types of instructions (Operations in the Instruction set)


● Types and sizes of operands
● Addressing Modes
● Addressing Memory
● Encoding and Instruction Formats
● Compiler related issues
CPU Register/Process Register

● One of small set of data holding places that are part of the computer processor
● A register may hold an instruction, a storage address, or any kind of data (such as a bit sequence
or individual characters)
● Some instructions specify registers as part of the instruction. e.g.- an instruction may specify
that the contents of two defined registers be added together and then placed in a specified
register
● Processor typically contains multiple index registers, also known as address registers or registers
of modification. Effective address of any entity in a computer includes the base, index, and
relative addresses, all of which are stored in the index register.
● A shift register is another type of CPU register. Bits enter the shift register at one end and
emerge from the other end. Flip flops, also known as bistable gates, store and process the data.
Instruction format
● Zero-address instruction

CMA

CME

● One-address instruction

ADD 06H

LOAD 20H

● Two-address instruction

MOV R1, R2

ADD R1, R2

● Three-address instruction

ADD R1, R2,R3


Instruction format
Zero address format
X = (A+B)*(C+D)

TOP means top of stack M[X] is any memory location


One address format
X = (A+B)*(C+D)

AC is accumulator M[] is any memory location M[T] is temporary location


Two address format
X = (A+B)*(C+D)

R1, R2 are registers M[] is any memory location


Three address format
X = (A+B)*(C+D)

R1, R2 are registers M[] is any memory location


Instruction format
● Parts of the instruction format are: 1. Addressing Mode 2. Operation Code( OPCODE) 3.
OPERAND
● Data is represented in the instruction format with the help of addressing mode

● Addressing mode is the first part of the instruction format

● Data can either be stored in the memory of a computer or it can be located in the register of the

CPU

● Operation code gives instructions to the processor to perform the specific Operation

● Operation code is the second part of the instruction format

● Operand is the part of the instruction format that specifies the data or the address of the data

● Depending upon the processor of the computer the instruction format contains zero to three

operands
Instruction Set
● An instruction set is a group of commands for a central processing unit (CPU) in machine
language.
● All CPUs have instruction sets that enable commands directing CPU to switch the relevant
transistors.
● The instructions tell the CPU to perform tasks.
● Example of instruction: read, write, move
● The instructions are made up of a specific number of bits. For example: CPU's instructions
might be 8 bits, where first 4 bits make up operation code that tells computer what to do, next 4
bits are operand, which tells computer the data that should be used.
●
Basic Instruction Cycle
Types of Instruction Set
● Reduced instruction set computer (RISC)
● Minimal instruction set computers (MISC)
● Complex instruction set computer (CISC)
● Explicitly parallel instruction computing (EPIC)
● Very long instruction word (VLIW)
● Zero instruction set computer (ZISC)
● One instruction set computer (OISC)
RISC
● RISC (reduced instruction set computer) is a microprocessor that is designed to perform a
smaller number of types of computer instructions so that it can operate at a higher speed
(perform more millions of instructions per second, or MIPS).
● Reduced Instruction Set Computer Central Processing Units (RISC CPUs) was designed to
execute one instruction per cycle, five stages in total. Those stages are, Fetch, Decode, Execute,
Memory, and Write.
● Fetch: In the Fetch stage, instruction is being fetched from the memory.
● Decode: During the Decode stage, we decode the instruction and fetch the source operands
● Execute: During the execute stage, the computer performs the operation specified by the
instruction
● Memory: If there is any data that needs to be accessed, it is done in the memory stage
● Write: If we need to store the result in the destination location, it is done during the writeback
stage,
RISC Pipeline
CISC

● Main objective of a CISC processor is to minimize the program size by


reducing the number of instructions in a program.
● Utilize complex instruction sets in order to complete any given task rather
than executing a simple set of instructions in a single clock cycle
● Major goal behind design of CISC is to have such an instruction set that
works well with the tasks and data structures of Higher-Level Languages.
This
● CISC architecture supports a variety of addressing modes and therefore,
the instruction length is of variable nature.
Features of CISC Processor
● Decoding: instructions are of complex nature, thus offers complex instruction
decoding.
● Instruction size: instructions within this processor are large in size and are of variable
nature.
● Data Types and Addressing Modes: involves more data types and complex
addressing modes.
● General Purpose Registers: operations are performed in the memory itself and the
results of operations are also stored within the memory so due to this reason less
general-purpose registers are needed in the case of CISC processors.
● Clock Cycle: as the size of instructions here is variable thus more than one clock
cycle may be used for instruction execution.
CISC Architecture
●
CISC Advantages

● Code sizes are small in the case of the CISC processors.


● Compiler’s work is reduced to a large extent high-level language statement
is not required to be converted into assembly language.
● Shortcode length supports less RAM requirement.
CISC Disadvantages

● High complexity makes the system somewhat inefficient.


● Instruction is executed in more than one clock cycle.
● It does not support instruction pipelining.
●

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