Silicon (2022) 14:12293–12301

https://doi.org/10.1007/s12633-022-01932-z

ORIGINAL PAPER

Design and Implementation of Negative Capacitance Based

Electrostatic Doped Double Gate Tunnel Field Effect Transistor
Mohd Ashraf Lone 1 & Leo Raj Solay 2 & Amandeep Singh 1 & S. Intekhab Amin 3 & Sunny Anand 2

Received: 28 February 2022 / Accepted: 6 May 2022 / Published online: 14 May 2022
# The Author(s), under exclusive licence to Springer Nature B.V. 2022

Abstract
This paper proposes a novel design of negative capacitance based electrostatic doped double gate tunnel field effect transistor
(NC-ED DG TFET). The electrostatic doped double gate tunnel FET (ED DG TFET) offers reduced thermal budget and process
complexity by eliminating doping process. By including ferroelectric material at gate insulator, negative capacitance is intro-
duced which further improved the switching performance of the ED DG TFET. Silvaco TCAD 2-D simulator have been utilized
for designing the NC-ED DG TFET. The performance enhancement in terms of sub-threshold slope (Sub-VT) resulted low, high
current ratio (ION/IOFF) and reduced threshold voltage (VT) when compared with ED DG TFET device. The effect of varying of
ferroelectric thickness on various parameters like trans-conductance, drain characteristics, polarized charge, threshold voltage,
etc. are explored.

Keywords Negative capacitance . Electrostatic doped . Band to band tunnelling . Sub-threshold slope . Tunnel FETs

1 Introduction increasing the chances of failure and reliability issues of the

devices [7, 8]. Electrostatic doped double gate tunnel field
Scaling of transistors had enabled operation of the circuit effect transistors (ED DG TFETs) [9] help us to overcome
faster and low power consumable besides the other advantage these issues by which the drain, and source region are induced
of reducing the package area [1]. But the consequences with by the application of proper bias at polarity gates (PGs) [10,
respect to short channel effects (SCE) resulting from scaling 11]. In short channel devices, creating sharp doping profile at
had adversely affected the consumption of power at nanoscale source, drain regions is not an easy task by the conventional
range [2]. There is lot of power wastage during the transition doping methods. In this device without using conventional
of a transistor [3]. To mitigate these effects various devices doping methods, high carrier density regions are created by
have been proposed and one of them is Tunnel field effect applying appropriate voltages which abolishes the need of
transistors (TFETs). The advantage of TFETs over metal ox- high thermal budget.
ide semiconductor field effect transistors (MOSFETs) is that To enhance the performance of ED double gate TFET (ED
the transport mechanism is band to band tunnelling rather than DG TFET), the negative capacitance concept is introduced to
thermionic emission [4]. TFETs provides low subthreshold ED DG TFET and thus, NC-ED DG TFET is proposed. This
swing [5] and low leakage [6]. As with nano meter scale device replaces the gate insulator by the ferroelectric material
regime, rigorous high temperature doping processes induce which provides the exceptional properties of negative capac-
variations such as random doping fluctuations (RDF) which itance by which the power consumption can be reduced to a
effect the electrical parameters of the device, thereby great extent [12]. The ferroelectric behaves like a voltage step-
up transformer that amplifies the internal voltage that could
reduce the voltage required for the working of a transistor. To
* Amandeep Singh get the same amount of charge in the channel, smaller voltage
[email protected] is needed when compared to what was required classically
[13]. This would increase ON state current (ION) and further
1
National Institute of Technology Srinagar, Srinagar, JK, India lowers the subthreshold value. In this proposed device NC-ED
2
Amity University, Noida, Uttar Pradesh, India DG TFET the subthreshold swing is reduced by two mecha-
3
Jamia Millia Islamia University, New Delhi, India
nisms, which are tunnelling mechanism [14] and negative

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12294 Silicon (2022) 14:12293–12301

capacitance mechanism. This device can be operated at lower simulation parameters used for designing ED DG TFET are
operating voltage which decreases the consumption of power. given in the Table 1. The parameters used for designing NC-
Many researchers have found that the negative capacitance ED DG TFET are same as that of ED DG TFET with thick-
state is unstable, but it can be stabilized by putting it in series ness of the ferroelectric as 2.8 × 10− 4 cm.
with dielectric capacitor [12]. Various ferroelectric materials The capacitive model for the ferroelectric transistor is
such as PbTiO3, PZT (PbZr/TiO3) and BaTiO3, etc., are used shown Fig. 1(b) alongside of NC ED DG TFET. This model
in negative capacitance FET technology. First break through is evaluated for the device using MATLAB software by
was made by introducing negative differential capacitance as a employing Landau-Khalatnikov equation. One thing to point
gate insulator which lower the subthreshold slope below the out here is that this model indicates capacitances for single
limit of 60mv/dec in MOSFETs [10]. Further a new design gate, a similar symmetric model can be formulated for the
was proposed which achieved below 30mv/dec slope in non- double gate device. The capacitance CMOS in series with the
hysteresis NC-FET [15]. Negative capacitance technique is ferroelectric capacitance (CFE) stabilizes the ferroelectric ma-
further applied to double gate MOSFET with PZT gate stack terial for negative capacitance region. So, the combination of
for which the device can work at gate voltage of 0.24 V [16]. CMOS and CFE will be positive to stabilize the negative capac-
Recently Negative capacitance is incorporated in TFET which itance operation. The voltage drop across ferroelectric is cal-
uses lead zirconate titanate (PZT) as gate insulator by which culated by using Landau-Khalatnikov (L-K) equation using
the ON current was improved [17]. MATLAB given as in Eq. 1.
In this proposed device, negative capacitance phenomenon
is achieved by planting a ferroelectric capacitor in series con- V FE ¼ T FE ð2
Qt þ 4Q3t þ 6Q5t Þ ð1Þ
nection with the gate of ED DG TFET. The ferroelectric ma-
Here TFE denotes thickness and the constants α, β, and γ
terial used here is lead zirconate titanate (PZT). To extract the
are the material’s Landau constants. The value of ferroelectric
advantages of ferroelectric material’s negative capacitance on
capacitance (CFE) is given by the variation in charge (Qt) with
the device, combination of numerical simulation model and
reference to the ferroelectric voltage (VFE), so CFE will be
the Landau–Khalatnikov (L–K) models are used. The device
calculated as given in Eq. 2.
is simulated in ATLAS device simulator and MATLAB soft-
ware to investigate the results of NC-ED DG TFET. ED DG C FE ¼ 1=T FE ð2
þ 12Q2t þ 30Q4t Þ ð2Þ
TFET device is designed in ATLAS simulator and then
MATLAB software is used to introduce the negative capaci- The negative capacitance gate voltage (VGNC) will then be
tance ferroelectric model. the summation of the ferroelectric voltage and the gate volt-
age, i.e., VGNC=VMOS +VFE. In the proposed device ferroelec-
tric material PZT is incorporated by inserting values of
2 Structure and Simulation Parameters Landau coefficients α, β and γ of the material in the L-K
of the Device equation as given in the Table 2. The advantages of the PZT
material are adequate polarization rate with reliability and
The structure of the electrostatic doped double gate tunnel high dielectric capacitance [19, 20]. The simulation method-
FET and the proposed structure is shown in Fig. 1. The sim- ology used for the simulation of the device is given in
ulations of the ED DG TFET in Fig. 1(a) is done by using a Fig. 1(c).
high-k dielectric HfO2 as a gate insulator having an oxide In the SILVACO tool [21], various models were activated
thickness of 3.2 nm. The structure of Fig. 1(b) possesses neg- for carrying the simulation process-nonlocal band to band
ative capacitance due to the ferroelectric material placed in tunnelling model is introduced to account for tunnelling
series with the dielectric. The NC-ED DG TFET has been mechanism. The trap aided tunnelling is also facilitated by
designed using the ATLAS device simulator and the impact Schenk. Universal Schottky tunnelling model is also enabled
of ferroelectric material is analysed by designing a capacitance as NiSi contacts are used at the source and drain terminals. For
model in the MATLAB software. For designing of NC-ED observing the effect of temperature, Klassen and analytic
DG TFET, a lightly doped silicon film of thickness 10 nm is physical models are enabled for relating low field carrier mo-
employed having carrier concentration of 1015 cm−3. The bility with temperature.
source and drain regions are generated using polarity gate
concept [18]. For developing source region, a negative voltage
of 1.2 V is applied to PG-2 to create sufficient hole concen- 3 Simulation Results and Discussions
tration beneath the polarity gate as given in [10]. Similarly
drain region can be developed by applying the positive volt- The property of negative capacitance (CFE) exhibited by the
age of 1.2 V at PG-1. The source drain contacts are made up of ferroelectric material is shown in the Fig. 2. Unlike normal
nickel silicide (NiSi) with 0.45 eV barrier height. The other capacitors, ferroelectric capacitors exhibit an inverted curve

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Silicon (2022) 14:12293–12301 12295

PG - 1 SGAP, D GATE SGAP, S PG - 2

Create mesh structure, define
HfO2 TOX
mesh region, and set bias
NiSi NiSi
SILICON FILM TSi
D S
HfO2 TOX Define various models

PG - 1 GATE PG - 2

(a)
Converged
NO

VGNC
GATE YES
PG - 1 SGAP, D SGAP, S PG - 2 CFE VFE
FE
Extract data from
HfO2 TOX simulator
NiSi NiSi
SILICON FILM TSi
D S CMOS
HfO2 TOX Compute transfer characteristic,

FE Output characteristics, etc., from

PG - 1 PG - 2
L-K equation
GATE

(b) (c)
Fig. 1 Cross sectional view of (a) ED DG TFET (b) NC-ED DG TFET and (c) Simulation methodology

by which a good capacitive hold on the channel can be ob- property of the ferroelectric material can be utilised to analyse
tained. The series connection of ferroelectric and semiconduc- the performance of the device without any degrading effects
tor capacitances will give the total capacitance (CT). The semi- of the thickness of the material which are discussed in later
conductor capacitance stabilizes the ferroelectric negative ca- sections in detail. Here the gate voltage is considerably re-
pacitance to give the total capacitance as stable positive ca- duced to realise the device to operate at very low voltages.
pacitance as shown in the Fig. 2. The negative capacitance dielectric acts as voltage step-up
Simulated results of the transfer characteristics of the de- transformer to realise the ON current at low gate voltage.
vice are shown and comparison is done without and with Hence NC-ED DG TFET will be useful for low power appli-
negative capacitance effect in Fig. 3(a). For simulations of cations. Moreover, the value of subthreshold slope has been
the device, thickness of ferroelectric material has been taken reduced considerably by negative capacitance to 2.5mV/de-
here as 2.8 × 10− 4 cm so that the negative capacitance cade from 12mv/decade in ED DG TFET [9]. Further it can be
interpreted that at 0.6 V at gate, the ION is three order greater in
NC-ED DG TFET as that of ED DG TFET, therefore making
Table 1 Parameters values for the design and simulation of ED DG it suitable for high performance applications. The
TFET transconductance curve is shown in Fig. 3(b) including the
effects of negative capacitance. Transconductance is the prime
Parameter Value
measure of amplification performance for a device. Due to
Silicon thickness film (TSI) 10 nm boosting up of voltage by the ferroelectric material, better
Channel length 50 nm
Gate work function 4.5 eV
Gate oxide thickness 3.2 nm Table 2 Landau coefficients for the ferroelectric material (PZT) used in
Gate-Source spacer length (SGAP,S) 5 nm NC-ED DG TFET device [19]
Gate-Drain spacer length (SGAP,D) 20 nm
Ferroelectric material α (cm/F) β(cm5/F/Coul2) γ(cm9/F/Coul4)
Silicon film doping 1×1015 cm− 3
PG-1 & PG-2 work function 4.5 eV PZT − 1.8e11 5.8e22 0

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12296 Silicon (2022) 14:12293–12301

the device at other values. To prevent the unexpected behav-

iour of the device because of hysteresis in the ferroelectric
material the thickness variation is kept in a limit. Moreover,
result without negative capacitance is also added to get deep
insight about the demonstrated results. The parameter and
their values are given in Table 3.
Figure 5(a) demonstrates the impact of variations of the
ferroelectric thickness on the characteristics of the drain cur-
rent. It can be seen the drain current values are same for all
thicknesses but the gate voltage at which these values are
attained are different. Higher value of the thickness (tFE1)
shows less threshold voltage, and the maximum drain current
Fig. 2 Ferroelectric material and total capacitance with gate voltage
can be attained at lower values and hence it can be concluded
that less power will be dissipated for higher thickness of the
amplification is achieved at low gate voltage and hence im- ferroelectric material. Proper care should be given while
proves the performance of device at lower gate voltage. It can choosing the thickness of the ferroelectric for having better
be interpreted from the results that NC-ED DG TFET provide results as the higher thickness value will have hysteresis
better amplification as compared to ED DG TFET at same effect.
input voltage. This make NC-ED DG TFET suitable for sens- Transconductance characteristics of the device with vary-
ing applications. ing ferroelectric thickness is shown in Fig. 5(b). With increase
Figure 4 shows the capacitance values and cut off frequen- in gate voltage, there is increase in the tunnelling of carriers
cy (FT) variation with respect to the gate voltage. Here the and hence results in increase in gain or transconductance of
value of CGG is calculated by adding the gate to source capac- the device. With the increase in thickness of the ferroelectric
itance and gate to drain capacitance i.e., CGG=CGS+CGD. The material this gain occurs at reduced voltage and hence the
value of cut off frequency is calculated as F T ¼ gm =2C GG device will show amplification at lower gate voltage and thus
where gm represents the transconductance of the device. FT is consumes less power.
used to determine frequency response of the device indicating Potential change with gate voltage by varying PZT thick-
the frequency where short circuit current gain is unity and is ness is shown in Fig. 6(a). The probe is applied in the centre of
achieved at low voltage for the device with negative capaci- channel to consider the centre potential for this result.
tance. This further illustrates the low voltage operating prop- Potential is built due to the attraction of electrons and repul-
erty of the NC-ED DG TFET. sion of holes by the applied gate voltage. Figure 6(a) illustrates
that the centre potential remains constant for all thicknesses,
but threshold voltage is scaled down. Hence potential en-
4 Sensitivity Analysis hancement is observed at higher thicknesses of the ferroelec-
tric material for NC-ED DG TFET device. Figure 6(b) shows
In this section results are extracted by varying the thickness of the variation of electric field with respect to gate voltage with
ferroelectric dielectric material. The behaviour of device is different ferroelectric thicknesses. The electric field is the in-
analysed over few values of the thickness of the material, dication of force required to create the flow of charge. With
but these few values are enough to expect the behaviour of the increase of ferroelectric thickness, field profile can be

Fig. 3 (a) Transfer characteristics

and (b) Transconductance curve
of the NC-ED DG TFET at VDS =
1V

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Silicon (2022) 14:12293–12301 12297

Fig. 4 Variation of (a) CGs (b)

CGD (c) CGG (b) FT with gate
voltage (VGS)

achieved at lower voltage without disturbing the pattern and voltages are obtained at thickness of 1.5 × 10− 4 cm and the
thus lesser voltage is needed for the proper operation of the values are decreasing with increase in the thickness of the
device. Figure 6(c) and (d) shows the variation of electron and ferroelectric material as it will show hysteresis effect at higher
hole concentration with gate voltage which is examined at thicknesses. So, the necessary thickness must be chosen for
different values of tFE respectively. Electron and hole concen- the optimisation of the device. Due to the dopingless nature of
tration profile shows early variation with respect to gate volt- our device, thickness required is higher than doped devices to
age for higher thickness of the ferroelectric material. This have sufficient charge formation.
early variation results due to decreasing of threshold voltage Figure 7(b) shows the variation of thickness of the ferro-
with increasing ferroelectric dielectric thickness. It can also be electric with polarised charge. The separation of positive and
pointed out here that there is a shift in voltage in presence of negative charges results in charge polarisation. This result is
negative capacitance which shows the less power requirement important also in selecting the appropriate thickness of ferro-
for visualising the similar electron and hole characteristics. electric material. The polarised charge increases as the thick-
The impact of varying thickness of the ferroelectric mate- ness reduces due to the inverse relationship as the number of
rial on the voltage is shown in Fig. 7(a). VFE is the voltage of randomly oriented domains inside the ferroelectric material
the ferroelectric material PZT and VGNC represents the total will be low inside thin ferroelectric. Low polarised charge is
voltage which is combination of the ferroelectric voltage and required for better operation of the device and hence suitable
applied gate voltage (VGMOS + VFE). Higher value of the thickness should be chosen to have improved performance.
Figure 8(a) illustrates the threshold voltage and subthresh-
old slope with the variation of ferroelectric thickness.
Table 3 Various Subthreshold slope is an important parameter determining
thickness and their Thickness Value (cm) the power dissipation of a device during switching from
values used for NC-ED OFF to ON state. It should be low to have a better transition
DG TFET device tFE1 2.8×10−4
tFE2 2.4×10−4
performance of a device. Negative capacitance helps to reduce
tFE3 2.1×10−4
both threshold voltage as well as subthreshold slope. Due to
the phenomenon of voltage amplification by ferroelectric ma-
tFE4 1.8×10−4
terial less voltage is required to be applied at the gate terminal
tFE5 1.5×10−4
to turn the device in ON state and hence reducing the threshold

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12298 Silicon (2022) 14:12293–12301

Fig. 5 (a) Drain current

characteristics and (b)
Transconductance, obtained by
varying ferroelectric material
thickness PZT (tFE) with gate
voltage

voltage below 0.5 V. The analytical expression for the sub- negative capacitance to decrease its value below unity and
threshold slope for MOSFET is given as the second term is optimised by using tunnel FET to change
   the conduction mechanism from band transition to band
@VG @VG kB T
SS ¼ ¼ ln 10 ð3Þ tunnelling. So, the value of subthreshold slope is reduced to
@ðlog10 IÞ @ϕs q value of nearly 2.5mV/decade at thickness of 2.7 × 10− 4 cm.
 
@VG Cs By increasing the thickness of the PZT, threshold voltage and
¼ 1þ ð4Þ
@ϕs Cins subthreshold slope decreases to have better performance in
accordance with the earlier obtained results. But thickness of
the ferroelectric material cannot be increased due to hysteresis
In case of MOSFETs the second term (ln 10 kBT/q) is effect. Figure 8(b) illustrates the effect of variation of the fer-
constant (60 mV/decade at room temperature). But in the pro- roelectric thickness on OFF state current and ON-OFF current
posed device, two concepts are merged to minimise subthresh- ratio. It can be observed that the OFF current is almost con-
old value. Here the first term ( @V G =@ϕs )is optimised by stant with the variation of thickness at lower values but

Fig. 6 (a) Channel Potential (b)

Electric Field (c) Electron
concentration (d) Hole
concentration, variations with
different thickness of PZT with
respect to gate voltage

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Silicon (2022) 14:12293–12301 12299

Fig. 7 Variation of (a) negative

capacitance gate voltage and
ferroelectric voltage (b) polarized
charge with thickness of the
ferroelectric material

increases at higher tFE values. This increase in OFF current in size while maintaining the operational constraints of the
will ultimately result in reduction of ON-OFF current ratio. physical models. Polarization is defined as the magnitude of
This result also got the reason of hysteresis behaviour of PZT the dipole moment divided by the volume of the polarised
at higher values of tFE. So, it is necessary to choose a suitable substance. Figure 9, The polarisation increases exponentially
value of thickness of ferroelectric dielectric for better results of as the positive value of the ferroelectric voltage increases until
device. Figure 8(c) shows the effect of SS with channel length a certain point, at which point it begins to decline due to the
variation. One of the advantage of the electrostatic doped low field strength. Saturation occurs as the voltage is in-
Tunnel FET is the immunity towards the channel length var- creased in the negative direction until a certain point, at which
iation and the similar trend was observed here. It is observed point the cycle ends due to the decreasing field strength. The
that the change in SS is only − 0.3mV/decade when we go polarisation effect observed for positive and negative ferro-
from 50 to 200 nm channel length. This indicates there is not electric voltages is caused by this hysteresis.
much adverse effects with the scaling of the device. With the
decrease of channel length, SS increase slightly due to the
decrease in threshold voltage and consequently OFF current 5 Conclusion
will be restricted to higher value.
Figure 9 shows how [22] was used to model and calibrate Negative capacitance based electrostatic doped double gate
the simulation of the proposed device. The device is calibrated tunnel FET (NC-ED DG TFET) is designed and simulated.
using the same physical models and dimensions that were Electrostatic doped double gate tunnel FET device is one of
previously defined. The proposed device has been reduced the potential devices to provide benefit of low power

Fig. 8 Variation of (a)

subthreshold slope and threshold
voltage (b) OFF current and ON
to OFF current ratio (c)
Subthreshold Slope with channel
length, with thickness of
ferroelectric material at VDS =1 V

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12300 Silicon (2022) 14:12293–12301

Research Involving Human Participants and/or Animals NA.

Informed Consent NA.

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