INTEGRATED CIRCUITS

DATA SHEET

SAA4961
Integrated multistandard comb filter
Preliminary specification 1997 Feb 03
File under Integrated Circuits, IC02
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

FEATURES GENERAL DESCRIPTION

• One chip adaptive multistandard comb filter The SAA4961 is an adaptive alignment-free one chip
• Time discrete but continuous amplitude signal comb filter compatible with both PAL and NTSC systems
processing with analog interfaces and provides high performance in Y/C separation.
• Internal delay lines, filters, clock processing and signal
switches
• Alignment-free
• No hanging dots or residual cross colour on vertical
transients
• Few external components.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

VCCA analog supply voltage 4.75 5 5.5 V
VDDD digital supply voltage 4.75 5 5.5 V
VCCO analog supply voltage output buffer 4.75 5 5.5 V
VCCPLL analog supply voltage PLL 4.75 5 5.5 V
ICCO analog supply current output buffer − 70 90 mA
IDDD digital supply current − 10 20 mA
ICCA analog supply current − 35 40 mA
ICCPLL analog supply current PLL − 1.5 3.0 mA
V17(p-p) CVBS and Y input signal (peak-to-peak value) 0.7 1 1.4 V
V10(p-p) chrominance input signal (peak-to-peak value) − 0.7 1 V
V1(p-p) subcarrier input signal (peak-to-peak value) 100 200 400 mV
V14(p-p) luminance output signal (peak-to-peak value) 0.6 1 1.54 V
V12(p-p) chrominance output signal (peak-to-peak value) − 0.7 1.1 V
V15(p-p) CVBS and Y output signal (peak-to-peak value) 0.6 1 1.54 V

ORDERING INFORMATION

TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
SAA4961 DIP28 plastic dual in-line package; 28 leads (600 mil) SOT117-1

1997 Feb 03 2
 +5 V +5 V +5 V +5 V

1997 Feb 03
A 100 µF A 100 µF A 100 µF D 100 µF A A

handbook, full pagewidth

100 nF 100 nF
100 nF 100 nF 100 nF 100 nF

BLOCK DIAGRAM
D A 47 Ω
Philips Semiconductors

PLLGND VCCPLL AGND VCCA OGND VCCO DGND VDDD REFBP REFDL
26 27 9 7 11 8 21 22 5 24
+5 V HDET VDET

FSC 1
CURRENT VOLTAGE
BYP 3 CONT1 REFERENCE REFERENCE
HSEL LPF
LPFO1
SSYN 6 CONTROL CONT2
SYSPAL
FSCSW 13 CLOCK
CL3
SYS2 23 CONTROL
CL3
SYS1 20 STOPS
15 CVBSO
COMBENA 25
DELAY LPFO1 S2A
COMPENSATION
SYS1 SYS2 CVBSDL
Integrated multistandard comb filter

CONT1
CL3
A CSY 19 SYNC HDET

3
14 YO
SEPARATOR VDET
100 nF BPF LPFO1 S2B

Yext/CVBS 17 YCOMB
CLAMP CL3 −1 CONT1 STOPS
CL3
100 nF CCOMB
DELAY COMB
BPF BPF LPFO2 12 CO
LINES FILTER
+5 V LPFI S1
S2C
CL3 CL3 CONT1
CONT2
LPFION 18
BPF

HSEL CL3 CL3 CL3

SYSPAL
Cext 10 SAA4961
BIAS
100 nF
4 16 2 28
i.c. i.c. i.c. i.c. MHA546

Remark: all switches in LOW position.

Fig.1 Block diagram.

SAA4961
Preliminary specification
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

PINNING

SYMBOL PIN DESCRIPTION

FSC 1 subcarrier frequency input
i.c. 2 internally connected
BYP 3 bypass mode forcing input
i.c. 4 internally connected
REFBP decoupling capacitor for band-pass
5
filter reference handbook, halfpage
FSC 1 28 i.c.
SSYN 6 bypass definition input
VCCA 7 analog supply voltage i.c. 2 27 VCCPLL

VCCO 8 analog supply voltage output buffer BYP 3 26 PLLGND

AGND 9 analog ground (signal reference) i.c. 4 25 COMBENA
Cext 10 external chrominance input signal
REFBP 5 24 REFDL
OGND 11 analog ground output buffer
SSYN 6 23 SYS2
CO 12 chrominance output signal
VCCA 7 22 VDDD
FSCSW 13 fsc reference selection input SAA4961
VCCO 8 21 DGND
YO 14 luminance output signal
CVBSO 15 uncombed CVBS output signal AGND 9 20 SYS1

i.c. 16 internally connected Cext 10 19 CSY

Yext/CVBS 17 CVBS (VBS) input signal OGND 11 18 LPFION
LPFION 18 disable alias-filter CO 12 17 Yext/CVBS
CSY 19 storage capacitor
FSCSW 13 16 i.c.
SYS1 20 standard select 1 input
YO 14 15 CVBSO
DGND 21 digital ground
MHA547
VDDD 22 digital supply voltage
SYS2 23 standard select 2 input
REFDL 24 decoupling capacitor for delay lines
COMBENA 25 COMB-mode output signal
PLLGND 26 analog ground PLL
VCCPLL 27 analog supply voltage PLL
Fig.2 Pin configuration.
i.c. 28 internally connected

1997 Feb 03 4
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

FUNCTIONAL DESCRIPTION Pin description

Functional requirements FSC (PIN 1)
The multistandard comb filter processes the video Input for the reference frequency fsc (see note 2 of Chapter
standards PAL B, G, H, M, N and NTSC M. PAL D and I “Characteristics”) or 2 × fsc. For SECAM standard signals
signals can also be processed but with the drawback of a the best signal performance in BYPASS-mode is achieved
slightly reduced bandwidth. by switching the FSC input signal off externally.
For SECAM and SVHS signals the input signals can be
BYP (PIN 3)
bypassed to the output without processing by selecting the
BYPASS-mode. Input signal that controls the operation mode. A low-pass
filter is added to the input for suppression of subcarrier
A sync separation circuit is incorporated to generate
frequencies. Thus applications are supported where the
control signals for the internal clock processing. With a
operation mode (COMB or BYPASS) is controlled by the
sync compression of up to 12 dB the sync separator works
DC-level of the FSC input signal at pin 1. For those
properly (see Fig.4).
applications the BYP input can be externally connected to
The IC is controlled via six pins: FSC (pin 1).
1. BYP forces the IC into the BYPASS-mode (comb filter Depending on SSYN (pin 6) the function of BYP can be
function off) adapted to a certain application with respect to the polarity
2. SSYN defines whether the COMB-mode is entered of the logic level and with respect to the behaviour when
synchronously or not and defines the polarity of the entering the COMB-mode.
BYP pin
Depending on SSYN the BYP input can be either inverted
3. SYS1 selects the video standard or non-inverted with the function as shown in Table 2.
4. SYS2 selects the video standard
5. FSCSW selects the reference frequency fsc or 2 × fsc Table 2 Bypass function

6. LPFION enables the internal pre-filter. SSYN BYP SELECTED MODE

It is possible to select the following modes of operation: LOW LOW COMB-mode
COMB-mode: luminance and chrominance comb filter LOW HIGH BYPASS-mode
function active if BYPASS-mode not active. HIGH LOW BYPASS-mode
BYPASS-mode: signal processing not active, all clocks HIGH HIGH COMB-mode
inactive, Cext (pin 10) is bypassed to CO (pin 12) and
Yext/CVBS (pin 17) is bypassed to YO (pin 14) and
Depending on SSYN the behaviour when entering the
CVBSO (pin 15). This mode is forced via BYP (pin 3).
COMB-mode is different for the both selectable logic
If the stimulus of the mode is changed, the IC is following polarities while the BYPASS-mode is always entered
the new mode after the stabilization time given in Table 1. asynchronously (immediately).

Table 1 Stabilization time after mode change Table 3 Behaviour when entering the COMB-mode

MAXIMUM SSYN ENTERING COMB-MODE

MODE CHANGE STABILIZATION LOW immediately if BYP = LOW
TIME
HIGH synchronized by vertical pulse if
COMB-mode to BYPASS-mode 1 line BYP = HIGH
BYPASS-mode to COMB-mode 1 field
The PLL and the clock processing are always stopped if
The mode change from BYPASS to COMB depends on the selected level for BYPASS is applied to BYP
SSYN (pin 6) and can be asynchronous or synchronous (independent of the vertical pulse).
related to the vertical pulse. The mode change from
COMB to BYPASS is always performed asynchronously.

1997 Feb 03 5
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

REFBP (PIN 5) YO (PIN 14)

Decoupling capacitor for the band-pass filter reference VBS output signal. This output can be switched between
voltage. the comb filtered luminance signal (including
synchronization) and the external (C)VBS signal from the
SSYN (PIN 6) input Yext/CVBS. In COMB-mode the output signal is
delayed by 2 lines (1 line at NTSC) and by an additional
Input signal that controls the function of BYP (pin 3).
processing delay.
VCCA, VCCO, VDDD AND VCCPLL (PINS 7, 8, 22 AND 27)
Table 6 YO output signal
Supply voltages.
MODE YO OUTPUT SIGNAL
AGND, OGND, DGND AND PLLGND (PINS 9, 11, COMB comb filtered luminance signal
21 AND 26) BYPASS external CVBS signal of Yext/CVBS input
Ground connection. AGND is used as signal reference for
all analog input and output signals. CVBSO (PIN 15)
CVBS output signal directly from the input in
Cext (PIN 10) BYPASS-mode or delayed by the signal processing time
Input for an external chrominance signal which is of 2 lines (1 line at NTSC) and an additional processing
correlated to the external VBS signal. delay.

CO (PIN 12) Table 7 CVBSO output signal

Chrominance output signal. This output can be switched MODE CVBSO OUTPUT SIGNAL
between the comb filtered chrominance from the CVBS COMB delay compensated CVBS signal
signal and the external chrominance signal from the input BYPASS external CVBS signal of Yext/CVBS input
Cext if the IC is forced into BYPASS-mode.
Yext/CVBS (PIN 17)
Table 4 CO output signal
Input for the CVBS signal or for an external VBS signal.
MODE CO OUTPUT SIGNAL
COMB comb filtered chrominance signal LPFION (PIN 18)
BYPASS external chrominance signal of Cext input Input signal to disable the internal pre-filter LPFI.

FSCSW (PIN 13) Table 8 Pre-filter mode

Input signal to select between fsc or 2 × fsc as reference at LPFION SELECTED MODE
the FSC input pin.
LOW LPFI inactive
Table 5 Reference frequency selection HIGH LPFI active
Floating LPFI active
FSCSW SELECTED REFERENCE
HIGH 2 × fsc CSY (PIN 19)
LOW fsc
Sync top capacitor for the sync separator.

1997 Feb 03 6
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

SYS1 AND SYS2 (PINS 20 AND 23) The comb filter output BPF reduces the alias components
that are the result of the non-linear signal processing within
System switch input signals to adapt the signal processing
the logical comb filter.
to the different CVBS standards.
LOGICAL COMB FILTER
Table 9 System switch input signals
Separates the chrominance from the band-pass filtered
SYS1 SYS2 STANDARD CVBS signal.
LOW LOW PAL M
LOW HIGH PAL B, G, H, D and I; note 1 COMPENSATION DELAY
HIGH LOW NTSC M Compensates the internal processing time of the
HIGH HIGH PAL N band-pass filters and the logical comb filter section.

Note ADDER
1. The standard PAL B, G, H, D and I is internally preset The comb filtered luminance output signal is obtained by
as default. adding the delayed CVBS signal and the inverted comb
filtered chrominance signal.
REFDL (PIN 24)
Decoupling capacitor for the delay line reference voltage. LOW-PASS FILTER INPUT (LPFI)
Analog input low-pass filter to reduce the outband
COMBENA (PIN 25) frequencies of EMC. The input low-pass filter is included in
Output signal that indicates the current mode of operation. the signal path but it can be switched off via the input
This output is forced to LOW if the comb filter is in signal LPFION.
BYPASS-mode.
LOW-PASS FILTER OUTPUTS (LPFO1 AND LPFO2)
Table 10 Mode of operation Two different types of output low-pass filters (LPFO1 and
COMBENA SELECTED MODE LPFO2) are necessary to get equal signal delays within the
luminance path and the chrominance path (important for
LOW BYPASS-mode; PLL and clock good transient behaviour). The low-pass output filter type
processing stopped LPFO1 is used for the luminance output while LPFO2 is
HIGH COMB-mode used for the chrominance output. The filters are analog 3rd
order elliptic low-pass filters that convert the output signals
Internal functional description from the time discrete to the time continuous domain
(reconstruction filter).
SWITCHED CAPACITOR DELAY LINE
Delays the CVBS input signal by 2 lines and 4 lines LPF CONTROL
(all PAL standards) or by 1 line and 2 lines (NTSC
Automatic tuning of the low-pass filters is achieved by
standard). Input signals for the delay lines are the CVBS
adjusting the filter delays. The control information for all
signal, the clock CL3 (3 × fsc), the control signal HSEL and
filters (CONT1 and CONT2) is derived from a built-in
the standard selection signal SYSPAL.
reference filter (LPFO1-type) that is part of a control loop.
Output signals are the non-delayed, the 2-line delayed and The control loop tunes the reference filter delay and thus
the 4-line delayed CVBS signal (PAL) or the 1-line delayed all other filter delays to a time constant derived from the
and the 2-line delayed CVBS signal (NTSC). system clock CL3.

SWITCHED CAPACITOR BAND-PASS FILTERS (BPFS) CONTROL AND CLOCK PROCESSING (CLOCK CONTROL)
The comb filter input BPFs attenuate the low frequencies The control and clock processing block (see Fig.9)
to guarantee a correct signal processing within the logical consists of the sub-blocks PLL, the clock processing and
comb filter. the mode control. The PLL and the clock processing are
released for operation if the input level at BYP selects the
COMB-mode.

1997 Feb 03 7
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

Main tasks of the control and clock processing are: Table 11 Function of STOPS signal
• Clock generation of system clock CL3 STOPS-STATE SELECTED MODE
• Delay line start control
LOW COMB
• Mode control. HIGH BYPASS
The signal processing is based on a 3 × fsc system clock
(CL3), that is generated by the clock processing from the HORIZONTAL AND VERTICAL SYNC SEPARATOR
fsc signal at FSC (pin 1) via a PLL. Because the subcarrier
A built-in sync separator circuit generates the HDET and
frequency divided by the line frequency results not in an
VDET signals from the Yext/CVBS input signal. This circuit
integer value a clock phase correction of 180° is necessary
is still operating properly at input signals with a 12 dB
every second line for PAL standards or every line for
attenuated sync in a normal 700 mV black-to-white video
NTSC standard. The clock phase correction is controlled
signal (see Fig.4).
by the input signals horizontal sync. Additionally the delay
line start is synchronized once a field to the input signals
CLAMP
horizontal sync. The 25 Hz PAL offset is corrected in this
way. The black level clamping of the video input signal is
performed by the sync separator stage. The clamping level
The PLL provides a master clock MCK of 6 × fsc, which is
is nearly adequate to the voltage at REFDL (pin 24).
locked to the subcarrier frequency at FSC (pin 1).
The system clock CL3 (3 × fsc) is obtained from MCK by a SIGNAL SWITCH S1
divide-by-two circuit. The 180° phase shift is generated by
stopping the divide-by-two circuit for one MCK clock cycle. The switch is included to bypass the low-pass input filter.

The generated clock is a pseudo-line-locked clock that is For the CVBS input of the delay line block two signals can
referenced to fsc. The sync separator generates the be selected via the slow signal switch S1.
necessary signals HDET and VDET indicating the line (H)
and the field (V) sync periods. Table 12 Function of signal switch S1

The current mode of operation (BYPASS or COMB) is LPFION-STATE DELAY LINE INPUT
external readable via COMBENA (pin 25). LOW non-pre-filtered input signal
The input signals of the control and clock processing Yext/CVBS
(CLOCK CONTROL) are: HIGH pre-filtered input signal Yext/CVBS
HDET: analog horizontal pulse from sync separator Floating pre-filtered input signal Yext/CVBS
VDET: analog vertical pulse from sync separator
SIGNAL SWITCH S2A
FSC: subcarrier frequency (fsc or 2 × fsc)
For the CVBSO output two signals can be selected via the
FSCSW: reference frequency selection
signal switch S2A.
BYP: BYPASS control signal
SSYN: vertical synchronous mode selection for BYP Table 13 CVBSO output signal
and polarity selection of BYP.
CVBSO OUTPUT
The output signals are: STOPS-STATE MODE
SIGNAL
CL3: system clock (3 × fsc) LOW delayed input CVBSDL COMB
HSEL: line start signals for the delay lines HIGH non-delayed input BYPASS
STOPS: forces the comb filter via the switches S2A, Yext/CVBS
S2B and S2C into the BYPASS-mode (always
asynchronous) or COMB-mode (synchronous or SIGNAL SWITCH S2B AND S2C
asynchronous with VINT; depending on SSYN)
Two switches are included to bypass the comb filter signal
COMBENA: HIGH during COMB-mode; otherwise processing. The input video signal Cext for the switch S2C
LOW. is internally biased.

1997 Feb 03 8
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

For the YO output two signals can be selected via S2B For the CO output two signals can be selected via S2C
(see Table 14). (see Table 15).

Table 14 YO output signal Table 15 CO output signal

STOPS-STATE YO OUTPUT SIGNAL MODE STOPS-STATE CO OUTPUT SIGNAL MODE

LOW YCOMB COMB LOW CCOMB COMB
(combed luminance) (combed chrominance)
HIGH input Yext/CVBS BYPASS HIGH input Cext BYPASS

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage − 6.5 V
V input voltage protection threshold except pin 1 −0.3 VCC + 0.3 V
ICC total supply current − 155 mA
IO output current (CO, YO and CVBSO) − ±15 mA
output current (COMBENA) − 10 mA
Ptot total power dissipation − 900 mW
Tamb operating ambient temperature 0 70 °C
Tstg storage temperature −25 +150 °C
Ves electrostatic handling note 1

Note
1. Human Body Model: C = 100 pF; R = 1.5 kΩ; V = 2 kV; machine model: C = 200 pF; R = 0 Ω; V = 300 V.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air 31 K/W

1997 Feb 03 9
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

CHARACTERISTICS
VDDD = VCCA = VCCO = VCCPLL = 5 V; Tamb = 25 °C; input signal Yext/CVBS = 1 V (p-p) (0 dB); input signal
C = 0.7 V (p-p) (0 dB); input signal FSC = 200 mV (p-p), sine wave, DC level = 2 V; input signal LPFION = 5 V; test
signal: EBU colour bar 100/0/75/0 “CCIR471-1”; source impedance for Yext/CVBS, Cext = 75 Ω decoupled with 100 nF;
source impedance for FSC = 75 Ω; load impedance for CVBSO, YO, CO = 1 kΩ and 20 pF in parallel; unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply voltage
VCCA analog supply voltage (pin 7) note 1 4.75 5 5.5 V
VCCO analog supply voltage output buffer note 1 4.75 5 5.5 V
(pin 8)
VDDD digital supply voltage (pin 22) note 1 4.75 5 5.5 V
VCCPLL analog supply voltage PLL (pin 27) note 1 4.75 5 5.5 V
FSC (pin 1)
V1(p-p) input AC voltage (peak-to-peak value) 100 200 400 mV
input AC voltage is valid for
sine wave − − − −
square wave 0.4 0.5 0.6 duty
cycle
V1 input DC level 0 − 5.3 V
C1 input capacitance − − 10 pF
Ileak input leakage current − − 10 µA
Z1 source impedance − − 800 Ω
BYP (pin 3)
VIH HIGH level input voltage 2.4 − VCC V
VIL LOW level input voltage 0 0.85 1.5 V
Ileak input leakage current − − 10 µA
C3 input capacitance − − 10 pF
REFBP (pin 5)
V5 DC voltage 1.1 1.25 1.4 V
SSYN (pin 6)
VIH HIGH level input voltage 2.4 − VCC V
VIL LOW level input voltage 0 0.85 1.5 V
Ileak input leakage current − − 10 µA
C6 input capacitance − − 10 pF
VCCA (pin 7)
ICCA analog supply current − 35 40 mA
VCCO (pin 8)
ICCO supply current − 70 90 mA

1997 Feb 03 10
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Cext (pin 10)
V10 input voltage (AC coupled) − 0 3 dB
R10 input resistance 1.25 V 500 700 1000 kΩ
C10 input capacitance − − 10 pF
Z10 source impedance − − 1 kΩ
CO (pin 12)
V10/V12 BYPASS-mode: CO/Cext fsc ±0.3fsc; note 2 −1 0 +1 dB
COMB-mode: transfer function C-path see Fig.10
V12 DC offset voltage related to input −400 0 +400 mV
∆V12 DC jump when forcing into − 100 450 mV
BYPASS-mode
R12 output resistance − 10 100 Ω
RL load resistance (to ground) 0.3 − − kΩ
CL load capacitance (to ground) − − 25 pF
V17/V12 suppression (comb depth) see Figs 5 and 7;
note 3
PAL B, G, H, D, I 283 × fH 26 30 − dB
(283 − 43) × fH 20 24 − dB
(283 + 35) × fH 20 24 − dB
PAL M, NTSC M 227 × fH 26 30 − dB
(227 − 35) × fH 20 24 − dB
(227 + 28) × fH 20 24 − dB
PAL N 229 × fH 26 30 − dB
(229 − 35) × fH 20 24 − dB
(229 + 28) × fH 20 24 − dB
FPN fixed pattern noise for divided clock 0.75fsc − − −30 dB
frequencies referenced to 0.7 V (p-p) fsc − − −50 dB
1.5fsc − − −37 dB
2fsc − − −30 dB
αcr crosstalk suppression at vertical see Fig.3 26 30 − dB
transients no-colour ↔ colour
(0.7 V/Veff)
S/N signal-to-noise ratio (0.7 V/Veff noise) unweighted; 56 72 − dB
fsc ±0.3fsc; note 2
αcr crosstalk between different inputs 0 to 5 MHz − −60 −40 dB
V12(p-p) FSC residue in BYPASS-mode related − − −60 dB
to 700 mV (p-p)
Gd differential gain 0.95 − −

1997 Feb 03 11
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

FSCSW (pin 13)
VIH HIGH level input voltage 2 − VCC V
VIL LOW level input voltage 0 − 0.8 V
C13 input capacitance − − 10 pF
Ileak input leakage current − − 10 µA
YO (pin 14)
V14/V17 BYPASS-mode: CO/Cext 0 to 5 MHz −1 0 +1 dB
COMB-mode: transfer function Y-path see Fig.11
V14 DC offset voltage related to input −400 0 +400 mV
∆V14 DC jump when forcing into − 200 450 mV
BYPASS-mode
R14 output resistance − 10 100 Ω
RL load resistance (to ground) 0.3 − − kΩ
CL load capacitance (to ground) − − 25 pF
V17/V14 suppression (comb depth) see Figs 6 and 8;
note 3
PAL B, G, H, D, I 283.75 × fH 26 30 − dB
(283.75 − 43) × fH 10 12 − dB
(283.75 + 35) × fH 18 24 − dB
PAL M 227.25 × fH 26 30 − dB
(227.25 − 35) × fH 10 12 − dB
(227.25 + 28) × fH 18 24 − dB
PAL N 229.25 × fH 26 30 − dB
(229.25 − 35) × fH 10 12 − dB
(229.25 + 28) × fH 18 24 − dB
NTSC M 227.5 × fH 26 30 − dB
(227.5 − 35) × fH 10 12 − dB
(227.5 + 28) × fH 18 24 − dB
FPN fixed pattern noise for divided clock 0.75fsc − − −40 dB
frequencies referenced to 0.7 V (p-p) fsc − − −30 dB
black-to-white
1.5fsc − − −30 dB
2fsc − − −20 dB
αcr crosstalk suppression at vertical see Fig.3 26 30 − dB
transients gray ↔ multi-burst
(0.7 V/Veff)
S/N signal-to-noise ratio (0.7 V/Veff noise) unweighted; 56 72 − dB
200 kHz to 5 MHz
αcr crosstalk between different inputs 0 to 5 MHz − −60 −40 dB
V14(p-p) FSC residue in BYPASS-mode related − − −60 dB
to 700 mV (p-p)
Gd differential gain 0.95 − −

1997 Feb 03 12
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CVBSO (pin 15)
V15/V17 BYPASS-mode: CVBSO/CVBS 0 to 5 MHz −1 0 +1 dB
COMB-mode: transfer function CVBS-path see Fig.11
V15 DC offset voltage −400 0 +400 mV
∆V15 DC jump when forcing into − 200 450 mV
BYPASS-mode
R15 output resistance − 10 100 Ω
RL load resistance (to ground) 0.3 − − kΩ
CL load capacitance (to ground) − − 25 pF
FPN fixed pattern noise for divided clock 0.75fsc − − −40 dB
frequencies referenced to 0.7 V (p-p) fsc − − −30 dB
black-to-white
1.5fsc − − −30 dB
2fsc − − −20 dB
S/N signal-to-noise ratio (0.7 V/Veff noise) unweighted; 56 72 − dB
200 kHz to 5 MHz
αcr crosstalk between different inputs 0 to 5 MHz − −60 −40 dB
V15(p-p) FSC residue in BYPASS-mode related − − −60 dB
to 700 mV (p-p)
Gd differential gain 0.95 − −
Pd differential phase − 2 3 deg
Yext/CVBS (pin 17)
V17 input voltage (AC coupled) 12 dB sync −3 0 +3 dB
attenuation
possible; see Fig.4
I17 input current during sync pulse −10 −8.0 − µA
during active video − 0.84 1.5 µA
V17 DC voltage during black level 1.1 1.25 1.4 V
Z17 source impedance − − 1 kΩ
LPFION (pin 18)
VIH HIGH level input voltage 2 − VCC V
VIL LOW level input voltage 0 − 0.8 V
I18 input current 0.8 V − 8 20 µA
2.0 V − 8 20 µA
C18 input capacitance − − 10 pF
CSY (pin 19)
V19 DC voltage 0 2 VCC V

1997 Feb 03 13
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SYS1 (pin 20)
VIH HIGH level input voltage 2 − VCC V
VIL LOW level input voltage 0 − 0.8 V
I20 input current 0.8 V − 7.5 20 µA
2.0 V − 7.5 20 µA
C20 input capacitance − − 10 pF
VDDD (pin 22)
IDDD supply current − 10 20 mA
SYS2 (pin 23)
VIH HIGH level input voltage 2 − VCC V
VIL LOW level input voltage 0 − 0.8 V
I23 input current 0.8 V − 8 20 µA
2.0 V − 8 20 µA
C23 input capacitance − − 10 pF
REFDL (pin 24)
V24 DC voltage 1.1 1.25 1.4 V
COMBENA (pin 25)
VOL LOW level output voltage 3 mA 0.26 0.4 0.55 V
VOH HIGH level output voltage 4 − VCC V
IOH HIGH level output current 2.4 V −55 −24 − µA
VCCPLL (pin 27)
I27 supply current − 1.5 3 mA
Notes
1. ∆V = V CCA – V DDD ≤ 300 mV ∆V = V CCA – V CCPLL ≤ 300 mV
∆V = V CCA – V CCO ≤ 300 mV ∆V = V CCO – V CCPLL ≤ 300 mV
∆V = V CCO – V DDD ≤ 300 mV ∆V = V DDD – V CCPLL ≤ 300 mV
All voltages are related to AGND.
2. fsc = subcarrier frequency
fsc = 4.43361875 MHz for PAL B, G, H, D, I
fsc = 3.57561149 MHz for PAL M
fsc = 3.58205625 MHz for PAL N
fsc = 3.579545 MHz for NTSC M.
3. fH = line frequency
fH = 15.625 kHz for PAL B, G, H, N, D, I
fH = 15.734264 kHz for PAL M, NTSC M.

1997 Feb 03 14
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

handbook, full pagewidthinput

line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8

output

vertical transient MHA367

Output voltage measured in Veff related to 0.7 V input voltage.

Fig.3 Vertical transmission by different video signals from line to line.

handbook, full pagewidth

1.0

(V)

0.45

0.3
0.225

0.15

0
MHA370

Fig.4 EBU colour bar 100/0/75/0 with 12 dB sync attenuation.

1997 Feb 03 15
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

handbook, full pagewidth

U, V: PAL B, G, H, D, I
fsc (U, V: PAL M, N)

V U
(U) (V)

Y Y

(n − 1)fH (n − 0.75)fH (n − 0.25)fH nfH MHA548

Fig.5 Principle frequency response of a comb filtered PAL chrominance signal.

handbook, full pagewidth

U, V: PAL B, G, H, D, I
fsc (U, V: PAL M, N)

Y Y

V U
(U) (V)

(n − 1)fH (n − 0.75)fH (n − 0.25)fH nfH MHA549

Fig.6 Principle frequency response of a comb filtered PAL luminance signal.

1997 Feb 03 16
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

handbook, full pagewidth

fsc

Y Y

(n − 1)fH (n − 0.5)fH nfH MHA550

Fig.7 Principle frequency response of a comb filtered NTSC chrominance signal.

handbook, full pagewidth

fsc

Y Y

(n − 1)fH (n − 0.5)fH nfH MHA551

Fig.8 Principle frequency response of a comb filtered NTSC luminance signal.

1997 Feb 03 17
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

handbook, full pagewidth

1
SSYN 1
&
VINT

& 1
=1 COMBENA

BYP

STOPS
1

CL3
CL3
HDET 4
HSEL
VDET
CLOCK
PROCESSING SYSPAL
SYS1
VINT
SYS2

FSC MCK
PLL
FSCSW

STOP MHA552

Fig.9 Clock control.

1997 Feb 03 18
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

handbook, full pagewidth

gain
MGL067
(dB)
+1
0

−2
−3

−25
−30

0.4 0.66 0.85 1 1.12 1.35 2.0 frequency (fsc)

Fig.10 Chrominance path: tolerance band with anti-alias filter.

gain
handbook, full pagewidth
(dB)

+1
0
−1
−2

−3

−5

−32
0.7 1 1.12 1.5 2.26 2.7
frequency (fsc)
MHA373

Fig.11 Luminance and CVBSO path: tolerance band with anti-alias filter.

1997 Feb 03 19
1997 Feb 03
handbook, full pagewidth
FSC
FSC i.c. VDDDS
Philips Semiconductors

1 28 VDDD 33 µH 1

75 Ω i.c. VCCPLL 10 100 100 2

2 27 VCCPLL nF nF µF

BYP PLLGND
3 26
VCCOS
COMBENA VCCO
i.c. COMBENA 33 µH 1
4 25
TEST AND APPLICATION INFORMATION

10 100 100 2
47 Ω REFBP REFDL nF nF µF
5 24
100 100
100 nF nF µF
SSYN
6 VDDD VCCAS
Integrated multistandard comb filter

VCCA 33 µH 1
SYS2
VCCA 23
VCCA 7 2
10 100 100

20
VDDD nF nF µF
VCCO
SAA4961 22
VCCO 8
DGND
21
AGND VCCPLLS
9 SYS1
VCCPLL 33 µH 1
75 Ω 20
Cext
Cext CSY 10 100 100 2
10 19 nF nF µF
100 nF 100 nF
OGND LPFION
11 18 MHA553
SVHS CVBS
4 SVHS-C CO Yext/CVBS
12 17
3 10 kΩ
100 nF
2 FSCSW i.c. 75 Ω
13 16
1
10 kΩ VDDD YO CVBSO
14 15
SVHS-Y 10 kΩ

Fig.12 Test circuit.

SAA4961
Preliminary specification
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

handbook, full pagewidth

I2C-bus
PCF8574

I2C-I/O PORT
5.6 kΩ

SYS1 SYS2 COMBENA BYP FSC

20 23 25 3 1
Cext CO
SVHS-C 10 12 TDA9141 −(R − Y)

SAA4961 MSD
YO
SVHS-VBS 14 −(B − Y)
TDA8540 COMB FILTER TDA4665
CVBS1 Yext/CVBS CVBSO
17 15 BBDL VB
SWITCH
CVBS2 6 13
SSYN FSCSW
I2C-bus CVBSO I2C-bus
+5 V
MHA554

Fig.13 Application diagram: SAA4961 with TDA9141.

handbook, full pagewidth +5 V

3.3 kΩ
I2C-bus 1 kΩ
PCF8574

I2C-I/O PORT BC548

3.58 MHZ 4.43 MHZ

COMBENA SYS2 SYS1 BYP FSC
25 23 20 3 1
Cext CO
SVHS-C 10 12 TDA9160/62 −(R − Y)
MSD
SAA4961 YO −(B − Y)
SVHS-VBS COMB FILTER 14
VB
TDA8540 CVBSO TDA4665
CVBS1 Yext/CVBS
17 15 BBDL TXT
SWITCH
CVBS2 6 13
SSYN FSCSW
I2C-bus I2C-bus
+5 V
MHA555

Fig.14 Application diagram: SAA4961 with TDA9160/62.

1997 Feb 03 21
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

handbook, full pagewidth

I2C-bus
PCF8574

I2C-I/O PORT
IF input

SYS2 SYS1 BYP FSC

23 20 3 1
Cext CO
SVHS-C 10 12 TDA8366 R

SAA4961 MSD
YO
SVHS-VBS 14 G
TDA8540 COMB FILTER TDA4665
CVBS1 Yext/CVBS CVBSO
17 15 BBDL B
SWITCH
CVBSint 6 13
SSYN FSCSW
I2C-bus CVBSO I2C-bus

MHA556

Fig.15 Application diagram: SAA4961 with TDA8366.

1997 Feb 03 22
1997 Feb 03
I2C-bus
PCF8574
Philips Semiconductors

I2C-I/O PORT

NT4
NT3
SECAM
PAL

2 × FSC

PAL SECAM NT3 NT4

BYP SYS1 SYS2 FSC
CHROMINANCE TDA4655
3 20 23 1 BANDPASS MSD −(R − Y)
Integrated multistandard comb filter

Cext CO
SVHS-C 10 12 TDA4665 −(B − Y)
BBDL

23
SAA4961 PAL SECAM NT3 NT4
SVHS-VBS COMB FILTER LUMINANCE
TRAP
TDA8540 Yext/CVBS VBS
CVBS1 YO
17 14
SWITCH
CVBSO
CVBS2 6 13 15 CVBSO

SSYN FSCSW
I2C-bus MHA557
+5 V

Remark: all switches in LOW position.

handbook, full pagewidth

Fig.16 Application diagram: SAA4961 with TDA4655.

SAA4961
Preliminary specification
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

PACKAGE OUTLINE

DIP28: plastic
handbook, full pagewidthdual in-line package; 28 leads (600 mil) SOT117-1
seating plane

D ME

A2 A

L A1

c
Z e w M
b1
(e 1)
b
28 15 MH

pin 1 index

1 14

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A A1 A2 Z (1)
UNIT max. min. max. b b1 c D (1) E (1) e e1 L ME MH w max.
1.7 0.53 0.32 36.0 14.1 3.9 15.80 17.15
mm 5.1 0.51 4.0 2.54 15.24 0.25 1.7
1.3 0.38 0.23 35.0 13.7 3.4 15.24 15.90
0.066 0.020 0.013 1.41 0.56 0.15 0.62 0.68
inches 0.20 0.020 0.16 0.10 0.60 0.01 0.067
0.051 0.014 0.009 1.34 0.54 0.13 0.60 0.63

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

92-11-17
SOT117-1 051G05 MO-015AH
95-01-14

1997 Feb 03 24
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

SOLDERING The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the
Introduction
specified maximum storage temperature (Tstg max). If the
There is no soldering method that is ideal for all IC printed-circuit board has been pre-heated, forced cooling
packages. Wave soldering is often preferred when may be necessary immediately after soldering to keep the
through-hole and surface mounted components are mixed temperature within the permissible limit.
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for Repairing soldered joints
printed-circuits with high population densities. In these
Apply a low voltage soldering iron (less than 24 V) to the
situations reflow soldering is often used.
lead(s) of the package, below the seating plane or not
This text gives a very brief insight to a complex technology. more than 2 mm above it. If the temperature of the
A more in-depth account of soldering ICs can be found in soldering iron bit is less than 300 °C it may remain in
our “IC Package Databook” (order code 9398 652 90011). contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1997 Feb 03 25
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

NOTES

1997 Feb 03 26
Philips Semiconductors Preliminary specification

Integrated multistandard comb filter SAA4961

NOTES

1997 Feb 03 27
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Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

© Philips Electronics N.V. 1997 SCA53

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands 547047/1200/01/pp28 Date of release: 1997 Feb 03 Document order number: 9397 750 01688