Superlattices and Microstructures xxx (xxxx) xxx

Contents lists available at ScienceDirect

Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Performance evaluation of gate engineered InAs–Si heterojunction

surrounding gate TFET
M. Sathishkumar a, *, T.S. Arun Samuel a, K. Ramkumar b, I. Vivek Anand a, S.B. Rahi c
a
Department of ECE, National Engineering College, Kovilpatti, 628503, India
b
School of Electronics Engineering, Vellore Institute of Technology, Vellore, 632014, India
c
Department of Electrical Engineering, Indian Institute of Technology Kanpur, 208016, India

A R T I C L E I N F O A B S T R A C T

Keywords: In semiconductor industry, at nanoscale dimensions, numerous field effect devices have been
Analytical model proposed and investigated for further improvement in performance of low power circuit and
Heterojunction system. In the present research report, a novel low power FET device structure namely: Sur­
Surface potential
rounding Gate Triple Material Heterojunction Tunnel Field Effect Transistor (SGTM-heTFET) has
Surrounding gate
Tunneling
been proposed with the analytical modeling approach. The benefits of surrounding gate and
TFET tunnel FETs are coupled to create a new structure, to decrease short channel effects. Three
different gate materials with different work functions replace the gate material that surrounds the
device. An analytical model of surface potential(ψ), electric field(E) and drain current (IDS) have
been developed for SGTM-heTFET. With the use of low work function material such as 4.0eV,
4.6eV and 4.0eV, the proposed model shows a better ON current of 10− 5 A/μm for a VGS of 0.7V,
ON-OFF ratio of 1010 with the sub-threshold swing of 50mV/dec. The developed model’s for
SGTM-heTFET shows excellent device characteristics and have been verified using TCAD simu­
lation, ensuring the model’s accuracy.

1. Introduction

CMOS devices are scaled down to nanometre technology, in order to obtain low power consumption and noise immunity. Scaling
down, the devices in an assertive manner not only reduces the power but also offers more packaging density and switching speed. This
makes the device to suite for high frequency applications [1–4]. However, the limitations experienced are increase in short channel
effects and degradation in the device performance. The degradation is caused not only because of the short channel effect but also due
to the increase in subthreshold swing than fundamental limit in the MOSFET. It raises above 60 mV/decade and increases the leakage
current (OFF current) [4–6]. One of the promising devices that offers low power application is Tunnel FET (TFET), which works under
reverse bias condition and has a p-i-n (p-type; intrinsic; n-type) structure. TFET works on the principle of injecting the majority carrier
through the source region by which it reaches the channel by band-to-band tunnelling mechanism. This makes the subthreshold swing
to limit its value to 60 mV/decade. However, the major limitation of TFET is the ON current. Due to this low ON current the per­
formance of the device gets affected. In order to overcome the drawbacks, various device architectures like dual gate, triple gate, GAA,
surrounding gate and quadruple gate architectures are proposed [7–11] and various device geometry modifications also caried out

* Corresponding author.
E-mail addresses: [email protected] (M. Sathishkumar), [email protected] (T.S.A. Samuel), [email protected]
(K. Ramkumar), [email protected] (I.V. Anand), [email protected] (S.B. Rahi).

https://doi.org/10.1016/j.spmi.2021.107099
Received 16 July 2021; Received in revised form 19 October 2021; Accepted 19 November 2021
Available online 20 November 2021
0749-6036/© 2021 Elsevier Ltd. All rights reserved.

Please cite this article as: M. Sathishkumar, Superlattices and Microstructures, https://doi.org/10.1016/j.spmi.2021.107099
M. Sathishkumar et al. Superlattices and Microstructures xxx (xxxx) xxx

Fig. 1. Structure of surrounding gate triple material heterojunction TFET.

Fig. 2. 3D view of Surrounding Gate Triple Material Heterojunction TFET.

Table 1
Device parameters.
Parameters Value

Doping at Source 1x1020 cm− 3

Doping at Channel 1x1017 cm− 3

Doping at Drain 5x1018 cm− 3

Silicon Body thickness (tsi) 20 nm

Oxide layer thickness(tox) 1 nm
High-k material thickness(thigh-k) 1 nm
Channel length (Lch) 45 nm
Metal work function (φM1, φM2, φM3) 4.0–4.7eV
(Al, Mo, Sb)
Metal Gate Lengths (L1, L2, L3) 15 nm, 15 nm, 15 nm

[12–19]. This lowering of subthreshold swing regime makes the improvement in device performance and also reduces the static power
consumption.

2. Device structure and simulation model

In this work, heterojunction arrangement namely, Indium Arsenide (InAs) –Si with triple material and surrounding gate geometry
are merged to form a new structure. InAs exhibits thin bandgap and high mobility taken as source material and Silicon material is used
in channel and drain region. The probability of the tunnelling & drain current is enhanced by reducing the tunnelling barrier width
between source-channel by which band bending occurs and this is made possible by the introduction InAs material. Here, to decrease
the leakage current through gate oxide layer, high-k dielectric (Hafnium oxide) oxides are used and also to minimize the scattering due

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M. Sathishkumar et al. Superlattices and Microstructures xxx (xxxx) xxx

Fig. 3. Energy band diagram of SGTM-heTFET for OFF & ON State.

Fig. 4. Energy band diagram and minimum tunneling path of SGTM-heTFET.

to phonons, to increase the carrier mobility an intermediate layer with SiO2 has been placed between the silicon channel and high-k
dielectric. Fig. 1 depicts the proposed device structure of SGTM-heTFET and Fig. 2 gives the 3-D view of the proposed device. The
proposed device structure is simulated using TCAD simulation tool and the several device parameters used in the simulation is given in
Table 1.
The band diagram of the proposed device structure is given in Fig. 3a and b which depicts the band diagrams in ON and OFF state.
The existence of large potential barrier between the source and channel during the OFF state resulted in no tunneling. As the gate
voltage surpasses the threshold voltage, the potential barrier becomes narrower which in turn allows notable amount of tunneling
current (see Fig. 4).

3. Analytical model

3.1. Surface potential model

The Poisson equation in cylindrical coordinates is given as follows

( ) ( )
1 ∂ ∂φ(r, z) ∂2 φ r, z qNC
r + =− (1)
r ∂r ∂r ∂z2 εsi

for. 0 ≤ z ≤ L , 0 ≤ r ≤ R
where, φ(r,z) – represents the 2D potential profile.

NC – channel doping
εsi – silicon permittivity
R – radius of silicon nanowire
➢ Using Young’s approximation

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M. Sathishkumar et al. Superlattices and Microstructures xxx (xxxx) xxx

φi (r, z) = f0i (z) + f1i (z) r + f2i (z)r2 (2)

Where f0i (r, z), f1i (z), f2i (z) are used as Z functions and i = 1,2,3.
Region 1: 0 ≤ z ≤ L1

φ1 (r, z) = f01 (z) + f11 (z) r + f21 (z)r2 (3)

Region 2: L1 ≤ z ≤ L2

φ2 (r, z) = f02 (z) + f12 (z) r + f22 (z)r2 (4)

Region 1: L2 ≤ z ≤ L3

φ3 (r, z) = f03 (z) + f13 (z) r + f23 (z)r2 (5)

The Poisson equation is solved by using necessary boundary condition, resulting in a potential profile.

1. The value of electric field is zero at the Centre for silicon, therefore
⃒
dφ(r, z)⃒⃒
(6)
dr ⃒ r=0

φ(0, z) = φC (z) this will give.

f11 (z) = f12 (z) = f13 (z) = 0, where φC (z) represents center potential.

2. Surface potential is derived from equations (3)–(5) and calculated by replacing the variables r as R, thus generally written as,

φi (r, z) = φCi (z) + f2i (z) r2 , ​ i = 1, 2, 3 (7)

3. The electric field at the silicon and the dielectric interface can be written as
⃒
dφ1 (r, z)⃒⃒ εox VGS1 − φS1 (z)
= (8)
dr ⃒r=R εsi ′
toxeq
⃒
dφ2 (r, z)⃒⃒ εox VGS2 − φS2 (z)
= (9)
dr ⃒r=R εsi ′
toxeq
⃒
dφ3 (r, z)⃒⃒ εox VGS3 − φS3 (z)
= (10)
dr ⃒r=R εsi ′
toxeq

Where toxeq = tox + εtóxox [thigh− + tox ]

′
k

tóx − SiO2 thickness

tox − HfO2 thickness

εox − Permittivity of SiO2

Using the above boundary conditions, the value of center potential can be obtained as
[ ]
εox VGS1 1 εox VGS1
φC1 (z) = φS1 (z) 1 + ′ R − ′ R ; ​ 0 ≤ z ≤ L1 (11)
2εsi toxeq 2 εsi toxeq

[ ]
εox VGS2 1 εox VGS2
φC2 (z) = φS2 (z) 1 + ′ R − ′ R; L1 ≤ z ≤ L2 (12)
2εsi toxeq 2 εsi toxeq

[ ]
εox VGS3 1 εox VGS3
φC3 (z) = φS3 (z) 1 + ′ R − ′ R ; L2 ≤ z ≤ L3 (13)
2εsi toxeq 2 εsi toxeq

The above equations represent the center potential at three different material regions. Substituting equations (7)–(11) in the given
Poisson equation in (1) and after simplification,

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M. Sathishkumar et al. Superlattices and Microstructures xxx (xxxx) xxx

[ ]
2 εox VGS1 − φS2 (z) d2 φC1 (z) d2 φS1 (z) r2 εox 1 qNC
′ + − − ′ =− (14)
R εsi toxeq dz2 dz2 2R εsi toxeq εsi
[ ]
2 εox φS2 (z) d2 φS1 (z) r2 εox 1 qNC 2 εox VGS1 d2 φC1 (z)
− ′ − − ′ =− − ′ − (15)
R εsi toxeq dz 2 2R εsi toxeq εsi R εsi toxeq dz2
( )( )
qNC VGS
Let. λ2 = R
toxeq α = λ12 and βi = − therefore equation (15) becomes
εox ′
2 εsi εsi − λ2

[ ]
d2 φS1 (z) r2 εox 1 d2 φC1 (z)
− αφS1 (z) − − ′ = βi − (16)
dz2 2R εsi toxeq dz2

After rearranging the above expression with necessary substitutions, equation (16) can be expressed as

d2 φS1 (z)
− αφS1 (z) = βi (17)
dz2
The common solution for equation (17) can be written as
√̅̅ √̅̅ βi
φSi (z) = Ne αz
+ Oe− αz
− (18)
α
Equation (18) can be expressed as following to obtain surface potential expression for i = 1,2,3 and
√̅̅ √̅̅ β1
φS1 (z) = Ne αz
+ Oe− αz
− ; 0 ≤ z ≤ L1 under M1 (19)
α
√̅̅ √̅̅ β2
φS2 (z) = Ue α(z− L1 )
+ Ve− α(z− L1 )
− ; L1 ≤ z ≤ (L1 + L2 ) under M2 (20)
α
√̅̅ √̅̅ β3
φS3 (z) = Je α(z− L1 − L2 )
+ Ke− α(z− L1 − L2 )
− ; (L1 + L2 ) ≤ z ≤ L under M3 (21)
α

where N,O,U,V,J,K are arbitrary constants and the following boundary conditions are taken into consideration to solve for the con­
stants respectively.
At source side, heterojunction is formed since the source is made up of InAs and the channel is made up of Si and the potential is
given as φ(r, 0) = Vbi (S), where
{ }
1 [ ] NV
Vbi (s) = [χ 1 − χ 2 ] + 0.5 Eg1 − Eg2 + qVT ln (22)
q Ni

χ 1 − electron affinity of InAs

χ 2 − electron affinity of Si
At drain side, since both the channel and drain are made up of Si, the potential is given as.
φ(r, L) = Vbi (D) + VDS , where
( ) ( )
kT ND NC
Vbi (D) = ln 2
(23)
q ni
Surface potential at the edge of two different metals is continuous
φS1 (r, L1 ) = φS2 (r, L2 ) (24-a)

φS2 (r, L2 ) = φS3 (r, L3 ) (24-b)

At the edge of two different metals, the electric flux is,
⃒ ⃒
dφS1 (r, z)⃒⃒ dφ (r, z)⃒⃒
⃒ = S2 (25-a)
dz at z=L1 dz ⃒at z=L2
⃒ ⃒
dφS2 (r, z)⃒⃒ dφ (r, z)⃒⃒
⃒ = S3 (25-b)
dz at z=L2 dz ⃒at z=L3

Using the above boundary conditions, the values of the arbitrary constants in equation 19–21 can be obtained and written as

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M. Sathishkumar et al. Superlattices and Microstructures xxx (xxxx) xxx

( )
√̅̅ √̅̅ √̅̅̅
Vbi (S)e α(L1 +L2 +L3 )
− Vbi (D) − VDS + βα1 e α(L1 +L2 +L3 ) − βα2 + β2 − β1
2α
Sinh( α(L2 + L3 ))
O= √̅̅̅ (26)
2Sinh( α(L1 + L2 + L3 ))

β1
N = Vbi (S) − O + (27)
α
( )
√̅̅ β2 − β1
U = Ne αL1
+ (28)
2α
( )
β2 − β1 √̅̅
V= + Oe− αL1
(29)
2α
[ ]
√̅̅ √̅̅ β3
J = e− αL3
Vbi (D) + VDS − Ke− αL3
+ (30)
α
( )
√̅̅ √̅̅ √̅̅ √̅̅̅ √̅̅
(Vbi (D) + VDS )e− α(L3 +L1 )
+ βα3 e− α(L3 +L1 )
− Ne α L2
− β2 − β1
α Sinh( α (L2 − L1 )) + Oe− αL2
K= (31)
σ
√̅̅ √̅̅
where. σ is assumed to be = e− ( α (2L3 +L1 ))
+e αL1

3.2. Electric filed model

From equation (19) – (21), by differentiating, the vertical direction electric field is given by
− dφS1 (r) ( rλ√̅̅2 √̅̅ ) √̅̅̅
E1 (r) = = Ne − Oerλ 2 λ 2, 0 ≤ z ≤ L1 (32)
dr

− dφS2 (r) ( rλ√̅̅2 √̅̅ ) √̅̅̅

E2 (r) = = Ue − Verλ 2 λ 2, L1 ≤ z ≤ L1 + L2 (33)
dr

− dφS3 (r) ( rλ√̅̅2 √̅̅ ) √̅̅̅

E3 (r) = = Je − Kerλ 2 λ 2, L1 + L2 ≤ z ≤ L3 (34)
dr
Similarly, the electric field for the lateral direction can be calculated by differentiating equations (3)–(5) with respect to ‘z’ which is
given by Ez = dφdzS (z). Hence the total electric field can be obtained as
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
E = Er 2 + EZ 2

3.3. Drain current model

The tunneling process of drain current is computed by using Kane’s model [20], which describes the per unit volume generation
rate. When the BTBT current contribution is significant, the TFET current can be calculated as the sum of overall charge produced in
the device.
The drain tunnel current is given by
∫ ∫
Ids− tun = q GKANE dV = q W L GKANE dx (35)
TFET− Volume TFET− Volume

Where.
dV – elementary volume of the device, L,W- length and width of the gate, GKANE-generation rate. The Kane’s model obtained for a
semiconductor with direct bandgap in a uniform electric field is given by,
( / )
ED
(36)
3 /
GKANE = AKANE √̅̅̅̅̅ exp − BKANE Eg2 E
Eg

Where, AKANE, BKANE – material dependant constants, E-local electric field, Eg-bandgap, D-parameter separating the direct from the
indirect tunneling process.
The average electric field over the tunnel path is given by,
/
Eg q
E= (37)
lpath

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M. Sathishkumar et al. Superlattices and Microstructures xxx (xxxx) xxx

Where, lpath – tunnel path length.

The following assumptions are made to determine the TFETs tunnel current by considering the electrostatic potential profile of
TFET.

• The drain voltage has no effect on the potential profile in the region of the source channel where tunnelling occurs..
• The source doping for point tunnelling is high, so there is no depletion and potential drop in the source.
• There are no (inversion) charges in the channel and in the gate dielectric
• A gate dielectric with the same effective electrical thickness produces the same potential profile in the source and channel regions.

Tunneling of electrons is restricted in the proposed work by the assumption that tunnelling from the valance band to the conduction
band is permitted only when starting from an energy level lower than the hole fermi level.

3.4. Potential profile

The electrostatic potential in the underlying semiconductor is strictly controlled by the gate. The effect of the drain voltage is found
to be minor and can be ignored in the region directly beneath the gate. Adopting depletion region approximation.
The electric field obtained using depletion layer approximation is given by,
qNa
φ(z) = (x − xmax )2
2εS
For electrostatic potential, the electric field is expressed in terms of acceptor donor concentration
dφ qNa
E(x) = − = − (x − xmax )
dx εS
The tunnel current is determined by the potential profile in the source potential, which is perpendicular to the gate dielectric in line
tunnelling.
As described, depletion layer approximation for potential profile is given by,
φ=0 ; for x < xmax

qNA
φ= (x − xmax )2 ; for x > xmax (38)
2εS

Where, NA-source doping level, xmax-depletion starting position at source, εS - dielectric constant of the source.
To calculate lpath, the x coordinate of points of equivalent potential in the valance band and conduction band are considered.
2 Eg
The value of φV (x1 ) = qN
2εS (x1 − xmax ) +
A
q ; and

qNA
φC (x2 ) = (x2 − xmax )2
2εS
From the above equations tunneling path can be determined. The tunneling path length is given by.
lpath = x1 − x2 , on equating φV (x1 ) = φC (x2 ), it is obtained as
[( ( ) )2 ] 2ε E
S g
x2 + lpath − xmax − (x2 − xmax )2 = 2
q NA
After simplification
[ / ]
lpath 2 + 2Eg εS q2 NA
x2 ​ can ​ be ​ computed ​ as, ​ x2 = xmaxx − (39)
2lpath

Differentiate the above equation with respect to tunneling path length, lpath
( )
1 2Eg εS 1
dx = − 1− 2 × dlpath (40)
2 q NA lpath 2

Substitute the values of dx, E, GKANE in equation (35) Ids− tun can be obtained as

∫l2 ( )
Eg D− 1/2 ( √̅̅̅̅̅ ) 1 2Eg εS 1
Ids− tun =q W L AKANE exp − B KANE q E g lpath − 1 − × dlpath (41)
qD lpath D 2 q2 NA lpath 2
l1

Where, l1 and l2 denote the maximum and minimum tunnel path length in the depletion region.

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M. Sathishkumar et al. Superlattices and Microstructures xxx (xxxx) xxx

Fig. 5. Surface potential of SGTM-heTFET.

Fig. 6. Electric field of SGTM-heTFET with Vgs = 0.3V and 0.5V.

√̅̅̅̅̅̅̅̅̅̅̅̅ √̅̅̅̅̅̅̅̅( √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ )

2Eg εS 2εS Eg √̅̅̅̅̅̅̅̅̅
l1 = ; l2 = − ψ max − + ψ max
q2 NA qNA q

Where, ψ max – potential at the end of depletion layer.

The above integration can be simplified to an analytical formula by assuming that the exponent varies faster than the polynomial
factors as tunnelling length varies(lpath.)

4. Results and discussions

In this section, we have displayed a few analytical model results with the corresponding TCAD simulation results to show the
accurateness of the proposed model. In the simulation, band gap narrowing (BGN), Shockley–Read–Hall recombination (SRH),
electric-field-dependent Lombardi, a non-local band to band tunnelling models have been adopted. Here high-k dielectric (HfO2) oxide
is used to decrease the leakage current through gate oxide layer and also to minimize the scattering due to phonons. The reason for
SiO2 layer is to increase the carrier mobility. The surface potential, vertical electric field, lateral electric field and drain current
calculated using analytical expressions are perfectly matching with the results simulated using TCAD simulation tool. The proposed
triple material heterojunction surrounding gate TFET provides better electrical characteristics.
Fig. 5 provides the both analytical and simulated results of the surface potential for various gate to source voltages namely 0.1V,
0.3V, 0.5V and 0.7V. Increase in gate voltage results in increased potential in the lightly doped area. In the proposed stacked triple
material surrounding gate TFET, there is an abrupt change in the potential through the channel in the interface region of source and the
intrinsic region. The figure clearly shows that owing to the close proximity of gate bias, there is a revolutionary change in the potential
below the gate and which gives a major improvement in surface potential which leads to improved tunneling current. Simulated results

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M. Sathishkumar et al. Superlattices and Microstructures xxx (xxxx) xxx

Fig. 7. ID - VGS plot of Surrounding Gate Triple Material heterojunction TFET for different Gate work functions.

give better accuracy with the analytical results.

The different electric field profiles along the channel with various gate to source voltages (VGS = 0.3V & 0.5V) are shown in Fig. 6.
Apart from the source-channel junction, the electric field is very minimum for the entire channel area and it is getting some peak values
at the junction of different gate materials. It is observed that the peak value of the electric field occurs at the interface region of source
and channel with the value of 3x106 V/cm, which is the reason for the tunneling from source to channel and higher gate voltage
achieves better electric field at the tunnelling junction with increasing the tunnelling probability. The reason for the peak at the drain
side is due the drain influence of drain potential. The same results have also been related with the simulated one to check the cor­
rectness of the analytical one.
The drain current against gate voltage for different metal work functions are shown in Fig. 7. The results obtained by the model is in
good match with the simulated one. The figure compares four different plots by keeping φM1 = φM3 = 4.0eV and by varying the φM2 as
4.6eV and 4.7eV. Similarly, by keeping φM1 = φM3 = 4.1eV and by varying the φM2 as 4.6eV and 4.7eV. Due to the use of various gate
material work functions, the vertical electric field is increased. Further, the use of material with a low work function on the source side
results in a shortening of the tunnelling width, which improves the ON current. As stated above, the plot of VGS versus Ids with the work
functions of 4.0eV, 4.6eV and 4.0eV gives better ON current of 10− 5 A/μm, and the ON-OFF ratio of 1010 and also the sub-threshold
swing is measured as 50mV/dec when compared with the other three combinations.

5. Conclusion

In this work, an analytical model of surface potential, electric field and drain current have been developed for the proposed triple
material surrounding gate TFET with HfO2/SiO2 stacked arrangement. The use of stack arrangement is to expand the control of gate
along the channel, and thereby to increase the tunneling current. The drain current is calculated numerically using both the lateral and
vertical electric fields. The analytical model results have been compared with the simulated results which show a better accuracy. This
new device structure doubtlessly predicts enhanced gate control and shows remarkable characteristics and also with the help of work
function engineering, it has a higher drain current than its TFET counterparts.

Author statement

M.Sathishkumar: Conceptualization, Methodology and Writing – original draft preparation. T.S.Arun Samuel: Supervision, K.
Ramkumar: Simulation. I.Vivek Anand: Writing – review & editing: S.B.Rahi: Checked the comparison results and Validation.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to
influence the work reported in this paper.

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