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Adder

This project aims to design an efficient hybrid adder for high-speed applications. A 64-bit reconfigurable adder is proposed using a Carry Select Modified Tree adder to reduce area by 22% and power consumption by 47% compared to conventional designs. The adder is implemented in a 180nm CMOS technology at 1.8V. Simulation results show the adder achieves low area and power consumption suitable for multimedia applications requiring efficient arithmetic operations like addition.

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Tharak R
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13 views

Adder

This project aims to design an efficient hybrid adder for high-speed applications. A 64-bit reconfigurable adder is proposed using a Carry Select Modified Tree adder to reduce area by 22% and power consumption by 47% compared to conventional designs. The adder is implemented in a 180nm CMOS technology at 1.8V. Simulation results show the adder achieves low area and power consumption suitable for multimedia applications requiring efficient arithmetic operations like addition.

Uploaded by

Tharak R
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Title of the Project

Design of Delay Efficient Hybrid Adder for


High Speed Applications
Guide
XXXXXXX, XX
M.RAJA KUMAR (Phd),M.Tech
ECE Dept
Assistant Professor
PACE INSTITUTE
Department OF TECHNOLOGY
of Electronics & SCIENCES,
and Communication ONGOLE.
Engineering
PACE INSTITUTE OF TECHNOLOGY & SCIENCES, ONGOLE.

THALLAPALLI VENKATRAO 20KQ1A04H8


RAVIPATI THARAKNADH 20KQ1A04H0
ITTADI PAPA 20KQ1A04D0
DEPURI SRAVANI 20KQ1A04C9
AVALA SRIHARI 21KQ5A0414

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous)
OBJECTIVE
• To Improve the Data speed and reduce the Gate delay.

• To enhance chip design utilizations.

• the main objectives of a carry skip adder are to provide fast, efficient, and
reliable arithmetic operations while minimizing the area and power
consumption required for their implementation.

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 2
Abstract
• Multimedia systems play an essential part in our daily lives.
• Multimedia devices like cell phones, radios, televisions, and computers require
low-area and low-power reconfigurable adders.
• In this thesis, a novel 64-bit reconfigurable adder is proposed and implemented
to reduce the area and power consumption.
• A Carry Select Modified Tree (CSMT) based adder is used in the
reconfigurable adder to reduce the area by 22 % and the power consumption by
47 % when compared to the conventional design.
• The proposed adder, implemented in 180 nm CMOS technology at 1.8-volt
supply.

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 3
Introduction
➢An adder is a digital circuit that manipulates a combination of electronic
signals where a high signal is represented as 1 and a low signal is represented
as 0.
➢Adders are the basic circuits for constructing various complex designs such as
subtractors, dividers and multipliers which perform more advanced arithmetic
operations in many media signal processing applications.
➢Ultimately an adder can be called as the fundamental unit of modern
computing due to its extensive usage in real-time signal processes.
➢Modern-day circuits emphasize on the faster operation, smaller area, and
minimal power consumption, which leads to the need for better high speed, low
area, and energy-efficient adder designs

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 4
Different types of Adders
➢Half adder

➢Full adder

➢Ripple carry adder

➢Carry look ahead

➢Carry select adder

➢Carry skip adder

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 5
Software Implementation
❖ Vivado ML Edition 2022.2

➢Create a new project.

➢Create a testbench.

➢Run synthesis, implementation.

➢Open elaborated design.

➢Run simulation

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 6
Advantages
• Speed: Carry skip adders are designed to reduce the delay in generating the final
carry-out signal.
• Area: Compared to other types of adders such as ripple-carry adders or carry-
lookahead adders, carry skip adders require less area and fewer transistors to
implement.
• Power: Due to their efficient design, carry skip adders consume less power than other
types of adders. This is because they can generate the carry-out signal in fewer clock
cycles, reducing the amount of power required to execute the operation.
• Scalability: Carry skip adders can be easily scaled up or down to accommodate
different input sizes, making them suitable for a wide range of applications.
• Reliability: Carry skip adders are less prone to errors and glitches than other types of
adders, making them more reliable and accurate for complex calculations.

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 7
Schematic Block diagram

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 8
Delay Path Design

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 9
Simulation Results

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 10
Simulation Results

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 11
Thank you..

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING PACE Institute of Technology & Sciences (Autonomous) 12

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