SCAN INSERTION

BY
VAMSY
PREVIOUS SESSION QUESTIONS
WEEK 1 :

● What is pad, pin and port ?

● What is gated clock and disadvantages of it?
● What is integrated clock gating cell and how many types exists ?
● Why do we need DFT?
● What is Manufacturing Defect?
▪ What companies offer tools for DFT ?
● What is meant by Fault?
● Relation between Defect, Fault and Error?
● Explain ASIC Flow?
● Explain DFT Flow ?
● Difference between Verification and DFT ?
● What is Yield ?
● What are the different types of faults in DFT?
TOOLS USED FOR DFT

TOOLS MBIST Synthesis Scan Insertion Compression ATPG Pattern ATPG

INSERTION Insertion
Generation Simulation

Synopsys STAR Memory Design DFT Compiler DFT Compiler Tetramax VC

system Compiler
Simulator

Genus/RTL Genus/RTL Genus/RTL Compiler Genus/RTL Modus / Encounter NC

Compiler Compiler Compiler test
Cadence Simulator/Incisive

Tessent Shell/MBSIT Tessent

Architect
Mentor Real Time Tessent Tessent (Fast Scan/ Questa
Graphics DFT Advisor Testkompress TestKompress) Simulator
THE IDEA OF SCAN

SCAN is the idea using which one can control the inputs of the various gates and flip-flops inside the chip
and also observe the outputs from the internal flops in a planned manner.

Replace all selected flops with scan flops. The chip will initially taken into a special mode, called “scan mode”
by setting an input pin to an appropriate value.

Connect each scan cell to make into a scan chain.

One of the primary input pins will feed the input of the first flop in this chain in the scan mode. The output
of the very last flop will be taken to a primary output.
CONT..
Operated in three modes:

❑ Normal mode

--- All test signals are turned off.

--- The scan design operates in the circuit’s original functional configuration.

❑ DFT MODE:

Shift mode --- to shift data into and out of the scan cells.

Capture mode --- to capture test response into scan cells.

CONTROLLABILITY & OBSERVABILITY

● Controllability

The ability to drive the net to ‘0’ and ‘1’ is called controllability

● Observability

The ability to observe the effect of controlling is called observability.

SCAN BENEFITS

The following are benefits of employing a scan strategy:

➢ Highly automated process.

Using scan insertion tools, the process for inserting scan circuitry into a design is highly automated, thus requiring very little
manual effort.

➢ Highly-effective, predictable method.

Scan design is a highly-effective, well-understood, and well-accepted method for generating high test coverage for your
design.

➢ Ease of use.
Using scan methodology, you can insert both scan circuitry and run ATPG without the aid of a test engineer.
 SCAN METHODOLOGY

➢ Full ScanMethodology
• 1.All sequential cells replaced by corresponding scan counterparts

• 2. Sequential cells not scanned are black box cells

• 3.Combinatorial ATPGAlgorithm can beused

➢ Partial scan Methodology

• 1. Not all sequential cells are replaced by corresponding scan counterpart

• 2. Non-scanned cells are tested by sequential ATPGAlgorithm

➢ Partition scan Methodology

SCAN CELL DESIGN

A Scan Cell has two inputs

-- Data Input

-- Scan Input

• In normal/capture mode, data input is selected to update the output.

In normal mode --- Testmode =0.

In capture mode --- Testmode =1,In shift mode --- Testmode = 1

• In shift mode, scan input is selected to update the output.

TYPES OF SCAN CELL DESIGNS

1.Muxed-D Scan Cell

2.Clocked-Scan Cell

3.LSSD Scan Cell

CONT..
MUXED-D SCAN CELL
CONT..
CLOCKED-SCAN CELL
CONT..
LSSD SCAN CELL
CONT..
COMPARISON OF CELL DESIGNS
SCAN CHAIN

Scan chain testing is a method to detect various manufacturing faults in the silicon.Many types of
manufacturing faults may exist in the silicon.

A multiplexer is added at the input of the flip-flop with one input of the multiplexer acting as the functional
input D, while other being Scan-In (SI). The selection between D and SI is governed by the Scan Enable (SE)
signal.
CONT..

Using this basic Scan Flip-Flop as the building block, all the flops are connected in form of a chain, which
effectively acts as a shift register.

The first flop of the scan chain is connected to the scan-in port and the last flop is connected to the scan-
out port.

Scan testing is done in order to detect any manufacturing fault in the combinatorial logic block.

In order to do so, the ATPG tool try to excite each and every node within the combinatorial logic block by
applying input vectors(test vectors) at the flops of the scan chain.
SCAN CHAIN STICHING
CONT..
SCAN CHAIN OPERATION
WAVEFORM FOR SCAN SHIFT AND SCAN CAPTURE
SCAN ARCHITECTURES

❖ Full-Scan Design

All or almost all storage element are converted into scan cells and combinational ATPG is used for test
generation.

❖ Partial-Scan Design

A subset of storage elements are converted into scan cells and sequential ATPG is typically used for test
generation
PROBLEMS WITH SCAN DESIGN
DFT RULE CHECKS SUMMARY
POSSIBLE SCAN DRC’S LIST:

● Clock controllability

● Set/Reset controllability

● Tri State buses/buffers

● Potential Race condition

● X source violation
● Feedback loops
TRI STATE BUSES
CONT..
BI-DIRECTIONAL I/O PORTS
BI-DIRECTIONAL I/O PORTS
GATED CLOCKS
CONT..
The clock gating function should be disabled at least during the shift operation.An OR gate is used to force
CEN to 1 using either the test mode signal TM or scan enable signal SE.
DERIVED CLOCKS
CONT..
COMBINATIONAL FEEDBACK LOOPS
CONT..
ASYNCHRONOUS SET/RESET SIGNALS
CONT..
TOP -DOWN FLAT

● Single DFTinsertion operation at the top level of design.This flow is simple,but it requires that DFT insertion
● be repeated for the entire design if any part of the design changes
● A very large design that is not suitable for a single top-down DFTinsertion
● Time-consuming for large designs
● Routing Congestion
 BOTTOM - UP

● In bottom-up hierarchical scan synthesis, perform DFT insertion at a lower level of hierarchy, then incorporate those
completed scan structures into DFT insertion at a higher level of hierarchy.

● Test models to represent core designs during top-level DFT operations, which improves tool performance and capacity
for multimillion-gate designs.
● Re-architect DFT structures in a block independently of its surrounding design logic
● Time-consuming is less for large designs
● Create a DFT-inserted block that can be reused in future designs
● Routing Congestion
SCAN INPUTS/OUTPUTS
 SCAN INPUTS

● Design (netlist)
The supported design data format is gate-levelVerilog.
● Circuit Setup (or Dofile)
This is the set of commands that gives the tool information about the circuit and how to insert test structures.You can issue these
commands interactively in the tool session or place them in a dofile.
● Library
The design library contains descriptions of all the cells the design uses. library also Includes information that the tool uses to map
non-scan cells to scan cells and to select components for added test logic circuitry.The tool uses the library to translate the design data into a flat, gate-level
simulation model on which it runs its internal processes.
● Test Procedure File
This file defines the stimulus for shifting scan data through the defined scan chains.This input is only necessary on designs containing pre-
existing scan circuitry or requiring test setuppatterns.
SCAN OUTPUTS

● Design (Netlist)
This netlist contains the original design modified with the inserted test structures.The output netlist
format is gate-levelVerilog.

● ATPG Setup (Dofile and Test ProcedureFile)

The tool can automatically create a dofile and test procedure file that you can supply to the ATPG tool. These
files contain the circuit setup information that you specified to the tool as well as information on the test structures
that the tool inserted into the design.The tool creates these files for you when you issue the write_atpg_setup
command.
SUMMARY

• Tools used for scan

• What Is scan?
• Scan methodology and benefits
• Different types of scan design and flops
• Scan DRC’s
• Scan Inputs and Outputs