0% found this document useful (0 votes)
76 views

Lecture 4 Chap 31

This document provides an overview of RF transistor amplifier design. It discusses transistor biasing to minimize temperature effects and maximize stability. Design procedures are outlined using Y and S parameters to analyze stability, maximum available gain, and simultaneous conjugate matching for an unconditionally stable amplifier. Small-signal and power amplifiers are classified according to signal level and biasing scheme.

Uploaded by

Bitew Ayalew
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
76 views

Lecture 4 Chap 31

This document provides an overview of RF transistor amplifier design. It discusses transistor biasing to minimize temperature effects and maximize stability. Design procedures are outlined using Y and S parameters to analyze stability, maximum available gain, and simultaneous conjugate matching for an unconditionally stable amplifier. Small-signal and power amplifiers are classified according to signal level and biasing scheme.

Uploaded by

Bitew Ayalew
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 75

CHAPTER 3:

RF Transistor Amplifier Design


By: Dr. RP Singh
Communication Engg.

1
INTRODUCTION

 The design of RF small-signal amplifiers is a step-by-step


logical procedure with an exact solution for each problem.

 Detailed step-by-step procedures are followed in the design


process so that you can choose the transistor you want and
use it under any (realistic) operating conditions that you desire.

 The quiescent bias point of a transistor has a great effect on


its Y and S parameters.

 Biasing a transistor is, therefore, serious business and should


not be taken lightly.

2
INTRODUCTION


Next, we’ll jump head first into the rf aspect of amplifiers by
examining stability (tendency for oscillation), gain, impedance
matching, and general amplifier design, with emphasis on the
use of Y and S parameters as a design tool.

3
TRANSISTOR BIASING

 The amplifier must operate reliably and maintain certain


specifications ( gain, noise figure, etc. ) over large temperature
extremes, the dc bias network must be carefully considered.

 It has been shown that there are two basic internal transistor
characteristics that have a profound effect upon the
transistor’s dc operating point over temperature;

 They are ΔVBE and Δβ.

 The object of a good temperature-stable bias design (see Fig.)


is to minimize the effects of these parameters.

4
TRANSISTOR BIASING

 As the temperature increases, the base-to-emitter voltage


( VBE ) of a transistor decreases at the rate of about 2.5 mV/
degree C from its nominal room-temperature value of 0.7 volt
(for a silicon device).

 As VBE decreases, more base current is allowed to flow which,


in turn, produces more collector current and that is exactly what
we would like to prevent.

 The total change in VBE for a given temperature change is


called ΔVBE .

5
TRANSISTOR BIASING

 The primary external circuit factor that the circuit designer has
control over, and which tends to minimize the effects of ΔVBE, is
the emitter voltage (VE) of the transistor.

 This is shown in Fig. Here, a decrease in VBE with temperature


would cause an increase in emitter current and, hence, an
increase in VE.

 The increase in VE is a form of negative feedback that tends to


reverse bias the base-emitter junction and, therefore, decrease
the collector current.

6
TRANSISTOR BIASING

 A decrease in VBE, therefore, tends to be counteracted by the increase in


VE, and the collector current does not increase as much with
temperature. If these observations were put into equation form, we would
have:

 Thus, if VE were made equal to 20 times ΔVBE, the collector current would
change only 5% over temperature due to ΔVBE. It is important to note that
it is the value of the emitter voltage (VE) and not the value of the emitter
resistor ( RE ) that is the important bias-design criteria.

7
TRANSISTOR BIASING

8
TRANSISTOR BIASING

9
DESIGN USING Y PARAMETERS

 The RF small-signal performance of a transistor can be


completely characterized by its two-port admittance
parameters.

 Two of the most important considerations, in choosing a


transistor for use in any amplifier design, are its

- stability and

- its maximum available gain ( MAG ) .

10
Stability Calculations

 It is possible to predict the degree of stability (or lack thereof) of


a transistor before you actually place the device in a circuit.
This is done through a calculation of the Linvill stability factor,
C.

 When C is less than 1, the transistor is unconditionally stable at the


bias point you have chosen.
 If C is greater than 1, the transistor is potentially unstable and will
oscillate for certain values of source and load impedance.

11
DESIGN USING Y PARAMETERS

 Y parameters can also be used to predict the stability of an amplifier given


certain values of load and source impedance. This is called the Stern
stability factor and is given by

 In this case, if K is greater than 1. the circuit will be stable for that value of
source and load impedance.

 If K is less than 1, the circuit is potentially unstable and will most likely
oscillate at some frequency.

12
Maximum Available Gain

 The Linvill stability factor is therefore useful in finding stable transistors


while the Stern stability factor predicts possible stability problems with
circuits.

 The MAG of a transistor can be found by using the following equation:

 MAG is a useful calculation in the initial search for a transistor for any
particular application. It will give you a good indication as to whether or
not the transistor can provide enough gain for the task

13
Simultaneous Conjugate Matching
(Unconditionally Stable Transistors)

 Even though YL affects


the input admittance of the
transistor and Ys affects
its output admittance, it is
still possible to provide the
transistor with a
simultaneous conjugate
match for maximum power
transfer (from source to
load) by using the
following design
equations:

14
Example

15
Example

16
Example

17
Assignment

ASSN No. 1: DESIGN SMALL SIGNAL AMPLIFIER USING


S PARAMETERS
Solve Example 6.3, 6.4, 6.5, 6.6, 6.7 along with a smith chart
plotting. (15 Pts.)

ASSN No. 2: Explain in detail with a neat circuit diagram about Diode
detector and Power detectors. (15 Pts.)

18
RF POWER TRANSISTOR CHARACTERISTICS

 Instead of specifying the Y and S parameters for a power


transistor, manufacturers will typically

– specify the large-signal input impedance and the


large-signal output impedance for the device.

 These parameters are typically measured on the device


when it is operating as a matched amplifier at the desired
dc supply voltage and rf power output level.

19
TRANSISTOR BIASING

 The type of bias applied to an rf power transistor is


determined by the “class” of amplification that the
designer wishes.

 There are many different classes of amplification available


for the designer to choose from.

 The particular class chosen for a design will depend upon


the application at hand.

20
Why do we need Small signal or Power Amplifier

Most RF and microwave amplifiers today used


transistor devices such as Si or SiGe BJTs, GaAs
HBTs (Heterojunction Bipolar Transistor), GaAs or
InP (Indium Phosphide) FETs, or GaAs HEMTs
(High electron mobility transistor).

Microwave transistor amplifiers are rugged, low


cost, reliable and can be easily integrated in both
hybrid and monolithic integrated circuitry.

21
General Amplifier Block Diagram

vs(t) DC supply
vi(t)
ii(t) vo(t)
Zs Input Output
Amplifier
Matching Matching
Network Network io(t)
Pin PL
Vcc
Vs
ZL

The active
component

Input and output voltage relation of the amplifier


can be modeled simply as:
vo  t  a1vi  t   a2vi 2  t   a3vi 3  t   H .O.T .
22
Amplifier Classification
 Amplifier can be categorized in 2 manners.
 According to signal level:
 Small-signal Amplifier.

 Power/Large-signal Amplifier.

 According to D.C. biasing scheme of the active component:


 Class A.

 Class B.

 Class AB.

 Class C.

There
Thereare arealso
alsoother
otherclasses,
classes,such
suchas
asClass
ClassDD(D (Dstands
standsfor
for
digital),
digital),Class
ClassEEand
andClass
ClassF.F. These
Theseall
alluses
usesthe
thetransistor/FET
transistor/FETas
as
aaswitch.
switch.

23
Small-Signal Versus Large-Signal
Operation
Usually non-sinusoidal waveform

Large-signal: vo  t  a1vi  t   a2vi 2  t   a3vi 2  t   H .O.T .

Nonlinear

Small-signal: Linear vo  t  a1vi  t 

Sinusoidal waveform
Zs
vi(t)

Vs vo(t)
ZL

24
Small-Signal Amplifier (SSA)
 All amplifiers are inherently nonlinear.
 However when the input signal is small, the input and output
relationship of the amplifier is approximately linear.

vo  t  a1vi  t   a2 vi 2  t   a3vi 3  t   H .O.T . a1vi  t 


Linear relation
When vi(t)0 (< 2.6mV) vo  t  a1vi  t  (1.1)
 This linear relationship applies also to current and power.
 An amplifier that fulfills these conditions: (1) small-signal operation (2)
linear, is called Small-Signal Amplifier (SSA). SSA will be our focus.
 If a SSA amplifier contains BJT and FET, these components can be
replaced by their respective small-signal model, for instance the
hybrid-Pi model for BJT.

25
Example 1.1 - An RF Amplifier Schematic (1)
DC supply

Zs Input Output
Amplifier
Matching Matching
Network Network

R R
Port C
RD1 C RC

Vs
VCC CD2
R=100 Ohm CD1 R=470 Ohm
Num=3 C=100 pF
C=0.1 uF
ZL
R
L
RB1
LC
R=1 kOhm
L=100.0 nH
R=
RF power flow
L
L2
L=100.0 nH
R=
L
C Port
L4
Cc2 Output
L=12.0 nH
C=100.0 pF Num=2
L R=
Port C L
L1 pb_phl_BFR92A_ 19921214
Input Cc1 L3
L=4.7 nH Q1
Num=1 C=100.0 pF L=100.0 nH C
R=
C R= C2
C1 C=0.68 pF
C=3.3 pF R
RB2
R=1.5 kOhm

26
Typical RF Amplifier Characteristics

 To determine the performance of an amplifier, the following


characteristics are typically observed.
 1. Power Gain.
 2. Bandwidth (operating frequency range).
Important to small-signal
 3. Noise Figure. amplifier
 4. Phase response.
 5. Gain compression.
 6. Dynamic range. Important parameters of
 7. Harmonic distortion. large-signal amplifier
(Related to Linearity)
 8. Intermodulation distortion.
 9. Third order intercept point (TOI).

27
Power Gain
 For amplifiers functioning at RF and microwave frequencies, usually
of interest is the input and output power relation.
 The ratio of output power over input power is called the Power Gain
(G), usually expressed in dB.

Output Power 
Power Gain G 10 log10   dB (1.2)
 Input Power 
 There are a number of definition for power gain as we will see shortly.
 Furthermore G is a function of frequency and the input signal level.

28
Why Power Gain for RF and Microwave
Circuits? (1)
 Power gain is preferred for high frequency amplifiers as the
impedance encountered is usually low (due to presence of parasitic
capacitance).
Power = Voltage x Current

 For instance if the amplifier is required to drive 50Ω load the voltage
across the load may be small, although the corresponding current
may be large (there is current gain).
 For amplifiers functioning at lower frequency (such as IF frequency),
it is the voltage gain that is of interest, since impedance encountered
is usually higher (less parasitic).
 For instance if the output of IF amplifier drives the demodulator
circuits, which are usually digital systems, the impedance looking into
the digital system is high and large voltage can developed across it.
Thus working with voltage gain is more convenient.

29
Why Power Gain for RF and Microwave
Circuits? (2)
 Instead on focusing on voltage or current gain, RF engineers focus
on power gain.
 By working with power gain, the RF designer is free from the
constraint of system impedance. For instance in the simple receiver
block diagram below, each block contribute some power gain. A
large voltage signal can be obtained from the output of the final block
by attaching a high impedance load to it’s output.
v(t) 4.90 V
IF signal
RF signal power 7.5 mW
power 15 W
75 W
1 W BPF BPF t
LNA IF Amp.
400Ω
2
V
RF Portion LO IF Portion Paverage 
2R
(900 MHz) (45 MHz)
30
Harmonic Distortion (1)
When the input driving signal is
small, the amplifier is linear.
Harmonic components are
almost non-existent.

Zs

Vs
ZL f
0 f1 2f1 3f1 4f1
f
f1
Pout
harmonics
Harmonics
Harmonicsgeneration
generationreduces
reducesthethegain
gain
ofofthe
theamplifier,
amplifier,as
assome
someofofthe
theoutput
output Small-signal
power
poweratatthe
thefundamental
fundamentalfrequency
frequencyisis operation
shifted
shiftedtotohigher
higherharmonics.
harmonics. This
Thisresult
resultinin region
gain
gaincompression
compressionseen seenearlier!
earlier! Pin
31
Harmonic Distortion (2)
When the input driving signal is
too large, the amplifier becomes
nonlinear. Harmonics are
introduced at the output.

Zs

Vs
ZL f
0 f1 2f1 3f1 4f1
f
f1
Pout harmonics
Harmonics
Harmonicsgeneration
generationreduces
reducesthethegain
gain
ofofthe
theamplifier,
amplifier,as
assome
someofofthe
theoutput
output
power
poweratatthe
thefundamental
fundamentalfrequency
frequencyisis
shifted
shiftedtotohigher
higherharmonics.
harmonics. This
Thisresult
resultinin
gain
gaincompression
compressionseen seenearlier!
earlier! Pin
32
Power Gain, Dynamic Range and Gain
Compression
Input and output at same frequency
Pout
Pin Pout Ideal amplifier
(dBm)
Gain compression Device
30 1dB
occurs here Burn
20 out
10
Saturation
0 Linear
LinearRegion
Region
-10 Nonlinear
Nonlinear
-20 Dynamic range (DR) Region
Region
-30 Power gain Gp =
-40 Pout(dBm) - Pin(dBm)
= -30-(-43) = 13dB 1dB compression
-50 Point (Pin_1dB)
Noise Floor
-60
Pin
-70 -60 -50 -40 -30 -20 -10 0 10 20 (dBm)
33
Noise Figure (F)
• The amplifier also introduces noise into the output in
addition to the noise from the environment.
• Assuming small-signal operation.

Smaller SNRin

Zs

Noise Figure (F)= SNRin/SNRout


Vs • Since SNRin is always larger
than SNRout, F > 1 for an ZL
amplifier which contribute noise.
SNR:
SNR:
Signal
SignaltotoNoise
Noise
Ratio
Ratio Larger SNRout
34
Power Components in an Amplifier

Zs Amplifier

Vs ZL

2 basic source-
Approximate load networks
Linear circuit
Zs Z2

PAs + PL
Z1 PAo
Vs VAmp ZL
Pin -

PRs
PRo
35
Power Gain Definition
 From the power components, 3 types of power gain can be defined.
Power delivered to load PL
Power Gain G p   (2.1a)
Input power to Amp. Pin
Available load Power PAo
Available Power Gain G A   (2.1b)
Available Input power PAs
Power delivered to load PL
Transducer Gain GT   (2.1c)
Available Input power PAs

The effective power gain

 GP, GA and GT can be expressed as the S-parameters of the amplifier


and the reflection coefficients of the source and load networks. Refer
to Appendix 1 for the derivation.
36
TWO-PORT POWER GAIN
Power Gain = G = PL / Pin is the ratio of power dissipated in the load ZL to
the power delivered to the input of the two-port network. This gain is
independent of Zs although some active circuits are strongly dependent on
ZS.
Available Gain = GA = Pavn / Pavs is the ratio of the power available from
the two-port network to the power available from the source. This assumes
conjugate matching in both the source and the load, and depends on Z S but
not ZL.
Transducer Power Gain = GT = PL / Pavs is the ratio of the power delivered
to the load to the power available from the source. This depends on both
ZS and ZL.
If the input and output are both conjugately matched to the two-port, then
the gain is maximized and G = GA = GT
37
Naming Convention
InInthe
thespirit
spiritofofhigh-
high-
Zs frequency
frequencycircuit
circuitdesign,
design,
Amplifier where
wherefrequency
frequencyresponse
response
ofofamplifier
amplifierisischaracterized
characterized
Vs ZL bybyS-parameters
S-parametersand and
reflection
reflectioncoefficient
coefficientisis
used
usedextensively
extensively
instead
insteadofofimpedance,
impedance,
power
powergain
gaincancanbebeexpressed
expressed
ininterms
termsofofthese
theseparameters.
parameters.
s
L
2 - port
Source
Network
Load
Network  s11 s12  Network
s s22 
 21

1 2 38
TWO-PORT POWER GAIN

Figure 7.1: A two port network with general source and load impedance.

39
TWO-PORT POWER GAIN

From the definition of S parameters:


V1 S11V1  S12V2 S11V1  S12LV2 [3.1a]
V2 S 21V1  S 22V2 S 21V1  S 22LV2 [3.1b]

Eliminating V2- from [3.1a]:

V1 S S  Z  Z0 [3.2]
in   S11  12 21 L  in
V1 1  S 22L Z in  Z 0

V2 S S  Z  Z0
out   S 22  12 21 S  out [3.3]
V2 1  S11S Z out  Z 0

40
TWO-PORT POWER GAIN

By voltage division:
Z in
V1 VS V1  V1 V1 1  in  [3.4]
Z S  Z in
Using:
1  in
Z in Z 0 [3.5]
1  in
Solving for V1+:
VS 1  S 
V  1

[3.6]
2 1  S in 

41
TWO-PORT POWER GAIN
The average power delivered to the network:
2 2
1 VS 1  S
Pin 
2Z 0

V1 1  in
2
  8Z 1  S in
2
1    in
2
[3.7]
0
The power delivered to the load is:
 2
V
PL 
2

2Z 0
1    L
2
[3.8]

 2

PL 
V 1 S 21
2
1    L
2

2
2Z 0 1  S 22 L
[3.9]


VS
2
S 21
2
1  L
2
1   S
2

8Z 0 1  S 22 L 2 1  S in 2

42
TWO-PORT POWER GAIN

The power gain can be expressed as:


PL
G 
2
S 21 1  L   2

[3.10]
Pin 1  in  2
1  S  22 L
2

The available power from the source:


2 2
Vs 1  S [3.11]
Pavs Pin 
in S

8Z 0 1  S 2

The available power from the network:

Pavn PL  
Vs
2 2

S 21 1  out
2
1   S
2

[3.12]
 2
L out
8 Z 0 1  S  1    2
22 out S in 
L out

43
TWO-PORT POWER GAIN

The power available from the network:


2 2 2
Vs S 21 1  S
Pavn  [3.13]
8Z 0 1  S11S 1  out 2
 2

The available power gain:
P
G A  avn 
2
S 21 1  S  2
 [3.14]

Pavs 1  out 2 1  S11S  2

The transducer power gain:

GT 
PL

2

S 21 1  S 1  L
2
 2
 [3.15]
2 2
Pavs 1  S 22L 1  S in

44
Summary of Important Power Gain Expressions
and the Gain Dependency Diagram
s    1   2  s 2
  11 L
s 21
1 s  (4.1a) (4.1c)
1

GA   
22 L
2 2
s   1  s11s  1  2 
  22 s  
1 s 
2

11
2
s
2  1   2  s 2  1   2 
s21  1  L  L 21 s (4.1d)
GT     
GP    (4.1b) 2 2
2 2 1  s22L 1  1s
1  s22L  1  1 
 
GT  s s  s s (4.1e)
11 22 12 21

Note:
GA s L GP All GT, GP, GA, 1 and 2
depends on the S-
parameters.
1 2
The Gain Dependency Diagram
 s11 s12 
s 
 21 s22 
45
TWO-PORT POWER GAIN

A special case of the transducer power gain occurs when both input and
output are matched for zero reflection (in contrast to conjugate
matching).
2
GT  S 21 [5.1]

Another special case is the unilateral transducer power gain, G TU where


S12=0 (or is negligibly small). This nonreciprocal characteristic is
common to many practical amplifier circuits. Γin = S11 when S12 = 0, so
the unilateral transducer gain is:

GTU 
2

S 21 1  S
2
1   
L
2
[5.2]
2 2
1  S11S 1  S 22in

46
TWO-PORT POWER GAIN

Figure 7.2: The general transistor amplifier circuit.

47
TWO-PORT POWER GAIN

The separate effective gain factors:


2
1  S
GS  2
[5.3a]
1  in S
2
G0  S 21 [5.3b]
2
1  L
GL  2
[5.3c]
1  S 22 L

48
TWO-PORT POWER GAIN

If the transistor is unilateral, the unilateral transducer gain reduces


to GTU = GSG0GL , where:
2
1  S
GS  2
[5.4a]
1  S11S
2
G0  S 21 [5.4b]
2
1  L
GL  2 [5.4c]
1  S 22 L

49
Example 1 – Familiarization with the Gain
Expressions
 An RF amplifier has the following S-parameters at fo: s11=0.3<-70o,
s21=3.5<85o, s12=0.2<-10o, s22=0.4<-45o. The system is shown
below. Assuming reference impedance (used for measuring the S-
parameters) Zo=50, find:
 (a) GT, GA, GP.
 (b) PL, PA, Pinc.

40

Amplifier

5<0o ZL=73
 s11 s12 
s 
 21 s22 

50
Example 1 Cont...
Z Z Z Z
 Step 1 - Find  s and L . s  Z s Z o  0.111 L  Z L Zo 0.187
s o L o

 Step 2 - Find 1 and 2 . 1  s111 s 22DLL 0.146  j 0.151


 Step 3 - Find GT, GA, GP. s  Ds
2  22 0.265  j 0.358
1 s11s
 Step 4 - Find PL, PA.

G
1    13.742
s 21
2

L
2

Try to derive 1  s  1   
2 2

2 22 L 1
V
PA 8Res Z  0.078W These 2 relations
s
 1   2 2
s  s21
 2  
Z1  Z s GA  14.739
Pin PA  1  Z o  0.0714W 2 2
 Z 
1 s Z  1  s11s  1  2 
   
PL GP Pin 0.9814W  1   2  s 2  1   2 
L 21 s
GT      12.562
Again 2 2
Againnote
notethat
thatthis
thisisisan
an 1  s22L 1  1s
analysis
analysisproblem.
problem.
51
Class-A Amplifiers and Linearity

 A class-A amplifier is defined as an amplifier that is


biased so that the output current flows at all times.

 Thus, the input signal-drive level to the amplifier is kept


small enough to avoid driving the transistor into cutoff.

 The class-A amplifier is the most linear of all amplifier


types.

 Linearity is simply a measure of how closely the output


signal of the amplifier resembles the input signal.

52
Class-B Power Amplifiers

 A class-B amplifier is one in which the conduction angle for the transistor is
approximately 180".

 Thus, chosen so that the current through CR1 is rather high.

 This ensures that the bias to the transistor is stable.

 An alternative bias network is shown in Fig. 7-9.

 Here, two silicon diodes are used to forward bias an emitter-follower, which
is used as a current amplifier.

 The voltage at the emitter of Q1 and, hence, at the base of Q2, is still 0.7
volt due to the VBE drop across transistor Q,.

53
Class-B Power Amplifiers (Contd..)

54
Class-B Power Amplifiers (Contd..)

 The rf choke and capacitor shown in both Figs. 7-8 and 7-


9 are there only to prevent the flow of rf into the bias
network.

55
Class-C Power Amplifiers

 A class-C amplifier is one in which the conduction angle for the


transistor is significantly less than 180 degrees.

 The transistor is biased such that under steady-state conditions no


collector current flows.

 The transistor idles at cutoff.

 Linearity of the class-C amplifier is the poorest of the classes of


amplifiers.

 Its efficiency can approach 85%, however, which is much better than
either the class-B or the class-A amplifier.

56
Class-C Power Amplifiers (Contd..)

57
POWER AMPLIFIER DESIGN

 At the beginning of this chapter, you learned that the important


design information for rf power transistors is presented in the
form of large-signal impedance parameters.

 The formulas presented for small-signal transistor design,


using Y and S parameters, are no longer valid.

 Instead, the designer must model with the help of the data
sheet.

 Deciding what the input and output impedance of the transistor


looks like at the frequency of interest.

58
POWER AMPLIFIER DESIGN (Contd..)

 With this information in hand, the designer needs only to


match the input and output impedance of the device to the
source and load, respectively.

 These two steps require only that the designer read the
input and output impedances off of the data sheet, and then
apply the principles of Chapter 2 to complete the matching
network.

 Care must be taken to ensure that the information extracted


from the data sheet is of the proper format-series or shunt
information.

59
POWER AMPLIFIER DESIGN SPECIFICATIONS FOR MRF233

60
POWER AMPLIFIER DESIGN SPECIFICATIONS FOR MRF233

61
Optimum Collector Load Resistance

 In the absence of collector output resistance information on the


data sheet, it becomes necessary for the designer to make a
very simple calculation to determine the optimum load
resistance for the transistor ( Example 7-1 ) .

 This value of load resistance is dependent upon the output


power level required and is given by :

62
Example:

63
Driver Amplifiers and Interstage Matching

 Often it is required that power gain be distributed


throughout several amplifier stages in order to produce a
specified output power into a load.

 This is especially true in transmitter applications that


require a substantial amount of power into an antenna.

 The typical procedure for such a design involves finding,


first, an output transistor that will handle the required
output power and, then, designing driver amplifiers that will
provide the necessary drive power to the final transistor.

64
Driver Amplifiers and Interstage Matching (Contd..)

This type of gain distribution is shown in Fig. 7-17.

65
Example:

66
UHF/microwave RF integrated circuits

 Very wideband amplifiers (i.e., those operating from near-


dc to UHF or into the microwave regions) have
traditionally been very difficult to design and build with
consistent performance across the entire passband.

 Many such amplifiers have either gain irregularities, such


as “suck-outs” or peaks.

 Others suffer large variations of input and output


impedance over the frequency range.

67
UHF/microwave RF integrated circuits

 Consequently, such amplifiers were either very expensive


or didn’t work nearly as well as claimed.

 Hybrid Microwave Integrated Circuit (HMIC) and


Monolithic Microwave Integrated Circuit (MMIC) devices
were low-cost solutions to the problem.

68
What are HMICs and MMICs?

 MMICs are tiny “gain block” monolithic integrated circuits


that operate from dc or near dc to a frequency in the
microwave region.

 HMICs, on the other hand, are hybrid devices that


combine discrete and monolithic technology.

 Both devices are unique in that they present input and


output impedances that are a good match to the 50 or 75
ohms normally used as system impedances in RF circuits.

69
How MMICs are designed?

 Monolithic Microwave Integrated Circuits devices are


formed through photoetching and diffusion processes on
a substrate of silicon or some other semiconductor
material.

 Both active devices (such as transistors and diodes) and


some passive devices can be formed in this manner.

 Passive components, such as on-chip capacitors and


resistors, can be formed using various thin- and thick-film
technologies.

70
71
72
73
74
75

You might also like