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User’s Manual

µPD789104A, 789114A, 789124A,

789134A Subseries
8-bit Single-chip Microcontrollers

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µ PD789101A µ PD789121A
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µ PD789102A µ PD789122A
µ PD789104A µ PD789124A
µ PD789111A µ PD789131A
µ PD789112A µ PD789132A
µ PD789114A µ PD789134A
µ PD78F9116A µ PD78F9136A
µ PD789101A(A) µ PD789121A(A)
µ PD789102A(A) µ PD789122A(A)
µ PD789104A(A) µ PD789124A(A)
µ PD789111A(A) µ PD789131A(A)
µ PD789112A(A) µ PD789132A(A)
µ PD789114A(A) µ PD789134A(A)

Document No. U14643EJ1V0UM00 (1st edition)

Date Published June 2000 NS CP(K)

© 2000
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Printed in Japan

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NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
et4U.com related specifications governing the devices.
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STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

EEPROM is a trademark of NEC Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun-Microsystems, Inc.
OSF/Motif is a trademark of Open Software Foundation, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
TRON is an abbreviation of The Realtime Operating System Nucleus.
ITRON is an abbreviation of Industrial TRON.
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The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

Licence not needed: µPD78F9116A, 78F9136A

The customer must judge the need for license:
µPD789101A, 789102A, 789104A, 789101A(A), 789102A(A), 789104A(A)
µPD789111A, 789112A, 789114A, 789111A(A), 789112A(A), 789114A(A)
µPD789121A, 789122A, 789124A, 789121A(A), 789122A(A), 789124A(A)
µPD789131A, 789132A, 789134A, 789131A(A), 789132A(A), 789134A(A)

• The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative

et4U.co m purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full DataShee
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
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parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
et4U.com from country to country. DataShee
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NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Santa Clara, California Benelux Office Hong Kong
Tel: 408-588-6000 Eindhoven, The Netherlands Tel: 2886-9318
800-366-9782 Tel: 040-2445845 Fax: 2886-9022/9044
Fax: 408-588-6130 Fax: 040-2444580
800-729-9288 NEC Electronics Hong Kong Ltd.
NEC Electronics (France) S.A. Seoul Branch
NEC Electronics (Germany) GmbH Velizy-Villacoublay, France Seoul, Korea
Duesseldorf, Germany Tel: 01-30-67 58 00 Tel: 02-528-0303
Tel: 0211-65 03 02 Fax: 01-30-67 58 99 Fax: 02-528-4411
Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd.
NEC Electronics (UK) Ltd. Spain Office United Square, Singapore 1130
Milton Keynes, UK Madrid, Spain Tel: 65-253-8311
Tel: 01908-691-133 Tel: 91-504-2787 Fax: 65-250-3583
Fax: 01908-670-290 Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Taipei, Taiwan
Milano, Italy Scandinavia Office Tel: 02-2719-2377
Tel: 02-66 75 41 Taeby, Sweden Fax: 02-2719-5951
Fax: 02-66 75 42 99 Tel: 08-63 80 820
Fax: 08-63 80 388 NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1

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INTRODUCTION

Target Readers This manual is intended for users who wish to understand the functions of the
µPD789104A, 789114A, 789124A, 789134A Subseries and to design and develop
application systems and programs using these microcontrollers.
The target devices are shown as follows:
• µPD789104A Subseries: µPD789101A, 789102A, 789104A,
µPD789101A(A), 789102A(A), 789104A(A)
• µPD789114A Subseries: µPD789111A, 789112A, 789114A, 78F9116A,
µPD789111A(A), 789112A(A), 789114A(A)
• µPD789124A Subseries: µPD789121A, 789122A, 789124A,
µPD789121A(A), 789122A(A), 789124A(A)
• µPD789134A Subseries: µPD789131A, 789132A, 789134A, 78F9136A,
µPD789131A(A), 789132A(A), 789134A(A)
The µPD789104A/114A/124A/134A Subseries is a generic term for all the target
devices in this manual.
The oscillation frequency of the system clock is regarded as fX for ceramic/crystal
oscillation (µPD789104A and 789114A Subseries), and regarded as fCC for an RC
oscillation (µPD789124A and 789134A Subseries).

Purpose This manual is intended for users to understand the functions described in the
et4U.com organization below.
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Organization DataSheet4U.com
The µPD789104A, 789114A, 789124A, 789134A Subseries User's Manual is divided
into two parts: this manual and instructions (common to the 78K/0S Series).

µPD789104A,789114A,789124A, 78K/0S Series

789134A Subseries User’s Manual
User’s Manual (This manual) Instructions

• Pin functions • CPU function

• Internal block functions • Instruction set
• Interrupt • Instruction description
• Other internal peripheral functions

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How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields
of electrical engineering, logic circuits, and microcontrollers.

For users who use this document as the manual for the µPD789101A(A), 789102A(A),
789104A(A), 789111A(A), 789112A(A), 789114A(A), 789121A(A), 789122A(A),
789124A(A), 789131A(A), 789132A(A), and 789134A(A)
→ The only differences between standard products and (A) products are the quality
grades and the electrical specifications. (refer to 1.9 Differences between
Standard Quality Grade Products and (A) Products and 2.9 Differences
between Standard Quality Grade Products and (A) Products). For the (a)
products, read the part numbers in the following manner.
µPD789101A → µPD789101A(A) µPD789121A → µPD789121A(A)
µPD789102A → µPD789102A(A) µPD789122A → µPD789122A(A)
µPD789104A → µPD789104A(A) µPD789124A → µPD789124A(A)
µPD789111A → µPD789111A(A) µPD789131A → µPD789131A(A)
µPD789112A → µPD789112A(A) µPD789132A → µPD789132A(A)
µPD789114A → µPD789114A(A) µPD789134A → µPD789134A(A)
To understand the overall functions in general
→ Read this manual in the order of the CONTENTS.
How to interpret register formats
→ The name ¡V a bit whose number is encircled is reserved for the assembler and
is defined for the C compiler by the header file sfrbit.h.
et4U.com To learn the detailed functions of a register whose register name is known
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→ Refer to APPENDIX C REGISTER INDEX.
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To learn the details of the instruction functions of the 78K/0S Series
→ Refer to 78K/0S Series User’s Manual Instructions (U11047E).
To know the electrical specifications of the µPD789104A/114A/124A/134A Subseries
→ Refer to separately available Data Sheet.

Caution The application examples in this manual are created for "Standard" quality
grade products for general electric equipment. When using the application
examples in this manual for purposes which require "Special" quality grades,
thoroughly examine the quality grade of each part and circuit actually used.

Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H

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Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No.

English Japanese
µPD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A), U14590E U14590J
112A(A),114A(A) Data Sheet
µPD789121A,122A,124A,131A,132A,134A,121A(A),122A(A),124A(A),131A(A), U14678E U14678J
132A(A),134A(A) Data Sheet

µPD78F9116A Data Sheet U14667E U14667J

µPD78F9136A Data Sheet U14690E U14690J
µPD789104A,789114A,789124A,789134A Subseries User’s Manual This manual U14643J

78K/0S Series User’s Manual Instruction U11047E U11047J

78K/0, 78K/0S Series Application Note Flash Memory Write U14458E U14458J

Documents Related to Development Tools (User’s Manuals)

Document Name Document No.

English Japanese
RA78K0S Assembler Package Operation U11622E U11622J
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Assembly Language U11599E U11599J

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Structured Assembly Language U11623E U11623J
CC78K0S C Compiler Operation U11816E U11816J
Language U11817E U11817J

SM78K0S System Simulator WindowsTM Based Reference U11489E U11489J

SM78K Series System Simulator External components user open U10092E U10092J
interface specification
ID78K0S-NS Integrated Debugger Reference U12901E U12901J
Windows Based
IE-78K0S-NS In-Circuit Emulator U13549E U13549J
IE-789136-NS-EM1 Emulation Board U14363E U14363J

Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.

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Document Related to Embedded Software (User’s Manual)

Document Name Document No.

English Japanese

78K/0S Series OS MX78K0S Basics U12938E U12938J

Other Documents

Document Name Document No.

English Japanese

SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X

Semiconductor Device Mounting Technology Manual C10535E C10535J
Quality Grades on NEC Semiconductor Devices C11531E C11531J

NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892J
Guide to Microcomputer-Related Products by Third Party  U11416J

Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.

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CONTENTS

CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES) ................................................... 23

1.1 Features ............................................................................................................................... 23
1.2 Applications ........................................................................................................................ 23
1.3 Ordering Information ......................................................................................................... 24
1.4 Quality Grade ...................................................................................................................... 24
1.5 Pin Configuration (Top View) ........................................................................................... 25
1.6 78K/0S Series Lineup ........................................................................................................ 26
1.7 Block Diagram .................................................................................................................... 28
1.8 Outline of Functions .......................................................................................................... 29
1.9 Differences between Standard Quality Grade Products and (A) Products ............... 30

CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES) ................................................... 31

2.1 Features ............................................................................................................................... 31
2.2 Applications ........................................................................................................................ 31
2.3 Ordering Information ......................................................................................................... 32
2.4 Quality Grade ...................................................................................................................... 32
2.5 Pin Configuration (Top View) ........................................................................................... 33
2.6 78K/0S Series Lineup ........................................................................................................ 34
2.7 Block Diagram .................................................................................................................... 36
et4U.com 2.8 Outline of Functions .......................................................................................................... 37
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2.9 Differences between Standard Quality Grade Products and (A) Products ............... 38
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CHAPTER 3 PIN FUNCTIONS ......................................................................................................... 39
3.1 Pin Function List ................................................................................................................ 39
3.2 Description of Pin Functions ........................................................................................... 41
3.2.1 P00 to P03 (Port 0) .................................................................................................................. 41
3.2.2 P10, P11 (Port 1) ...................................................................................................................... 41
3.2.3 P20 to P25 (Port 2) .................................................................................................................. 41
3.2.4 P50 to P53 (Port 5) .................................................................................................................. 42
3.2.5 P60 to P63 (Port 6) .................................................................................................................. 42
3.2.6 RESET ...................................................................................................................................... 42
3.2.7 X1, X2 (µPD789104A, 789114A Subseries) ........................................................................... 42
3.2.8 CL1, CL2 (µPD789124A, 789134A Subseries) ....................................................................... 42
3.2.9 AVDD ............................................................................................................................................................................................................... 42
3.2.10 AVSS ............................................................................................................................................................................................................. 42
3.2.11 VDD ................................................................................................................................................................................................................ 42
3.2.12 VSS ................................................................................................................................................................................................................ 42
3.2.13 VPP (µPD78F9116A, 78F9136A only) .................................................................................... 43
3.2.14 IC0 (pin No.20) (mask ROM version only) ............................................................................ 43
3.2.15 IC0 (pins No.10 and No.21) ................................................................................................... 43
3.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ............. 44

CHAPTER 4 CPU ARCHITECTURE ................................................................................................ 47

4.1 Memory Space .................................................................................................................... 47
4.1.1 Internal program memory space .............................................................................................. 51
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4.1.2 Internal data memory (internal high-speed RAM) space ........................................................ 52

4.1.3 Special function register (SFR) area ....................................................................................... 52
4.1.4 Data memory addressing ......................................................................................................... 52
4.2 Processor Registers .......................................................................................................... 56
4.2.1 Control registers ....................................................................................................................... 56
4.2.2 General registers ...................................................................................................................... 59
4.2.3 Special function registers (SFRs) ............................................................................................ 60
4.3 Instruction Address Addressing ...................................................................................... 63
4.3.1 Relative addressing .................................................................................................................. 63
4.3.2 Immediate addressing .............................................................................................................. 64
4.3.3 Table indirect addressing ......................................................................................................... 65
4.3.4 Register addressing ................................................................................................................. 65
4.4 Operand Address Addressing .......................................................................................... 66
4.4.1 Direct addressing ..................................................................................................................... 66
4.4.2 Short direct addressing ............................................................................................................ 67
4.4.3 Special function register (SFR) addressing ............................................................................ 68
4.4.4 Register addressing ................................................................................................................. 69
4.4.5 Register indirect addressing .................................................................................................... 70
4.4.6 Based addressing ..................................................................................................................... 71
4.4.7 Stack addressing ...................................................................................................................... 71

CHAPTER 5 PORT FUNCTIONS ..................................................................................................... 73

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5.2 Port Configuration ............................................................................................................. 75
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5.2.1 Port 0 ........................................................................................................................................ 75
5.2.2 Port 1 ........................................................................................................................................ 76
5.2.3 Port 2 ........................................................................................................................................ 77
5.2.4 Port 5 ........................................................................................................................................ 81
5.2.5 Port 6 ........................................................................................................................................ 82
5.3 Port Function Control Registers ...................................................................................... 83
5.4 Operation of Port Functions ............................................................................................. 85
5.4.1 Writing to I/O port ..................................................................................................................... 85
5.4.2 Reading from I/O port .............................................................................................................. 85
5.4.3 Arithmetic operation of I/O port ................................................................................................ 86

CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES) ............................... 87

6.1 Function of Clock Generator ............................................................................................ 87
6.2 Configuration of Clock Generator ................................................................................... 87
6.3 Register Controlling Clock Generator ............................................................................ 88
6.4 System Clock Oscillator .................................................................................................... 89
6.4.1 System clock oscillator ............................................................................................................. 89
6.4.2 Divider ....................................................................................................................................... 92
6.5 Operation of Clock Generator .......................................................................................... 92
6.6 Changing Setting of CPU Clock ....................................................................................... 93
6.6.1 Time required for switching CPU clock ................................................................................... 93
6.6.2 Switching CPU clock ................................................................................................................ 93

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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES) ............................... 95

7.1 Function of Clock Generator ............................................................................................ 95
7.2 Configuration of Clock Generator ................................................................................... 95
7.3 Register Controlling Clock Generator ............................................................................ 96
7.4 System Clock Oscillator .................................................................................................... 97
7.4.1 System clock oscillator ............................................................................................................. 97
7.4.2 Divider ....................................................................................................................................... 100
7.5 Operation of Clock Generator .......................................................................................... 100
7.6 Changing Setting of CPU Clock ....................................................................................... 101
7.6.1 Time required for switching CPU clock ................................................................................... 101
7.6.2 Switching CPU clock ................................................................................................................ 101

CHAPTER 8 16-BIT TIMER 20 .......................................................................................................... 103

8.1 16-Bit Timer 20 Functions ................................................................................................. 103
8.2 16-Bit Timer 20 Configuration .......................................................................................... 104
8.3 Registers Controlling 16-Bit Timer 20............................................................................. 106
8.4 16-Bit Timer 20 Operation ................................................................................................. 109
8.4.1 Operation as timer interrupt ..................................................................................................... 109
8.4.2 Operation as timer output ........................................................................................................ 111
8.4.3 Capture operation ..................................................................................................................... 112
8.4.4 16-bit timer counter 20 readout ............................................................................................... 113

et4U.com CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80 .......................................................................... 115

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9.1 Functions of 8-Bit Timer/Event Counter 80 .................................................................... 115
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9.2 8-Bit Timer/Event Counter 80 Configuration .................................................................. 116
9.3 8-Bit Timer/Event Counter 80 Control Registers ........................................................... 118
9.4 Operation of 8-Bit Timer/Event Counter 80 .................................................................... 120
9.4.1 Operation as interval timer ....................................................................................................... 120
9.4.2 Operation as external event counter ....................................................................................... 122
9.4.3 Operation as square wave output ........................................................................................... 123
9.4.4 Operation as PWM output ........................................................................................................ 125
9.5 Notes on Using 8-Bit Timer/Event Counter 80 ............................................................... 127

CHAPTER 10 WATCHDOG TIMER .................................................................................................. 129

10.1 Functions of Watchdog Timer ........................................................................................ 129
10.2 Configuration of Watchdog Timer ................................................................................. 130
10.3 Watchdog Timer Control Register ................................................................................. 131
10.4 Operation of Watchdog Timer ........................................................................................ 133
10.4.1 Operation as watchdog timer ................................................................................................. 133
10.4.2 Operation as interval timer .................................................................................................... 134

CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES) .......................... 135

11.1 8-Bit A/D Converter Functions ....................................................................................... 135
11.2 8-Bit A/D Converter Configuration ................................................................................. 135
11.3 Registers Controlling 8-Bit A/D Converter ................................................................... 138
11.4 8-Bit A/D Converter Operation ....................................................................................... 140
11.4.1 Basic operation of 8-bit A/D converter ................................................................................... 140

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11.4.2 Input voltage and conversion result ....................................................................................... 141

11.4.3 Operation mode of 8-bit A/D converter .................................................................................. 143
11.5 Cautions Related to 8-Bit A/D Converter ...................................................................... 144

CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES) ........................ 149

12.1 10-Bit A/D Converter Functions ..................................................................................... 149
12.2 10-Bit A/D Converter Configuration .............................................................................. 149
12.3 Registers Controlling 10-Bit A/D Converter ................................................................. 152
12.4 10-Bit A/D Converter Operation ..................................................................................... 154
12.4.1 Basic operation of 10-bit A/D converter ................................................................................ 154
12.4.2 Input voltage and conversion result ...................................................................................... 155
12.4.3 Operation mode of 10-bit A/D converter ............................................................................... 157
12.5 Cautions Related to 10-Bit A/D Converter .................................................................... 158

CHAPTER 13 SERIAL INTERFACE 20 ........................................................................................... 163

13.1 Functions of Serial Interface 20 ..................................................................................... 163
13.2 Serial Interface 20 Configuration ................................................................................... 163
13.3 Serial Interface 20 Control Registers ............................................................................. 167
13.4 Serial Interface 20 Operation ......................................................................................... 174
13.4.1 Operation stop mode .............................................................................................................. 174
13.4.2 Asynchronous serial interface (UART) mode ........................................................................ 176
13.4.3 3-wire serial I/O mode ............................................................................................................ 189
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CHAPTER 14 MULTIPLIER .............................................................................................................. 199
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14.1 Multiplier Function ........................................................................................................... 199
14.2 Multiplier Configuration .................................................................................................. 199
14.3 Multiplier Control Register ............................................................................................. 201
14.4 Multiplier Operation ......................................................................................................... 202

CHAPTER 15 INTERRUPT FUNCTIONS ........................................................................................ 203

15.1 Interrupt Function Types................................................................................................. 203
15.2 Interrupt Sources and Configuration ............................................................................ 203
15.3 Interrupt Function Control Registers ............................................................................ 206
15.4 Interrupt Processing Operation ..................................................................................... 211
15.4.1 Non-maskable interrupt request acknowledgement operation ............................................. 211
15.4.2 Maskable interrupt request acknowledgement operation ..................................................... 213
15.4.3 Multiple interrupt processing .................................................................................................. 215
15.4.4 Interrupt request reserve ....................................................................................................... 217

CHAPTER 16 STANDBY FUNCTION .............................................................................................. 219

16.1 Standby Function and Configuration ............................................................................ 219
16.1.1 Standby function ..................................................................................................................... 219
16.1.2 Standby function control register (µPD789104A, 789114A Subseries) ............................... 220
16.2 Operation of Standby Function...................................................................................... 221
16.2.1 HALT mode ............................................................................................................................. 221
16.2.2 STOP mode ............................................................................................................................ 224

CHAPTER 17 RESET FUNCTION ................................................................................................... 227

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CHAPTER 18 µPD78F9116A, 78F9136A ........................................................................................ 231

18.1 Flash Memory Programming .......................................................................................... 232
18.1.1 Selecting communication mode ............................................................................................. 232
18.1.2 Function of flash memory programming ................................................................................ 233
18.1.3 Flashpro III connection example ........................................................................................... 233
18.1.4 Example of settings for Flashpro III (PG-FP3) ....................................................................... 237

CHAPTER 19 MASK OPTION (MASK ROM VERSION) ................................................................ 239

CHAPTER 20 INSTRUCTION SET .................................................................................................. 241

20.1 Operation ........................................................................................................................... 241
20.1.1 Operand identifiers and description methods ....................................................................... 241
20.1.2 Description of “operation” column ......................................................................................... 242
20.1.3 Description of “flag operation” column .................................................................................. 242
20.2 Operation List ................................................................................................................... 243
20.3 Instructions Listed by Addressing Type ....................................................................... 248

APPENDIX A DEVELOPMENT TOOLS ........................................................................................... 251

A.1 Language Processing Software ...................................................................................... 253
A.2 Flash Memory Writing Tools ............................................................................................ 254
et4U.com A.3 Debugging Tools................................................................................................................ 254
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A.3.1 Hardware .................................................................................................................................. 254
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A.3.2 Software ................................................................................................................................... 255

APPENDIX B EMBEDDED SOFTWARE ......................................................................................... 257

APPENDIX C REGISTER INDEX ...................................................................................................... 259

C.1 Register Name Index (Alphabetic Order) ....................................................................... 259
C.2 Register Symbol Index (Alphabetic Order) .................................................................... 261

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LIST OF FIGURES (1/4)

Figure No. Title Page

3-1. Pin Input/Output Circuits .................................................................................................................... 45

4-1. Memory Map (µPD789101A, 789111A, 789121A, 789131A) ........................................................... 47

4-2. Memory Map (µPD789102A, 789112A, 789122A, 789132A) ........................................................... 48
4-3. Memory Map (µPD789104A, 789114A, 789124A, 789134A) ........................................................... 49
4-4. Memory Map (µPD78F9116A, 78F9136A) ......................................................................................... 50
4-5. Data Memory Addressing (µPD789101A, 789111A, 789121A, 789131A) ....................................... 52
4-6. Data Memory Addressing (µPD789102A, 789112A, 789122A, 789132A) ....................................... 53
4-7. Data Memory Addressing (µPD789104A, 789114A, 789124A, 789134A) ....................................... 54
4-8. Data Memory Addressing (µPD78F9116A, 78F9136A) .................................................................... 55
4-9. Program Counter Configuration ......................................................................................................... 56
4-10. Program Status Word Configuration .................................................................................................. 56
4-11. Stack Pointer Configuration ................................................................................................................ 58
4-12. Data to be Saved to Stack Memory ................................................................................................... 58
4-13. Data to be Restored from Stack Memory .......................................................................................... 58
4-14. General Register Configuration .......................................................................................................... 59

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5-2. Block Diagram of P00 to P03 ............................................................................................................. 75
5-3. DataSheet4U.com
Block Diagram of P10 and P11 .......................................................................................................... 76
5-4. Block Diagram of P20 ......................................................................................................................... 77
5-5. Block Diagram of P21 ......................................................................................................................... 78
5-6. Block Diagram of P22, P23, and P25 ................................................................................................ 79
5-7. Block Diagram of P24 ......................................................................................................................... 80
5-8. Block Diagram of P50 to P53 ............................................................................................................. 81
5-9. Block Diagram of P60 to P63 ............................................................................................................. 82
5-10. Port Mode Register Format ................................................................................................................ 84
5-11. Pull-Up Resistor Option Register 0 Format ....................................................................................... 84
5-12. Pull-Up Resistor Option Register B2 Format ..................................................................................... 84

6-1. Block Diagram of Clock Generator .................................................................................................... 87

6-2. Processor Clock Control Register Format ......................................................................................... 88
6-3. External Circuit of System Clock Oscillator ....................................................................................... 89
6-4. Examples of Incorrect Resonator Connection ................................................................................... 90
6-5. Switching CPU Clock .......................................................................................................................... 93

7-1. Block Diagram of Clock Generator .................................................................................................... 95

7-2. Processor Clock Control Register Format ......................................................................................... 96
7-3. External Circuit of System Clock Oscillator ....................................................................................... 97
7-4. Examples of Incorrect Resonator Connection ................................................................................... 98
7-5. Switching CPU Clock .......................................................................................................................... 101

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LIST OF FIGURES (2/4)

Figure No. Title Page

8-1. Block Diagram of 16-Bit Timer 20 ...................................................................................................... 104

8-2. 16-Bit Timer Mode Control Register 20 Format ................................................................................ 107
8-3. Port Mode Register 2 Format ............................................................................................................. 108
8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation ........................... 109
8-5. Timing of Timer Interrupt Operation ................................................................................................... 110
8-6. Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation .............................. 111
8-7. Timer Output Timing ........................................................................................................................... 111
8-8. Settings of 16-Bit Timer Mode Control Register 20 at Capture Operation ...................................... 112
8-9. Capture Operation Timing (Both Edges of CPT20 Pin Are Specified) ............................................. 112
8-10. 16-Bit Timer Counter 20 Readout Timing .......................................................................................... 113

9-1. Block Diagram of 8-Bit Timer/Event Counter 80 ............................................................................... 117

9-2. 8-Bit Timer Mode Control Register 80 Format .................................................................................. 118
9-3. Port Mode Register 2 Format ............................................................................................................. 119
9-4. Interval Timer Operation Timing ......................................................................................................... 121
9-5. External Event Counter Operation Timing (with Rising Edge Specified) ......................................... 122
9-6. Square Wave Output Timing .............................................................................................................. 124
et4U.com 9-7. PWM Output Timing ............................................................................................................................ 126
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9-8. Start Timing of 8-Bit Timer Counter ................................................................................................... 127
9-9. DataSheet4U.com
External Event Counter Operation Timing ......................................................................................... 127

10-1 Block Diagram of Watchdog Timer ..................................................................................................... 130

10-2 Timer Clock Select Register 2 Format ............................................................................................... 131
10-3 Format of Watchdog Timer Mode Register ........................................................................................ 132

11-1. Block Diagram of 8-Bit A/D Converter ............................................................................................... 136

11-2. Format of A/D Converter Mode Register 0 ........................................................................................ 138
11-3. Format of Analog Input Channel Specification Register 0 ................................................................ 139
11-4. Basic Operation of 8-Bit A/D Converter ............................................................................................. 141
11-5. Relationships between Analog Input Voltage and A/D Conversion Result ...................................... 142
11-6. Software-Started A/D Conversion ...................................................................................................... 143
11-7. How to Reduce Current Consumption in Standby Mode .................................................................. 144
11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ...................... 145
11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) ........................... 145
11-10. Analog Input Pin Treatment ................................................................................................................ 146
11-11. A/D Conversion End Interrupt Request Generation Timing .............................................................. 147
11-12. AVDD Pin Treatment ............................................................................................................................ 147

12-1. Block Diagram of 10-Bit A/D Converter ............................................................................................. 150

12-2. Format of A/D Converter Mode Register 0 ........................................................................................ 152
12-3. Format of Analog Input Channel Specification Register 0 ................................................................ 153
12-4. Basic Operation of 10-Bit A/D Converter ........................................................................................... 155
12-5. Relationships between Analog Input Voltage and A/D Conversion Result ...................................... 156
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LIST OF FIGURES (3/4)

Figure No. Title Page

12-6. Software-Started A/D Conversion ...................................................................................................... 157

12-7. How to Reduce Current Consumption in Standby Mode .................................................................. 158
12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ...................... 159
12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) ........................... 159
12-10. Analog Input Pin Treatment ................................................................................................................ 160
12-11. A/D Conversion End Interrupt Request Generation Timing .............................................................. 161
12-12. AVDD Pin Treatment ............................................................................................................................ 161

13-1. Serial Interface 20 Block Diagram ..................................................................................................... 164

13-2. Baud Rate Generator Block Diagram ................................................................................................ 165
13-3. Serial Operating Mode Register 20 Format ....................................................................................... 167
13-4. Asynchronous Serial Interface Mode Register 20 Format ................................................................ 168
13-5. Asynchronous Serial Interface Status Register 20 Format ............................................................... 170
13-6. Baud Rate Generator Control Register 20 Format ........................................................................... 171
13-7. Asynchronous Serial Interface Transmit/Receive Data Format ........................................................ 183
13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing ..................................... 185
13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing ........................................... 186
et4U.com 13-10. Receive Error Timing .......................................................................................................................... 187
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13-11. 3-Wire Serial I/O Mode Timing ........................................................................................................... 192
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14-1. Block Diagram of Multiplier ................................................................................................................ 200
14-2. Multiplier Control Register 0 Format .................................................................................................. 201
14-3. Multiplier Operation Timing ................................................................................................................. 202

15-1. Basic Configuration of Interrupt Function .......................................................................................... 205

15-2. Interrupt Request Flag Register Format ............................................................................................ 207
15-3. Interrupt Mask Flag Register Format ................................................................................................. 208
15-4. External Interrupt Mode Register 0 Format ....................................................................................... 209
15-5. Program Status Word Configuration .................................................................................................. 210
15-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement ....................... 212
15-7. Timing of Non-Maskable Interrupt Request Acknowledgement ........................................................ 212
15-8. Acknowledging Non-Maskable Interrupt Request ............................................................................. 212
15-9. Interrupt Acknowledgement Program Algorithm ................................................................................ 214
15-10. Interrupt Request Acknowledgement Timing (Example of MOV A,r) ................................................ 215
15-11. Interrupt Request Acknowledgement Timing
(When Interrupt Request Flag Is Generated at the Last Clock During Instruction Execution) ....... 215
15-12. Example of Multiple Interrupts ........................................................................................................... 216

16-1. Oscillation Stabilization Time Select Register Format ...................................................................... 220

16-2. Releasing HALT Mode by Interrupt .................................................................................................... 222
16-3. Releasing HALT Mode by RESET Input ............................................................................................ 223
16-4. Releasing STOP Mode by Interrupt ................................................................................................... 225
16-5. Releasing STOP Mode by RESET Input ........................................................................................... 226
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LIST OF FIGURES (4/4)

Figure No. Title Page

17-1. Block Diagram of Reset Function ...................................................................................................... 227

17-2. Reset Timing by RESET Input ........................................................................................................... 228
17-3. Reset Timing by Overflow in Watchdog Timer .................................................................................. 228
17-4. Reset Timing by RESET Input in STOP Mode .................................................................................. 228

18-1. Communication Mode Selection Format ............................................................................................ 232

18-2. Flashpro III Connection in 3-Wire Serial I/O Mode ........................................................................... 233
18-3. Flashpro III Connection in UART Mode ............................................................................................. 234
18-4. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used) .............................................. 234
18-5. Flashpro III Connection in 3-Wire Serial I/O Mode ........................................................................... 235
18-6. Flashpro III Connection in UART Mode ............................................................................................. 235
18-7. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used) .............................................. 236

A-1. Development Tool Configuration ........................................................................................................ 252

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LIST OF TABLES (1/2)

Table No. Title Page

1-1. Differences between Standard Quality Grade Products and (A) Products ...................................... 30

2-1. Differences between Standard Quality Grade Products and (A) Products ...................................... 38

3-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins ...................... 44

4-1. Internal ROM Capacity ....................................................................................................................... 51

4-2. Vector Table ......................................................................................................................................... 51
4-3. Special Function Register List ............................................................................................................ 61

5-1. Port Functions ..................................................................................................................................... 74

5-2. Configuration of Port ........................................................................................................................... 75
5-3. Port Mode Register and Output Latch Settings When Using Alternate Functions .......................... 83

6-1. Configuration of Clock Generator ...................................................................................................... 87

6-2. Maximum Time Required for Switching CPU Clock .......................................................................... 93

et4U.com 7-1. Configuration of Clock Generator ...................................................................................................... 95

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7-2. Maximum Time Required for Switching CPU Clock .......................................................................... 101
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8-1. Configuration of 16-Bit Timer 20 ........................................................................................................ 104
8-2. Interval Time of 16-Bit Timer 20 ......................................................................................................... 109
8-3. Settings of Capture Edge ................................................................................................................... 112

9-1. Interval Time of 8-Bit Timer/Event Counter 80 .................................................................................. 115

9-2. Square Wave Output Range of 8-Bit Timer/Event Counter 80 ......................................................... 115
9-3. 8-Bit Timer/Event Counter 80 Configuration ...................................................................................... 116
9-4. Interval Time of 8-Bit Timer/Event Counter 80 (At fX = 5.0-MHz Operation) ................................... 120
9-5. Interval Time of 8-Bit Timer/Event Counter 80 (At fCC = 4.0-MHz Operation) ................................. 120
9-6. Square Wave Output Range of 8-Bit Timer/Event Counter 80 (At fX = 5.0-MHz Operation) .......... 123
9-7. Square Wave Output Range of 8-Bit Timer/Event Counter 80 (At fCC = 4.0-MHz Operation) ........ 123

10-1. Runaway Detection Time of Watchdog Timer ................................................................................... 129

10-2. Interval Time ........................................................................................................................................ 129
10-3. Configuration of Watchdog Timer ....................................................................................................... 130
10-4. Runaway Detection Time of Watchdog Timer ................................................................................... 133
10-5. Interval Time of Interval Timer ............................................................................................................ 134

11-1. Configuration of 8-Bit A/D Converter ................................................................................................. 135

12-1. Configuration of 10-Bit A/D Converter ............................................................................................... 149

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LIST OF TABLES (2/2)

Table No. Title Page

13-1. Serial Interface 20 Configuration ....................................................................................................... 163

13-2. Serial Interface 20 Operating Mode Settings .................................................................................... 169
13-3. Example of Relationships between System Clock and Baud Rate .................................................. 172
13-4. Relationship between ASCK20 Pin Input Frequency and Baud Rate
(When BRGC20 Is Set to 80H) .......................................................................................................... 173
13-5. Example of Relationship between System Clock and Baud Rate .................................................... 181
13-6. Relationship between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H) ................................................................................ 182
13-7. Receive Error Causes ......................................................................................................................... 187

15-1. Interrupt Source List ........................................................................................................................... 204

15-2. Flags Corresponding to Interrupt Request Signal ............................................................................. 206
15-3. Time from Generation of Maskable Interrupt Request to Processing .............................................. 213

16-1. HALT Mode Operating Status ............................................................................................................ 221

16-2. Operation after Release of HALT Mode ............................................................................................. 223
16-3. STOP Mode Operating Status ............................................................................................................ 224
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17-1. Hardware Status after Reset .............................................................................................................. 229

18-1. Differences between Flash Memory and Mask ROM Versions ........................................................ 231
18-2. Communication Mode ......................................................................................................................... 232
18-3. Functions of Flash Memory Programming ......................................................................................... 233
18-4. Example of Settings for PG-FP3 ........................................................................................................ 237

19-1. Selection of Mask Option for Pins ...................................................................................................... 239

20-1. Operand Identifiers and Description Methods ................................................................................... 241

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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)

1.1 Features

ROM and RAM capacities

Item Program Memory Data Memory

Part Number (Internal High-Speed RAM)

µPD789101A, 789111A ROM 2 Kbytes 256 bytes

µPD789102A, 789112A 4 Kbytes
µPD789104A, 789114A 8 Kbytes

µPD78F9116A Flash 16 Kbytes

memory

System clock: Crystal/ceramic oscillation

Two minimum instruction execution times selectable: high speed (0.4 µs) and low speed (1.6 µs) (system clock:
5.0 MHz)
20 I/O ports
Serial interface: 1 channel
3-wire serial I/O mode/UART mode selectable
8-bit resolution A/D converter: 4 channels (µPD789104A Subseries)
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3 timers
• 16-bit timer: DataSheet4U.com
1 channel
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
Multiplier: 8 bits × 8 bits = 16 bits
Vectored interrupt source: 10
Supply voltage: VDD = 1.8 to 5.5 V
Operating ambient temperature: TA = –40 to +85°C

1.2 Applications

Vacuum cleaners, washing machines, refrigerators, battery chargers, etc.

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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)

1.3 Ordering Information

Part Number Package Internal ROM

µPD789101AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789102AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789104AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789111AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789112AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789114AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD78F9116AMC-5A4 30-pin plastic SSOP (7.62 mm (300) ) Flash memory
µPD789101AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789102AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789104AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789111AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789112AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789114AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM

Remark ××× indicates ROM code suffix.

1.4 Quality Grade

et4U.com Part Number Package Quality Grade

DataShee
µPD789101AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789102AMC-×××-5A4 DataSheet4U.com
30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789104AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789111AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789112AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789114AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD78F9116AMC-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789101AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789102AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789104AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789111AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789112AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789114AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special

Remark ××× indicates ROM code suffix.

Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)

1.5 Pin Configuration (Top View)

• 30-pin plastic SSOP (7.62 mm (300) )

µPD789101AMC-×××-5A4 µPD789102AMC-×××-5A4 µPD789104AMC-×××-5A4
µPD789111AMC-×××-5A4 µPD789112AMC-×××-5A4 µPD789114AMC-×××-5A4
µPD78F9116AMC-5A4
µPD789101AMC(A)-×××-5A4 µPD789102AMC(A)-×××-5A4 µPD789104AMC(A)-×××-5A4
µPD789111AMC(A)-×××-5A4 µPD789112AMC(A)-×××-5A4 µPD789114AMC(A)-×××-5A4

P23/INTP0/CPT20/SS20 1 30 P22/SI20/RXD20
P24/INTP1/TO80/TO20 2 29 P21/SO20/TXD20
P25/INTP2/TI80 3 28 P20/SCK20/ASCK20
AVDD 4 27 P11
P60/ANI0 5 26 P10
P61/ANI1 6 25 VDD
P62/ANI2 7 24 VSS
P63/ANI3 8 23 X1
AVSS 9 22 X2
IC0 10 21 IC0
P50 11 20 IC0 (VPP)

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P51 12 19 RESET
P52 13 18 P03 DataShee
P53 DataSheet4U.com
14 17 P02
P00 15 16 P01

Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.

Remark Pin connection in parentheses is intended for the µPD78F9116A.

ANI0 to ANI3: Analog Input RxD20: Receive Data

ASCK20: Asynchronous Serial Input SCK20: Serial Clock
AVDD: Analog Power Supply SI20: Serial Input
AVSS: Analog Ground SO20: Serial Output
CPT20: Capture Trigger Input SS20: Chip Select Input
IC0: Internally Connected TI80: Timer Input
INTP0 to INTP2: Interrupt from Peripherals TO20, TO80: Timer Output
P00 to P03: Port 0 TxD20: Transmit Data
P10, P11: Port 1 VDD: Power Supply
P20 to P25: Port 2 VPP: Programming Power Supply
P50 to P53: Port 5 VSS: Ground
P60 to P63: Port 6 X1, X2: Crystal 1, 2
RESET: Reset
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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)

1.6 78K/0S Series Lineup

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products under mass production

Products under development

Y subseries supports SMB.

Small, general-purpose

44 pins µ PD789046 µ PD789026 with subsystem clock added

42/44 pins µ PD789026 µ PD789014 with timer reinforced and ROM and RAM expanded
28 pins µ PD789014 UART. Low-voltage (1.8-V) operation

Small, general-purpose + A/D

44/48 pins µ PD789217AY RC oscillation model of µ PD789197AY

44/48 pins µ PD789197AY µ PD789177 with internal EEPROMTM
44 pins µ PD789177 µ PD789177Y µ PD789167 with improved A/D
44 pins µ PD789167 µ PD789167Y µ PD789104A with improved timer
30 pins µ PD789156 µ PD789146 with improved A/D
30 pins µ PD789146 µ PD789104A with EEPROM added
30 pins µ PD789134A µ PD789124A with improved A/D
30 pins µ PD789124A RC oscillation model of µ PD789104A
30 pins µ PD789114A µ PD789104A with improved A/D
30 pins µ PD789104A µ PD789026 with A/D and multiplier added

et4U.com For inverter control

DataShee
44 pins µ PD789842 Internal inverter control circuit and UART
DataSheet4U.com
78K/0S
series For driving LCD

80 pins µ PD789417A µ PD789407A with improved A/D

80 pins µ PD789407A µ PD789456 with improved I/O
64 pins µ PD789456 µ PD789446 with improved A/D
64 pins µ PD789446 µ PD789426 with improved display output
64 pins µ PD789436 µ PD789426 with improved A/D
64 pins µ PD789426 µ PD789306 with A/D added
64 pins µ PD789316 RC oscillation model of µ PD789306
64 pins µ PD789306 Basic subseries for driving LCD

For driving Dot LCD

144 pins µ PD789835 Segment/common output: 96 pins

88 pins µ PD789830 Segment: 40 pins, common: 16 pins

For ASSP

52 pins µ PD789467 µ PD789327 with A/D added

52 pins µ PD789327 For remote controller. Internal LCD controller/driver
44 pins µ PD789800 For PC keyboard. Internal USB function
44 pins µ PD789840 For key pad. Internal POC
20 pins µ PD789861 RC oscillation model of µPD789860
20 pins µ PD789860 For keyless entry. Internal POC and key return circuit

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26 User’s Manual U14643EJ1V0UM00

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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)

The major differences between subseries are shown below.

Function Timer VDD

ROM 8-bit 10-bit
Serial Interface I/O MIN Remark
Capacity A/D A/D
Subseries Name 8-bit 16-bit Watch WDT Value

Small, µPD789046 16 K 1 ch 1 ch 1 ch 1 ch − − 1 ch (UART:1 ch) 34 pins 1.8 V −

general-
µPD789026 4 K-16 K −
purpose
µPD789014 2 K-4 K 2 ch − 22 pins

Small, µPD789177 16 K-24 K 3 ch 1 ch 1 ch 1 ch − 8 ch 1 ch (UART: 1 ch) 31 pins 1.8 V −

general-
µPD789167 8 ch −
purpose
+ A/D µPD789156 8 K-16 K 1 ch − − 4 ch 20 pins Internal
EEPROM
µPD789146 4 ch −

µPD789134A 2 K-8 K 4 ch RC oscillation

version
µPD789124A 4 ch −

µPD789114A − 4 ch −

µPD789104A 4 ch −

For µPD789842 8 K-16 K 3 ch Note 1 ch 1 ch 8 ch − 1 ch (UART: 1 ch) 30 pins 4.0 V −

inverter
control

For LCD µPD789417A 12 K-24 K 3 ch 1 ch 1 ch 1 ch 7 ch 1 ch (UART: 1 ch) 43 pins 1.8 V −

et4U.com driving
µPD789407A 7 ch − DataShee
µPD789456 12 K-16 K 2 ch −
DataSheet4U.com 6 ch 30 pins

µPD789446 6 ch −

µPD789436 − 6 ch 40 pins

µPD789426 6 ch −

µPD789316 8 K to 16K − 2 ch (UART: 1 ch) 23 pins RC oscillation

version

µPD789306 −

For Dot µPD789835 24 K-60 K 6 ch − 1 ch 1 ch 2 ch − 1 ch 27 pins 1.8 V −

LCD
µPD789830 24 K 1 ch 1 ch − 1 ch (UART: 1 ch) 30 pins 2.7 V
driving

ASSP µPD789467 4 K-24 K 2 ch − 1 ch 1 ch 1 ch − − 18 pins 1.8 V Internal LCD

µPD789327 − 1 ch 21 pins

µPD789800 8 K 2 ch 1 ch − 1 ch − 2 ch (USB: 1 ch) 31 pins 4.0 V −

µPD789840 4 ch 1 ch 29 pins 2.8 V

µPD789861 4 K − − − 14 pins 1.8 V RC oscillation

version,
Internal
EEPROM

µPD789860 Internal
EEPROM

Note 10-bit timer: 1 channel

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User’s Manual U14643EJ1V0UM00 27

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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)

1.7 Block Diagram

TI80/INTP2/P25 8-bit TIMER/

PORT0 P00 to P03
TO80/TO20 EVENT COUNTER 80
/INTP1/P24

TO20/TO80
/INTP1/P24 PORT1 P10, P11
16-bit TIMER 20
CPT20/INTP0
/SS20/P23

PORT2 P20 to P25

WATCHDOG TIMER
ROM
78K/0S (FLASH
CPU CORE MEMORY)
PORT5 P50 to P53
SCK20/ASCK20
/P20
SO20/TxD20/P21 SERIAL
INTERFACE 20
SI20/RxD20/P22
SS20/INTP0 PORT6 P60 to P63
/CPT20/P23
RAM

ANI0/P60 to
ANI3/P63
et4U.com AVDD A/D CONVERTER SYSTEM
RESET
DataShee
X1
CONTROL
AVSS X2
DataSheet4U.com

INTP0/CPT20
/P23/SS20
INTERRUPT
INTP1/TO80
CONTROL /TO20/P24
VDD VSS IC0
(VPP) INTP2/TI80/P25

Remarks 1. The size of the internal ROM varies depending on the product.
2. Items in parentheses apply to the µPD78F9116A.

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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)

1.8 Outline of Functions

Item µPD789101A µPD789102A µPD789104A µPD78F9116A

µPD789111A µPD789112A µPD789114A
Maks ROM Mask ROM Flash memory

Internal memory ROM 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes

High-speed RAM 256 bytes
System clock Crystal/ceramic oscillation

Minimum instruction execution time 0.4/1.6 µs (@5.0-MHz operation with system clock)
General registers 8 bits × 8 registers
Instruction set • 16-bit operations
• Bit manipulations (such as set, reset, and test)

Multiplier 8 bits × 8 bits = 16 bits

I/O ports Total: 20
• CMOS input: 4
• CMOS I/O: 12
• N-ch open-drain (12-V withstand voltage): 4
A/D converter 8-bit resolution × 4 channels (µPD789104A Subseries)
10-bit resolution × 4 channels (µPD789114A Subseries)

Serial interface 3-wire serial I/O mode/UART mode selectable: 1 channel

Timer 16-bit timer: 1 channel
et4U.com 8-bit timer/event counter: 1 channel
DataShee
Watchdog timer: 1 channel
Timer outputs DataSheet4U.com
One output

Vectored interrupt Maskable Internal: 6, External: 3

Non-maskable Internal: 1
Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = –40 to +85°C

Packages 30-pin plastic SSOP (7.62 mm (300) )

An outline of the timers is shown below.

16-Bit Timer 20 8-Bit Timer/Event Counter 80 Watchdog Timer

Operating Interval timer — 1 channel 1 channelNote
Mode External event timer — 1 channel —
Function Timer output 1 output 1 output —
PWM output — 1 output —
Square wave output — 1 output —
Capture 1 input — —
Interrupt source 1 1 1

Note Since the watchdog timer provides the watchdog timer function and interval timer function, select the one
out of two functions.

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User’s Manual U14643EJ1V0UM00 29

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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)

1.9 Differences between Standard quality Grade Products and (A) Products

Table 1-1 shows the differences between the standard quality grade products (µPD789101A, 789102A, 789104A,
789111A, 789112A, 789114A) and (A) products (µPD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A),
789114A(A)).

Table 1-1. Differences between Standard Quality Grade Products and (A) Products

Part Number Standard Quality Grade Products (A) Products

Item
Quality grade Standard Special

Electrical Specifications Refer to separate Data Sheets

et4U.com DataShee
DataSheet4U.com

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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)

2.1 Features

ROM and RAM capacities

Item Program Memory Data Memory

Part Number (Internal High-Speed RAM)

µPD789121A, 789131A ROM 2 Kbytes 256 bytes

µPD789122A, 789132A 4 Kbytes
µPD789124A, 789134A 8 Kbytes

µPD78F9136A Flash 16 Kbytes

memory

System clock: RC oscillation

Two minimum instruction execution times selectable: high speed (0.5 µs) and low speed (2.0 µs) (system clock:
4.0 MHz)
20 I/O ports
Serial interface: 1 channel
3-wire serial I/O mode/UART mode selectable
8-bit resolution A/D converter: 4 channels (µPD789124A Subseries)
et4U.com 10-bit resolution A/D converter: 4 channels (µPD789134A Subseries)
DataShee
3 timers
• 16-bit timer: DataSheet4U.com
1 channel
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
Multiplier: 8 bits × 8 bits = 16 bits
Vectored interrupt source: 10
Supply voltage: VDD = 1.8 to 5.5 V
Operating ambient temperature: TA = –40 to +85°C

2.2 Applications

Vacuum cleaners, washing machines, refrigerators, battery chargers, etc.

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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)

2.3 Ordering Information

Part Number Package Internal ROM

µPD789121AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789122AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789124AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789131AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789132AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789134AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD78F9136AMC-5A4 30-pin plastic SSOP (7.62 mm (300) ) Flash memory
µPD789121AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789122AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789124AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789131AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789132AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM
µPD789134AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Mask ROM

Remark ××× indicates ROM code suffix.

2.4 Quality Grade

et4U.com Part Number Package Quality Grade

DataShee
µPD789121AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789122AMC-×××-5A4 DataSheet4U.com
30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789124AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789131AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789132AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789134AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD78F9136AMC-5A4 30-pin plastic SSOP (7.62 mm (300) ) Standard
µPD789121AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789122AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789124AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789131AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789132AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special
µPD789134AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300) ) Special

Remark ××× indicates ROM code suffix.

Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)

2.5 Pin Configuration (Top View)

• 30-pin plastic SSOP (7.62 mm (300) )

µPD789121AMC-×××-5A4 µPD789122AMC-×××-5A4 µPD789124AMC-×××-5A4
µPD789131AMC-×××-5A4 µPD789132AMC-×××-5A4 µPD789134AMC-×××-5A4
µPD78F9136AMC-5A4
µPD789121AMC(A)-×××-5A4 µPD789122AMC(A)-×××-5A4 µPD789124AMC(A)-×××-5A4
µPD789131AMC(A)-×××-5A4 µPD789132AMC(A)-×××-5A4 µPD789134AMC(A)-×××-5A4

P23/INTP0/CPT20/SS20 1 30 P22/SI20/RXD20
P24/INTP1/TO80/TO20 2 29 P21/SO20/TXD20
P25/INTP2/TI80 3 28 P20/SCK20/ASCK20
AVDD 4 27 P11
P60/ANI0 5 26 P10
P61/ANI1 6 25 VDD
P62/ANI2 7 24 VSS
P63/ANI3 8 23 CL1
AVSS 9 22 CL2
IC0 10 21 IC0
P50 11 20 IC0 (VPP)
P51 12 19 RESET

et4U.com P52 13 18 P03

DataShee
P53 14 17 P02
P00 DataSheet4U.com
15 16 P01

Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.

Remark Pin connection in parentheses is intended for the µPD78F9136A.

ANI0 to ANI3: Analog Input RESET: Reset

ASCK20: Asynchronous Serial Input RxD20: Receive Data
AVDD: Analog Power Supply SCK20: Serial Clock
AVSS: Analog Ground SI20: Serial Input
CL1, CL2: RC oscillator SO20: Serial Output
CPT20: Capture Trigger Input SS20: Chip Select Input
IC0: Internally Connected TI80: Timer Input
INTP0 to INTP2: Interrupt from Peripherals TO20, TO80: Timer Output
P00 to P03: Port 0 TxD20: Transmit Data
P10, P11: Port 1 VDD: Power Supply
P20 to P25: Port 2 VPP: Programming Power Supply
P50 to P53: Port 5 VSS: Ground
P60 to P63: Port 6

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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)

2.6 78K/0S Series Lineup

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products under mass production

Products under development

Y subseries supports SMB.

Small, general-purpose

44 pins µ PD789046 µ PD789026 with subsystem clock added

42/44 pins µ PD789026 µ PD789014 with timer reinforced and ROM and RAM expanded
28 pins µ PD789014 UART. Low-voltage (1.8-V) operation

Small, general-purpose + A/D

44/48 pins µ PD789217AY RC oscillation model of µ PD789197AY

44/48 pins µ PD789197AY µ PD789177 with internal EEPROMTM
44 pins µ PD789177 µ PD789177Y µ PD789167 with improved A/D
44 pins µ PD789167 µ PD789167Y µ PD789104A with improved timer
30 pins µ PD789156 µ PD789146 with improved A/D
30 pins µ PD789146 µ PD789104A with EEPROM added
30 pins µ PD789134A µ PD789124A with improved A/D
30 pins µ PD789124A RC oscillation model of µ PD789104A
et4U.com 30 pins µ PD789114A µ PD789104A with improved A/D
30 pins µ PD789104A µ PD789026 with A/D and multiplier added DataShee
DataSheet4U.com
For inverter control

44 pins µ PD789842 Internal inverter control circuit and UART

78K/0S
series For driving LCD

80 pins µ PD789417A µ PD789407A with improved A/D

80 pins µ PD789407A µ PD789456 with improved I/O
64 pins µ PD789456 µ PD789446 with improved A/D
64 pins µ PD789446 µ PD789426 with improved display output
64 pins µ PD789436 µ PD789426 with improved A/D
64 pins µ PD789426 µ PD789306 with A/D added
64 pins µ PD789316 RC oscillation model of µ PD789306
64 pins µ PD789306 Basic subseries for driving LCD

For driving Dot LCD

144 pins µ PD789835 Segment/common output: 96 pins

88 pins µ PD789830 Segment: 40 pins, common: 16 pins

For ASSP

52 pins µ PD789467 µ PD789327 with A/D added

52 pins µ PD789327 For remote controller. Internal LCD controller/driver
44 pins µ PD789800 For PC keyboard. Internal USB function
44 pins µ PD789840 For key pad. Internal POC
20 pins µ PD789861 RC oscillation model of µPD789860
20 pins µ PD789860 For keyless entry. Internal POC and key return circuit

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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)

The major differences between subseries are shown below.

Function Timer VDD

ROM 8-bit 10-bit
Serial Interface I/O MIN Remark
Capacity A/D A/D
Subseries Name 8-bit 16-bit Watch WDT Value

Small, µPD789046 16 K 1 ch 1 ch 1 ch 1 ch − − 1 ch (UART:1 ch) 34 pins 1.8 V −

general-
µPD789026 4 K-16 K −
purpose
µPD789014 2 K-4 K 2 ch − 22 pins

Small, µPD789177 16 K-24 K 3 ch 1 ch 1 ch 1 ch − 8 ch 1 ch (UART: 1 ch) 31 pins 1.8 V −

general-
µPD789167 8 ch −
purpose
+ A/D µPD789156 8 K-16 K 1 ch − − 4 ch 20 pins Internal
EEPROM
µPD789146 4 ch −

µPD789134A 2 K-8 K 4 ch RC oscillation

version
µPD789124A 4 ch −

µPD789114A − 4 ch −

µPD789104A 4 ch −

For µPD789842 8 K-16 K 3 ch Note 1 ch 1 ch 8 ch − 1 ch (UART: 1 ch) 30 pins 4.0 V −

inverter
control

For LCD µPD789417A 12 K-24 K 3 ch 1 ch 1 ch 1 ch 7 ch 1 ch (UART: 1 ch) 43 pins 1.8 V −

et4U.com driving
µPD789407A 7 ch − DataShee
µPD789456 12 K-16 K 2 ch −
DataSheet4U.com 6 ch 30 pins

µPD789446 6 ch −

µPD789436 − 6 ch 40 pins

µPD789426 6 ch −

µPD789316 8 K to 16K − 2 ch (UART: 1 ch) 23 pins RC oscillation

version

µPD789306 −

For Dot µPD789835 24 K-60 K 6 ch − 1 ch 1 ch 2 ch − 1 ch 27 pins 1.8 V −

LCD
µPD789830 24 K 1 ch 1 ch − 1 ch (UART: 1 ch) 30 pins 2.7 V
driving

ASSP µPD789467 4 K-24 K 2 ch − 1 ch 1 ch 1 ch − − 18 pins 1.8 V Internal LCD

µPD789327 − 1 ch 21 pins

µPD789800 8 K 2 ch 1 ch − 1 ch − 2 ch (USB: 1 ch) 31 pins 4.0 V −

µPD789840 4 ch 1 ch 29 pins 2.8 V

µPD789861 4 K − − − 14 pins 1.8 V RC oscillation

version,
Internal
EEPROM

µPD789860 Internal
EEPROM

Note 10-bit timer: 1 channel

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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)

2.7 Block Diagram

TI80/INTP2/P25 8-bit TIMER/

PORT0 P00 to P03
TO80/TO20 EVENT COUNTER 80
/INTP1/P24

TO20/TO80
/INTP1/P24 PORT1 P10, P11
16-bit TIMER 20
CPT20/INTP0
/SS20/P23

PORT2 P20 to P25

WATCHDOG TIMER
ROM
78K/0S (FLASH
CPU CORE MEMORY)
PORT5 P50 to P53
SCK20/ASCK20
/P20
SO20/TxD20/P21 SERIAL
INTERFACE 20
SI20/RxD20/P22
SS20/INTP0 PORT6 P60 to P63
/CPT20/P23
RAM

ANI0/P60 to
ANI3/P63
RESET
et4U.com AVDD A/D CONVERTER SYSTEM
CL1 DataShee
CONTROL
AVSS CL2
DataSheet4U.com

INTP0/CPT20
/P23/SS20
INTERRUPT
INTP1/TO80
CONTROL /TO20/P24
VDD VSS IC0
(VPP)
INTP2/TI80/P25

Remarks 1. The size of the internal ROM varies depending on the product.
2. Items in parentheses apply to the µPD78F9136A.

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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)

2.8 Outline of Functions

Item µPD789121A µPD789122A µPD789124A µPD78F9136A

µPD789131A µPD789132A µPD789134A
Internal memory ROM Mask ROM Flash memory

2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes

High-speed RAM 256 bytes
System clock Crystal/ceramic oscillation

Minimum instruction execution time 0.5/2.0 µs (@4.0-MHz operation with system clock)
General registers 8 bits × 8 registers
Instruction set • 16-bit operations
• Bit manipulations (such as set, reset, and test)

Multiplier 8 bits × 8 bits = 16 bits

I/O ports Total: 20
• CMOS input: 4
• CMOS I/O: 12
• N-ch open-drain (12-V withstand voltage ): 4
A/D converter 8-bit resolution × 4 channels (µPD789124A Subseries)
10-bit resolution × 4 channels (µPD789134A Subseries)

Serial interface 3-wire serial I/O mode/UART mode selectable: 1 channel

Timer 16-bit timer: 1 channel
et4U.com 8-bit timer/event counter: 1 channel
DataShee
Watchdog timer: 1 channel
Timer outputs DataSheet4U.com
One output

Vectored interrupt Maskable Internal: 6, External: 3

Non-maskable Internal: 1
Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = –40 to +85°C

Packages 30-pin plastic SSOP (7.62 mm (300) )

An outline of the timers is shown below.

16-Bit Timer 20 8-Bit Timer/Event Counter 80 Watchdog Timer

Operating Interval timer — 1 channel 1 channelNote
Mode External event timer — 1 channel —
Function Timer output 1 output 1 output —
PWM output — 1 output —
Square wave output — 1 output —
Capture 1 input — —
Interrupt source 1 1 1

Note Since the watchdog timer provides the watchdog timer function and interval timer function, select the one
out of two functions.

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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)

2.9 Differences between Standard quality Grade Products and (A) Products

Table 2-1 shows the differences between the standard quality grade products (µPD789121A, 789122A, 789124A,
789131A, 789132A, 789134A) and (A) products (µPD789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A),
789134A(A)).

Table 2-1. Differences between Standard Quality Grade Products and (A) Products

Part Number Standard Quality Grade Products (A) Products

Item
Quality grade Standard Special

Electrical Specifications Refer to separate Data Sheets

et4U.com DataShee
DataSheet4U.com

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38 User’s Manual U14643EJ1V0UM00

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CHAPTER 3 PIN FUNCTIONS

3.1 Pin Function List

(1) Port pins

Pin Name Input/Output Function After Reset Alternate Function

P00 to P03 Input/output Port 0 Input —
4-bit input/output port
Input/output can be specified in 1-bit units
When used as an input port, an on-chip pull-up
resistor can be specified by means of pull-up resistor
option register 0 (PU0).
P10, P11 Input/output Port 1 Input —
2-bit input/output port
Input/output can be specified in 1-bit units
When used as an input port, an on-chip pull-up
resistor can be specified by means of pull-up resistor
option register 0 (PU0).
P20 Input/output Port 2 Input SCK20/ASCK20
P21 6-bit input/output port SO20/TxD20
Input/output can be specified in 1-bit units
et4U.com P22
An on-chip pull-up resistor can be specified by means
SI20/RxD20
DataShee
P23 INTP0/CPT20/SS20
of pull-up resistor option register B2 (PUB2)
DataSheet4U.com
P24 INTP1/TO80/TO20
P25 INTP2/TI80
P50 to P53 Input/output Port 5 Input —
4-bit N-channel open-drain input/output port
Input/output can be specified in 1-bit units
For a mask ROM version, an on-chip pull-up resistor
can be specified by the mask option.
P60 to P63 Input Port 6 Input ANI0 to ANI3
4-bit input port

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CHAPTER 3 PIN FUNCTIONS

(2) Non-port pins

Pin Name Input/Output Function After Reset Alternate Function

INTP0 Input External interrupt input for which the valid edge (rising Input P23/CPT20/SS20

INTP1 edge, falling edge, or both rising and falling edges) P24/TO80/TO20
INTP2 can be specified. P25/TI80
SI20 Input Serial data input to serial interface Input P22/RxD20

SO20 Output Serial data output from serial interface Input P21/TxD20
SCK20 Input/output Serial clock input/output for serial interface Input P20/ASCK20
ASCK20 Input Serial clock input to asynchronous serial interface Input P20/SCK20

SS20 Input Chip select input to serial interface Input P23/CPT20/INTP0

RxD20 Input Serial data input to asynchronous serial interface Input P22/SI20
TxD20 Output Serial data output from asynchronous serial interface Input P21/SO20

TI80 Input External count clock input to 8-bit timer (TM80) Input P25/INTP2
TO80 Output 8-bit timer (TM80) output Input P24/INTP1/TO20
TO20 Output 16-bit timer (TM20) output Input P24/INTP1/TO80

CPT20 Input Capture edge input Input P23/INTP0/SS20

ANI0 to ANI3 Input A/D converter analog input Input P60 to P63
AVSS — A/D converter ground potential — —

AVDD — A/D converter analog power supply — —

et4U.com DataShee
X1 Input Connecting crystal resonator for system clock — —
X2 — oscillation (µPD789104A, 789114A Subseries) — —
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CL1 Input Connecting resistor (R) and capacitor (C) for system — —
CL2 — clock oscillation (µPD789124A and 789134A Subseries) — —
RESET Input System reset input Input —

VDD — Positive power supply — —

VSS — Ground potential — —
IC0 — Internally connected. Directly connect to the VSS pin. — —

VPP — Sets flash memory programming mode. Applies high — —

voltage when a program is written or verified. Connect
directly to VSS in normal operation mode.

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CHAPTER 3 PIN FUNCTIONS

3.2 Description of Pin Functions

3.2.1 P00 to P03 (Port 0)

These pins constitute a 4-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode
register 0 (PM0). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by
means of pull-up resistor option register 0 (PU0).

3.2.2 P10, P11 (Port 1)

These pins constitute a 2-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode
register 1 (PM1). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by
means of pull-up resistor option register 0 (PU0).

3.2.3 P20 to P25 (Port 2)

These pins constitute a 6-bit I/O port. In addition, they function as timer input/outputs, external interrupt inputs,
and serial interface data and clock input/outputs.
Port 2 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In this mode, P20 to P25 function as a 6-bit I/O port. Port 2 can be specified as input or output mode in 1-
bit units by using port mode register 2 (PM2). Use of an on-chip pull-up resistor can be specified in 1-bit units
by using pull-up resistor option register B2 (PUB2), regardless of the setting of port mode register 2 (PM2).

et4U.com (2) Control mode

DataShee
In this mode, P20 to P25 function as the timer input/output, the external interrupt input, and the clock input/
output of the serial interface and theDataSheet4U.com
data input/output.

(a) TI80
This is the external clock input pin for 8-bit timer/event counter 80.

(b) TO20, TO80

TO20 is the output pin of the 16-bit timer. TO80 is the output pin of the 8-bit timer.

(c) CPT20
This is the input pin of the capture edge.

(d) INTP0 to INTP2

These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both rising
and falling edges) can be specified.

(e) SI20, SO20

These are the serial data I/O pins of the serial interface.

(f) SCK20
These are the serial clock I/O pins of the serial interface.

(g) SS20
This is the chip select input pin of the serial interface.

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CHAPTER 3 PIN FUNCTIONS

(h) RxD20, TxD20

These are the serial data I/O pins of the asynchronous serial interface.

(i) ASCK20
This is the serial clock input pin of the asynchronous serial interface.

Caution When using these pins as serial interface pins, the input/output mode and output latch must be
set according to the functions to be used. For the details of the setting, refer to Table 13-2 Serial
Interface 20 Operating Mode Settings.

3.2.4 P50 to P53 (Port 5)

This is a 4-bit N-ch open-drain I/O port. Port 5 can be specified in input or output mode in 1-bit units by using
port mode register 5 (TM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by the mask
option.

3.2.5 P60 to P63 (Port 6)

This is a 4-bit input-only port. In addition to general-purpose input ports, these pins function as the A/D converter
input pins.
(1) Port mode
In the port mode, port 6 functions as a 4-bit input-only port.

(2) Control mode

et4U.com In the control mode, the pins of port 6 can be used as A/D converter analog inputs (ANI0 to ANI3).
DataShee

3.2.6 RESET DataSheet4U.com

This pin inputs an active-low system reset signal.

3.2.7 X1, X2 (µPD789104A, 789114A Subseries)

These pins are used to connect a crystal resonator for system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.

3.2.8 CL1, CL2 (µPD789124A, 789134A Subseries)

Resistor (R) and capacitor (C) connect pins for system clock oscillation.

3.2.9 AVDD
Analog power supply pin of the A/D converter. Always use the same potential as that of the VDD pin even when
the A/D converter is not used.

3.2.10 AVSS
This is a ground potential pin of the A/D converter. Always use the same potential as that of the VSS pin even
when the A/D converter is not used.

3.2.11 VDD
Positive power supply pin

3.2.12 VSS
Ground pin

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CHAPTER 3 PIN FUNCTIONS

3.2.13 VPP (µPD78F9116A, 78F9136A only)

A high voltage should be applied to this pin when the flash memory programming mode is set and when the program
is written or verified.
Directly connect this pin to VSS in the normal operation mode.

3.2.14 IC0 (pin No.20) (mask ROM version only)

The IC0 (Internally Connected) pin (No. 20) (refer to 1.5 Pin Configuration (Top View), 2.5 Pin Configuration
(Top View)) is used to set the µPD789104A/114A/124A/134A subseries in the test mode before shipment. In the
normal operation mode, connect this pin directly to the VSS pin with as short a wiring length as possible.
If a potential difference is generated between the IC0 pin and VSS pin due to a long wiring length between the IC0
pin and VSS pin or external noise superimposed on the IC0 pin, the user program may not run correctly.

Connect the IC0 pin directly to the VSS pin.

VSS IC0 (pin No.20)

Keep short

et4U.com 3.2.15 IC0 (pins No.10 and No.21)

DataShee
The IC0 pins (No.10 and No.21) (refer to 1.5 Pin Configuration (Top View), 2.5 Pin Configuration (Top View)
are internally connected. DataSheet4U.com
Connect the IC0 pins directly to VSS.

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CHAPTER 3 PIN FUNCTIONS

3.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins

The input/output circuit type for each pin and the recommended connection of pins are shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins

Pin Name Input/Output Circuit Type Input/Output Recommended Connection of Unused Pins

P00 to P03 5-A Input/output Input: Independently connect these pins to VDD or
P10, P11 VSS via a resistor.
Output: Leave open
P20/SCK20/ASCK20 8-A

P21/SO20/TxD20
P22/SI20/RxD20
P23/INTP0/CPT20/SS20 Input: Independently connect these pins to VSS via

P24/INTP1/TO80/TO20 a resistor.
Output: Leave open
P25/INTP2/TI80
P50 to P53 13-W Input: Independently connect these pins to VDD via a
(Mask ROM version) resistor.

P50 to P53 13-V Output: Leave open

( µPD78F9116A, 78F9136A)
P60/ANI0 to P63/ANI3 9-C Input Connect to VDD or VSS.
et4U.com AVDD — — Connect to VDD. DataShee
AVSS Connect to VSS.
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RESET 2 Input —
IC0 — — Connect directly to VSS.

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CHAPTER 3 PIN FUNCTIONS

Figure 3-1. Pin Input/Output Circuits

Type 2 Type 9-C

P-ch Comparator
IN +
N-ch –
IN
AVSS
VREF
(Threshold voltage)

Schmitt-triggered input with hysteresis characteristics

Input
enable

Type 5-A VDD Type 13-V

Pull-up
P-ch IN/OUT
enable
Output data
VDD N-ch
Output disable

Data P-ch VSS

IN/OUT
et4U.com Input enable
DataShee
Output N-ch
disable Middle-voltage input buffer
VSS DataSheet4U.com

Input
enable

Type 8-A VDD Type 13-W

VDD
Pull-up resistor
Pull-up (mask option)
P-ch
enable
IN/OUT
VDD
Output data
N-ch
Data Output disable
P-ch

IN/OUT VSS
Output N-ch Input enable
disable
VSS
Middle-voltage input buffer

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[MEMO]

et4U.com DataShee
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CHAPTER 4 CPU ARCHITECTURE

4.1 Memory Space

The µPD789104A/114A/124A/134A Subseries can access 64 Kbytes of memory space. Figures 4-1 through 4-
4 show the memory maps.

Figure 4-1. Memory Map (µPD789101A, 789111A, 789121A, 789131A)

FFFFH

Special function registers

256 × 8 bits

FF00H
FEFFH

Internal high-speed RAM

256 × 8 bits

FE00H
et4U.com FDFFH
DataShee
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Reserved
Data
memory space
07FFH

0800H
07FFH

Program area

Program 0080H
Internal ROM
memory space 2,048 × 8 bits 007FH
CALLT table area
0040H
003FH
Program area
0016H
0015H
Vector table area
0000H 0000H

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CHAPTER 4 CPU ARCHITECTURE

Figure 4-2. Memory Map (µPD789102A, 789112A, 789122A, 789132A)

FFFFH

Special function registers

256 × 8 bits

FF00H
FEFFH

Internal high-speed RAM

256 × 8 bits

FE00H
FDFFH

Reserved
Data
memory space
0FFFH

1000H
0FFFH

Program area

et4U.com DataShee

Internal ROMDataSheet4U.com
Program 0080H
memory space 4,096 × 8 bits 007FH
CALLT table area
0040H
003FH
Program area
0016H
0015H
Vector table area
0000H 0000H

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CHAPTER 4 CPU ARCHITECTURE

Figure 4-3. Memory Map (µPD789104A, 789114A, 789124A, 789134A)

FFFFH

Special function registers

256 × 8 bits

FF00H
FEFFH

Internal high-speed RAM

256 × 8 bits

FE00H
FDFFH

Reserved
Data
memory space
1FFFH

2000H
1FFFH

Program area

et4U.com DataShee

Program DataSheet4U.com 0080H

Internal ROM
memory space 8,192 × 8 bits 007FH
CALLT table area
0040H
003FH
Program area
0016H
0015H
Vector table area
0000H 0000H

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CHAPTER 4 CPU ARCHITECTURE

Figure 4-4. Memory Map (µPD78F9116A, 78F9136A)

FFFFH

Special function registers

256 × 8 bits

FF00H
FEFFH

Internal high-speed RAM

256 × 8 bits

FE00H
FDFFH

Reserved
Data
memory space
3FFFH

4000H
3FFFH

Program area

et4U.com DataShee
0080H
Program Flash memoryDataSheet4U.com
memory space 16,384 × 8 bits 007FH
CALLT table area
0040H
003FH
Program area
0016H
0015H
Vector table area
0000H 0000H

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CHAPTER 4 CPU ARCHITECTURE

4.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The µPD789104A/114A/124A/134A Subseries provides the following internal ROMs (or flash memory) containing
the following capacities.

Table 4-1. Internal ROM Capacity

Part Number Internal ROM

Structure Capacity

µPD789101A, 789111A, 789121A, 789131A Mask ROM 2,048 × 8 bits

µPD789102A, 789112A, 789122A, 789132A 4,096 × 8 bits
µPD789104A, 789114A, 789124A, 789134A 8,192 × 8 bits

µPD78F9116A, 78F9136A Flash memory 16,384 × 8 bits

The following areas are allocated to the internal program memory space:

(1) Vector table area

A 22-byte area of addresses 0000H to 0015H is reserved as a vector table area. This area stores program
start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16-
bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an
et4U.com odd address.
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Table 4-2. Vector Table

Vector Table Address Interrupt Request Vector Table Address Interrupt Request
0000H RESET input 000CH INTSR20/INTCSI20

0004H INTWDT 000EH INTST20

0006H INTP0 0010H INTTM80
0008H INTP1 0012H INTTM20

000AH INTP2 0014H INTAD0

(2) CALLT instruction table area

In a 64-byte area of addresses 0040H to 007FH, the subroutine entry address of a 1-byte call instruction
(CALLT) can be stored.

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CHAPTER 4 CPU ARCHITECTURE

4.1.2 Internal data memory (internal high-speed RAM) space

The µPD789104A/114A/124A/134A Subseries provides a 256-byte internal high-speed RAM.
The internal high-speed RAM can also be used as a stack memory.

4.1.3 Special function register (SFR) area

Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (refer
to Table 4-3).

4.1.4 Data memory addressing

The µPD789104A/114A/124A/134A Subseries provides a variety of addressing modes which take account of
memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FEFFH),
particular addressing modes are possible to meet the functions of the special function registers (SFRs) and general
registers. Figures 4-5 through 4-8 show the data memory addressing modes.

Figure 4-5. Data Memory Addressing (µPD789101A, 789111A, 789121A, 789131A)

FFFFH

Special function registers (SFRs) SFR addressing

256 × 8 bits
FF20H
FF1FH

FF00H
et4U.com FEFFH DataShee
DataSheet4U.com Short direct
Internal high-speed RAM
addressing
256 × 8 bits

FE20H
FE1FH

FE00H
FDFFH Direct addressing

Register indirect
addressing

Based addressing

Reserved

0800H
07FFH

Internal ROM
2,048 × 8 bits

0000H

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CHAPTER 4 CPU ARCHITECTURE

Figure 4-6. Data Memory Addressing (µPD789102A, 789112A, 789122A, 789132A)

FFFFH

Special function registers (SFRs) SFR addressing

256 × 8 bits
FF20H
FF1FH

FF00H
FEFFH

Short direct
Internal high-speed RAM
addressing
256 × 8 bits

FE20H
FE1FH

FE00H
FDFFH Direct addressing

Register indirect
addressing

Based addressing

Reserved
et4U.com DataShee
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1000H
0FFFH

Internal ROM
4,096 × 8 bits

0000H

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CHAPTER 4 CPU ARCHITECTURE

Figure 4-7. Data Memory Addressing (µPD789104A, 789114A, 789124A, 789134A)

FFFFH

Special function registers (SFRs) SFR addressing

256 × 8 bits
FF20H
FF1FH

FF00H
FEFFH

Short direct
Internal high-speed RAM
addressing
256 × 8 bits

FE20H
FE1FH
FE00H
FDFFH
Direct addressing

Register indirect
addressing

Based addressing

Reserved
et4U.com DataShee
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2000H
1FFFH

Internal ROM
8,192 × 8 bits

0000H

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CHAPTER 4 CPU ARCHITECTURE

Figure 4-8. Data Memory Addressing (µPD78F9116A, 78F9136A)

FFFFH

Special function registers (SFRs) SFR addressing

256 × 8 bits
FF20H
FF1FH

FF00H
FEFFH

Short direct
Internal high-speed RAM
addressing
256 × 8 bits

FE20H
FE1FH
FE00H
FDFFH
Direct addressing

Register indirect
addressing

Based addressing

Reserved

et4U.com DataShee
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4000H
3FFFH

Flash memory
16,384 × 8 bits

0000H

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CHAPTER 4 CPU ARCHITECTURE

4.2 Processor Registers

The µPD789104A/114A/124A/134A Subseries provides the following on-chip processor registers:

4.2.1 Control registers

The control registers contain special functions to control the program sequence statuses and stack memory. The
program counter, program status word, and stack pointer are control registers.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents is set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 4-9. Program Counter Configuration

15 0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

et4U.com (2) Program status word (PSW)

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The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
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Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.
RESET input sets the PSW to 02H.

Figure 4-10. Program Status Word Configuration

7 0

PSW IE Z 0 AC 0 0 1 CY

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CHAPTER 4 CPU ARCHITECTURE

(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledge operations of CPU.
When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable
interrupt are disabled.
When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgement is
controlled with an interrupt mask flag for various interrupt sources.
This flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

(c) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to (1). It is reset (0) in
all other cases.

(d) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.

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CHAPTER 4 CPU ARCHITECTURE

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.

Figure 4-11. Stack Pointer Configuration

15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 4-12 and 4-13.

Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.

Figure 4-12. Data to be Saved to Stack Memory

PUSH rp CALL, CALLT Interrupt

instruction instructions
et4U.com SP SP _ 3
DataShee

SP SP _ 2 SP SP _ 2
DataSheet4U.com SP _ 3 PC7 to PC0

Register pair
SP _ 2 SP _ 2 PC7 to PC0 SP _ 2 PC15 to PC8
lower

Register pair
SP _ 1 SP _ 1 PC15 to PC8 SP _ 1 PSW
higher

SP SP SP

Figure 4-13. Data to be Restored from Stack Memory

POP rp RET instruction RETI instruction

instruction

Register pair
SP SP PC7 to PC0 SP PC7 to PC0
lower

Register pair
SP + 1 SP + 1 PC15 to PC8 SP + 1 PC15 to PC8
higher

SP SP + 2 SP SP + 2 SP + 2 PSW

SP SP + 3

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CHAPTER 4 CPU ARCHITECTURE

4.2.2 General registers

The general registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and in addition, two 8-bit registers in pairs can be used as a 16-
bit register (AX, BC, DE, and HL).
They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).

Figure 4-14. General Register Configuration

(a) Absolute names

16-bit processing 8-bit processing

R7
RP3
R6

R5
RP2
R4

R3
RP1
R2

et4U.com R1
DataShee
RP0
R0
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15 0 7 0

(b) Functional names

16-bit processing 8-bit processing

H
HL
L

D
DE
E

B
BC
C

A
AX
X

15 0 7 0

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CHAPTER 4 CPU ARCHITECTURE

4.2.3 Special function registers (SFRs)

Unlike general registers, special function registers have their own functions and are allocated to the 256-byte area
FF00H to FFFFH.
Special function registers can be manipulated, like general registers, with operation, transfer, and bit manipulation
instructions. The bit units in which one register can be manipulated (1, 8, and 16) differ depending on the special
function register type.
Each bit unit for manipulation can be specified as follows.

• 1-bit manipulation
A symbol reserved by assembler is described as the operand (sfr.bit) of a 1-bit manipulation instruction. This
manipulation can also be specified with an address.

• 8-bit manipulation
A symbol reserved by assembler is described as the operand (sfr) of an 8-bit manipulation instruction. This
manipulation can also be specified with an address.

• 16-bit manipulation
A symbol reserved by assembler is described as the operand of a 16-bit manipulation instruction. When
specifying an address, describe an even address.

Table 4-3 lists the special function registers. The meanings of the symbols in this table are as follows:

et4U.com • Symbol
DataShee
Indicates the addresses of the implemented special function registers. The symbols shown in this column are
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the reserved words of the assembler, and have already been defined in the header file called “sfrbit.h” of the
C compiler. Therefore, these symbols can be used as instruction operands if assembler or integrated debugger
is used.

• R/W
Indicates whether the special function register in question can be read or written.
R/W: Read/write
R: Read only
W: Write only

• Bit units for manipulation

Indicates the bit units (1, 8, and 16) in which the special function register in question can be manipulated.

• After reset
Indicates the status of the special function register when the RESET signal is input.

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CHAPTER 4 CPU ARCHITECTURE

Table 4-3. Special Function Register List (1/2)

Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset
1 bit 8 bits 16 bits

FF00H Port 0 P0 R/W √ √ — 00H

FF01H Port 1 P1 √ √ —
FF02H Port 2 P2 √ √ —

FF05H Port 5 P5 √ √ —
FF06H Port 6 P6 R √ √ —
FF10H 16-bit multiplication result storage register 0 MUL0L MUL0 — √ Note 1 √ Note 2 Undefined

FF11H MUL0H
FF14H A/D conversion result register Note 3 ADCR0 — √ √ Note 2
FF15H

FF16H 16-bit compare register 20 CR20L CR20 W — √ Note 1 √ Note 2 FFFFH

FF17H CR20H
FF18H 16-bit timer counter 20 TM20L TM20 R — √ Note 1 √ Note 2 0000H

FF19H TM20H
FF1AH 16-bit capture register 20 TCP20L TCP20 — √ Note 1 √ Note 2 Undefined
FF1BH TCP20H

FF20H Port mode register 0 PM0 R/W √ √ — FFH

et4U.com DataShee
FF21H Port mode register 1 PM1 √ √ —
FF22H Port mode register 2 PM2
DataSheet4U.com √ √ —

FF25H Port mode register 5 PM5 √ √ —

FF32H Pull-up resistor option register B2 PUB2 √ √ — 00H
FF42H Time clock select register 2 TCL2 — √ —

FF48H 16-bit timer mode control register 20 TMC20 √ √ —

FF50H 8-bit compare register 80 CR80 W — √ —
FF51H 8-bit timer counter 80 TM80 R — √ — Undefined

FF53H 8-bit timer mode control register 80 TMC80 R/W √ √ — 00H

Notes 1. Although these registers are usually accessed in 16-bit units, they can also be accessed in 8-bit units.
Access these registers in 8-bit units by means of direct addressing.
2. These registers can be accessed in 16-bit units only by means of short direct addressing.
3. When this register is used as an 8-bit A/D converter (µPD789104A and 789124A Subseries), it can
be accessed only in 8-bit units. At this time, the register address is FF15H. When this register is used
as a 10-bit A/D converter (µPD789114A and 789134A Subseries), it can be accessed only in 16-bit
units. When using the µPD78F9116A as the flash memory version of the µPD789101A, 789102A,
or 789104A, or when using the µPD78F9136A as the flash memory version of the µPD789121A,
789122A, or 789124A, this register can be accessed in 8-bit units. However, only the object file
assembled with the µPD789101A, 789102A, or 789104A, or object file assembled with the µPD789121A,
789122A, or 789124A can be used.

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CHAPTER 4 CPU ARCHITECTURE

Table 4-3. Special Function Register List (2/2)

Address Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation After Reset
1 bit 8 bits 16 bits

FF70H Asynchronous serial interface mode register 20 ASIM20 R/W √ √ — 00H

FF71H Asynchronous serial interface status register 20 ASIS20 R √ √ —
FF72H Serial operating mode register 20 CSIM20 R/W √ √ —

FF73H Baud rate generator control register 20 BRGC20 — √ —

FF74H Transmit shift register 20 TXS20 SIO20 W — √ — FFH
Receive buffer register 20 RXB20 R — √ — Undefined

FF80H A/D converter mode register 0 ADM0 R/W √ √ — 00H

FF84H Analog input channel specification register 0 ADS0 √ √ —
FFD0H Multiplication data register A0 MRA0 W √ √ — Undefined

FFD1H Multiplication data register B0 MRB0 √ √ —

FFD2H Multiplier control register 0 MULC0 R/W √ √ — 00H
FFE0H Interrupt request flag register 0 IF0 √ √ —

FFE1H Interrupt request flag register 1 IF1 √ √ —

FFE4H Interrupt mask flag register 0 MK0 √ √ — FFH
FFE5H Interrupt mask flag register 1 MK1 √ √ —

FFECH External interrupt mode register 0 INTM0 — √ — 00H

et4U.com DataShee
FFF7H Pull-up resistor option register 0 PU0 √ √ —
FFF9H Watchdog timer mode register WDTM
DataSheet4U.com √ √ —

FFFAH Oscillation stabilization time select register Note OSTS — √ — 04H

FFFBH Processor clock control register PCC √ √ — 02H

Note µPD789104A, 789114A Subseries only

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CHAPTER 4 CPU ARCHITECTURE

4.3 Instruction Address Addressing

An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information is
set to the PC and branched by the following addressing (For details of each instruction, refer to 78K/0S Series User’s
Manual Instruction (U11047E)).

4.3.1 Relative addressing

[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.
In other words, the range of branch in relative addressing is between –128 and +127 of the start address of
the following instruction.
This function is carried out when the “BR $addr16” instruction or a conditional branch instruction is executed.

[Illustration]

15 0
... PC is the start address of
et4U.com PC
the next instruction of DataShee
a BR instruction.
+
DataSheet4U.com
15 8 7 6 0

α S

jdisp8

15 0

PC

When S = 0, α indicates all bits “0”.

When S = 1, α indicates all bits “1”.

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CHAPTER 4 CPU ARCHITECTURE

4.3.2 Immediate addressing

[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the “CALL !addr16 and BR !addr16” instructions are executed.
CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces.

[Illustration]
In case of CALL !addr16, BR !addr16 instruction

7 0

CALL or BR

Low Addr.

High Addr.

15 8 7 0

PC

et4U.com DataShee
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CHAPTER 4 CPU ARCHITECTURE

4.3.3 Table indirect addressing

[Function]
Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can
refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.

[Illustration]

7 6 5 1 0

Instruction code 1 1 ta4–0 1

15 8 7 6 5 1 0

Effective address 0 0 0 0 0 0 0 0 0 1 0

7 Memory (Table) 0

Low Addr.

Effective address + 1 High Addr.

et4U.com DataShee
DataSheet4U.com

15 8 7 0

PC

4.3.4 Register addressing

[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the “BR AX” instruction is executed.

[Illustration]

7 0 7 0

rp A X

15 8 7 0

PC

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CHAPTER 4 CPU ARCHITECTURE

4.4 Operand Address Addressing

The following various methods are available to specify the register and memory (addressing) which undergo
manipulation during instruction execution.

4.4.1 Direct addressing

[Function]
The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier Description
addr16 Label or 16-bit immediate data

[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code 0 0 1 0 1 0 0 1 OP code

0 0 0 0 0 0 0 0 00H

et4U.com 1 1 1 1 1 1 1 0 FEH
DataShee
DataSheet4U.com
[Illustration]

7 0
OP code

addr16 (low)

addr16 (high)

Memory

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CHAPTER 4 CPU ARCHITECTURE

4.4.2 Short direct addressing

[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high-
speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of all SFR areas. In this
area, ports which are frequently accessed in a program and a compare register of the timer/event counter are
mapped, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to
1FH, bit 8 is set to 1. Refer to [Illustration].

[Operand format]

Identifier Description
saddr Label or FE20H to FF1FH immediate data

saddrp Label or FE20H to FF1FH immediate data (even address only)

[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H

et4U.com Instruction code 1 1 1 1 0 1 0 1 OP code DataShee

DataSheet4U.com
1 0 0 1 0 0 0 0 90H (saddr-offset)

0 1 0 1 0 0 0 0 50H (immediate data)

[Illustration]

7 0

OP code

saddr-offset

Short direct memory

15 8 0
Effective
address 1 1 1 1 1 1 1 α

When 8-bit immediate data is 20H to FFH, α = 0.

When 8-bit immediate data is 00H to 1FH, α = 1.

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CHAPTER 4 CPU ARCHITECTURE

4.4.3 Special function register (SFR) addressing

[Function]
Memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction
word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier Description

sfr Special function register name

[Description example]
MOV PM0, A; When selecting PM0 for sfr

Instruction code 1 1 1 0 0 1 1 1

0 0 1 0 0 0 0 0

[Illustration]

et4U.com DataShee
7 0

OP code DataSheet4U.com
sfr-offset

SFR
15 8 7 0
Effective
1 1 1 1 1 1 1 1
address

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CHAPTER 4 CPU ARCHITECTURE

4.4.4 Register addressing

[Function]
General registers are accessed as operands. The general register to be accessed is specified with the register
specify code and functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When
an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

[Operand format]

Identifier Description

r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL

‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X,
A, C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]
MOV A, C; When selecting the C register for r

Instruction code 0 0 0 0 1 0 1 0

et4U.com 0 0 1 0 0 1 0 1 DataShee
DataSheet4U.com
Register specify code

INCW DE; When selecting the DE register pair for rp

Instruction code 1 0 0 0 1 0 0 0

Register specify code

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CHAPTER 4 CPU ARCHITECTURE

4.4.5 Register indirect addressing

[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair
to be accessed is specified with the register pair specify code in the instruction code. This addressing can
be carried out for all the memory spaces.

[Operand format]

Identifier Description
— [DE], [HL]

[Description example]
MOV A, [DE]; When selecting register pair [DE]

Instruction code 0 0 1 0 1 0 1 1

[Illustration]

15 8 7 0

DE D E
et4U.com Memory address specified DataShee
7 0 by register pair DE
DataSheet4U.com
The contents of addressed
memory are transferred
7 0

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CHAPTER 4 CPU ARCHITECTURE

4.4.6 Based addressing

[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum
is used to address the memory. Addition is performed by expanding the offset data as a positive number to
16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description
— [HL+byte]

[Description example]
MOV A, [HL+10H]; When setting byte to 10H

Instruction code 0 0 1 0 1 1 0 1

0 0 0 1 0 0 0 0

4.4.7 Stack addressing

et4U.com [Function] DataShee

The stack area is indirectly addressed with the stack pointer (SP) contents.
DataSheet4U.com
This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN
instructions are executed or the register is saved/reset upon generation of an interrupt request.
Stack addressing enables to address the internal high-speed RAM area only.

[Description example]
In the case of PUSH DE

Instruction code 1 0 1 0 1 0 1 0

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D a t a S h e4eU
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[MEMO]

et4U.com DataShee
DataSheet4U.com

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CHAPTER 5 PORT FUNCTIONS

5.1 Functions of Ports

The µPD789104A/114A/124A/134A Subseries provides the ports shown in Figure 5-1, enabling various methods
of control.
Numerous other functions are provided that can be used in addition to the digital I/O port function. For more
information on these additional functions, refer to CHAPTER 3 PIN FUNCTIONS.

Figure 5-1. Port Types

P50 P00
Port 5 Port 0
P53 P03

P60 P10
P11 Port 1
Port 6
P63
P20

Port 2

et4U.com P25
DataShee
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CHAPTER 5 PORT FUNCTIONS

Table 5-1. Port Functions

Pin Name Input/Output Function After Reset Alternate Function

P00 to P03 Input/output Port 0 Input —
4-bit I/O port
Input/output can be specified in 1-bit units
When used as input port, an on-chip pull-up resistor can
be specified by means of pull-up resistor option
register 0 (PU0).
P10, P11 Input/output Port 1 Input —
2-bit I/O port
Input/output can be specified in 1-bit units
When used as input port, an on-chip pull-up resistor can
be specified by means of pull-up resistor option
register 0 (PU0).
P20 Input/output Port 2 Input ASCK20/SCK20
P21 6-bit I/O port TxD20/SO20
Input/output can be specified in 1-bit units
P22 RxD20/SI20
An on-chip pull-up resistor can be specified by means
P23 of pull-up resistor option register B2 (PUB2). INTP0/CPT20/SS20
P24 INTP1/TO80/TO20
P25 INTP2/TI80
P50 to P53 Input/output Port 5 Input —
4-bit N-ch open-drain I/O port
et4U.com Input/output can be specified in 1-bit units
DataShee
An on-chip pull-up resistor can be specified for mask
DataSheet4U.com
ROM versions by the mask option.

P60 to 63 Input Port 6 Input ANI0 to ANI3

4-bit input-only port

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CHAPTER 5 PORT FUNCTIONS

5.2 Port Configuration

A port consists of the following hardware.

Table 5-2. Configuration of Port

Parameter Configuration
Control register Port mode register (PMm: m = 0 to 2, 5)
Pull-up resistor option register 0 (PU0)
Pull-up option register B2 (PUB2)
Port Total: 20 (input: 7, input/output: 16)

Pull-up resistor • Mask ROM versions

Total: 16 (software control: 12, mask option specification: 4)
• Flash memory versions
Total: 12 (software control only)

5.2.1 Port 0
This is a 4-bit I/O port with output latches. Port 0 can be specified as input or output mode in 1-bit units by using
port mode register 0 (PM0). When pins P00 to P03 are used as input port pins, on-chip pull-up resistors can be
connected in 4-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 0 to input mode.
Figure 5-2 shows the block diagram of port 0.
et4U.com DataShee
Figure 5-2. Block Diagram of P00 to P03
DataSheet4U.com
VDD

WRPU0

PU00
P-ch
RD
Selector
Internal bus

WRPORT

Output latch
P00 to P03
(P00 to P03)
WRPM

PM00 to PM03

PU0: Pull-up resistor option register 0

PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
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CHAPTER 5 PORT FUNCTIONS

5.2.2 Port 1
This is a 2-bit I/O port with output latches. Port 1 can be specified as input or output mode in 1-bit units by using
port mode register 1 (PM1). When pins P10 and P11 are used as input port pins, on-chip pull-up resistors can be
connected in 2-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 1 to input mode.
Figure 5-3 shows the block diagram of port 1.

Figure 5-3. Block Diagram of P10 and P11

VDD

WRPU0

PU01
P-ch
RD
Selector
Internal bus

WRPORT

Output latch
P10, P11
(P10, P11)
et4U.com WRPM DataShee
DataSheet4U.com
PM10, PM11

PU0: Pull-up resistor option register 0

PM: Port mode register
RD: Port 1 read signal
WR: Port 1 write signal

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CHAPTER 5 PORT FUNCTIONS

5.2.3 Port 2
This is a 6-bit I/O port with output latches. Port 2 can be specified as input or output mode in 1-bit units by using
port mode register 2 (PM2). Use of on-chip pull-up resistors can be specified for pins P20 to P25 in 1-bit units by
using pull-up resistor option register B2 (PUB2).
The port is also used as a serial interface I/O, clock I/O, timer I/O, and external i;Derrupt input.
RESET input sets port 2 to input mode.
Figures 5-4 through 5-7 show block diagrams of port 2.

Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set according
to the function to be used. For how to set the latches, see Table 13-2 Serial Interface 20 Operating
Mode Settings.

Figure 5-4. Block Diagram of P20

VDD

WRPUB2

PUB20 P-ch

Alternate
function
et4U.com DataShee
RD
DataSheet4U.com
Selector
Internal bus

WRPORT

Output latch
(P20) P20/ASCK20/
SCK20
WRPM

PM20

Alternate
function

PUB2: Pull-up resistor option register B2

PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal

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CHAPTER 5 PORT FUNCTIONS

Figure 5-5. Block Diagram of P21

VDD

WRPUB2

PUB21 P-ch

RD

Selector
Internal bus

WRPORT

Output latch
(P21) P21/TxD20/
SO20
WRPM

PM21

et4U.com DataShee
Alternate
function DataSheet4U.com

Serial output
enable signal

PUB2: Pull-up resistor option register B2

PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal

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CHAPTER 5 PORT FUNCTIONS

Figure 5-6. Block Diagram of P22, P23, and P25

VDD

WRPUB2

PUB22, PUB23,
P-ch
PUB25

Alternate
function
RD

Selector
Internal bus

WRPORT

Output latch
P22/RxD20/SI20
(P22, P23, P25)
P23/INTP0/CPT20/
WRPM SS20
P25/INTP2/TI80

PM22, PM23,
PM25

et4U.com DataShee
DataSheet4U.com

PUB2: Pull-up resistor option register B2

PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal

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CHAPTER 5 PORT FUNCTIONS

Figure 5-7. Block Diagram of P24

VDD

WRPUB2

PUB24 P-ch

Alternate
function
RD

Selector
P24/INTP1/
TO80/TO20
Internal bus

WRPORT

Output latch
(P24)
WRPM

PM24

Alternate
et4U.com function
DataShee
Alternate DataSheet4U.com
function

PUB2: Pull-up resistor option register B2

PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal

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CHAPTER 5 PORT FUNCTIONS

5.2.4 Port 5
This is a 4-bit N-ch open-drain I/O port with output latches. Port 5 can be specified as input or output mode in
1-bit units by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be
incorporated can be specified by the mask option.
RESET input sets port 5 to input mode.
Figure 5-8 shows a block diagram of port 5.

Figure 5-8. Block Diagram of P50 to P53

RD VDD

Mask option resistor

Mask ROM version only.
For flash memory version,
a pull-up resistor is not
incorporated.

Selector
P50 to P53
Internal bus

WRPORT

Output latch
(P50 to P53) N-ch

et4U.com DataShee
WRPM
DataSheet4U.com

PM50 to PM53

PM: Port mode register

RD: Port 5 read signal
WR: Port 5 write signal

Caution When using port 5 of µPD78F9116A and 78F9136A as an input port, be sure to observe the
restrictions listed below.

<1> When VDD = 1.8 to 5.5 V

Use within the range of TA = 25 to 85°C

<2> When TA = –40 to +85°C

Use within the range of VDD = 2.7 to 5.5 V

<3> When TA = –40 to +85°C and VDD = 1.8 to 5.5 V

Issue three consecutive read instructions when reading port 5.

If the above restrictions are not observed, the input value may be read incorrectly.
Note, however, that these resrictions do not apply when port 5 pins are used as output pins, or
DataSheet4U.com when the product is other than µPD78F9116A or 78F9136A.

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CHAPTER 5 PORT FUNCTIONS

5.2.5 Port 6
This is a 4-bit input port.
The port is also used as an analog input to the A/D converter.
RESET input sets port 6 to input mode.
Figure 5-9 shows a block diagram of port 6.

Figure 5-9. Block Diagram of P60 to P63

RD
Internal bus

+ P60/ANI0 to P63/ANI3
A/D converter
et4U.com –
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VREF

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CHAPTER 5 PORT FUNCTIONS

5.3 Port Function Control Registers

The following three types of registers control the ports.

• Port mode registers (PM0 to PM2, PM5)

• Pull-up resistor option register 0 (PU0)
• Pull-up resistor option register B2 (PUB2)

(1) Port mode registers (PM0 to PM2, PM5)

These registers are used to set port input/output in 1-bit units.
Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 5-3.

Caution As port 2 has an alternate function as external interrupt input, when the port function output
mode is specified and the output level is changed, the interrupt request flag is set. When
the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.

Table 5-3. Port Mode Register and Output Latch Settings When Using Alternate Functions

Pin Name Alternate Function PM×× P××

et4U.com Name Input/Output

DataShee
P23 INTP0 Input 1 ×
DataSheet4U.com
CPT20 Input 1 ×

P24 INTP1 Input 1 ×

TO80 Output 0 0
TO20 Output 0 0

P25 INTP2 Input 1 ×

TI80 Input 1 ×

Caution When Port 2 is used for serial interface pin, the I/O latch or output latch must be set according
to its function. For the setting method, refer to Table 13-2 Serial Interface 20 Operating Mode
Settings.

Remark ×: don’t care

PM××: Port mode register
P××: Port output latch

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CHAPTER 5 PORT FUNCTIONS

Figure 5-10. Port Mode Register Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W

PM1 1 1 1 1 1 1 PM11 PM10 FF21H FFH R/W

PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W

PM5 1 1 1 1 PM53 PM52 PM51 PM50 FF25H FFH R/W

PMmn Pmn pin input/output mode selection (m = 0 to 2, 5, n = 0 to 7)

0 Output mode (output buffer ON)

1 Input mode (output buffer OFF)

(2) Pull-up resistor option register 0 (PU0)

The pull-up resistor option register (PU0) sets whether to use on-chip pull-up resistors at each port or not.
At a port where use of on-chip pull-up resistors has been specified by PU0, the pull-up resistors can be internally
used only for the bits set in input mode. No on-chip pull-up resistors can be used for the bits set in output
mode, in spite of setting PU0. On-chip pull-up resistors can also not be used when the pins are used as the
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PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PU0 to 00H. DataSheet4U.com

Figure 5-11. Pull-Up Resistor Option Register 0 Format

Symbol 7 6 5 4 3 2 <1> <0> Address After reset R/W

PU0 0 0 0 0 0 0 PU01 PU00 FFF7H 00H R/W

PU0m Pm on-chip pull-up resistor selection (m = 0, 1)

0 On-chip pull-up resistor not used

1 On-chip pull-up resistor used

(3) Pull-up resistor option register B2 (PUB2)

This register specifies whether an on-chip pull-up resistor is connected to each pin of port 2. The pin so
specified by PUB2 is connected to on-chip pull-up resistor regardless of the setting of the port mode register.
PUB2 is set with a 1-bit or 8-bit manipulation instruction.
RESET input sets this register to 00H.

Figure 5-12. Pull-Up Resistor Option Register B2 Format

Symbol 7 6 <5> <4> <3> <2> <1> <0> Address After reset R/W
PUB2 0 0 PUB25 PUB24 PUB23 PUB22 PUB21 PUB20 FF32H 00H R/W

PUB2n P2n on-chip pull-up resistor selection (n = 0 to 5)

DataSheet4U.com 0 On-chip pull-up resistor not used

1 On-chip pull-up resistor used

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CHAPTER 5 PORT FUNCTIONS

5.4 Operation of Port Functions

The operation of a port differs depending on whether the port is set in input or output mode, as described below.

5.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is OFF.
The data once written to the output latch is retained until new data is written to the output latch.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin
that is set in the input mode and not subject to manipulation become undefined.

5.4.2 Reading from I/O port

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(1) In output mode
The contents of the output latch can DataSheet4U.com
be read by using a transfer instruction. The contents of the output latch
are not changed.

(2) In input mode

The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed.

Caution When using port 5 of µPD78F9116A and 78F9136A as an input port, be sure to observe the
restrictions listed below.

<1> When VDD = 1.8 to 5.5 V

Use within the range of TA = 25 to 85°C

<2> When TA = –40 to +85°C

Use within the range of VDD = 2.7 to 5.5 V

<3> When TA = –40 to +85°C and VDD = 1.8 to 5.5 V

Issue three consecutive read instructions when reading port 5.

If the above restrictions are not observed, the input value may be read incorrectly.
Note, however, that these resrictions do not apply when port 5 pins are used as output pins, or
when the product is other than µPD78F9116A or 78F9136A.

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CHAPTER 5 PORT FUNCTIONS

5.4.3 Arithmetic operation of I/O port

(1) In output mode

An arithmetic operation can be performed with the contents of the output latch. The result of the operation
is written to the output latch. The contents of the output latch are output from the port pins.
The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is OFF.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin
that is set in the input mode and not subject to manipulation become undefined.

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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)

6.1 Function of Clock Generator

The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The system clock oscillator is the following type.

• System clock (crystal/ceramic) oscillator

This circuit oscillates at frequencies of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP
instruction.

6.2 Configuration of Clock Generator

The clock generator consists of the following hardware.

Table 6-1. Configuration of Clock Generator

Item Configuration

Control register Processor clock control register (PCC)

Oscillator Crystal/ceramic oscillator

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Figure 6-1. Block Diagram of Clock Generator
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Prescaler

Clock to peripheral
X1 hardware
System clock Prescaler
X2 oscillator fX
fX
22
Selector

Standby
STOP Wait control
control CPU clock (fCPU)
circuit
circuit

PCC1

Processor clock control register (PCC)

Internal bus

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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)

6.3 Register Controlling Clock Generator

The clock generator is controlled by the following register:

• Processor clock control register (PCC)

(1) Processor clock control register (PCC)

PCC sets the CPU clock selection and the ratio of division.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.

Figure 6-2. Processor Clock Control Register Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

PCC 0 0 0 0 0 0 PCC1 0 FFFBH 02H R/W

PCC1 CPU clock (fCPU) selection

0 fX (0.2 µ s)

1 fX/22 (0.8 µ s)

Caution Bit 0 and bits 2 to 7 must be set to 0.

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Remarks 1. fX: System clock oscillation frequency
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2. Values in parentheses are when operating at fX = 5.0 MHz.
3. Minimum instruction execution time: 2fCPU
• When fCPU = 0.2 µs: 0.4 µs
• When fCPU = 0.8 µs: 1.6 µs

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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)

6.4 System Clock Oscillator

6.4.1 System clock oscillator

The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the
X1 and X2 pins.
An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the X1
pin, and leave the X2 pin open.
Figure 6-3 shows the external circuit of the system clock oscillator.

Figure 6-3. External Circuit of System Clock Oscillator

(a) Crystal or ceramic oscillation (b) External clock

VSS External
X1 clock X1

Open X2
X2
Crystal
or
ceramic resonator

Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
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• DataSheet4U.com
Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do
not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.

Figure 6-4 shows incorrect examples of resonator connection.

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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)

Figure 6-4. Examples of Incorrect Resonator Connection (1/2)

(a) Too long wiring (b) Crossed signal line

PORTn
(n = 0 to 2, 5, 6)

VSS X1 X2 VSS X1 X2

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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)

Figure 6-4. Examples of Incorrect Resonator Connection (2/2)

(c) Wiring near high fluctuating current (d) Current flowing through ground line of
oscillator (potential at points A, B, and
C fluctuates)

VDD

Pmn
VSS X1 X2
VSS X1 X2

High current

A B C

High current

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(e) Signal is fetched
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VSS X1 X2

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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)

6.4.2 Divider
The divider divides the output of the system clock oscillator (fX) to generate various clocks.

6.5 Operation of Clock Generator

The clock generator generates the following clocks and controls the operating modes of the CPU, such as the
standby mode:

• System clock fX
• CPU clock fCPU
• Clock to peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC), as follows:

(a) The slow mode 2fCPU (1.6 µs: at 5.0-MHz operation) of the system clock is selected when the RESET signal
is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is
stopped.

(b) Two types of CPU clocks fCPU (0.2 µs and 0.8 µs: at 5.0-MHz operation) can be selected by the PCC setting.

(c) Two standby modes, STOP and HALT, can be used.

et4U.com (d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral
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hardware is stopped when the system clock is stopped (except the external clock input operation).
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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)

6.6 Changing Setting of CPU Clock

6.6.1 Time required for switching CPU clock

The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (refer to Table 6-2).

Table 6-2. Maximum Time Required for Switching CPU Clock

Set Value before Switching Set Value after Switching

PCC1 PCC1 PCC1
0 1

0 4 clocks
1 2 clocks

Remark Two clocks are the minimum instruction execution

time of the CPU clock before switching.

6.6.2 Switching CPU clock

The following figure illustrates how the CPU clock switches.

Figure 6-5. Switching CPU Clock

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VDD

RESET

CPU clock
Slow Fastest
operation operation

Wait (6.55 ms: at 5.0-MHz operation)

Internal reset operation

<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during
which oscillation stabilizes (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the low speed of the system clock (1.6 µs: at 5.0-MHz
operation).
<2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest
speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can
be selected.
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)

7.1 Function of Clock Generator

The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock
oscillator consists of the following type.

• System clock (RC) oscillator

This circuit oscillates at frequencies of 2.0 to 4.0 MHz. Oscillation can be stopped by executing the STOP
instruction.

7.2 Configuration of Clock Generator

The clock generator consists of the following hardware.

Table 7-1. Configuration of Clock Generator

Item Configuration

Control register Processor clock control register (PCC)

Oscillator RC oscillator

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Figure 7-1. Block Diagram of Clock Generator
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Prescaler

Clock to peripheral
CL1 hardware
System clock Prescaler
CL2 oscillator fCC
fCC
22
Selector

Standby
STOP Wait control
control CPU clock (fCPU)
circuit
circuit

PCC1

Processor clock control register (PCC)

Internal bus

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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)

7.3 Register Controlling Clock Generator

The clock generator is controlled by the following register:

• Processor clock control register (PCC)

(1) Processor clock control register (PCC)

PCC sets the CPU clock selection and the ratio of division.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 02H.

Figure 7-2. Processor Clock Control Register Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

PCC 0 0 0 0 0 0 PCC1 0 FFFBH 02H R/W

PCC1 CPU clock (fCPU) selection

0 fCC (0.25 µ s)

1 fCC /22 (1.0 µ s)

Caution Bit 0 and bits 2 to 7 must be set to 0.

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Remarks 1. fCC: System clock oscillation frequency
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2. Values in parentheses are when operating at fX = 4.0 MHz.
3. Minimum instruction execution time: 2fCPU
• When fCPU = 0.25 µs: 0.5 µs
• When fCPU = 1.0 µs: 2.0 µs

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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)

7.4 System Clock Oscillator

7.4.1 System clock oscillator

The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (4.0 MHz TYP.) connected across
the CL1 and CL2 pins.
An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the CL1
pin, and leave the CL2 pin open.
Figure 7-3 shows the external circuit of the system clock oscillator.

Figure 7-3. External Circuit of System Clock Oscillator

(a) RC oscillation (b) External clock

External CL1
CL1
clock
C R
CL2 Open CL2
VSS

Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
et4U.com in the above figures to avoid an adverse effect from wiring capacitance.
DataShee

• DataSheet4U.com
Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do
not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.

Figure 7-4 shows incorrect examples of resonator connection.

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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)

Figure 7-4. Examples of Incorrect Resonator Connection (1/2)

(a) Too long wiring (b) Crossed signal line

PORTn
(n = 0 to 2, 5, 6)

CL1 CL2 VSS CL1 CL2 VSS

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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)

Figure 7-4. Examples of Incorrect Resonator Connection (2/2)

(c) Wiring near high fluctuating current (d) Current flowing through ground line of
oscillator (potential at points A and B
fluctuates)

VDD

PORTn
(n = 0 to 2, 5, 6)

CL1 CL2 VSS

CL1 CL2 VSS
High current

A B

High current

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(e) Signal is fetched
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CL1 CL2 VSS

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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)

7.4.2 Divider
The divider divides the output of the system clock oscillator (fCC) to generate various clocks.

7.5 Operation of Clock Generator

The clock generator generates the following clocks and controls the operating modes of the CPU, such as the
standby mode:

• System clock fCC

• CPU clock fCPU
• Clock to peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC), as follows:

(a) The slow mode 2fCPU (2.0 µs: at 4.0-MHz operation) of the system clock is selected when the RESET signal
is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is
stopped.

(b) Two types of CPU clocks fCPU (0.5 µs and 1.0 µs: at 4.0-MHz operation) can be selected by the PCC setting.

(c) Two standby modes, STOP and HALT, can be used.

et4U.com (d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)

7.6 Changing Setting of CPU Clock

7.6.1 Time required for switching CPU clock

The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (refer to Table 7-2).

Table 7-2. Maximum Time Required for Switching CPU Clock

Set Value before Switching Set Value after Switching

PCC1 PCC1 PCC1
0 1

0 4 clocks
1 2 clocks

Remark Two clocks are the minimum instruction execution

time of the CPU clock before switching.

7.6.2 Switching CPU clock

The following figure illustrates how the CPU clock switches.

Figure 7-5. Switching CPU Clock

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VDD

RESET

CPU clock
Slow Fastest
operation operation

Wait (32 µs: at 4.0-MHz operation)

Internal reset operation

<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during
which oscillation stabilizes (27/fCC) is automatically secured.
After that, the CPU starts instruction execution at the low speed of the system clock (2.0 µs: at 4.0-MHz
operation).
<2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest
speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can
be selected.
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CHAPTER 8 16-BIT TIMER 20

The 16-bit timer counter references the free running counter and provides the functions such as timer interrupt
and timer output. In addition, the count value can be captured by a trigger pin.

8.1 16-Bit Timer 20 Functions

16-bit timer 20 has the following functions.

• Timer interrupt
• Timer output
• Count value capture

(1) Timer interrupt

An interrupt is generated when a count value and compare value matches.

(2) Timer output

Timer output control is possible when an count value and compare value matches.

(3) Count value capture

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CHAPTER 8 16-BIT TIMER 20

8.2 16-Bit Timer 20 Configuration

16-bit timer 20 consists of the following hardware.

Table 8-1. Configuration of 16-Bit Timer 20

Item Configuration
Timer counter 16 bits × 1 (TM20)
Register Compare register: 16 bits × 1 (CR20)
Capture register: 16 bits × 1 (TCP20)
Timer output 1 (TO20)
Control register 16-bit timer mode control register 20 (TMC20)
Port mode register 2 (PM2)

Figure 8-1. Block Diagram of 16-Bit Timer 20

Internal bus
16-bit timer mode
control register 20
(TMC20)
P24
TOF20 CPT201CPT200 TOC20 TCL201TCL200 TOE20 output latch PM24

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F/F TO20/P24/
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16-bit compare register 20 (CR20) INTP1/TO80
16-bit timer mode
Match control register 20
INTTM20
2
fCLK/2
Selector

OVF
16-bit timer counter 20 (TM20)
fCLK/26

CPT20/P23/ Edge detection 16-bit capture 16-bit counter

INTP0/SS20 circuit register 20 (TCP20) read buffer

Internal bus

Remark fCLK: fX or fCC

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CHAPTER 8 16-BIT TIMER 20

(1) 16-bit compare register 20 (CR20)

This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and when
they match, generates an interrupt request (INTTM20).
CR20 is set with a 16-bit memory manipulation instruction. The values 0000H to FFFFH can be set.
RESET input sets this register to FFFFH.

Cautions 1. Although this register is manipulated with a 16-bit memory manipulation instruction, an
8-bit memory manipulation instruction can be used. When manipulated with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
2. When rewriting CR20 during count operation, set CR20 to interrupt disable from interrupt
mask flag register 0 (MK10) beforehand. Also, set the timer output data to inversion
disable using 16-bit timer mode control register 20 (TMC20).
When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur
at the moment of rewrite.

(2) 16-bit timer counter 20 (TM20)

This is a 16-bit register that counts count pulses.
TM20 is read with a 16-bit memory manipulation instruction.
This register is free running during count clock input.
RESET input clears this register to 0000H and after which it resumes free running.

Cautions 1. The count value after releasing stop becomes undefined because the count operation
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2. Although this register is manipulated with a 16-bit memory manipulation instruction, an
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8-bit memory manipulation instruction can be used. When manipulated with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
3. When manipulated with an 8-bit memory manipulation instruction, readout should be
performed in the order from lower byte to higher byte and must be in pairs.

(3) 16-bit capture register 20 (TCP20)

This is a 16-bit register that captures the contents of 16-bit timer counter 20 (TM20).
TCP20 is set with a 16-bit memory manipulation instruction.
RESET input sets this register to undefined.

Caution Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-
bit memory manipulation instruction can be used. When manipulated with an 8-bit memory
manipulation instruction, the accessing method should be direct addressing.

(4) 16-bit counter read buffer

This buffer latches a counter value and retains the count value of 16-bit timer counter 20 (TM20).

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CHAPTER 8 16-BIT TIMER 20

8.3 Registers Controlling 16-Bit Timer 20

The following two types of registers control 16-bit timer 20.

• 16-bit timer mode control register 20 (TMC20)

• Port mode register 2 (PM2)

(1) 16-bit timer mode control register 20 (TMC20)

16-bit timer mode control register 20 (TMC20) controls the setting of the counter clock, capture edge, etc.
TMC20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC20 to 00H.

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CHAPTER 8 16-BIT TIMER 20

Figure 8-2. 16-Bit Timer Mode Control Register 20 Format

Symbol 7 <6> 5 4 3 2 1 <0> Address After reset R/W

TMC20 TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 FF48H 00H R/W Note

TOD20 Timer output data

0 Timer output of 0
1 Timer output of 1

TOF20 Overflow flag set

0 Clear by reset and software

1 Set by overflow of 16-bit timer

CPT201 CPT200 Capture edge selection

0 0 Capture operation disabled

0 1 Rising edge of CPT20

1 0 Falling edge of CPT20

1 1 Both edges of CPT20

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TOC20 Timer output data inverse control
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0 Inverse disabled
1 Inverse enabled

TCL201 TCL200 16-bit timer counter 20 count clock selection

At fX = 5.0 MHz At fCC = 4.0 MHz

0 0 fX/22 (1.25 MHz) fCC/22 (1.0 MHz)

0 1 fX/26 (78.1 kHz) fCC/26 (62.5 kHz)

Other than above Setting prohibited

TOE20 16-bit timer 20 output control

0 Output disabled (port mode)

1 Output enabled

Note Bit 7 is read-only.

Remark fX : System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 8 16-BIT TIMER 20

(2) Port mode register 2 (PM2)

This register sets the input/output of port 2 in 1-bit units.
To use the P24/TO20/INTP1/TO80 pin for timer output, set the output latch of PM24 and P24 to 0.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.

Figure 8-3. Port Mode Register 2 Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W

PM24 P24 pin input/output mode selection

0 Output mode (output buffer on)

1 Input mode (output buffer off)

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CHAPTER 8 16-BIT TIMER 20

8.4 16-Bit Timer 20 Operation

8.4.1 Operation as timer interrupt

In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register
20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200.
To operate the 16-bit timer 20 as a timer interrupt, the following settings are required.
• Set count values to CR20
• Set 16-bit timer mode control counter 20 (TMC20) as shown in Figure 8-4.

Figure 8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation

TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20

TMC20 – 0/1 0/1 0/1 0/1 0 0/1 0/1

Setting of count clock (see Table 8-2)

Caution If both the CPT201 and CPT200 flags are set to 0, the capture edge becomes setting prohibited.

When the count value of 16-bit timer counter 20 (TM20) coincides with the value set to CR20, counting of TM20
continues and an interrupt request signal (INTTM20) is generated.
Table 8-3 shows the interval time, and Figure 8-5 shows the timing of the timer interrupt operation.
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Caution When rewriting CR20 during count operation, be sure to follow the procedure below.
<1> DataSheet4U.com
Set CR20 to interrupt disable (by setting bit 7 of interrupt mask flag register 0 (MK0) to 1).
<2> Set inversion control of timer output data to disable (TOC20 = 0)
When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the
moment of rewrite.

Table 8-2. Interval Time of 16-Bit Timer 20

TCL201 TCL200 Count Clock Interval Time

At fX = 5.0 MHz At fCC = 4.0 MHz At fX = 5.0 MHz At fCC = 4.0 MHz
0 0 22/fX (0.8 µs) 22/fCC (1.0 µs) 218/fX (52.4 ms) 218/fCC (65.5 ms)
0 1 26/fX (12.8 µs) 26/fCC (16 µs) 222/fX (838.9 ms) 222/fCC (1,048 ms)
Other than above Setting prohibited

Remark fX : System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 8 16-BIT TIMER 20

Figure 8-5. Timing of Timer Interrupt Operation

Count clock

TM20 count value 0000H 0001H N FFFFH 0000H 0001H N FFFFH

CR20 N N N N N

INTTM20

Interrupt accept Interrupt accept

TO20

TOF20

Overflow flag set

Remark N = 0000H to FFFFH

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CHAPTER 8 16-BIT TIMER 20

8.4.2 Operation as timer output

Timer outputs are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance
based on the intervals of the value set in TCL201 and TCL200.
To operate the 16-bit timer 20 as a timer output, the following settings are required.
• Set P24 to output mode (PM24 = 0)
• Set P24 output latch to 0
• Set the count value to CR20
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-6

Figure 8-6. Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation

TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20

TMC20 – 0/1 0/1 0/1 1 0 0/1 1

TO20 output enable

Setting of count clock (see Table 8-2)
Inverse enable of timer output data

Caution If both CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation prohibited.

When the count value of the 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of
the TO20/P24/INTP1/TO80 pin is inverted. This enables timer output. At that time, TM20 count is continued and
et4U.com an interrupt request signal (INTTM20) is generated.
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Figure 8-7 shows the timing of timer output (see Table 8-2 for the interval time of the 16-bit timer 20).
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Figure 8-7. Timer Output Timing

Count clock

TM20 count value 0000H 0001H N FFFFH 0000H 0001H N FFFFH

CR20 N N N N N

INTTM20

Interrupt accept Interrupt accept

TO20Note

TOF20

Overflow flag set

Note The TO20 initial value becomes low level during output enable (TOE20 = 1).

Remark N = 0000H to FFFFH

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CHAPTER 8 16-BIT TIMER 20

8.4.3 Capture operation

The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) in
synchronization with a capture trigger.
Set as shown in Figure 8-8 to allow 16-bit timer 20 to start the capture operation.

Figure 8-8. Settings of 16-Bit Timer Mode Control Register 20 at Capture Operation

TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20

TMC20 – 0/1 0/1 0/1 0/1 0 0/1 0/1

Count clock selection

Capture edge selection (see Table 8-3)

16-bit capture register 20 (TCP20) starts the capture operation after the CPT20 capture trigger edge has been
detected, and latches and retains the count value of 16-bit timer counter 20. TCP20 fetches the count value within
2 clocks and retains the count value until the next capture edge detection.
Table 8-3 and Figure 8-9 show the setting contents of the capture edge and capture operation timing, respectively.

Table 8-3. Settings of Capture Edge

CPT201 CPT200 Capture Edge Selection

et4U.com 0 0 Capture operation prohibited

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0 1 CPT20 pin rising edge
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1 0 CPT20 pin falling edge
1 1 CPT20 pin both edges

Caution Because TCP20 is rewritten when a capture trigger edge is detected during TCP20 read, disable
the capture trigger detection during TCP20 read.

Figure 8-9. Capture Operation Timing (Both Edges of CPT20 Pin Are Specified)

Count clock

TM20 0000H 0001H N M–1 M

Count read buffer 0000H 0001H N M

TCP20 Undefined N M

Capture start Capture start

CPT20

Capture edge detection Capture edge detection

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CHAPTER 8 16-BIT TIMER 20

8.4.4 16-bit timer counter 20 readout

The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction.
TM20 readout is performed through a counter read buffer. The counter read buffer latches the TM20 count value.
Buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises
and the count value is retained. The counter read buffer value at the retention state can be read out as the count
value.
Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM20 higher
byte falls.
RESET input clears TM20 to 0000H and restarts free running.
Figure 8-10 shows the timing of 16-bit timer counter 20 readout.

Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during oscillation stabilization time.
2. Although TM20 is a dedicated 16-bit transfer instruction register, an 8-bit transfer instruction
can be used.
Execute an 8-bit transfer instruction by direct addressing.
3. When using an 8-bit transfer instruction, execute in the order from lower byte to higher byte
in pairs. If the only lower byte is read, the pending state of the counter read buffer is not
canceled, and if the only higher byte is read, an undefined count value is read.

Figure 8-10. 16-Bit Timer Counter 20 Readout Timing

et4U.com CPU clock

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Count clock DataSheet4U.com

TM20 0000H 0001H N N+1

Count read buffer 0000H 0001H N

TM20 read signal

Read signal latch

prohibited period

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

The 8-bit timer/event counter can be used as an interval timer, external event counter, and for square wave output
and PWM output of arbitrary frequency.

9.1 Functions of 8-Bit Timer/Event Counter 80

8-bit timer/event counter 80 has the following functions:

• Interval timer
• External event counter
• Square wave output
• PWM output

(1) 8-bit interval timer

When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time
interval set in advance.

Table 9-1. Interval Time of 8-Bit Timer/Event Counter 80

et4U.com Minimum Interval Time Maximum Interval Time Resolution

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At fX = 5.0 MHz 1/fX (200 ns) 2 /fX (51.2 µs)
8
1/fX (200 ns)
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23/fX (1.6 µs) 11
2 /fX (409.6 µs) 23/fX (1.6 µs)
At fCC = 4.0 MHz 1/fCC (250 ns) 28/fCC (64 µs) 1/fCC (250 ns)

23/fCC (2.0 µs) 2 /fCC (512 µs)

11
23/fCC (2.0 µs)

Remark f X: System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

(2) External event counter

The number of pulses of an externally input signal can be measured.

(3) Square wave output

A square wave of arbitrary frequency can be output.

Table 9-2. Square Wave Output Range of 8-Bit Timer/Event Counter 80

Minimum Pulse Width Maximum Pulse Width Resolution

At fX = 5.0 MHz 1/fX (200 ns) 28/fX (51.2 µs) 1/fX (200 ns)

23/fX (1.6 µs) 211/fX (409.6 µs) 23/fX (1.6 µs)

At fCC = 4.0 MHz 1/fCC (250 ns) 28/fCC (64 µs) 1/fCC (250 ns)
23/fCC (2.0 µs) 211/fCC (512 µs) 23/fCC (2.0 µs)

Remark f X: System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

(4) PWM output

8-bit resolution PWM output can be produced.

9.2 8-Bit Timer/Event Counter 80 Configuration

8-bit timer/event counter 80 consists of the following hardware.

Table 9-3. 8-Bit Timer/Event Counter 80 Configuration

Item Configuration

Timer counter 8 bits × 1 (TM80)

Register Compare register: 8 bits × 1 (CR80)
Timer output 1 (TO80)

Control register 8-bit timer mode control register 80 (TMC80)

Port mode register 2 (PM2)

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 80

Internal bus

8-bit compare register 80

(CR80)

Match
INTTM80
TO20
fCLK output Note
Clear
Selector

8-bit timer counter 80

fCLK/23 (TM80) R
INV Q
TI80/P25/
INTP2 Q
S
OVF
TO80/P24/
INTP1/TO20

P24 output PM24

TCE80 PWME80 TCL801 TCL800 TOE80 latch

8-bit timer mode control

register 80 (TMC80)
Internal bus

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Note Refer to block diagram of 16-bit timer 20
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Remark fCLK: fX or fCC

(1) 8-bit compare register 80 (CR80)

This is an 8-bit register that compares the value set to CR80 with the 8-bit timer counter 80 (TM80) count value,
and if they match, generates an interrupt request (INTTM80).
CR80 is set with an 8-bit memory manipulation instruction. The values 00H to FFH can be set.
RESET input makes CR80 undefined.

Cautions 1. When rewriting CR80 in timer counter operation mode (i.e. PWME80 (bit 6 of 8-bit timer
mode control register 80 (TMC80) is set to 0), be sure to stop the timer operation before
hand. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request
signal may occur at the moment of rewrite.
2. Do not set CR80 to 00H in the PWM output mode (when PWME80 = 1); otherwise, PWM
may not be output normally.

(2) 8-bit timer counter 80 (TM80)

This is an 8-bit register to count count pulses.
TM80 is read with an 8-bit memory manipulation instruction.
RESET input clears TM80 to 00H.

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

9.3 8-Bit Timer/Event Counter 80 Control Registers

The following two types of registers are used to control the 8-bit timer/event counter 80.

• 8-bit timer mode control register 80 (TMC80)

• Port mode register 2 (PM2)

(1) 8-bit timer mode control register 80 (TMC80)

This register enables/stops operation of 8-bit timer counter 80 (TM80), sets the counter clock of TM80, and
controls the operation of the output control circuit of 8-bit timer/event counter 80.
TMC80 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC80 to 00H.

Figure 9-2. 8-Bit Timer Mode Control Register 80 Format

Symbol <7> <6> 5 4 3 2 1 <0> Address After reset R/W

TMC80 TCE80 PWME80 0 0 0 TCL801TCL800 TOE80 FF53H 00H R/W

TCE80 8-bit timer counter 80 operation control

0 Operation stop (TM80 cleared to 0)

1 Operation enable

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PWME80 Operation mode selection

0 Timer counter operating mode

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1 PWM output operating mode

TCL801TCL800 8-bit timer counter 80 count clock selection

At fX = 5.0-MHz operation At fCC = 4.0-MHz operation

0 0 fX (5.0 MHz) fCC (4.0 MHz)
0 1 fX/23 (625 kHz) fCC/23 (500 kHz)

1 0 Rising edge of TI80

1 1 Falling edge of TI80

TOE80 8-bit timer/event counter 80 output control

0 Output disable (port mode)

1 Output enable

Caution Be sure to set TMC80 after stopping timer operation.

Remark f X: System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

(2) Port mode register 2 (PM2)

This register sets port 2 to input/output in 1-bit units.
When using the P24/TO80/INTP1/TO20 pin for timer output, set the output latch of PM24 and P24 to 0.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.

Figure 9-3. Port Mode Register 2 Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W

PM2n P2n pin input/output mode selection (n = 0 to 5)

0 Output mode (output buffer ON)

1 Input mode (output buffer OFF)

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

9.4 Operation of 8-Bit Timer/Event Counter 80

9.4.1 Operation as interval timer

The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit
compare register 80 (CR80) in advance.
To operate the 8-bit timer/event counter as an interval timer, the following settings are required.

<1> Set 8-bit timer counter 80 (TM80) to operation disable (by setting TCE80 (bit 7 of 8-bit timer mode control
register 80 (TMC80)) to 0).
<2> Set the count clock of the 8-bit timer/event counter 80 (see Tables 9-4 and 9-5)
<3> Set the count value to CR80
<4> Set TM80 to operation enable (TCE80 = 1)

When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, the value of TM80 is cleared
to 0 and TM80 continue counting. At the same time, an interrupt request signal (INTTM80) is generated.
Tables 9-4 and 9-5 show the interval time, and Figure 9-4 shows the timing of interval timer operation.

Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite.
2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts.
et4U.com Therefore, always follow the above procedure when operating the 8-bit timer/event counter
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Table 9-4. Interval Time of 8-Bit Timer/Event Counter 80 (At fX = 5.0-MHz Operation)

TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution

0 0 1/fX (200 ns) 28/fX (51.2 µs) 1/fX (200 ns)
0 1 23/fX (1.6 µs) 211/fX (409.6 µs) 23/fX (1.6 µs)

1 0 TI80 input cycle 28 × TI80 input cycle TI80 input edge cycle
1 1 TI80 input cycle 28 × TI80 input cycle TI80 input edge cycle

Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)

Table 9-5. Interval Time of 8-Bit Timer/Event Counter 80 (At fCC = 4.0-MHz Operation)

TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution

0 0 1/fCC (250 ns) 2 /fCC (64 µs)
8
1/fCC (250 ns)
0 1 2 /fCC (2.0 µs)
3
2 /fCC (512 µs)
11
23/fCC (2.0 µs)

1 0 TI80 input cycle 28 × TI80 input cycle TI80 input edge cycle
1 1 TI80 input cycle 2 × TI80 input cycle
8
TI80 input edge cycle

Remark fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

Figure 9-4. Interval Timer Operation Timing

Count clock

TM80 count value 00H 01H N 00H 01H N 00H 01H N

Clear Clear

CR80 N N N N

TCE80

Count start

INTTM80

Interrupt accept Interrupt accept

TO80

et4U.com Interval time Interval time Interval time

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Remark Interval time = (N + 1) × t : N = 00H to FFH

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

9.4.2 Operation as external event counter

The external event counter counts the number of external clock pulses input to the TI80/P25/INTP2 pin by using
8-bit timer counter 80 (TM80).
To operate the 8-bit timer/event counter 80 as an external event counter, the following settings are required.

<1> Set P25 to input mode (PM25 = 1)

<2> Set 8-bit timer counter 80 (TM80) to operation disable (by setting TCE80 (bit 7 of 8-bit timer mode control
register 80 (TMC80)) to 0).
<3> Specify the rising/falling edges of TI80 (see Tables 9-4 and 9-5), and set TO80 to output disable (i.e. set
TOE80 (bit 0 of TMC80) to 0) and PWM output to disable (i.e. set PWME80 (bit 6 of TMC80) to 0).
<4> Set the count value to CR80.
<5> Set TM80 to operation enable (TCE80 = 1)

Each time the valid edge specified by bit 1 (TCL800) of TMC80 is input, the value of 8-bit timer counter 80 (TM80)
is incremented.
When the count value of TM80 matches the value set to CR80, the value of TM80 is cleared to 0 and TM80 continues
counting. At the same time, an interrupt request signal (INTTM80) is generated.
Figure 9-5 shows the timing of the external event counter operation (with rising edge specified).

Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite.
2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using
et4U.com an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
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occur after the timer starts.
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Therefore, always follow the above procedure when operating the 8-bit timer/event counter
as an interval timer.

Figure 9-5. External Event Counter Operation Timing (with Rising Edge Specified)

TI80 pin input

TM80 count value 00H 01H 02H 03H 04H 05H N–1 N 00H 01H 02H 03H

CR80 N

TCE80

INTTM80

Remark N = 00H to FFH

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

9.4.3 Operation as square wave output

The 8-bit timer/event counter can generate output square waves of a given frequency at intervals specified by the
count value set to the 8-bit compare register 80 (CR80) in advance.
To operate the 8-bit timer/event counter 80 for square wave output, the following settings are required.

<1> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0.
<2> Set 8-bit timer counter 80 (TM80) to operation disable (TCE80 = 0).
<3> Set the count clock of the 8-bit timer/event counter 80 (see Tables 9-4 and 9-5), TO80 to output enable
(TOE80 = 1), and PWM output to disable (PWME80 = 0).
<4> Set the count value to CR80.
<5> Set TM80 to operation enable (TCE80 = 1).

When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, the TO80/P24/INTP1/TO20
pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output.
As soon as a match occurs, the TM80 value is cleared to 0 and TM80 continues counting. At the same time, an interrupt
request signal (INTTM80) is generated.
Square wave output is cleared (0) when bit 7 (TCE80) in TMC80 is set to 0.
Table 9-6 shows square wave output range, and Figure 9-6 shows timing of square wave output.

Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite.
2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using
et4U.com an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
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occur after the timer starts.
Therefore, always followDataSheet4U.com
the above procedure when operating the 8-bit timer/event counter
as an interval timer.

Table 9-6. Square Wave Output Range of 8-Bit Timer/Event Counter 80 (At fX = 5.0-MHz Operation)

TCL801 TCL800 Minimum Pulse Width Maximum Pulse Width Resolution

0 0 1/fX (200 ns) 2 /fX (51.2 µs)
8
1/fX (200 ns)

0 1 2 /fX (1.6 µs)

3
2 /f X (409.6 µs)
11
23/fX (1.6 µs)

Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)

Table 9-7. Square Wave Output Range of 8-Bit Timer/Event Counter 80 (At fCC = 4.0-MHz Operation)

TCL801 TCL800 Minimum Pulse Width Maximum Pulse Width Resolution

0 0 1/fCC (250 ns) 28/fCC (64 µs) 1/fCC (250 ns)

0 1 23/fCC (2.0 µs) 211/f CC (512 µs) 23/fCC (2.0 µs)

Remark fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

Figure 9-6. Square Wave Output Timing

Count clock

TM80 count value 00H 01H N 00H 01H N 00H 01H N

Clear Clear

CR80 N N N N

TCE80

Count start

INTTM80

Interrupt accept Interrupt accept

TO80Note

Note The initial value of TO80 during output enable (TOE80 = 1) becomes low level.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

9.4.4 Operation as PWM output

PWM output enables interrupt generation repeatedly at intervals specified by the count value set to 8-bit compare
register 80 (CR80) in advance.
To use 8-bit timer/counter 80 for PWM output, the following settings are required.

<1> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0.
<2> Set 8-bit timer counter 80 (TM80) to operation disable (TCE80 = 0).
<3> Set the count clock of the 8-bit timer/event counter 80 (see Tables 9-4 and 9-5), TO80 to output enable
(TOE80 = 1), and PWM output to enable (PWME80 = 1).
<4> Set the count value to CR80
<5> Set TM80 to operation enable (TCE80 = 1)

When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, TM80 continues counting,
and an interrupt request signal (INTTM80) is generated.

Cautions 1. When CR80 is rewritten during timer operation, a high level may be output for the next one
cycle (refer to 9.5 (2) Setting of 8-bit compare register 80).
2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts. Therefore, always follow the above procedure when operating
8-bit compare register 80 as a PWM output.

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Figure 9-7. PWM Output Timing

Count clock

TM80 00H 01H ••• M ••• FFH 00H 01H 02H ••• M M+1 M+2 ••• FFH 00H 01H ••• M ••• •••

CR80 M

TCE80

OVF

INTTM80

TO80Note

M = 01H to FFH

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Note The initial value of TO80 upon output enable (TOE80 = 1) is low level.
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Caution Do not set CR80 to 00H in the PWM output mode; otherwise PWM may not be output normally.

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

9.5 Notes on Using 8-Bit Timer/Event Counter 80

(1) Error on starting timer

An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated. This
is because 8-bit timer counter 80 (TM80) is started in asynchronization with the count pulse.

Figure 9-8. Start Timing of 8-Bit Timer Counter

Count pulse

TM80
00H 01H 02H 03H 04H
count value

Timer start

(2) Setting of 8-bit compare register 80

8-bit compare register 80 (CR80) can be set to 00H.
Therefore, one pulse can be counted when the 8-bit timer/event counter operates as an event counter.

Figure 9-9. External Event Counter Operation Timing

et4U.com DataShee
Tl80 input DataSheet4U.com

CR80 00H

TM80
count value 00H 00H 00H 00H

Interrupt request flag

Cautions 1. When rewriting CR80 in timer counter operation mode (i.e. PWME80 (bit 6 of 8-bit timer
mode control register 80 (TMC80) is set to 0), be sure to stop the timer operation before
hand. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request
signal may occur at the moment of rewrite.

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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80

2. When rewriting CR80 in PWM output operation mode (PWME80 = 1), a high level may be
output for the next one cycle (count pulse x 256). This phenomenon occurs if a value
smaller than the value of TM80 is written to CR80.

Count clock

TM80 00H 01H … M … FFH 00H 01H 02H … FFH 00H 01H … …

CR80 M 01H

TCE80

OVF

Match Signal

TO80

M = 02H-FFH Rewriting to CR80

M→01H

3. Do not set CR80 to 00H in the PWM output mode (when PWME80 = 1); otherwise, PWM
may not be output normally.

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CHAPTER 10 WATCHDOG TIMER

The watchdog timer can generate non-maskable interrupts, maskable interrupts and RESET with arbitrary preset
intervals.

10.1 Functions of Watchdog Timer

The watchdog timer has the following functions:

• Watchdog timer
• Interval timer

Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).

(1) Watchdog timer

The watchdog timer is used to detect program runaway. When a runaway is detected, a non-maskable interrupt
or the RESET signal can be generated.

Table 10-1. Runaway Detection Time of Watchdog Timer

et4U.com DataShee
Runaway
At fX = 5.0-MHz Operation At fCC = 4.0-MHz Operation
Detection Time DataSheet4U.com
211 × 1/fW 410 µs 512 µs

213 × 1/fW 1.64 ms 2.05 ms

215 × 1/fW 6.55 ms 8.19 ms
2 17 × 1/fW 26.2 ms 32.8 ms

fW: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)

(2) Interval timer

The interval timer generates an interrupt at a given interval set in advance.

Table 10-2. Interval Time

Interval Time At fX = 5.0-MHz Operation At fCC = 4.0-MHz Operation

2 11
× 1/fW 410 µs 512 µs
2 13
× 1/fW 1.64 ms 2.05 ms
2 15
× 1/fW 6.55 ms 8.19 ms

2 17
× 1/fW 26.2 ms 32.8 ms

fW: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 10 WATCHDOG TIMER

10.2 Configuration of Watchdog Timer

The watchdog timer consists of the following hardware:

Table 10-3. Configuration of Watchdog Timer

Item Configuration
Control register Timer clock select register 2 (TCL2)
Watchdog timer mode register (WDTM)

Figure 10-1. Block Diagram of Watchdog Timer

Internal bus

fW
Prescaler TMMK4
24
fW fW fW
26 28 210 INTWDT
TMIF4 maskable
interrupt request
Selector

Control
7-bit counter RESET
circuit

et4U.com Clear INTWDT

DataShee
non-maskable
interrupt request
3 DataSheet4U.com

TCL22 TCL21 TCL20 RUN WDTM4 WDTM3

Timer clock select register 2 Watchdog timer mode register (WDTM)

(TCL2)
Internal bus

Remark fW: fX or fCC

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CHAPTER 10 WATCHDOG TIMER

10.3 Watchdog Timer Control Register

The following two types of registers are used to control the watchdog timer.

• Timer clock select register 2 (TCL2)

• Watchdog timer mode register (WDTM)

(1) Timer clock select register 2 (TCL2)

This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.

Figure 10-2. Timer Clock Select Register 2 Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

TCL2 0 0 0 0 0 TCL22 TCL21 TCL20 FF42H 00H R/W

TCL22 TCL21 TCL20 Watchdog timer count clock selection Interval time

At fX = 5.0-MHz operation At fCC = 4.0-MHz operation At fX = 5.0-MHz operation At fCC = 4.0-MHz operation

0 0 0 fX/24 (312.5 kHz) fCC/24 (250 KHZ) 211/fX (410 µ s) 211/fCC (512 µs)

0 1 0 fX/26 (78.1 kHz) fCC/26 (62.5 KHZ) 213/fX (1.64 ms) 213/fCC (2.05 ms)
et4U.com 1 0 0 fX/28 (19.5 kHz) fCC/28 (15.6 KHZ) 215/fX (6.55 ms) 215/fCC (8.19 ms)
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1 1 0 fX/210 (4.88 kHz) fCC/210 (3.91 KHZ) 217/fX (26.2 ms) 217/fCC (32.8 ms)
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Other than above Setting prohibited

Remark f X: System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 10 WATCHDOG TIMER

(2) Watchdog timer mode register (WDTM)

This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.

Figure 10-3. Format of Watchdog Timer Mode Register

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W

WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W

RUN Selects operation of watchdog timerNote 1

0 Stops counting

1 Clears counter and starts counting

WDTM4 WDTM3 Selects operation mode of watchdog timerNote 2

0 0 Operation stop
0 1 Interval timer mode (overflow and maskable interrupt occur)Note 3
1 0 Watchdog timer mode 1 (overflow and non-maskable interrupt occur)
1 1 Watchdog timer mode 2 (overflow occurs and reset operation started)
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Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is
started, it cannot be stopped byDataSheet4U.com
any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts operations as an interval timer when RUN is set to 1.

Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by timer clock select register 2 (TCL2).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of interrupt
request flag 0) has been set to 0. When watchdog timer mode 1 or 2 is selected under
the condition where TMIF4 is 1, a non-maskable interrupt occurs at the completion of
rewriting.

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CHAPTER 10 WATCHDOG TIMER

10.4 Operation of Watchdog Timer

10.4.1 Operation as watchdog timer

The watchdog timer operates to detect a runaway when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20
to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started.
Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been started. By setting
RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the runaway detection
time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN
to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.

Caution The actual runaway detection time may be up to 0.8% shorter than the set time.

Table 10-4. Runaway Detection Time of Watchdog Timer

TCL22 TCL21 TCL20 Runaway Detection Time At fX = 5.0-MHz Operation At fCC = 4.0-MHz Operation
0 0 0 211 × 1/fW 410 µs 512 µs

0 1 0 213 × 1/fW 1.64 ms 2.05 ms

1 0 0 215 × 1/fW 6.55 ms 8.19 ms
1 1 0 217 × 1/fW 26.2 ms 32.8 ms
et4U.com DataShee
fW: fX or fCC
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fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 10 WATCHDOG TIMER

10.4.2 Operation as interval timer

When bits 4 and 3 (WDTM4, WDTM3) of watchdog timer mode register (WDTM) are set to 1, the watchdog timer
also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value
set in advance.
Select a count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).
The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.
In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to
1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected),
the interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than
the set time.

Table 10-5. Interval Time of Interval Timer

TCL22 TCL21 TCL20 Interval Time At fX = 5.0-MHz Operation At fCC = 4.0-MHz Operation
0 0 0 2 11
× 1/fW 410 µs 512 µs
0 1 0 2 13
× 1/fW 1.64 ms 2.05 ms

1 0 0 2 15
× 1/fW 6.55 ms 8.19 ms
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1 1 0 2 17
× 1/fW 26.2 ms 32.8 ms

fW: fX or fCC DataSheet4U.com

fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

11.1 8-Bit A/D Converter Functions

The 8-bit A/D converter is an 8-bit resolution converter to convert analog input to digital signals. This converter
can control up to four channels of analog inputs (ANI0 to ANI3).
A/D conversion can only be started by software.
One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with
an interrupt request (INTAD0) being issued each time an A/D session is completed.

11.2 8-Bit A/D Converter Configuration

The 8-bit A/D converter consists of the following hardware.

Table 11-1. Configuration of 8-Bit A/D Converter

Item Configuration
Analog input 4 channels (ANI0 to ANI3)
Register Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)

et4U.com Control register A/D converter mode register 0 (ADM0)

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Analog input channel specification register 0 (ADS0)
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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

Figure 11-1. Block Diagram of 8-Bit A/D Converter

AVDD

P-ch

Tap selector
Sample and hold circuit
ANI0/P60
Selector
ANI1/P61 Voltage comparator
ANI2/P62
AVSS
ANI3/P63

AVSS Successive
approximation
register (AR)

Control INTAD0
circuit

A/D conversion result

register 0 (ADCR0)
2

ADS01 ADS00 ADCS0 FR02 FR01 FR00

Analog input channel A/D converter mode register 0
specification register 0 (ADM0)
et4U.com (ADS0)
DataShee
Internal bus
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(1) Successive approximation register (SAR)

The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).

(2) A/D conversion result register 0 (ADCR0)

ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into ADCR0, which is an 8-bit register that holds the result
of A/D conversion.
ADCR0 can be read with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.

(3) Sample and hold circuit

The sample and hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.

(4) Voltage comparator

The voltage comparator compares an analog input with the voltage output by the series resistor string.

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

(5) Series resistor string

The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against
which analog inputs are compared.

(6) ANI0 to ANI3 pins

Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the
analog signals for A/D conversion.

Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage
greater than AVDD or less than AVSS (even if within the absolute maximum rating) is supplied
to any of these pins, the conversion value for the corresponding channel will be undefined.
Furthermore, the conversion values for the other channels may also be affected.

(7) AVSS pin

The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS pin, even while the A/D converter is not being used.

(8) AVDD pin

The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same potential
as the VDD pin, even while the A/D converter is not being used.

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

11.3 Registers Controlling 8-Bit A/D Converter

The following two registers are used to control the 8-bit A/D converter.

• A/D converter mode register 0 (ADM0)

• Analog input channel specification register 0 (ADS0)

(1) A/D converter mode register 0 (ADM0)

ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADM0 to 00H.

Figure 11-2. Format of A/D Converter Mode Register 0

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W

ADM0 ADCS0 0 FR02 FR01 FR00 0 0 0 FF80H 00H R/W

ADCS0 A/D conversion control

0 Conversion disabled

1 Conversion enabled

et4U.com FR02 FR01 FR00 A/D conversion time selectionNote 1 DataShee

At fX = 5.0-MHz operation
DataSheet4U.com At fCC = 4.0-MHz operation

0 0 0 144/fX (28.8 µ s) 144/fCC (36 µ s)

0 0 1 120/fX (24 µ s) 120/fCC (30 µ s)

0 1 0 96/fX (19.2 µ s) 96/fCC (24 µ s)

1 0 0 72/fX (14.4 µ s) 72/fCC (18 µ s)

1 0 1 60/fX (Setting prohibited Note 2) 60/fCC (15 µ s)

Note 2
1 1 0 48/fX (Setting prohibited ) 48/fCC (Setting prohibitedNote 2)
Other than above Setting prohibited

Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least
14 µs.
2. These bit combinations must not be used, as the A/D conversion time will fall below 14 µs.

Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to
11.5 (5) Timing when A/D conversion result become undefined).

Remark fX : System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

(2) Analog input channel specification register 0 (ADS0)

The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.
ADS0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.

Figure 11-3. Format of Analog Input Channel Specification Register 0

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

ADS0 0 0 0 0 0 0 ADS01 ADS00 FF84H 00H R/W

ADS01 ADS00 Analog input channel specification

0 0 ANI0

0 1 ANI1

1 0 ANI2

1 1 ANI3

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

11.4 8-Bit A/D Converter Operation

11.4.1 Basic operation of 8-bit A/D converter

<1> Select a channel for A/D conversion, using Analog input channel specification register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample and hold circuit.
<3> After sampling continues for a certain period of time, the sample and hold circuit is put on hold to keep
the input analog voltage until A/D conversion is completed.
<4> Bit 7 of the successive approximation A/D conversion register (SAR) is set. The series resistor string
voltage tap at the tap selector is set to half of AVDD.
<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage
comparator. If the analog input voltage is higher than half of AVDD, the MSB of the SAR is left set. If it
is lower than half of AVDD, the MSB is reset.
<6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of
the series resistor string is selected according to bit 7, which reflects the previous comparison result, as
follows:
• Bit 7 = 1: Three quarters of AVDD
• Bit 7 = 0: One quarter of AVDD
The tap voltage is compared with the analog input voltage. Bit 6 is set or reset according to the result
of comparison.
• Analog input voltage ≥ tap voltage: Bit 6 = 1
• Analog input voltage < tap voltage: Bit 6 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
et4U.com <8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value
DataShee
is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to
DataSheet4U.com
generate an A/D conversion end interrupt request (INTAD0).

Cautions 1. The first A/D conversion value immediately after starting the A/D conversion operation
may be undefined.
2. When in standby mode, the A/D converter stops operation.

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

Figure 11-4. Basic Operation of 8-Bit A/D Converter

Conversion
time
Sampling
time

A/D converter
Sampling A/D conversion
operation

C0H Conversion
SAR Undefined 80H or 40H result

Conversion
ADCR0
result

INTAD0

A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or Analog input channel specification register 0 (ADS0) during A/D
conversion, the ongoing A/D conversion is canceled. In this case, if ADCS0 is set (1), A/D conversion is restarted
et4U.com from the beginning. DataShee
RESET input makes the A/D conversion result register 0 (ADCR0) undefined.
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11.4.2 Input voltage and conversion result

The relationships between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion
result (A/D conversion result register 0 (ADCR0)) are represented by:

VIN
ADCR0 = INT ( × 256 + 0.5)
AVDD

or

AVDD AVDD
(ADCR0 – 0.5) × ≤ VIN < (ADCR0 + 0.5) ×
256 256

INT( ): Function that returns the integer part of a parenthesized value

VIN: Analog input voltage
AVDD: A/D converter supply voltage
ADCR0: Value in the A/D conversion result register 0 (ADCR0)

Figure 11-5 shows the relationships between the analog input voltage and the A/D conversion result.

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

Figure 11-5. Relationships between Analog Input Voltage and A/D Conversion Result

255

254

253

A/D conversion
result (ADCR0)
3

0
et4U.com 1 1 3 2 5 3 507 254 509 255 511 1 DataShee
512 256 512 256 512 256 512 256 512 256 512
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Input voltage/AVDD

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

11.4.3 Operation mode of 8-bit A/D converter

The 8-bit A/D converter is initially in the select mode. In this mode, Analog input channel specification register
0 (ADS0) is used to select an analog input channel from ANI0 to ANI3 for A/D conversion.
A/D conversion can only be started by software, that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.

• Software-started A/D conversion

Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied
to the analog input pin specified in Analog input channel specification register 0 (ADS0). Upon completion of
A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same, an
interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another
session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where
ADCS0 is 1 is written to ADM0 again during A/D conversion, the ongoing session of A/D conversion is
discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written
to the ADM0 again during A/D conversion, A/D conversion is completely stopped.

Figure 11-6. Software-Started A/D Conversion

Rewriting ADM0 Rewriting ADM0

ADCS0 = 1 ADCS0 = 1 ADCS0 = 0

et4U.com A/D conversion ANIn ANIn ANIn ANIm ANIm DataShee

DataSheet4U.comConversion is
discontinued; Stop
no conversion
result is preserved.

ADCR0 ANIn ANIn ANIm

INTAD0

Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

11.5 Cautions Related to 8-Bit A/D Converter

(1) Current consumption in the standby mode

When the A/D converter enters the standby mode, it stops its operation. Stopping conversion (bit 7 (ADCS0)
of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption.
Figure 11-7 shows how to reduce the current consumption in the standby mode.

Figure 11-7. How to Reduce Current Consumption in Standby Mode

AVDD

P-ch ADCS0

Series resistor string

AVSS

(2) Input range for the ANI0 to ANI3 pins

Be sure to keep the input voltage at ANI0 to ANI3 within its rating. If a voltage not lower than AVDD or not
higher than AVSS (even within the absolute maximum rating) is input to a conversion channel, the conversion
et4U.com output of the channel becomes undefined. It may affect the conversion output of the other channels. DataShee
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(3) Conflict

<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading
from ADCR0
Reading from ADCR0 takes precedence. After reading, the new conversion result is written to the ADCR0.

<2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register
0 (ADM0) or Analog input channel specification register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion
end interrupt request signal (INTAD0) is generated.

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

(4) Conversion results immediately following start of A/D conversion

The first A/D conversion value immediately following the start of A/D converter operation may be undefined.
Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as annulling
the first conversion result.

(5) Timing that makes the A/D conversion result undefined

If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D
converter operation has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 11-8 and 11-9.

Figure 11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)

A/D conversion end A/D conversion end

ADCR0 Normal conversion result Undefined value

INTAD0

ADCS0

et4U.com Normal conversion result read out A/D operation stopped Undefined value read out DataShee
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Figure 11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)

A/D conversion end

ADCR0 Normal conversion result

INTAD0

ADCS0

A/D operation stopped Normal conversion result read out

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

(6) Noise prevention

To maintain a resolution of 8 bits, watch for noise to the AVDD and ANI0 to ANI3 pins. The higher the output
impedance of the analog input source is, the larger the effect by noise. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 11-8.

Figure 11-10. Analog Input Pin Treatment

If noise not lower than AVDD or not higher than

AVSS is likely to come to the AVDD pin, clamp
the voltage at the pin by attaching a diode with a
small VF (0.3 V or lower).

VDD

AVDD

C = 100 to 1000 pF
AVSS

et4U.com VSS
DataShee
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(7) ANI0 to ANI3

The analog input pins (ANI0 to ANI3) are alternate-function pins. They are used also as port pins (P60 to
P63).
If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports;
otherwise the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise
may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital
pulse to pins adjacent to the analog input pins during A/D conversion.

(8) Interrupt request flag (ADIF0)

Changing the content of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion
end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs.
In this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed,
even when A/D conversion has not been completed for the new analog input.
In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand.

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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)

Figure 11-11. A/D Conversion End Interrupt Request Generation Timing

Rewriting to ADM0 Rewriting to ADM0

(to begin conversion (to begin conversion ADIF0 has been set, but conversion
for ANIn) for ANIm) for ANIm has not been completed.

A/D conversion ANIn ANIn ANIm ANIm

ADCR0 ANIn ANIn ANIm ANIm

INTAD0

Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3

et4U.com (9) AVDD pin DataShee

The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3
DataSheet4U.com
input circuit.
Therefore, if the application is designed to be switched to backup power, the AVDD pin must be supplied with
the same voltage level as for the VDD pin, as shown in Figure 11-12.

Figure 11-12. AVDD Pin Treatment

VDD

Main power AVDD

source Backup
capacitor
VSS
AVSS

(10) Input impedance of the AVDD pin

A series resistor string of several 10 kΩ is connected across the AVDD and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually
connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher reference
voltage error.

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et4U.com DataShee
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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

12.1 10-Bit A/D Converter Functions

The 10-bit A/D converter is a 10-bit resolution converter to convert an analog input to digital signals. This converter
can control up to four channels of analog inputs (ANI0 to ANI3).
A/D conversion can only be started by software.
One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with
an interrupt request (INTAD0) being issued each time an A/D session is completed.

12.2 10-Bit A/D Converter Configuration

The A/D converter consists of the following hardware.

Table 12-1. Configuration of 10-Bit A/D Converter

Item Configuration
Analog input 4 channels (ANI0 to ANI3)
Register Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)

et4U.com Control register A/D converter mode register 0 (ADM0)

DataShee
Analog input channel specification register 0 (ADS0)
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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

Figure 12-1. Block Diagram of 10-Bit A/D Converter

AVDD

P-ch

Tap selector
Sample and hold circuit
ANI0/P60 Selector
ANI1/P61 Voltage comparator
ANI2/P62
ANI3/P63 AVSS

AVSS Successive
approximation
register (SAR)

Control INTAD0
circuit

A/D conversion result

register 0 (ADCR0)
2

ADS01 ADS00 ADCS0 FR02 FR01 FR00

Analog input channel A/D converter mode register 0
specification register 0 (ADM0)
et4U.com (ADS0)
DataShee
Internal bus

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(1) Successive approximation register (SAR)

The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).

(2) A/D conversion result register 0 (ADCR0)

ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into ADCR0, which is a 10-bit register the holds the result
of A/D conversion.
ADCR0 can be read with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.

Caution When using the µPD78F9116A as a flash memory version of the µPD789101A, 789102A, or
789104A, or the µPD78F9136A as a flash memory version of the µPD789121A, 789122A, or
789124A, an 8-bit access can be made by ADCR0. However, it is performed only with the
object file assembled by the µPD789101A, 789102A, or 789104A, or by the µPD789121A,
789122A, or 789124A, respectively.

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

(3) Sample and hold circuit

The sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.

(4) Voltage comparator

The voltage comparator compares an analog input with the voltage output by the series resistor string.

(5) Series resistor string

The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against
which analog inputs are compared.

(6) ANI0 to ANI3 pins

Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the
analog signals for A/D conversion.

Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage
greater than AVDD or less than AVSS (even if within the absolute maximum rating) is supplied
to any of these pins, the conversion value for the corresponding channel will be undefined.
Furthermore, the conversion values for the other channels may also be affected.

(7) AVSS pin

The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as
et4U.com the VSS pin, even while the A/D converter is not being used.
DataShee

(8) AVDD pin DataSheet4U.com

The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same potential
as the VDD pin, even while the A/D converter is not being used.

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

12.3 Registers Controlling 10-Bit A/D Converter

The following two registers are used to control the 10-bit A/D converter.

• A/D converter mode register 0 (ADM0)

• Analog input channel specification register 0 (ADS0)

(1) A/D converter mode register 0 (ADM0)

ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears the ADM0 to 00H.

Figure 12-2. Format of A/D Converter Mode Register 0

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W

ADM0 ADCS0 0 FR02 FR01 FR00 0 0 0 FF80H 00H R/W

ADCS0 A/D conversion control

0 Conversion disabled

1 Conversion enabled

et4U.com FR02 FR01 FR00 A/D conversion time selectionNote 1 DataShee

At fX = 5.0-MHz operation
DataSheet4U.com At fCC = 4.0-MHz operation

0 0 0 144/fX (28.8 µ s) 144/fCC (36 µ s)

0 0 1 120/fX (24 µ s) 120/fCC (30 µ s)

0 1 0 96/fX (19.2 µ s) 96/fCC (24 µ s)

1 0 0 72/fX (14.4 µ s) 72/fCC (18 µ s)

1 0 1 60/fX (Setting prohibited Note 2) 60/fCC (15 µ s)

Note 2
1 1 0 48/fX (Setting prohibited ) 48/fCC (Setting prohibitedNote 2)
Other than above Setting prohibited

Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least
14 µs.
2. These bit combinations must not be used, as the A/D conversion time will fall below 14 µs.

Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to
12.5 (5) Timing when A/D conversion result becomes undefined).

Remark fX : System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

(2) Analog input channel specification register 0 (ADS0)

The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0
is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.

Figure 12-3. Format of Analog Input Channel Specification Register 0

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

ADS0 0 0 0 0 0 0 ADS01 ADS00 FF84H 00H R/W

ADS01 ADS00 Analog input channel specification

0 0 ANI0

0 1 ANI1

1 0 ANI2

1 1 ANI3

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

12.4 10-Bit A/D Converter Operation

12.4.1 Basic operation of 10-bit A/D converter

<1> Select a channel for A/D conversion, using Analog input channel specification register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample and hold circuit.
<3> After sampling continues for a certain period of time, the sample and hold circuit is put on hold to keep
the input analog voltage until A/D conversion is completed.
<4> Bit 9 of the successive approximation A/D conversion register (SAR) is set. The series resistor string
voltage tap at the tap selector is set to half of AVDD.
<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage
comparator. If the analog input voltage is higher than half of AVDD, the MSB of the SAR is left set. If it
is lower than half of AVDD, the MSB is reset.
<6> Bit 8 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of
the series resistor string is selected according to bit 9, which reflects the previous comparison result, as
follows:
• Bit 9 = 1: Three quarters of AVDD
• Bit 9 = 0: One quarter of AVDD
The tap voltage is compared with the analog input voltage. Bit 8 is set or reset according to the result
of comparison.
• Analog input voltage ≥ tap voltage: Bit 8 = 1
• Analog input voltage < tap voltage: Bit 8 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
et4U.com <8> When comparison is completed for all of the 10 bits, a significant digital result is left in the SAR. This
DataShee
value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible
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to generate an A/D conversion end interrupt request (INTAD0).

Cautions 1. The A/D conversion value immediately after starting the A/D conversion operation may
be undefined.
2. When in standby mode, the A/D converter stops operation.

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

Figure 12-4. Basic Operation of 10-Bit A/D Converter

Conversion
Sampling time
time

A/D converter
Sampling A/D conversion
operation

Conversion
SAR Undefined result

Conversion
ADCR0
result

INTAD0

A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or Analog input channel specification register 0 (ADS0) during A/D
conversion, the ongoing A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning,
et4U.com if ADCS0 is set (1). DataShee
RESET input makes A/D conversion result register 0 (ADCR0) undefined.
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12.4.2 Input voltage and conversion result

The relationships between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion
result (A/D conversion result register 0 (ADCR0)) are represented by:

VIN
ADCR0 = INT ( × 1,024 + 0.5)
AVDD

or

AVDD AVDD
(ADCR0 – 0.5) × ≤ VIN < (ADCR0 + 0.5) ×
1,024 1,024

INT( ): Function that returns the integer part of a parenthesized value

VIN: Analog input voltage
AVDD: A/D converter supply voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0)

Figure 12-5 shows the relationships between the analog input voltage and the A/D conversion result.

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

Figure 12-5. Relationships between Analog Input Voltage and A/D Conversion Result

1,023

1,022

1,021

A/D conversion
result (ADCR0)
3

0
et4U.com e
1 1 3 2 5 3
2,048 1,024 2,048 1,024 2,048 1,024
2,043 1,022 2,045 1,023 2,047
2,048 1,024 2,048 1,024 2,048
1
DataShe
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Input voltage/AVDD

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

12.4.3 Operation mode of 10-bit A/D converter

The 10-bit A/D converter is initially in the select mode. In this mode, Analog input channel specification register
0 (ADS0) is used to select an analog input channel from ANI0 to ANI3 for A/D conversion.
A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.

• Software-started A/D conversion

Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for a voltage applied
to the analog input pin specified in Analog input channel specification register 0 (ADS0).
Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0).
At the same, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and
completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written
to the ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the ongoing session
of A/D conversion is discontinued, and a new session of A/D conversion begins for the new data. If data where
ADCS0 is 0 is written to ADM0 again during A/D conversion, A/D conversion is completely stopped.

Figure 12-6. Software-Started A/D Conversion

Rewriting ADM0 Rewriting ADM0

ADCS0 = 1 ADCS0 = 1 ADCS0 = 0

et4U.com e
DataShe
A/D conversion ANIn ANIn ANIn ANIm ANIm

DataSheet4U.comConversion is
discontinued; Stop
no conversion
result is preserved.

ADCR0 ANIn ANIn ANIm

INTAD0

Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

12.5 Cautions Related to 10-Bit A/D Converter

(1) Current consumption in the standby mode

When the A/D converter enters the standby mode, it stops its operation. Stopping conversion (bit 7 (ADCS0)
of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption.
Figure 12-7 shows how to reduce the current consumption in the standby mode.

Figure 12-7. How to Reduce Current Consumption in Standby Mode

AVDD

P-ch ADCS0

Series resistor string

AVSS

(2) Input range for the ANI0 to ANI3 pins

Be sure to keep the input voltage at ANI0 to ANI3 within its rating. If a voltage not lower than AVDD or not
higher than AVSS (even within the absolute maximum rating) is input a conversion channel, the conversion
et4U.com e
output of the channel becomes undefined. It may affect the conversion output of the other channels.
DataShe
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(3) Conflict

<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading
from ADCR0
Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0.

<2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register
0 (ADM0) or Analog input channel specification register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion
end interrupt request signal (INTAD0) is generated.

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

(4) Conversion results immediately following start of A/D conversion

The first A/D conversion value immediately following the start of A/D converter operation may be undefined.
Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as annulling
the first conversion result.

(5) Timing that makes the A/D conversion result undefined

If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D
converter operation has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 12-8 and 12-9.

Figure 12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)

A/D conversion end A/D conversion end

ADCR0 Normal conversion result Undefined value

INTAD0

ADCS0

et4U.com e
Normal conversion result read out A/D operation stopped Undefined value read out DataShe
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Figure 12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)

A/D conversion end

ADCR0 Normal conversion result

INTAD0

ADCS0

A/D operation stopped Normal conversion result read out

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

(6) Noise prevention

To maintain a resolution of 10 bits, watch for noise to the AVDD and ANI0 to ANI3 pins. The higher the output
impedance of the analog input source is, the larger the effect by noise is. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 12-10.

Figure 12-10. Analog Input Pin Treatment

If noise not lower than AVDD or not higher than

AVSS is likely to come to the AVDD pin, clamp
the voltage at the pin by attaching a diode with
a small VF (0.3 V or lower).

VDD

AVDD

C = 100 to 1000 pF
AVSS

et4U.com VSS e
DataShe
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(7) ANI0 to ANI3

The analog input pins (ANI0 to ANI3) are alternate-function pins. They are used also as port pins (P60 to
P63).
If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports;
otherwise, the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise
may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital
pulse to pins adjacent to the analog input pins during A/D conversion.

(8) Interrupt request flag (ADIF0)

Changing content of the A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion
end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs.
In this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed,
even when A/D conversion has not been completed for the new analog input.
In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand.

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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)

Figure 12-11. A/D Conversion End Interrupt Request Generation Timing

Rewriting to ADM0 Rewriting to ADM0

(to begin conversion (to begin conversion ADIF0 has been set, but conversion
for ANIn) for ANIm) for ANIm has not been completed.

A/D conversion ANIn ANIn ANIm ANIm

ADCR0 ANIn ANIn ANIm ANIm

INTAD0

Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3

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(9) AVDD pin DataShe
The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3
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input circuit.
Therefore, if the application is designed to be changed to backup power, the AVDD pin must be supplied with
the same voltage level as for the VDD pin, as shown in Figure 12-10.

Figure 12-12. AVDD Pin Treatment

VDD
AVDD
Main power Backup
source capacitor
VSS
AVSS

(10) Input impedance of the AVDD pin

A series resistor string of several 10 kΩ is connected across the AVDD and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually
connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher reference
voltage error.

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CHAPTER 13 SERIAL INTERFACE 20

13.1 Functions of Serial Interface 20

Serial interface 20 has the following three modes.

• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode

(1) Operation stop mode

This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.

(2) Asynchronous serial interface (UART) mode

This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex
communication.
Serial interface channel 0 contains a dedicated UART baud rate generator, enabling communication over a
wide range of baud rates. It is also possible to define baud rates by dividing the frequency of the input clock
pulse at the ASCK20 pin.
It is recommended that ceramic/crystal oscillation be used for the system clock in the UART mode. Because
the frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the
et4U.com baud rate generator, there may be problems in send/receive operations. e
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(3) 3-wire serial I/O mode (switchableDataSheet4U.com

between MSB-first and LSB-first transmission)
This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data
lines (SI20 and SO20).
As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time
for data transmission than asynchronous serial interface mode.
Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB
or LSB, channel 0 can be connected to any device regardless of whether that device is designed for MSB-
first or LSB-first transmission.
3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having
conventional clock synchronous serial interfaces, such as those of the 75XL, 78K, and 17K Series devices.

13.2 Serial Interface 20 Configuration

Serial interface 20 consists of the following hardware.

Table 13-1. Serial Interface 20 Configuration

Item Configuration
Register Transmit shift register 20 (TXS20)
Receive shift register 20 (RXS20)
Receive buffer register 20 (RXB20)
Control register Serial operating mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
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164

Figure 13-1. Serial Interface 20 Block Diagram

Internal bus
Serial operation mode Asynchronous serial Asynchronous serial
register 20 (CSIM20) interface status register 20 interface mode register 20
Receive buffer (ASIS20) (ASIM20)
CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 PE20 FE20 OVE20 TXE20 RXE20 PS201 PS200 CL20 SL20
register 20 (RXB20)

Switching of the first bit

Transmit shift
register 20 (TXS20) Transmit
SI20/P22/ shift clock
Receive shift
RxD20 register 20 (RXS20)

CHAPTER 13
Selector CSIE20
Reception
Port mode
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shift clock
register (PM21) Data phase
DAP20
SO20/P21/ control
TxD20 Parity operation

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SERIAL INTERFACE 20
Stop bit addition
4 INTST20
Transmission data counter
Parity operation
SL20, CL20, PS200, PS201
Stop bit addition INTSR20/INTCSI20
Reception data counter
Reception enabled Transmission
Reception clock and reception Baud rate CSIE20
Start bit clock control generator note CSCK20
Detection clock
detection fX/2 to fX/28
Reception detected
4
SS20/P23/ CSIE20
CPT20/INTP0 TPS203 TPS202 TPS201 TPS200
CSCK20 Internal clock output Baud rate generator
SCK20/P20/ Clock phase
control register 20 (BRGC20)
ASCK20 control
External clock input
Internal bus

Note See Figure 13-2 for the configuration of the baud rate generator.
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Figure 13-2. Baud Rate Generator Block Diagram

Reception detection clock

Transmission
Transmission shift clock 1/2 clock counter

fX/2
fX/22

Selector

Selector
fX/23
Reception shift clock 1/2 fX/24

Selector
Reception fX/25
clock counter fX/26

CHAPTER 13
fX/27
fX/28
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TXE20 SCK20/ASCK20/P20

RXE20

SERIAL INTERFACE 20
CSIE20

Reception detection

TPS203 TPS202 TPS201 TPS200

Baud rate generator
control register 20
(BRGC20)
Internal bus
165

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CHAPTER 13 SERIAL INTERFACE 20

(1) Transmit shift register 20 (TXS20)

TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bit-
serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data
to TXS20 triggers transmission.
TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read.
RESET input sets TXS20 to FFH.

Caution Do not write to TXS20 during transmission.

TXS20 and receive buffer register 20 (RXB20) are mapped at the same address, so that any
attempt to read from TXS20 results in a value being read from RXB20.

(2) Receive shift register 20 (RXS20)

RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one
entire byte has been received, RXS20 transfers the reception data to receive buffer register 20 (RXB20).
RXS20 cannot be manipulated directly by a program.

(3) Receive buffer register 20 (RXB20)

RXB20 holds receive data. New receive data is transferred from receive shift register 0 (RXS20) per 1 byte
of data received.
When the data length is specified as seven bits, the receive data is sent to bits 0 to 6 of RXB20, in which the
MSB is always fixed to 0.
et4U.com RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written to. e
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RESET input makes RXB20 undefined.
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Caution RXB20 and transmit shift register 20 (TXS20) are mapped at the same address, so that any
attempt to write to RXB20 results in a value being written to TXS20.

(4) Transmission control circuit

The transmission control circuit controls transmission. For example, it adds start, parity, and stop bits to the
data in transmit shift register 20 (TXS20), according to the setting of asynchronous serial interface mode
register 20 (ASIM20).

(5) Reception control circuit

The reception control circuit controls reception according to the setting of asynchronous serial interface mode
register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected,
asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error.

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CHAPTER 13 SERIAL INTERFACE 20

13.3 Serial Interface 20 Control Registers

Serial interface 20 is controlled by the following four registers.

• Serial operating mode register 20 (CSIM20)

• Asynchronous serial interface mode register 20 (ASIM20)
• Asynchronous serial interface status register 20 (ASIS20)
• Baud rate generator control register 20 (BRGC20)

(1) Serial operating mode register 20 (CSIM20)

CSIM20 is used to make the settings related to 3-wire serial I/O mode.
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.

Figure 13-3. Serial Operating Mode Register 20 Format

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W
CSIM20 CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 FF72H 00H R/W

CSIE20 3-wire serial I/O mode operation control

0 Operation disabled

1 Operation enabled
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SSE20 SS20-pin selection Function of the SS20/P23 pin Communication status
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0 Not used Port function Communication enabled
1 Used 0 Communication enabled
1 Communication disabled

DAP20 3-wire serial I/O mode data phase selection

0 Outputs at the falling edge of SCK20.

1 Outputs at the rising edge of SCK20.

DIR20 First-bit specification

0 MSB

1 LSB

CSCK20 3-wire serial I/O mode clock selection

0 External clock pulse input to the SCK20 pin.

1 Output of the dedicated baud rate generator

CKP20 3-wire serial I/O mode clock phase selection

0 Clock is low active, and SCK20 is at high level in the idle state

1 Clock is high active, and SCK20 is at low level in the idle state

DataSheet4U.com Cautions 1. Bits 4 and 5 must be fixed to 0.

2. CSIM20 must be cleared to 00H, if UART mode is selected.

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CHAPTER 13 SERIAL INTERFACE 20

(2) Asynchronous serial interface mode register 20 (ASIM20)

ASIM20 is used to make the settings related to asynchronous serial interface mode.
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.

Figure 13-4. Asynchronous Serial Interface Mode Register 20 Format

Symbol <7> <6> 5 4 3 2 1 0 Address After reset R/W

ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 FF70H 00H R/W

TXE20 Transmit operation control

0 Send operation stop

1 Send operation enable

RXE20 Receive operation control

0 Receive operation stop

1 Receive operation enable

PS201 PS200 Parity bit specification

et4U.com 0 0 No parity e
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0 1 Always add 0 parity at transmission.
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Parity check is not performed at reception (No parity error is generated).

1 0 Odd parity

1 1 Even parity

CL20 Transmit data character length specification

0 7 bits

1 8 bits

SL20 Transmit data stop bit length

0 1 bit

1 2 bits

Cautions 1. Bits 0 and 1 must be fixed to 0.

2. If 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
3. Switch operating modes after halting a serial transmit/receive operation.

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CHAPTER 13 SERIAL INTERFACE 20

Table 13-2. Serial Interface 20 Operating Mode Settings

(1) Operation stopped mode

ASIM20 CSIM20 PM22 P21 PM21 P21 PM20 P20 First Shift P22/SI20/RxD20 P21/SO20/TxD20 P20/SCK20/
TXE20 RXE20 CSIE20 DIR20 CSCK20 Bit Clock Pin Function Pin Function ASCK20 Pin
Function
0 0 0 × × ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 — — P22 P21 P20
Other than above Setting prohibited

(2) 3-wire serial I/O mode

ASIM20 CSIM20 PM22 P22 PM21 P21 PM20 P20 First Shift P22/SI20/RxD20 P21/SO20/TxD20 P20/SCK20/
TXE20 RXE20 CSIE20 DIR20 CSCK20 Bit Clock Pin Function Pin Function ASCK20 Pin
Function
0 0 1 0 0 ×Note 1 ×Note 2 0 1 1 × MSB External SI20Note 2 SCK20 SCK20
clock (CMOS output) input
1 0 1 Internal SCK20
clock output
1 1 0 1 × LSB External SCK20
clock input
1 0 1 Internal SCK20
clock output
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Other than above Setting prohibited DataShe
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(3) Asynchronous serial interface mode

ASIM20 CSIM20 PM22 P22 PM21 P21 PM20 P20 First Shift P22/SI20/RxD20 P21/SO20/TxD20 P20/SCK20/
TXE20 RXE20 CSIE20 DIR20 CSCK20 Bit Clock Pin Function Pin Function ASCK20 Pin
Function
1 0 0 0 0 ×Note 1 ×Note 1 0 1 1 × LSB External P22 TxD20 ASCK20
clock (CMOS output) input
×Note 1 ×Note 1 Internal P20
clock
0 1 0 0 0 1 × ×Note 1 ×Note 1 1 × External RD20 P21 ASCK20
clock input
×Note 1 ×Note 1 Internal P20
clock
1 1 0 0 0 1 × 0 1 1 × External TxD20 ASCK20
clock (CMOS output) input
×Note 1 ×Note 1 Internal P20
clock
Other than above Setting prohibited

Notes 1. These pins can be used for port functions.

2. When only transmission is used, these pins can be used as P22 (CMOS input/output).

Remark ×: don’t care.

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CHAPTER 13 SERIAL INTERFACE 20

(3) Asynchronous serial interface status register 20 (ASIS20)

ASIS20 is used to display the type of a reception error, if it occurs while asynchronous serial interface mode
is set.
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
The contents of ASIS20 are undefined in 3-wire serial I/O mode.
RESET input clears ASIS20 to 00H.

Figure 13-5. Asynchronous Serial Interface Status Register 20 Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

ASIS20 0 0 0 0 0 PE20 FE20 OVE20 FF71H 00H R

PE20 Parity error flag

0 No parity error has occurred.

1 A parity error has occurred (parity mismatch in transmission data).

FE20 Flaming error flag

0 No framing error has occurred.

1 A framing error has occurred (no stop bit detected).Note 1

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OVE20 Overrun error flag DataShe
0 No overrun error has occurred. DataSheet4U.com
Note 2
1 An overrun error has occurred.
(Before data was read from the reception buffer register, the subsequent reception sequence was
completed.)

Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface
mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every
time the data is received an overrun error is generated.

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CHAPTER 13 SERIAL INTERFACE 20

(4) Baud rate generator control register 20 (BRGC20)

BRGC20 is used to specify the serial clock for serial interface.
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.

Figure 13-6. Baud Rate Generator Control Register 20 Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

BRGC20 TPS203 TPS202 TPS201 TPS200 0 0 0 0 FF73H 00H R/W

TPS203 TPS202 TPS201 TPS200 3-bit counter source clock selection n

0 0 0 0 fX/2 (2.5 MHz) 1

0 0 0 1 fX/22 (1.25 MHz) 2

0 0 1 0 fX/23 (625 kHz) 3

0 0 1 1 fX/24 (313 kHz) 4

0 1 0 0 fX/25 (156 kHz) 5

0 1 0 1 fX/26 (78.1 kHz) 6

0 1 1 0 fX/27 (39.1 kHz) 7

0 1 1 1 fX/28 (19.5 kHz) 8

Note
1 0 0 0 –
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External clock pulse input at the ASCK20 pin
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Other than above Setting prohibited
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Note An external clock can only be used in UART mode.

Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of
baud rate generator is disrupted and communications cannot be performed normally. Be
sure not to write to BRGC20 during communication operations.
2. Be sure not to select n = 1 during operation at fX = 5.0 MHz because n = 1 exceeds the
baud rate limit.
3. When the external input clock is selected, set port mode register 2 (PM2) in input mode.

Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)

2. n: Value specified in TPS200 to TPS203 (1 ≤ n ≤ 8)
3. Values in parentheses apply to operation with fX = 5.0 MHz.

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CHAPTER 13 SERIAL INTERFACE 20

The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal
scaled from the clock input from the ASCK20 pin.

(a) Generation of baud rate transmit/receive clock by means of system clock

The transmit/receive clock is generated by scaling the system clock. The baud rate generated from the
system clock is estimated by using the following expression.

fX
[Baud rate] = [Hz]
2n + 1 ×8

fX: System clock oscillation frequency (ceramic/crystal oscillation)

n: Values in Figure 13-6 specified by the setting in TPS200 to TPS203 (2 ≤ n ≤ 8)

Table 13-3. Example of Relationship between System Clock and Baud Rate

Baud Rate (bps) n BRGC20 Set Value Error (%)

fX = 5.0 MHz fX = 4.9152 MHz
1,200 8 70H 1.73 0
2,400 7 60H
4,800 6 50H
9,600 5 40H
19,200 4 30H

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CHAPTER 13 SERIAL INTERFACE 20

(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin
The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate
generated from the clock input from the ASCK20 pin is estimated by using the following expression.

fASCK
[Baud rate] = [Hz]
16

fASCK: Frequency of clock pulse received at the ASCK20 pin

Table 13-4. Relationship between ASCK20 Pin Input Frequency

and Baud Rate (When BRGC20 Is Set to 80H)

Baud Rate (bps) ASCK20 Pin input Frequency (kHz)

75 1.2
150 2.4
300 4.8
600 9.6
1,200 19.2
2,400 38.4
4,800 76.8
9,600 153.6
19,200 307.2
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31,250 500.0
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38,400 614.4
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CHAPTER 13 SERIAL INTERFACE 20

13.4 Serial Interface 20 Operation

Serial interface 20 provides the following three types of modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode

13.4.1 Operation stop mode

In the operation stop mode, serial transfer is not executed, therefore, the power consumption can be reduced. The
P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports.

(1) Register setting

Operation stop mode is set by serial operating mode register 20 (CSIM20) and asynchronous serial interface
mode register 20 (ASIM20).

(a) Serial operation mode register 20 (CSIM20)

CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W

CSIM20 CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 FF72H 00H R/W
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CSIE20 Operation control in 3-wire serial I/O mode
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0 Operation disable
1 Operation enable

Caution Be sure to set bits 4 and 5 to 0.

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CHAPTER 13 SERIAL INTERFACE 20

(b) Asynchronous serial interface mode register 20 (ASIM20)

ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.

Symbol <7> <6> 5 4 3 2 1 0 Address After reset R/W

ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 FF70H 00H R/W

TXE20 Transmit operation control

0 Transmit operation stop

1 Transmit operation enable

RXE20 Receive operation control

0 Receive operation stop

1 Receive operation enable

Caution Be sure to set bits 0 and 1 to 0.

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CHAPTER 13 SERIAL INTERFACE 20

13.4.2 Asynchronous serial interface (UART) mode

In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication
is possible.
This device incorporates a UART-dedicated baud rate generator that enables communication at the desired transfer
rate from many options. In addition, the baud rate can also be defined by dividing the input clock to the ASCK pin.
The UART-dedicated baud rate generator also can output the 31.25-kbps baud rate that complies with the MIDI
standard.
It is recommended that the ceramic/crystal oscillation be used for the system clock in the UART mode. Because
the frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the baud rate
generator, there may be problems in send/receive operations.

(1) Register setting

The UART mode is set by serial operating mode register 20 (CSIM20), asynchronous serial interface mode
register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), and baud rate generator
control register 20 (BRGC20).

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CHAPTER 13 SERIAL INTERFACE 20

(a) Serial operating mode register 20 (CSIM20)

CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Set 00H to CSIM20 when UART mode is selected.

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W

CSIM20 CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 FF72H 00H R/W

CSIE20 3-wire serial I/O mode operation control

0 Operation disabled

1 Operation enabled

SSE20 SS20-pin selection Function of the SS20/P23 pin Communication status

0 Not used Port function Communication enabled

1 Used 0 Communication enabled
1 Communication disabled

DAP20 3-wire serial I/O mode data phase selection

0 Outputs at the falling edge of SCK20.

1 Outputs at the rising edge of SCK20.

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DIR20 First-bit specification
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0 MSB

1 LSB

CSCK20 3-wire serial I/O mode clock selection

0 External clock pulse input to the SCK20 pin.

1 Output of the dedicated baud rate generator

CKP20 3-wire serial I/O mode clock phase selection

0 Clock is low active, and SCK20 is high level in the idle state

1 Clock is high active, and SCK20 is low level in the idle state

Caution Bits 4 and 5 must be fixed to 0.

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CHAPTER 13 SERIAL INTERFACE 20

(b) Asynchronous serial interface mode register 20 (ASIM20)

ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.

Symbol <7> <6> 5 4 3 2 1 0 Address After reset R/W

ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 FF70H 00H R/W

TXE20 Transmit operation control

0 Transmit operation stop

1 Transmit operation enable

RXE20 Receive operation control

0 Receive operation stop

1 Receive operation enable

PS201 PS200 Parity bit specification

0 0 No parity
0 1 Always add 0 parity at transmission.
Parity check is not performed at reception (No parity error is generated).

1 0 Odd parity
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CL20 Character length specification

0 7 bits
1 8 bits

SL20 Transmit data stop bit length specification

0 1 bit

1 2 bits

Cautions 1. Be sure to set bits 0 and 1 to 0.

2. Switch operating modes after halting the serial transmit/receive operation.

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CHAPTER 13 SERIAL INTERFACE 20

(c) Asynchronous serial interface status register 20 (ASIS20)

ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS20 to 00H.

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

ASIS20 0 0 0 0 0 PE20 FE20 OVE20 FF71H 00H R

PE20 Parity error flag

0 Parity error not generated

1 Parity error generated (when the parity of transmit data does not match.)

FE20 Flaming error flag

0 Framing error not generated

1 Framing error generated (when stop bit is not detected.)Note 1

OVE20 Overrun error flag

0 Overrun error not generated

1 Overrun error generatedNote 2
(when the next receive operation is completed before the data is read from the receive buffer register.)

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Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface
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mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every
time the data is received an overrun error is generated.

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CHAPTER 13 SERIAL INTERFACE 20

(d) Baud rate generator control register 20 (BRGC20)

BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

BRGC20 TPS203 TPS202 TPS201 TPS200 0 0 0 0 FF73H 00H R/W

TPS203 TPS202 TPS201 TPS200 3-bit counter source clock selection n

0 0 0 0 fX/2 (2.5 MHz) 1

0 0 0 1 fX/22 (1.25 MHz) 2

0 0 1 0 fX/23 (625 kHz) 3

0 0 1 1 fX/24 (313 kHz) 4

0 1 0 0 fX/25 (156 kHz) 5

0 1 0 1 fX/26 (78.1 kHz) 6

0 1 1 0 fX/27 (39.1 kHz) 7

0 1 1 1 fX/28 (19.5 kHz) 8

1 0 0 0 Input clock from external to ASCK20 pin. –

Other than above Setting prohibited

et4U.com Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of e
DataShe
baud rate generator is disrupted and communications cannot be performed normally. Be
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sure not to write to BRGC20 during communication operation.
2. Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds
the baud rate limit.
3. When the external input clock is selected, set port mode register 2 (PM2) to input mode.

Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)

2. n: Values specified by the setting in TPS200 to TPS203 (1 ≤ n ≤ 8)
3. Values in parentheses apply to operation with fX = 5.0 MHz.

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The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or
a signal scaled from the clock input from the ASCK20 pin.

(i) Generation of baud rate transmit/receive clock by means of system clock

The transmit/receive clock is generated by scaling the system clock. The baud rate generated from
the system clock is estimated by using the following expression.

fx
[Baud rate] = [Hz]
2n + 1 × 8

fX: System clock oscillation frequency (ceramic/crystal oscillation)

n: Values in the above table specified by the setting in TPS200 to TPS203 (2 ≤ n ≤ 8)

Table 13-5. Example of Relationship between System Clock and Baud Rate

Baud Rate (bps) n BRGC20 Set Value Error (%)

fX = 5.0 MHz fX = 4.9152 MHz
1,200 8 70H 1.73 0
2,400 7 60H
4,800 6 50H
9,600 5 40H
19,200 4 30H

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(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin
The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud
rate generated from the clock input from the ASCK20 pin is estimated by using the following
expression.

fASCK
[Baud rate] = [Hz]
16

fASCK: Frequency of clock input to ASCK20 pin.

Table 13-6. Relationship between ASCK20 Pin Input Frequency

and Baud Rate (When BRGC20 Is Set to 80H)

Baud Rate (bps) ASCK20 Pin input Frequency (kHz)

75 1.2
150 2.4
300 4.8
600 9.6
1,200 19.2
2,400 38.4
4,800 76.8
9,600 153.6

et4U.com 19,200 307.2 e

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31,250 500.0
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38,400 614.4

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CHAPTER 13 SERIAL INTERFACE 20

(2) Communication operation

(a) Data format

The transmit/receive data format is as shown in Figure 13-7. One data frame consists of a start bit,
character bits, parity bit and stop bit(s).
The specification of character bit length, parity selection, and specification of stop bit length for each data
frame is carried out using asynchronous serial interface mode register 20 (ASIM20).

Figure 13-7. Asynchronous Serial Interface Transmit/Receive Data Format

One data frame

Start Parity
D0 D1 D2 D3 D4 D5 D6 D7 Stop bit
bit bit

• Start bits .................. 1 bit

• Character bits .......... 7 bits/8 bits
• Parity bits ................. Even parity/odd parity/0 parity/no parity
• Stop bits ................... 1 bit/2 bits

When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
et4U.com transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is e
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always “0”.
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The serial transfer rate is selected by means of ASIM20 and baud rate generator control register 20
(BRGC20).
If a serial data receive error is generated, the receive error contents can be determined by reading the
status of asynchronous serial interface status register 20 (ASIS20).

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CHAPTER 13 SERIAL INTERFACE 20

(b) Parity types and operation

The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.

(i) Even parity

• At transmission
The transmission operation is controlled so that the number of bits with a value of “1” in the transmit
data including parity bit may be even. The parity bit value should be as follows.

The number of bits with a value of “1” is an odd number in transmit data: 1
The number of bits with a value of “1” is an even number in transmit data: 0

• At reception
The number of bits with a value of “1” in the receive data including parity bit is counted, and if the
number is odd, a parity error is generated.

(ii) Odd parity

• At transmission
Conversely to even parity, the transmission operation is controlled so that the number of bits with
et4U.com a value of “1” in the transmit data including parity bit may be odd. The parity bit value should be e
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as follows.
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The number of bits with a value of “1” is an odd number in transmit data: 0
The number of bits with a value of “1” is an even number in transmit data: 1

• At reception
The number of bits with a value of “1” in the receive data including parity bit is counted, and if the
number is even, a parity error is generated.

(iii) 0 Parity
When transmitting, the parity bit is set to “0” irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective
of whether the parity bit is set to “0” or “1”.

(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is
no parity bit. Since there is no parity bit, a parity error is not generated.

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CHAPTER 13 SERIAL INTERFACE 20

(c) Transmission
A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start
bit, parity bit and stop bit are added automatically.
When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a
transmission completion interrupt (INTST20) is generated.

Figure 13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing

(a) Stop bit length: 1

STOP
TxD20 (Output) D0 D1 D2 D6 D7 Parity

START

INTST20

(b) Stop bit length: 2

TxD20 (Output) D0 D1 D2 D6 D7 Parity STOP

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START DataShe
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INTST20

Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a transmit
operation. If ASIM20 register is rewritten during transmission, subsequent transmission
may not be performed (the normal state is restored by RESET input).
It is possible to determine whether transmission is in progress by software by using a
transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set by
INTST20.

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CHAPTER 13 SERIAL INTERFACE 20

(d) Reception
When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive
operation is enabled and sampling of the RxD20 pin input is performed.
RxD20 pin input sampling is performed using the serial clock specified by ASIM20.
When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time
determined by the specified baud rate has passed, the data sampling start timing signal is output. If the
RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit,
the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data,
a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to receive
buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated.
If an error is generated, the receive data in which the error was generated is still transferred to RXB20,
and INTSR20 is generated.
If the RXE20 bit is reset (0) during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are
not changed, and INTSR20 is not generated.

Figure 13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing

STOP
RxD20 (Input) D0 D1 D2 D6 D7 Parity

START
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INTSR20
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Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If RXB20
is not read, an overrun error will be generated when the next data is received, and the
receive error state will continue indefinitely.

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CHAPTER 13 SERIAL INTERFACE 20

(e) Receive errors

The following three errors may occur during a receive operation: a parity error, framing error, or overrun
error. The data reception result error flag is set in asynchronous serial interface status register 20
(ASIS20). Receive error causes are shown in Table 13-7.
It is possible to determine what kind of error was generated during reception by reading the contents of
ASIS20 in the reception error interrupt servicing (see Figures 13-9 and 13-10).
The contents of ASIS20 are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).

Table 13-7. Receive Error Causes

Receive Errors Cause

Parity error Transmission-time parity specification and reception data parity do not match

Framing error Stop bit not detected

Overrun error Reception of next data is completed before data is read from receive register buffer

Figure 13-10. Receive Error Timing

(a) Parity error generated

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STOP
RxD20 (Input) D0 D1 D2 D6 D7 Parity
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START

INTSR20

(b) Framing error or overrun error generated

STOP
RxD20 (Input) D0 D1 D2 D6 D7 Parity

START

INTSR20

Cautions 1. The contents of the ASIS20 register are reset (0) by reading receive buffer register 20
(RXB20) or receiving the next data. To ascertain the error contents, read ASIS20
before reading RXB20.
2. Be sure to read receive buffer register 20 (RXB20) even if a receive error is generated.
If RXB20 is not read, an overrun error will be generated when the next data is received,
and the receive error state will continue indefinitely.

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CHAPTER 13 SERIAL INTERFACE 20

(3) UART mode cautions

(a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing
the next transmission.

(b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
reception, receive buffer register 20 (RXB20) and receive completion interrupt 20 (INTSR20) are as
follows.

RxD20 Pin Parity

RXB20

INTSR20

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<1> <3>
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<2>
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When RXE20 is set to 0 at a time indicated by <1>, RXB20 holds the previous data and does not generate
INTSR20.
When RXE20 is set to 0 at a time indicated by <2>, RXB20 renews the data and does not generate INTSR20.
When RXE20 is set to 0 at a time indicated by <3>, RXB20 renews the data and generates INTSR20.

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CHAPTER 13 SERIAL INTERFACE 20

13.4.3 3-wire serial I/O mode

The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc. that incorporate
a conventional synchronous clocked serial interface, such as the 75XL Series, 78K Series, 17K Series, etc.
Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input
(SI20).

(1) Register setting

3-wire serial I/O mode settings are performed using serial operating mode register 20 (CSIM20), asynchronous
serial interface mode register 20 (ASIM20), and baud rate generator control register 20 (BRGC20).

(a) Serial operating mode register 20 (CSIM20)

CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W

CSIM20 CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 FF72H 00H R/W

CSIE20 3-wire serial I/O mode operation control

0 Operation disabled

1 Operation enabled

SSE20 SS20-pin selection Function of the SS20/P23 pin Communication status

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0 Not used Port function Communication enabled
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1 Used DataSheet4U.com 0 Communication enabled

1 Communication disabled

DAP20 3-wire serial I/O mode data phase selection

0 Outputs at the falling edge of SCK20.

1 Outputs at the rising edge of SCK20.

DIR20 First-bit specification

0 MSB

1 LSB

CSCK20 3-wire serial I/O mode clock selection

0 External clock pulse input to the SCK20 pin.

1 Output of the dedicated baud rate generator

CKP20 3-wire serial I/O mode clock phase selection

0 Clock is low active, and SCK20 is at high level in the idle state

1 Clock is high active, and SCK20 is at low level in the idle state

Caution Bits 4 and 5 must be fixed to 0.

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CHAPTER 13 SERIAL INTERFACE 20

(b) Asynchronous serial interface mode register 20 (ASIM20)

ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
When the 3-wire serial I/O mode is selected, 00H must be set to ASIM20.

Symbol <7> <6> 5 4 3 2 1 0 Address After reset R/W

ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 FF70H 00H R/W

TXE20 Transmit operation control

0 Transmit operation stop

1 Transmit operation enable

RXE20 Receive operation control

0 Receive operation stop

1 Receive operation enable

PS201 PS200 Parity bit specification

0 0 No parity
0 1 Always add 0 parity at transmission.
Parity check is not performed at reception (No parity error is generated).
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1 0 Odd parity DataShe
1 1 Even parity DataSheet4U.com

CL20 Character length specification

0 7 bits
1 8 bits

SL20 Transmit data stop bit length specification

0 1 bit

1 2 bits

Cautions 1. Be sure to set bits 0 and 1 to 0.

2. Switching operation modes must be performed after the serial transmit/receive
operation is halted.

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CHAPTER 13 SERIAL INTERFACE 20

(c) Baud rate generator control register 20 (BRGC20)

BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

BRGC20 TPS203 TPS202 TPS201 TPS200 0 0 0 0 FF73H 00H R/W

TPS203 TPS202 TPS201 TPS200 3-bit counter source clock selection n

0 0 0 0 fX/2 (2.5 MHz) 1

0 0 0 1 fX/22 (1.25 MHz) 2

0 0 1 0 fX/23 (625 kHz) 3

0 0 1 1 fX/24 (313 kHz) 4

0 1 0 0 fX/25 (156 kHz) 5

0 1 0 1 fX/26 (78.1 kHz) 6

0 1 1 0 fX/27 (39.1 kHz) 7

0 1 1 1 fX/28 (19.5 kHz) 8

Other than above Setting prohibited

Cautions 1. When writing to BRGC20 is performed during a communication operation, the baud
rate generator output is disrupted and communication cannot be performed normally.
et4U.com Be sure not to write to BRGC20 during communication operation. e
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2. Be sure not to select n = 1 during an operation at fX = 5.0 MHz because n = 1 exceeds
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the baud rate limit.
3. When the external input clock is selected, set port mode register 2 (PM2) in input mode.

Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)

2. n: Values specified by TPS200 to TPS203 (1 ≤ n ≤ 8)
3. Values in parentheses apply to operation with fX = 5.0 MHz.

If the internal clock is used as the serial clock for the 3-wire serial I/O mode, set the TPS200 to TPS203
bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula.
When the serial clock is input from off-chip, setting BRGC20 is not necessary.

fx
Serial clock frequency = [Hz]
2n + 1

fX: System clock oscillation frequency (ceramic/crystal oscillation)

n: Values in the above table specified by the setting in TPS200 to TPS203 (1 ≤ n ≤ 8)

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CHAPTER 13 SERIAL INTERFACE 20

(2) Communication operation

In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/
received bit by bit in synchronization with the serial clock.
The transmit shift register (TXS20/SIO20) and receive shift register (RXS20) shift operations are performed
in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20 latch and
output from the SO20 pin. Also, receive data input to the SI0 pin is latched in the receive buffer register (RXB20/
SIO20) on the rise of SCK20.
At the end of an 8-bit transfer, the operation of TXS20/SIO20 or RXS20 stops automatically, and the interrupt
request signal (INTCSI20) is generated.

Figure 13-11. 3-Wire Serial I/O Mode Timing (1/7)

(i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SO20 Note
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DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
e
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SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

INTCSI20

Note The value of the last bit previously output is output.

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CHAPTER 13 SERIAL INTERFACE 20

Figure 13-11. 3-Wire Serial I/O Mode Timing (2/7)

(ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

INTCSI20

Note The value of the last bit previously output is output.

et4U.com (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) e

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SS20

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

Hi-Z Note 1
Hi-Z
SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2

INTCSI20

Notes 1. The value of the last bit previously output is output.

2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.

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CHAPTER 13 SERIAL INTERFACE 20

Figure 13-11. 3-Wire Serial I/O Mode Timing (3/7)

(iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0)

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

INTCSI20

(v) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)

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SIO20 DataShe
Write
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SCK20 1 2 3 4 5 6 7 8

SIO20 Write (master)Note

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

INTCSI20

Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the
first bit before the first rising of SCK20.

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CHAPTER 13 SERIAL INTERFACE 20

Figure 13-11. 3-Wire Serial I/O Mode Timing (4/7)

(vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1)

SS20

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SIO20 Write (master)Note 1

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

Hi-Z Note 2
Hi-Z
SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

INTCSI20

et4U.com Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs e
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the first bit before the first rising of SCK20.
2. SO20 is high until SS20DataSheet4U.com
rises after completion of DO0 output. When SS20 is high, SO20 is in
a high-impedance state.

(vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

INTCSI20

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CHAPTER 13 SERIAL INTERFACE 20

Figure 13-11. 3-Wire Serial I/O Mode Timing (5/7)

(viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SIO20 Write (master)Note

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

INTCSI20

Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the
first bit before the first falling of SCK20.
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(ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1)
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SS20

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SIO20 Write (master)Note 1

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

Hi-Z Note 2
Hi-Z
SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

INTCSI20

Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs
the first bit before the first falling of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in
a high-impedance state.
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CHAPTER 13 SERIAL INTERFACE 20

Figure 13-11. 3-Wire Serial I/O Mode Timing (6/7)

(x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SO20 Note DO7 DO6 DO5 DOI4 DO3 DO2 DO1 DO0

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

INTCSI20

Note The value of the last bit previously output is output.

et4U.com (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) e

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SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SO20 Note DO7 DO6 DO5 DOI4 DO3 DO2 DO1 DO0

INTCSI20

Note The value of the last bit previously output is output.

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CHAPTER 13 SERIAL INTERFACE 20

Figure 13-11. 3-Wire Serial I/O Mode Timing (7/7)

(xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1)

SS20

SIO20
Write

SCK20 1 2 3 4 5 6 7 8

SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

Hi-Z Hi-Z
SO20 Note 1
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2

INTCSI20

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Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.DataSheet4U.com
When SS20 is high, SO20 is in a high-impedance state.

(3) Transfer start

Serial transfer is started by setting transfer data to the transmission shift register (TXS20/SIO20) when the
following two conditions are satisfied.

• Serial operation mode register 20 (CSIM20) bit 7 (CSIE20) = 1

• Internal serial clock is stopped or SCK20 is a high level after 8-bit serial transfer.

Caution If CSIE20 is set to “1” after data write to TXS20/SIO20, transfer does not start.

A termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI20).

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CHAPTER 14 MULTIPLIER

14.1 Multiplier Function

The multiplier has the following function:

• Calculation of 8 bits × 8 bits = 16 bits

14.2 Multiplier Configuration

(1) 16-bit multiplication result storage register 0 (MUL0)

This register stores the 16-bit result of multiplication.
This register holds the result of multiplication after 16 CPU clocks have elapsed.
MUL0 is set with a 16-bit memory manipulation instruction.
RESET input makes this register undefined.

Caution Although this register is manipulated with a 16-bit memory manipulation instruction, it can
be also manipulated with an 8-bit memory manipulation instruction. When using an 8-bit
memory manipulation instruction, however, access the register by means of direct addressing.

(2) Multiplication data registers A and B (MRA0 and MRB0)

et4U.com These are 8-bit multiplication data storage registers. The multiplier multiplies the values of MRA0 and MRB0. e
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MRA0 and MRB0 are set with a 1-bit or 8-bit memory manipulation instructions.
RESET input makes these registersDataSheet4U.com
undefined.
Figure 14-1 shows the block diagram of the multiplier.

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CHAPTER 14 MULTIPLIER

Figure 14-1. Block Diagram of Multiplier

Internal bus

Multiplication data Multiplication data

register A (MRA0) register B (MRB0)

Counter value
Selector 3-bit counter CPU clock
3

Start Clear

Counter output
16-bit
adder

16-bit multiplication result

storage register 0 (Master) (MUL0)

16-bit multiplication result

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storage register 0 (Slave)
e
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MULST0 Reset

Multiplier control
register 0 (MULC0)

Internal bus

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CHAPTER 14 MULTIPLIER

14.3 Multiplier Control Register

The multiplier is controlled by the following register:

• Multiplier control register (MULC0)
MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier.
MULC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.

Figure 14-2. Multiplier Control Register 0 Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

MULC0 0 0 0 0 0 0 0 MULST0 FFD2H 00H R/W

MULST0 Multiplier operation start control bit Operating status of multiplier

0 Stops operation after resetting counter to 0. Operation stops

1 Enables operation Operation in progress

Caution Be sure to set bits 1 to 7 to 0.

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CHAPTER 14 MULTIPLIER

14.4 Multiplier Operation

The multiplier of the µPD789104A/114A/124A/134A Subseries can execute the calculation of 8 bits × 8 bits = 16
bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H.

<1> Counting is started by setting MULST0.

<2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter
value is incremented by one.
<3> If MULST0 is cleared when the counter value is 111B, the operation is stopped. At this time, MUL0 holds
the data.
<4> While MULST0 is low, the counter and slave are cleared.

Figure 14-3. Multiplier Operation Timing

CPU clock

MRA0 AA

MRB0 D3

MULST0

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DataShe
Counter 000B 001B 010B 011B
DataSheet4U.com 100B 101B 110B 111B 000B

Selector output 00AA 0154 0000 0000 0AA0 0000 2A80 5500 00AA

MUL0 00AA 01FE 01FE 01FE 0C9E 0C9E 371E 8C1E

(Master)

(Slave) 0000 00AA 01FE 01FE 01FE 0C9E 0C9E 371E 0000

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CHAPTER 15 INTERRUPT FUNCTIONS

15.1 Interrupt Function Types

The following two types of interrupt functions are used.

(1) Non-maskable interrupt

This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
The non-maskable interrupt has one source of interrupt from the watchdog timer.

(2) Maskable interrupt

These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt has a predetermined priority as shown in Table 15-1.
A standby release signal is generated.
The maskable interrupt has three sources of external interrupts and six sources of internal interrupts.

15.2 Interrupt Sources and Configuration

et4U.com There are total of 10 non-maskable and maskable interrupts in the interrupt sources (see Table 15-1). e
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CHAPTER 15 INTERRUPT FUNCTIONS

Table 15-1. Interrupt Source List

Interrupt Type PriorityNote 1 Interrupt Source Internal Vector Basic

/External Table Configuration
Name Trigger Address TypeNote 2
Non-maskable — INTWDT Watchdog timer overflow (watchdog timer Internal 0004H (A)
mode 1 selected)
Maskable 0 INTWDT Watchdog timer overflow (interval timer (B)
mode selected)

1 INTP0 Pin input edge detection External 0006H (C)

2 INTP1 0008H
3 INTP2 000AH

4 INTSR20 End of serial interface 20 UART reception Internal 000CH (B)

INTCSI20 End of serial interface 20 3-wire transfer
5 INTST20 End of serial interface 20 UART 000EH
transmission

6 INTTM80 Generation of 8-bit timer/event counter 80 0010H

match signal
7 INTTM20 Generation of 16-bit timer 20 0012H
match signal
8 INTAD0 A/D conversion completion signal 0014H

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Notes 1. Priority is the priority applicable when two or more maskable interrupts are simultaneously generated. DataShe
0 is the highest priority and 8 is the lowest priority.
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2. Basic configuration types A to C correspond to A to C in Figure 15-1.

Remark As the interrupt source of the watchdog timer (INTWDT), either a non-maskable interrupt or a maskable
interrupt (internal) can be selected.

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CHAPTER 15 INTERRUPT FUNCTIONS

Figure 15-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal bus

Interrupt request Vector table

address generator

Standby release signal

(B) Internal maskable interrupt

Internal bus

MK IE

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Vector table
e
Interrupt request IF
address generator DataShe
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Standby release signal

(C) External maskable interrupt

Internal bus

External interrupt mode

register (INTM0) MK IE

Vector table
Interrupt Edge address generator
request detector IF

Standby
release signal

IF: Interrupt request flag

IE: Interrupt enable flag
MK: Interrupt mask flag

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CHAPTER 15 INTERRUPT FUNCTIONS

15.3 Interrupt Function Control Registers

The following four registers are used to control the interrupt functions.

• Interrupt request flag registers (IF0, IF1)

• Interrupt mask flag registers (MK0, MK1)
• External interrupt mode register (INTM0)
• Program status word (PSW)

Table 15-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt
requests.

Table 15-2. Flags Corresponding to Interrupt Request Signal

Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag
INTWDT TMIF4 TMMK4
INTP0 PIF0 PMK0
INTP1 PIF1 PMK1
INTP2 PIF2 PMK2
INTSR20/INTCSI20 SRIF20 SRMK20
INTST20 STIF20 STMK20
INTTM80 TMIF80 TMMK80
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INTTM20 TMIF20 TMMK20 DataShe
INTAD0 ADIF0 DataSheet4U.com ADMK0

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CHAPTER 15 INTERRUPT FUNCTIONS

(1) Interrupt request flag registers (IF0, IF1)

The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction
is executed. It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request
or upon RESET input.
IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.

Figure 15-2. Interrupt Request Flag Register Format

Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset R/W

IF0 TMIF20 TMIF80 STIF20 SRIF20 PIF2 PIF1 PIF0 TMIF4 FFE0H 00H R/W

Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W

IF1 0 0 0 0 0 0 0 ADIF0 FFE1H 00H R/W

××IF× Interrupt request flag

0 No interrupt request signal is generated

1 Interrupt request signal is generated; Interrupt request state

Cautions 1. TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer.
If the watchdog timer mode 1 and 2 are used, set the TMIF4 flag to 0.
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2. Because port 2 has an alternate function as the external interrupt input, when the output DataShe
level is changed by specifying the output mode of the port function, an interrupt request
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flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output
mode.

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CHAPTER 15 INTERRUPT FUNCTIONS

(2) Interrupt mask flag registers (MK0, MK1)

The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service.
MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.

Figure 15-3. Interrupt Mask Flag Register Format

Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset R/W
MK0 TMMK20 TMMK80 STMK20 SRMK20 PMK2 PMK1 PMK0 TMMK4 FFE4H FFH R/W

Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W

MK1 1 1 1 1 1 1 1 ADMK0 FFE5H FFH R/W

××MK× Interrupt servicing control

0 Interrupt servicing enabled

1 Interrupt servicing disabled

Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1
and 2, its value becomes undefined.
2. Because port 2 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request
et4U.com flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output e
DataShe
mode.
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CHAPTER 15 INTERRUPT FUNCTIONS

(3) External interrupt mode register 0 (INTM0)

This register is used to set the valid edge of INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.

Figure 15-4. External Interrupt Mode Register 0 Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

INTM0 ES21 ES20 ES11 ES10 ES01 ES00 0 0 FFECH 00H R/W

ES21 ES20 INTP2 valid edge selection

0 0 Falling edge

0 1 Rising edge

1 0 Setting prohibited

1 1 Both rising and falling edges

ES11 ES10 INTP1 valid edge selection

0 0 Falling edge

0 1 Rising edge

1 0 Setting prohibited
et4U.com e
1 1 Both rising and falling edges DataShe
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ES01 ES00 INTP0 valid edge selection

0 0 Falling edge
0 1 Rising edge

1 0 Setting prohibited

1 1 Both rising and falling edges

Cautions 1. Be sure to set bits 0 and 1 to 0.

2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will enable
interrupts.

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CHAPTER 15 INTERRUPT FUNCTIONS

(4) Program status word (PSW)

The program status word is a register used to hold the instruction execution result and the current status for
interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped.
This register can be read/written in 8-bit units and can carry out operations using a bit manipulation and
dedicated instructions (EI, DI). When a vectored interrupt request is acknowledged, PSW is automatically
saved into a stack, and the IE flag is reset to 0. It is reset from the stack by the RETI and POP PSW instructions.
RESET input sets PSW to 02H.

Figure 15-5. Program Status Word Configuration

Symbol 7 6 5 4 3 2 1 0 After reset

PSW IE Z 0 AC 0 0 1 CY 02H

Used when normal instruction is executed

IE Interrupt acknowledge enable/disable

0 Disable

1 Enable

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CHAPTER 15 INTERRUPT FUNCTIONS

15.4 Interrupt Processing Operation

15.4.1 Non-maskable interrupt request acknowledgement operation

The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the
IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 15-6 shows the flowchart from non-maskable interrupt request generation to acknowledgement. Figure
15-7 shows the timing of non-maskable interrupt request acknowledgement. Figure 15-8 shows the acknowledgement
operation if multiple non-maskable interrupts are generated.

Caution During a non-maskable interrupt service program execution, do not input another non-maskable
interrupt request; if it is input, the service program will be interrupted and the new interrupt
request will be acknowledged.

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CHAPTER 15 INTERRUPT FUNCTIONS

Figure 15-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement

Start

WDTM4 = 1
No
(watchdog timer mode
is selected)
Interval timer
Yes

WDT No
overflows

Yes

WDTM3 = 0
No
(non-maskable interrupt
is selected)
Reset processing
Yes

Interrupt request is generated

Interrupt processing is started

WDTM: Watchdog timer mode register

et4U.com WDT: Watchdog timer e
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Figure 15-7. Timing of Non-Maskable Interrupt Request Acknowledgement

Save PSW and PC, and Interrupt processing

CPU processing Instruction Instruction jump to interrupt processing program

TMIF4

Figure 15-8. Acknowledging Non-Maskable Interrupt Request

Main routine

First interrupt processing

NMI request
NMI request (second)
(first)

Second interrupt processing

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CHAPTER 15 INTERRUPT FUNCTIONS

15.4.2 Maskable interrupt request acknowledgement operation

A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding
interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when
the IE flag is set to 1).
The time required to start the interrupt processing after a maskable interrupt request has been generated is shown
in Table 15-3.
Refer to Figures 15-10 and 15-11 for the interrupt request acknowledgement timing.

Table 15-3. Time from Generation of Maskable Interrupt Request to Processing

Minimum Time Maximum TimeNote

9 clocks 19 clocks

Note The wait time is maximum when an

interrupt request is generated immediately
before BT and BF instruction.

1
Remark 1 clock: (fCPU: CPU clock)
fCPU

When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the interrupt request assigned the highest priority.
A pending interrupt is acknowledged when the status where it can be acknowledged is set.
Figure 15-9 shows the algorithm of acknowledging interrupt requests.
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When a maskable interrupt request is acknowledged, the contents of PSW and PC are saved to the stack in that DataShe
order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the
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PC, and execution branches.
To return from interrupt processing, use the RETI instruction.

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CHAPTER 15 INTERRUPT FUNCTIONS

Figure 15-9. Interrupt Acknowledgement Program Algorithm

Start

No
××IF = 1 ?

Yes (Interrupt request generated)

No
××MK = 0 ?

Yes Interrupt request pending

No
IE = 1 ?

Yes Interrupt request pending

Vectored interrupt
processing

××IF: Interrupt request flag

××MK: Interrupt mask flag
et4U.com IE: Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable) e
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CHAPTER 15 INTERRUPT FUNCTIONS

Figure 15-10. Interrupt Request Acknowledgement Timing (Example of MOV A,r)

8 clocks

Clock

Save PSW and PC, jump

CPU MOV A,r Interrupt processing program
to interrupt processing

Interrupt

If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n–
1, the interrupt is acknowledged after the instruction under execution is complete. Figure 15-10 shows an example
of the interrupt request acknowledgement timing for an 8-bit data transfer instruction MOV A,r. Since this instruction
is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgement
processing is performed after the MOV A,r instruction is completed.

Figure 15-11. Interrupt Request Acknowledgement Timing

(When Interrupt Request Flag Is Generated at the
Last Clock During Instruction Execution)

8 clocks

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Clock DataShe
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Save PSW and PC, jump Interrupt

CPU NOP MOV A,r processing
to interrupt processing program

Interrupt

If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgement processing
starts after the next instruction is executed.
Figure 15-11 shows an example of the interrupt acknowledgement timing for an interrupt request flag that is set
at the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is
executed, and then the interrupt acknowledgement processing is performed.

Caution Interrupt requests are reserved while the interrupt request flag register (IF0, IF1) or the interrupt
mask flag register (MK0, MK1) is being accessed.

15.4.3 Multiple interrupt processing

Multiple interrupt processing in which another interrupt is acknowledged while an interrupt is being processed can
be processed by priority. When the priority is controlled by the default priority and two or more interrupts are generated
at once, interrupt processing is performed according to the priority assigned to each interrupt request in advance (refer
to Table 15-1).

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CHAPTER 15 INTERRUPT FUNCTIONS

Figure 15-12. Example of Multiple Interrupts

Example 1. Multiple interrupts are acknowledged

Main processing INTxx processing INTyy processing

IE = 0 IE = 0
EI EI

INTxx INTyy

RETI RETI

During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and a multiple interrupt is generated.
An EI instruction is issued before each interrupt request acknowledgement, and the interrupt request acknowledgement
et4U.com enable state is set. e
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Example 2. A multiple interrupt is not generated because interrupts are not enabled

Main processing INTxx processing INTyy processing

EI IE = 0
INTyy INTyy is kept pending

RETI

INTxx

IE = 0

RETI

Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request
INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy request is reserved and acknowledged
after the INTxx processing is performed.

IE = 0: Interrupt request acknowledgement disabled

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CHAPTER 15 INTERRUPT FUNCTIONS

15.4.4 Interrupt request reserve

Some instructions may reserve the acknowledgement of an instruction request until the completion of the execution
of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt)
is generated during the execution. The following shows such instructions (interrupt request reserve instruction).

• Manipulation instruction for the interrupt request flag register (IF0, IF1)
• Manipulation instruction for the interrupt mask flag register (MK0, MK1)

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[MEMO]

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CHAPTER 16 STANDBY FUNCTION

16.1 Standby Function and Configuration

16.1.1 Standby function

The standby function is to reduce the power consumption of the system and can be effected in the following two
modes:

(1) HALT mode

This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillation circuit continues oscillating. This mode does not reduce the power
consumption as much as the STOP mode, but is useful for resuming processing immediately when an interrupt
request is generated, or for intermittent operations.

(2) STOP mode

This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillation circuit and stops the entire system. The power consumption of the CPU can be substantially reduced
in this mode.
The low voltage (VDD = 1.8 V) of the data memory can be retained. Therefore, this mode is useful for retaining
the contents of the data memory at an extremely low current.
et4U.com The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent e
DataShe
operation. However, some time is required until the system clock oscillation circuit stabilizes after the STOP
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mode has been released. If processing must be resumed immediately by using an interrupt request, therefore,
use the HALT mode.

In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode
are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.

Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then
execute the STOP instruction.

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CHAPTER 16 STANDBY FUNCTION

16.1.2 Standby function control register (µPD789104A, 789114A Subseries)

The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled
with the oscillation stabilization time select register (OSTS)Note.
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 215/fX, instead
of 217/fX.

Note µPD789104A and 789114A Subseries only.

The µPD789124A and 789134A Subseries do not provide an oscillation stabilization time select register.
The oscillation stabilization time of the µPD789124A and 789134A Subseries is fixed to 27/fCC.

Figure 16-1. Oscillation Stabilization Time Select Register Format

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W

OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection

0 0 0 212/fX (819 µs)

0 1 0 215/fX (6.55 ms)

1 0 0 217/fX (26.2 ms)

Other than above Setting prohibited
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Caution The wait time after the STOP mode in a ceramic/crystal oscillator is released does not
include the time from STOPDataSheet4U.com
mode release to clock oscillation start (“a” in the figure
below), regardless of release by RESET input or by interrupt generation.

STOP mode release

X1 pin voltage
waveform

a
VSS

Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)

2. Values in parentheses apply to operation with fX = 5.0 MHz.

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CHAPTER 16 STANDBY FUNCTION

16.2 Operation of Standby Function

16.2.1 HALT mode

(1) HALT mode

The HALT mode is set by executing the HALT instruction.
The operation status in the HALT mode is shown in the following table.

Table 16-1. HALT Mode Operating Status

Item HALT Mode Operating Status

Clock generator System clock can be oscillated.
Clock supply to CPU stops.
CPU Operation stopped

Port (Output latch) Retains the status before setting the HALT mode.
16-bit timer 20 Operable
8-bit timer/event counter 80 Operable

Watchdog timer Operable

Serial interface 20 Operable
A/D converter Operation stopped

Multiplier Operation stopped

et4U.com External interrupt Operable Note

e
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Note Maskable interrupt that is notDataSheet4U.com

masked

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CHAPTER 16 STANDBY FUNCTION

(2) Releasing HALT mode

The HALT mode can be released by the following three types of sources:

(a) Releasing by unmasked interrupt request

The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is
able to be acknowledged, vectored interrupt processing is performed. If the interrupt is disabled, the
instruction at the next address is executed.

Figure 16-2. Releasing HALT Mode by Interrupt

HALT
instruction Wait

Standby
release signal

Operating
mode HALT mode Wait Operating mode

Oscillation
Clock

Remarks 1. The broken lines indicate the case where the interrupt request that has released the
standby mode is acknowledged.
2. The wait time is as follows:
et4U.com • When vectored interrupt processing is performed: 9 to 10 clocks e
DataShe
• When vectored interrupt processing is not performed: 1 to 2 clocks
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(b) Releasing by non-maskable interrupt request
The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored
interrupt processing is performed.

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(c) Releasing by RESET input

When the HALT mode is released by the RESET signal, execution branches to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started.

Figure 16-3. Releasing HALT Mode by RESET Input

HALT
instruction WaitNote

RESET
signal
Oscillation
Operating Reset stabilization Operating
mode HALT mode period wait status mode
Oscillation
Oscillation stop Oscillation
Clock

Note In the µPD789104A and 789114A Subseries, 215/fX: 6.55 ms (at fX = 5.0-MHz operation)
In the µPD789124A and 789134A Subseries, 27/fCC: 32 µs (at fCC = 4.0-MHz operation)

Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

et4U.com Table 16-2. Operation after Release of HALT Mode e

DataShe

Releasing Source MK×× DataSheet4U.com

IE Operation
Maskable interrupt request 0 0 Executes next address instruction
0 1 Executes interrupt processing

1 × Retains HALT mode

Non-maskable interrupt request — × Executes interrupt processing
RESET input — — Reset processing

×: don’t care

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CHAPTER 16 STANDBY FUNCTION

16.2.2 STOP mode

(1) Setting and operation status of STOP mode

The STOP mode is set by executing the STOP instruction.

Cautions 1. When the STOP mode is set, the X2 or CL2 pin is internally pulled up to VDD to suppress
the current leakage of the oscillation circuit block. Therefore, do not use the STOP mode
in a system where the external clock is used as the system clock.
2. Because the standby mode can be released by an interrupt request signal, the standby
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait
time set by the oscillation stabilization time select register (OSTS) elapses, and then an
operation mode is set.

The operation status in the STOP mode is shown in the following table.

Table 16-3. STOP Mode Operating Status

Item STOP Mode Operating Status

Clock generator System clock oscillation stopped

CPU Operation stopped
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Port (Output latch) Retains the status before setting the STOP mode DataShe
16-bit timer 20 Operation stopped DataSheet4U.com
8-bit timer/event counter 80 Operable Note 1
Watchdog timer Operation stopped

Serial interface 20 Operable Note 2

A/D converter Operation stopped
Multiplier Operation stopped

External interrupt Operable Note 3

Notes 1. Operation is possible only when TI80 is selected as the count clock.
2. Operation is possible in both 3-wire serial I/O and UART modes while an external clock is being
used.
3. Maskable interrupt that is not masked

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CHAPTER 16 STANDBY FUNCTION

(2) Releasing STOP mode

The STOP mode can be released by the following two types of sources:

(a) Releasing by unmasked interrupt request

The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is able
to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time
has elapsed. If the interrupt is disabled, the instruction at the next address is executed.

Figure 16-4. Releasing STOP Mode by Interrupt

WaitNote
STOP (set time by OSTS)
instruction

Standby
release signal

Operating Oscillation stabilization Operating

mode STOP mode wait status mode
Oscillation
Oscillation stop Oscillation
Clock

Note OSTS is not provided in the µPD789124A and 789134A Subseries, and the wait time is fixed to
27/fCC.
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Remark The broken lines indicate the case where the interrupt request that has released the standby
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(b) Releasing by RESET input

When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.

Figure 16-5. Releasing STOP Mode by RESET Input

STOP
WaitNote
instruction

RESET
signal
Oscillation
Operating Reset stabilization Operating
mode STOP mode period wait status mode
Oscillation
Oscillation stop Oscillation
Clock

Note In the µPD789104A and 789114A Subseries, 215/fX: 6.55 ms (at fX = 5.0-MHz operation)
In the µPD789124A and 789134A Subseries, 27/fCC: 32 µs (at fCC = 4.0-MHz operation)

Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)

fCC: System clock oscillation frequency (RC oscillation)

et4U.com Table 16-4. Operation after Release of STOP Mode e

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Releasing Source MK×× IE DataSheet4U.com Operation
Maskable interrupt request 0 0 Executes next address instruction

0 1 Executes interrupt processing

1 × Retains STOP mode
RESET input — — Reset processing

×: don’t care

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CHAPTER 17 RESET FUNCTION

The following two operations are available to generate reset signals.

(1) External reset input with RESET pin

(2) Internal reset by program runaway time detection with watchdog timer

External and internal reset have no functional differences. In both cases, program execution starts at the addresses
0000H and 0001H by reset signal input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
item is set to the status shown in Table 17-1. Each pin has a high impedance during reset input or during the oscillation
stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation
stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset,
and program execution is started after the oscillation stabilization time has elapsed (see Figures 17-2 through 17-
4).

Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.
However, the port pins become high impedance.
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Figure 17-1. Block Diagram of Reset Function
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RESET Reset signal

Reset control circuit

Over-
flow Interrupt function
Count clock Watchdog timer

Stop

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CHAPTER 17 RESET FUNCTION

Figure 17-2. Reset Timing by RESET Input

X1, CL1
Reset period Oscillation
During normal Normal operation
(oscillation stabilization
operation (reset processing)
stops) time wait

RESET

Internal
reset signal

Delay Delay

Hi-Z
Port pin

Figure 17-3. Reset Timing by Overflow in Watchdog Timer

X1, CL1

Reset period Oscillation

During normal operation Normal operation
(oscillation stabilization
(reset processing)
continues) time wait
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Overflow in
watchdog timer
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Internal
reset signal

Hi-Z
Port pin

Figure 17-4. Reset Timing by RESET Input in STOP Mode

X1, CL1
STOP instruction execution
Stop status Reset period Oscillation Normal operation
During normal operation (oscillation (oscillation stabilization
stops) stops) time wait (reset processing)

RESET

Internal
reset signal

Delay Delay

Hi-Z
Port pin

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CHAPTER 17 RESET FUNCTION

Table 17-1. Hardware Status after Reset (1/2)

Hardware Status after Reset

Program counter (PC)Note 1 The contents of reset
vector tables (0000H and
0001H) are set.

Stack pointer (SP) Undefined

Program status word (PSW) 02H
RAM Data memory UndefinedNote 2

General register UndefinedNote 2

Port (P0 to P2, P5) (Output latch) 00H
Port mode register (PM0 to PM2, PM5) FFH

Pull-up resistor option register 0 (PU0) 00H

Pull-up resistor option register B2 (PUB2) 00H
Processor clock control register (PCC) 02H

Oscillation stabilization time select register (OSTS)Note 3 04H

16-bit timer 20 Timer counter (TM20) 0000H
Compare register (CR20) FFFFH

Mode control register (TMC20) 00H

Capture register (TPC20) Undefined

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Compare register (CR80) Undefined
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Mode control register (TMC80) 00H
Watchdog timer Timer clock select register (TCL2) 00H

Mode register (WDTM) 00H

A/D converter Mode register (ADM0) 00H
Input channel specification register (ADS0) 00H

Conversion result register (ADCR0) Undefined

Serial interface 20 Mode register (CSIM20) 00H
Asynchronous serial interface mode register (ASIM20) 00H

Asynchronous serial interface status register (ASIS20) 00H

Baud rate generator control register (BRGC20) 00H
Transmit shift register (TXS20) FFH

Receive buffer register (RXB20) Undefined

Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined.
All other hardware remains unchanged after reset.
2. If the reset signal is input in the standby mode, the status before reset is retained even after reset.
3. µPD789104A, 789114A Subseries only

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CHAPTER 17 RESET FUNCTION

Table 17-1. Hardware Status after Reset (2/2)

Hardware Status after Reset

Multiplier 16-bit multiplication result storage register (MUL0) Undefined

Data register A (MRA0) Undefined

Data register B (MRB0) Undefined
Control register (MULC0) 00H

Interrupt Request flag register (IF0, IF1) 00H

Mask flag register (MK0, MK1) FFH
External interrupt mode register (INTM0) 00H

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CHAPTER 18 µPD78F9116A, 78F9136A

The µPD78F9116A is a version with flash memory instead of the internal ROM of the mask ROM version in the
µPD789104A and 789114A Subseries. The µPD78F9136A is a version with flash memory instead of the internal ROM
of the mask ROM version in the µPD789124A and 789134A Subseries. The differences between the flash memory
and the mask ROM versions are shown in Table 18-1.

Table 18-1. Differences between Flash Memory and Mask ROM Versions

Item Flash Memory Mask ROM

µPD78F9116A µPD789101A µPD789102A µPD789104A
µPD789111A µPD789112A µPD789114A
µPD78F9136A µPD789121A µPD789122A µPD789124A
µPD789131A µPD789132A µPD789134A
Internal ROM 16 Kbytes 2 Kbytes 4 Kbytes 8 Kbytes
memory (flash memory)
High-speed RAM 256 bytes
Pull-up resistor 12 (software control only) 16 (software control: 12, mask option specification: 4)
VPP pin Provided Not provided
Electrical specifications Refer to the individual data sheets.
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Cautions 1. There are differences inDataSheet4U.com
noise immunity and noise radiation between the flash memory
versions and mask ROM versions. When pre-producing an application set with the flash
memory version and then mass-producing it with the mask ROM version, be sure to conduct
sufficient evaluations for the commercial samples (not engineering samples) of the mask
ROM versions.
2. A/D conversion result register 0 (ADCR0) is manipulated by an 8-bit memory manipulation
instruction or a 16-bit memory manipulation instruction, when used as an 8-bit A/D converter
(µPD789104A, 789124A Subseries) or 10-bit A/D converter (µPD789114A, 789134A Subseries),
respectively.
However, if the µPD78F9116A is used as the flash memory version of the µPD789101A,
789102A, 789104A, ADCR0 can be manipulated by an 8-bit memory manipulation instruction,
providing an object file has been assembled in the µPD789101A, 789102A, 789104A. If the
µPD78F9136A is used as the flash memory version of the µPD789121A, 789122A, 789124A,
ADCR0 can be manipulated by an 8-bit memory manipulation instruction, providing an object
file has been assembled in the µPD789121A, 789122A, 789124A.

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CHAPTER 18 µPD78F9116A, 78F9136A

18.1 Flash Memory Programming

The on-chip program memory in the µPD78F9116A, 78F9136A is flash memory.

The flash memory can be written with the µPD78F9116A mounted on the target system (on-board). Connect the
dedicated flash programmer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and target system
to write the flash memory.

Remark FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd.

18.1.1 Selecting communication mode

The flash memory is written by using Flashpro III and by means of serial communication. Select a communication
mode from those listed in Table 18-2. To select a communication mode, the format shown in Figure 18-1 is used.
Each communication mode is selected by the number of VPP pulses shown in Table 18-2.

Table 18-2. Communication Mode

Communication Mode Pins Used Number of VPP Pulses

3-wire serial I/O SCK20/ASCK20/P20 0
SO20/TxD20/P21
SI20/RxD20/P22
UART TxD20/SO20/P21 8
RxD20/SI20/P22

et4U.com Pseudo 3-wire mode Note P00 (Serial clock input) 12

e
P01 (Serial data output) DataShe
P02 (Serial data input)
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Note Serial transfer is performed by controlling a port by software.

Caution Be sure to select a communication mode based on the VPP pulse number shown in Table 18-2.

Figure 18-1. Communication Mode Selection Format

10 V

VPP VDD
1 2 n
VSS

VDD
RESET
VSS

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CHAPTER 18 µPD78F9116A, 78F9136A

18.1.2 Function of flash memory programming

By transmitting/receiving commands and data in the selected communication mode, operations such as writing
to the flash memory are performed. Table 18-3 shows the major functions of flash memory programming.

Table 18-3. Functions of Flash Memory Programming

Function Description
Batch erase Erases all contents of memory
Batch blank check Checks erased state of entire memory
Data write Write to flash memory based on write start address and number of data written (number of bytes)
Batch verify Compares all contents of memory with input data

18.1.3 Flashpro III connection example

Connection between the Flashpro III and the µPD78F9116A and 78F9136A differs depending on the communication
mode (3-wire serial I/O, UART, or pseudo 3-wire mode). Figures 18-2 to 18-4 show the connection examples in the
respective modes.

(a) Connection between µPD78F9116A and Flashpro III

Figure 18-2. Flashpro III Connection in 3-Wire Serial I/O Mode

et4U.com Flashpro III µ PD78F9116A e

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VPPnNote VPP
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VDD VDD, AVDD

RESET RESET

CLK X1

SCK SCK20

SO SI20

SI SO20

GND VSS, AVSS

Note n = 1, 2

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CHAPTER 18 µPD78F9116A, 78F9136A

Figure 18-3. Flashpro III Connection in UART Mode

Flashpro III µ PD78F9116A

VPPnNote VPP

VDD VDD, AVDD

RESET RESET

CLK X1

SO RxD20

SI TxD20
GND VSS, AVSS

Note n = 1, 2

Figure 18-4. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used)

Flashpro III µ PD78F9116A

VPPnNote VPP

VDD VDD, AVDD

RESET RESET
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SCK DataSheet4U.com P00 (Serial clock)
SO P02 (Serial input)

SI P01 (Serial output)

GND VSS, AVSS

Note n = 1, 2

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CHAPTER 18 µPD78F9116A, 78F9136A

(b) Connection between µPD78F9136A and Flashpro III

Figure 18-5. Flashpro III Connection in 3-Wire Serial I/O Mode

Flashpro III µ PD78F9136A

VPPnNote VPP

VDD VDD, AVDD

RESET RESET

CLK P03

SCK SCK20

SO SI20

SI SO20

GND VSS, AVSS

Note n = 1, 2

Figure 18-6. Flashpro III Connection in UART Mode

Flashpro III µ PD78F9136A

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VPPnNote VPP DataShe

VDD DataSheet4U.com VDD, AVDD

RESET RESET

CLK P03

SO RxD20

SI TxD20
GND VSS, AVSS

Note n = 1, 2

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CHAPTER 18 µPD78F9116A, 78F9136A

Figure 18-7. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used)

Flashpro III µ PD78F9136A

VPPnNote VPP

VDD VDD, AVDD

RESET RESET

CLK P03

SCK P00 (Serial clock)

SO P02 (Serial input)

SI P01 (Serial output)

GND VSS, AVSS

Note n = 1, 2

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CHAPTER 18 µPD78F9116A, 78F9136A

18.1.4 Example of settings for Flashpro III (PG-FP3)

Make the following setting when writing to flash memory using Flashpro III (PG-FP3).

<1> Load the parameter file.

<2> Select serial mode and serial clock using the type command.
<3> An example of the settings for the PG-FP3 is shown below.

Table 18-4. Example of Settings for PG-FP3

Communication Mode Example of Setting for PG-FP3 Number of VPP PulsesNote 1

3-wire serial I/O COMM PORT SIO-ch0 0
CPU CLK On Target Board
In Flashpro
On Target Board 4.1943 MHz
SIO CLK 1.0 MHz
In Flashpro 4.0 MHz
SIO CLK 1.0 MHz
UART COMM PORT UART-ch0 8
CPU CLK On Target Board
On Target Board 4.1943 MHz
UART BPS 9600 bpsNote 2
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Pseudo 3-wire COMM PORT Port A 12 DataShe
CPU CLK On Target Board
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In Flashpro
On Target Board 4.1943 MHz
SIO CLK 1.0 kHz
In Flashpro 4.0 MHz
SIO CLK 1.0 kHz

Notes 1. The number of VPP pulses supplied from Flashpro III when serial communication is initialized. The
pins to be used for communication are determined according to the number of these pulses.
2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps.

Remark COMM PORT: Selection of serial port

SIO CLK: Selection of serial clock frequency
CPU CLK: Selection of source of CPU clock to be input

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CHAPTER 19 MASK OPTION (MASK ROM VERSION)

Table 19-1. Selection of Mask Option for Pins

Pin Mask Option

P50 to P53 On-chip pull-up resistor can be specified in 1-bit units.

For P50 to P53 (port 5), an on-chip pull-up resistor can be specified by the mask option. The mask option is specified
in 1-bit units.

Caution The flash memory versions do not provide the on-chip pull-up resistor function.

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CHAPTER 20 INSTRUCTION SET

This chapter lists the instruction set of the µPD789104A/114A/124A/134A Subseries. For the details of the
operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User’s Manual
Instruction (U11047E).

20.1 Operation

20.1.1 Operand identifiers and description methods

Operands are described in “Operand” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description
methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described
as they are. Each symbol has the following meaning.

• #: Immediate data specification • $: Relative address specification

• !: Absolute address specification • [ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
et4U.com parenthesis in the table below, R0, R1, R2, etc.) can be used for description. e
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Table 20-1. Operand Identifiers and Description Methods

Identifier Description Method

r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
rp AX (RP0), BC (RP1), DE (RP2), HL (RP3)
sfr Special-function register symbol

saddr FE20H to FF1FH Immediate data or labels

saddrp FE20H to FF1FH Immediate data or labels (even addresses only)
addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
addr5 0040H to 007FH Immediate data or labels (even addresses only)
word 16-bit immediate data or label
byte 8-bit immediate data or label
bit 3-bit immediate data or label

Remark Refer to Table 4-3 Special Function Register List for symbols of special function registers.

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CHAPTER 20 INSTRUCTION SET

20.1.2 Description of “operation” column

A: A register; 8-bit accumulator

X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
IE: Interrupt request enable flag
NMIS: Flag indicating non-maskable interrupt servicing in progress
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×H, ×L : Higher 8 bits and lower 8 bits of 16-bit register
∧: Logical product (AND) DataSheet4U.com
∨: Logical sum (OR)
∨: Exclusive logical sum (exclusive OR)
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)

20.1.3 Description of “flag operation” column

(Blank): Unchanged
0: Cleared to 0
1: Set to 1
×: Set/cleared according to the result
R: Previously saved value is restored

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CHAPTER 20 INSTRUCTION SET

20.2 Operation List

Flag
Mnemonic Operands Byte Clock Operation
Z AC CY
MOV r,#byte 3 6 r ← byte
saddr,#byte 3 6 (saddr) ← byte
sfr,#byte 3 6 sfr ← byte
A,r Note 1
2 4 A←r
r,A Note 1
2 4 r←A
A,saddr 2 4 A ← (saddr)
saddr,A 2 4 (saddr) ← A
A,sfr 2 4 A ← sfr
sfr,A 2 4 sfr ← A
A,!addr16 3 8 A ← (addr16)
!addr16,A 3 8 (addr16) ← A
PSW,#byte 3 6 PSW ← byte × × ×
A,PSW 2 4 A ← PSW
PSW,A 2 4 PSW ← A × × ×
A,[DE] 1 6 A ← (DE)
[DE],A 1 6 (DE) ← A
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A,[HL] 1 6
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[HL],A 1 6 (HL) ← A
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A,[HL+byte] 2 6 A ← (HL+byte)
[HL+byte],A 2 6 (HL+byte) ← A
XCH A,X 1 4 A↔X
A,r Note 2 2 6 A↔r
A,saddr 2 6 A ↔ (saddr)
A,sfr 2 6 A ↔ sfr
A,[DE] 1 8 A ↔ (DE)
A,[HL] 1 8 A ↔ (HL)
A,[HL+byte] 2 8 A ↔ (HL+byte)

Notes 1. Except r = A.
2. Except r = A, X.

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control
Register (PCC).

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CHAPTER 20 INSTRUCTION SET

Flag
Mnemonic Operands Byte Clock Operation
Z AC CY
MOVW rp,#word 3 6 rp ← word
AX,saddrp 2 6 AX ← (saddrp)
saddrp,AX 2 8 (saddrp) ← AX
AX,rp Note 1 4 AX ← rp
rp,AX Note 1 4 rp ← AX
XCHW AX,rp Note 1 8 AX ↔ rp
ADD A,#byte 2 4 A,CY ← A + byte × × ×
saddr,#byte 3 6 (saddr),CY ← (saddr) + byte × × ×
A,r 2 4 A,CY ← A + r × × ×
A,saddr 2 4 A,CY ← A + (saddr) × × ×
A,!addr16 3 8 A,CY ← A + (addr16) × × ×
A,[HL] 1 6 A,CY ← A + (HL) × × ×
A,[HL+byte] 2 6 A,CY ← A + (HL+byte) × × ×
ADDC A,#byte 2 4 A,CY ← A+ byte + CY × × ×
saddr,#byte 3 6 (saddr),CY ← (saddr) + byte + CY × × ×
A,r 2 4 A,CY ← A + r + CY × × ×
A,saddr 2 4 A,CY ← A + (saddr) + CY × × ×

et4U.com A,!addr16 3 8 A,CY ← A + (addr16) + CY × × × e

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A,[HL] 1 6 A,CY ← A + (HL) + CY × × ×
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A,[HL+byte] 2 6 A,CY ← A + (HL+byte) + CY × × ×
SUB A,#byte 2 4 A,CY ← A – byte × × ×
saddr,#byte 3 6 (saddr), CY ← (saddr) – byte × × ×
A,r 2 4 A,CY ← A – r × × ×
A,saddr 2 4 A,CY ← A – (saddr) × × ×
A,!addr16 3 8 A,CY ← A – (addr16) × × ×
A,[HL] 1 6 A,CY ← A – (HL) × × ×
A,[HL+byte] 2 6 A,CY ← A – (HL+byte) × × ×

Note Only when rp = BC, DE, or HL.

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control
Register (PCC).

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CHAPTER 20 INSTRUCTION SET

Flag
Mnemonic Operands Byte Clock Operation
Z AC CY
SUBC A,#byte 2 4 A,CY ← A – byte – CY × × ×
saddr,#byte 3 6 (saddr),CY ← (saddr) – byte – CY × × ×
A,r 2 4 A,CY ← A – r – CY × × ×
A,saddr 2 4 A,CY ← A – (saddr) – CY × × ×
A,!addr16 3 8 A,CY ← A – (addr16) – CY × × ×
A,[HL] 1 6 A,CY ← A – (HL) – CY × × ×
A,[HL+byte] 2 6 A,CY ← A – (HL+byte) – CY × × ×
AND A,#byte 2 4 A ← A ∧ byte ×
saddr,#byte 3 6 (saddr) ← (saddr) ∧ byte ×
A,r 2 4 A←A∧r ×
A,saddr 2 4 A ← A ∧ (saddr) ×
A,!addr16 3 8 A ← A ∧ (addr16) ×
A,[HL] 1 6 A ← A ∧ (HL) ×
A,[HL+byte] 2 6 A ← A ∧ (HL+byte) ×
OR A,#byte 2 4 A ← A ∨ byte ×
saddr,#byte 3 6 (saddr) ← (saddr) ∨ byte ×
A,r 2 4 A←A∨r ×

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A,!addr16 3 8 A ← A ∨ (addr16) ×
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A,[HL] 1 6 A ← A ∨ (HL) ×
A,[HL+byte] 2 6 A ← A ∨ (HL+byte) ×
XOR A,#byte 2 4 A ← A ∨ byte ×
saddr,#byte 3 6 (saddr) ← (saddr) ∨ byte ×
A,r 2 4 A←A∨r ×
A,saddr 2 4 A ← A ∨ (saddr) ×
A,!addr16 3 8 A ← A ∨ (addr16) ×
A,[HL] 1 6 A ← A ∨ (HL) ×
A,[HL+byte] 2 6 A ← A ∨ (HL+byte) ×

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control
Register (PCC).

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CHAPTER 20 INSTRUCTION SET

Flag
Mnemonic Operands Byte Clock Operation
Z AC CY
CMP A,#byte 2 4 A – byte × × ×
saddr,#byte 3 6 (saddr) – byte × × ×
A,r 2 4 A–r × × ×
A,saddr 2 4 A – (saddr) × × ×
A,!addr16 3 8 A – (addr16) × × ×
A,[HL] 1 6 A – (HL) × × ×
A,[HL+byte] 2 6 A – (HL+byte) × × ×
ADDW AX,#word 3 6 AX,CY ← AX + word × × ×
SUBW AX,#word 3 6 AX,CY ← AX – word × × ×
CMPW AX,#word 3 6 AX – word × × ×
INC r 2 4 r←r+1 × ×
saddr 2 4 (saddr) ← (saddr) + 1 × ×
DEC r 2 4 r←r–1 × ×
saddr 2 4 (saddr) ← (saddr) – 1 × ×
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp – 1
ROR A,1 1 2 (CY,A7 ← A0, Am–1 ← Am) × 1 ×

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RORC A,1 1 2 (CY ← A0, A7 ← CY, Am–1 ← Am) × 1 ×
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ROLC A,1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 ×
SET1 saddr.bit 3 6 (saddr.bit) ← 1
sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW.bit ← 1 × × ×
[HL].bit 2 10 (HL).bit ← 1
CLR1 saddr.bit 3 6 (saddr.bit) ← 0
sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0 × × ×
[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 1 1
CLR1 CY 1 2 CY ← 0 0
NOT1 CY 1 2 CY ← CY ×

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control
Register (PCC).

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CHAPTER 20 INSTRUCTION SET

Flag
Mnemonic Operands Byte Clock Operation
Z AC CY
CALL !addr16 3 6 (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALLT [addr5] 1 8 (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP – 2
RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI 1 8 PCH ← (SP + 1), PCL ← (SP), R R R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
PUSH PSW 1 2 (SP – 1) ← PSW, SP ← SP – 1
rp 1 4 (SP – 1) ← rpH, (SP – 2) ← rpL, SP ← SP – 2
POP PSW 1 4 PSW ← (SP), SP ← SP + 1 R R R
rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
MOVW SP, AX 2 8 SP ← AX
AX, SP 2 6 AX ← SP
BR !addr16 3 6 PC ← addr16
$addr16 2 6 PC ← PC + 2 + jdisp8
AX 1 6 PCH ← A, PCL ← X
BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0
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BZ $saddr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1 DataShe
BNZ $saddr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0
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BT saddr.bit,$addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
sfr.bit,$addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit,$addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit,$addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1
BF saddr.bit,$addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit,$addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit,$addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit,$addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 0
DBNZ B,$addr16 2 6 B ← B – 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C,$addr16 2 6 C ← C – 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
saddr,$addr16 3 8 (saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP 1 2 No Operation
EI 3 6 IE ← 1 (Enable Interrupt)
DI 3 6 IE ← 0 (Disable Interrupt)
HALT 1 2 Set HALT Mode
STOP 1 2 Set STOP Mode

Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the Processor Clock Control
Register (PCC).

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CHAPTER 20 INSTRUCTION SET

20.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ

2nd Operand
#byte A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte] $addr16 1 None
1st Operand

A ADD MOVNote MOV MOV MOV MOV MOV MOV MOV ROR
ADDC XCHNote XCH XCH XCH XCH XCH ROL
SUB ADD ADD ADD ADD ADD RORC
SUBC ADDC ADDC ADDC ADDC ADDC ROLC
AND SUB SUB SUB SUB SUB
OR SUBC SUBC SUBC SUBC SUBC
XOR AND AND AND AND AND
CMP OR OR OR OR OR
XOR XOR XOR XOR XOR
CMP CMP CMP CMP CMP

r MOV MOV INC

DEC

B, C DBNZ

sfr MOV MOV

saddr MOV MOV DBNZ INC

ADD DEC
ADDC
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AND
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OR
XOR
CMP

!addr16 MOV

PSW MOV MOV PUSH

POP

[DE] MOV

[HL] MOV

[HL+byte] MOV

Note Except r = A.

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CHAPTER 20 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand
#word AX rpNote saddrp SP None
1st Operand
AX ADDW MOVW MOVW MOVW
SUBW XCHW
CMPW
rp MOVW MOVWNote INCW
DECW
PUSH
POP
saddrp MOVW
SP MOVW

Note Only when rp = BC, DE, or HL.

(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF

2nd Operand
$addr16 None
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A.bit BT SET1
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BF CLR1
sfr.bit BT SET1
BF CLR1
saddr.bit BT SET1
BF CLR1
PSW.bit BT SET1
BF CLR1
[HL].bit SET1
CLR1
CY SET1
CLR1
NOT1

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CHAPTER 20 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ

2nd Operand
AX !addr16 [addr5] $addr16
1st Operand
Basic Instructions BR CALL CALLT BR
BR BC
BNC
BZ
BNZ
Compound Instructions DBNZ

(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

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APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for the development of systems that employ the µPD789104A/114A/
124A/134A Subseries.
Figure A-1 shows the development tool configuration.

• Support of the PC98-NX Series

Unless otherwise specified, the µPD789104A/114A/124A/134A Subseries supported by IBM PC/AT™ and
compatibles can be used for the PC98-NX Series. When using the PC98-NX Series, refer to the descriptions
of the IBM PC/AT and compatibles.

• Windows
Unless otherwise specified, “Windows” indicates the following OSs.
Windows 3.1
Windows 95
Windows NT™ Ver. 4.0

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tool Configuration

Language processing software

• Assembler package Embedded software
• C compiler package
• OS
• System simulator
• Device file
• C compiler source file
• Integrated debugger

Host machine (PC or EWS)

Interface adapter

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In-circuit emulator
Flash programmer

Emulation board Power supply unit

Flash memory
write adapter

Flash memory Emulation probe

Conversion socket

Target system

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APPENDIX A DEVELOPMENT TOOLS

A.1 Language Processing Software

RA78K0S A program that converts a program written in mnemonic into object codes that can
Assembler package be executed by microcontrollers.
In addition, automatic functions to generate symbol tables and optimize branch
instructions are also provided.
Used in combination with a device file (DF789136) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler
package).
Part number: µS××××RA78K0S
CC78K0S A program that converts a program written in C language into object codes that can
C compiler package be executed by microcontrollers.
Used in combination with an assembler package (RA78K0S) and device file
(DF789136) (both sold separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler
package).
Part number: µS××××CC78K0S
DF789136Note File containing the information inherent to the device.
Device file Used in combination with RA78K0S, CC78K0S, and SM78K0S (all sold separately).
Part number: µS××××DF789136
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CC78K0S-L Source file of functions for generating the object library included in the C compiler
C compiler source file package.
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Necessary for changing the object library included in the C compiler package
according to customerís specifications. Since this is a source file, its working
environment does not depend on any particular operating system.
Part number: µS××××CC78K0S-L

Note DF789136 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S.

Remark ×××× in the part number differs depending on the host machine and operating system to be used.

µS××××RA78K0S
µS××××CC78K0S
µS××××DF789136
µS××××CC78K0S-L

×××× Host Machine OS Supply Media

AA13 PC-9800 Series Japanese WindowsNote 3.5" 2HD FD
AB13 IBM PC/AT and compatibles Japanese WindowsNote 3.5" 2HC FD
3P16 HP9000 Series 700™ HP-UX™ (Rel.10.10) DAT (DDS)
3K13 SPARCstation™ SunOS™ (Rel.4.1.1) 3.5" 2HC FD
3K15 Solaris™ (Rel.2.5.1) 1/4" CGMT
3R13 NEWS™ (RISC) NEWS-OS™ (Rel.6.1) 3.5" 2HC FD

Note Also operates in the DOS environment

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APPENDIX A DEVELOPMENT TOOLS

A.2 Flash Memory Writing Tools

Flashpro III Dedicated flash programmer for microcontrollers incorporating flash memory
(Part No. FL-PR3, PG-FP3)
Flash programmer
FA-30MC Adapter for writing to flash memory and connected to Flashpro III.
Flash memory writing adapter • FA-30MC: for 30-pin plastic SSOP (MC-5A4 type)

Remark The FL-PR3 and FA-30MC are products made by Naito Densei Machida Mfg. Co., Ltd.
(TEL +81-44-822-3813).

A.3 Debugging Tools

A.3.1 Hardware

IE-78K0S-NS In-circuit emulator for debugging the hardware and software of an application system using
In-circuit emulator the 78K/0S Series. Supports an integrated debugger (ID78K0S-NS). Used in combination
with an AC adapter, emulation probe, and interface adapter for connecting the host machine.
IE-70000-MC-PS-B Adapter for supplying power from an AC 100 to 240 V outlet.
AC adapter
IE-70000-98-IF-C Adapter necessary when using a PC-9800 series PC (except notebook type) as the host
Interface adapter machine of the IE-78K0S-NS (C bus supported)
IE-70000-CD-IF-A PC card and interface cable necessary when using a notebook PC as the host machine of

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IE-70000-PC-IF-C Interface adapter necessary when using an IBM PC/AT or compatible as the host machine
Interface adapter DataSheet4U.com
of the IE-78K0S-NS (ISA bus supported)
IE-70000-PCI-IF Adapter necessary when using a personal computer incorporating the PCI bus as the host
Interface adapter machine of the IE-78K0S-NS
IE-789136-NS-EM1 Board for emulating the peripheral hardware inherent to the device. Used in combination with
Emulation board an in-circuit emulator.
NP-36GS Probe for connecting the in-circuit emulator and target system.
Emulation probe This is for a 30-pin plastic SSOP (MC-5A4 type).
NGS-30 Conversion socket to connect the NP-36GS and a target system board on which a 30-pin
Conversion socket plastic SSOP (MC-5A4 type) can be mounted.

Remark The NP-36GS, and NGS-30 are products made by Naito Densei Machida Mfg. Co., Ltd. For details of
these products, contact Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813).

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APPENDIX A DEVELOPMENT TOOLS

A.3.2 Software

ID78K0S-NS Control program for debugging the 78K/0S Series.

Integrated debugger This program provides a graphical user interface. It runs on Windows for personal computer
(Supports in-circuit emulator users and on OSF/Motif™ for engineering work station users, and has visual designs and
IE-78K0S-NS) operationability that comply with these operating systems. In addition, it has a powerful debug
function that supports C language. Therefore, trace results can be displayed at a C language
level by the window integration function that links the source program, disassembled display,
and memory display, to the trace result. This software also allows users to add other function
extension modules such as a task debugger and system performance analyzer to improve
the debug efficiency for programs using a real-time operating system.
Used in combination with a device file (DF789136) (sold separately).
Part number: µS××××ID78K0S-NS

Remark ×××× in the part number differs depending on the host machine and operating system to be used.

µS××××ID78K0S-NS

×××× Host Machine OS Supply Media

AA13 PC-9800 Series Japanese WindowsNote 3.5" 2HD FD
AB13 IBM PC/AT compatibles Japanese WindowsNote 3.5" 2HC FD

Note Also operates in the DOS environment.

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SM78K0S DataSheet4U.com
Debugs the program at C source level or assembler level while simulating operation of the
System simulator target system on the host machine.
SM78K0S runs in Windows.
By using SM78K0S, the logic and performance of an application can be verified independently
of hardware development even when the in-circuit emulator is not used. This enhances
development efficiency and improves software quality.
Used in combination with a device file (DF789136) (sold separately).
Part number: µS××××SM78K0S
DF789136Note File containing the information inherent to the device.
Device file Used in combination with the RA78K0S, CC78K0S, and SM78K0S (all sold separately).
Part number: µS××××DF789136

Note DF789136 is a common file that can be used with the RA78K0S, CC78K0S, and SM78K0S.

Remark ×××× in the part number differs depending on the host machine and operating system to be used.

µS××××SM78K0S

×××× Host Machine OS Supply Media

AA13 PC-9800 Series Japanese WindowsNote 3.5" 2HD FD
AB13 IBM PC/AT compatibles Japanese WindowsNote 3.5" 2HC FD

Note Also operates in the DOS environment.

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APPENDIX B EMBEDDED SOFTWARE

The following embedded software products are available for efficient program development and maintenance of
the µPD789104A/114A/124A/134A Subseries.

MX78K0S MX78K0S is a subset OS that is based on the µITRON specification. Supplied with the MX78K0S
OS nucleus. The MX78K0S OS controls tasks, events, and time. In task control, the MX78K0S OS
controls task execution order, and then perform the switching process to a task to be executed.
<Caution when used in a PC environment>
The MX78K0S is a DOS-based application. Use this software in the DOS pane when running it on
Windows.
Part number: µS××××MX78K0S

Remark ×××× in the part number differ depending on the host machine and OS used.

µS××××MX78K0S

×××× Host Machine OS Supply Media

AA13 PC-9800 Series Japanese WindowsNote 3.5" 2HD FD
AB13 IBM PC/AT compatibles Japanese WindowsNote 3.5" 2HD FD

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Can also be operated in the DOS environment.

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APPENDIX C REGISTER INDEX

C.1 Register Name Index (Alphabetic Order)

8-bit compare register 80 (CR80) ................................................................................................................ 117

8-bit timer mode control register 80 (TMC80) ............................................................................................. 118
8-bit timer counter 80 (TM80) ...................................................................................................................... 117
16-bit compare register 20 (CR20) .............................................................................................................. 106
16-bit multiplication result storage register 0 (MUL0) ................................................................................. 199
16-bit timer capture register 20 (TCP20) ..................................................................................................... 106
16-bit timer mode control register 20 (TMC20) ........................................................................................... 107
16-bit timer counter 20 (TM20) .................................................................................................................... 106

[A]
Asynchronous serial interface mode register 20 (ASIM20) ............................................... 168, 175, 178, 190
Asynchronous serial interface status register 20 (ASIS20) ................................................................ 170, 179
A/D conversion result register 0 (ADCR0) ................................................................................................... 136
A/D converter mode register 0 (ADM0) ....................................................................................................... 138
Analog input channel specification register 0 (ADS0) ................................................................................ 139

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Baud rate generator control register 20 (BRGC20) ................................................................... 171, 180, 191
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[E]
External interrupt mode register 0 (INTM0) ................................................................................................. 209

[I]
Interrupt mask flag register 0 (MK0) ............................................................................................................ 208
Interrupt mask flag register 1 (MK1) ............................................................................................................ 208
Interrupt request flag register 0 (IF0) ........................................................................................................... 207
Interrupt request flag register 1 (IF1) ........................................................................................................... 207

[M]
Multiplication data register A0 (MRA0) ........................................................................................................ 199
Multiplication data register B0 (MRB0) ........................................................................................................ 199
Multiplier control register 0 (MULC0) ........................................................................................................... 201

[O]
Oscillation stabilization time select register (OSTS) ................................................................................... 220

[P]
Port 0 (P0) ....................................................................................................................................................... 75
Port 1 (P1) ....................................................................................................................................................... 76
Port 2 (P2) ....................................................................................................................................................... 77
Port 5 (P5) ....................................................................................................................................................... 81
Port 6 (P6) ....................................................................................................................................................... 82
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APPENDIX C REGISTER INDEX

Port mode register 0 (PM0) ............................................................................................................................ 83

Port mode register 1 (PM1) ............................................................................................................................ 83
Port mode register 2 (PM2) ........................................................................................................... 83, 109, 119
Port mode register 5 (PM5) ............................................................................................................................ 83
Processor clock control register (PCC) ................................................................................................... 88, 96
Pull-up resistor option register 0 (PU0) ......................................................................................................... 84
Pull-up resistor option register B2 (PUB2) .................................................................................................... 84

[R]
Receive buffer register 20 (RXB20) ............................................................................................................. 166

[S]
Serial operating mode register 20 (CSIM20) ...................................................................... 167, 174, 177, 189

[T]
Timer clock select register 2 (TCL2) ............................................................................................................ 131
Transmit shift register 20 (TXS20) ............................................................................................................... 166

[W]
Watchdog timer mode register (WDTM) ...................................................................................................... 132

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APPENDIX C REGISTER INDEX

C.2 Register Symbol Index (Alphabetic Order)

[A]
ADCR0: A/D conversion result register 0 ................................................................................................ 136
ADM0: A/D converter mode register 0 .................................................................................................. 138
ADS0: Analog input channel specification register 0 ........................................................................... 139
ASIM20: Asynchronous serial interface mode register 20 ............................................. 168, 175, 178, 190
ASIS20: Asynchronous serial interface status register 20 .............................................................. 170, 179

[B]
BRGC20: Baud rate generator control register 20 ................................................................... 171, 180, 191

[C]
CR20: 16-bit compare register 20 ......................................................................................................... 106
CR80: 8- bit compare register 80 .......................................................................................................... 117
CSIM20: Serial operating mode register 20 .................................................................... 167, 174, 177, 189

[I]
IF0: Interrupt request flag register 0 ................................................................................................. 207
IF1: Interrupt request flag register 1 ................................................................................................. 207
INTM0: External interrupt mode register 0 ............................................................................................. 209

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MK0: Interrupt mask flag register 0 ..................................................................................................... 208
MK1: DataSheet4U.com
Interrupt mask flag register 1 ..................................................................................................... 208
MRA0: Multiplication data register A0 ................................................................................................... 199
MRB0: Multiplication data register B0 ................................................................................................... 199
MUL0: 16-bit multiplication result storage register 0 ............................................................................ 199
MULC0: Multiplier control register 0 ........................................................................................................ 201

[O]
OSTS: Oscillation stabilization time select register .............................................................................. 220

[P]
P0: Port 0 ............................................................................................................................................ 75
P1: Port 1 ............................................................................................................................................ 76
P2: Port 2 ............................................................................................................................................ 77
P5: Port 5 ............................................................................................................................................ 81
P6: Port 6 ............................................................................................................................................ 82
PCC: Processor clock control register ............................................................................................ 88, 96
PM0: Port mode register 0 .................................................................................................................... 83
PM1: Port mode register 1 .................................................................................................................... 83
PM2: Port mode register 2 ................................................................................................... 83, 109, 119
PM5: Port mode register 5 .................................................................................................................... 83
PU0: Pull-up resistor option register 0 ................................................................................................. 84
PUB2: Pull-up resistor option register B2 ............................................................................................... 84

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APPENDIX C REGISTER INDEX

[R]
RXB20: Receive buffer register 20 .......................................................................................................... 166

[T]
TCL2: Timer clock select register 2 ...................................................................................................... 131
TCP20: 16-bit timer capture register 20 ................................................................................................. 106
TM20: 16-bit timer counter 20 ............................................................................................................... 106
TM80: 8-bit timer counter 80 ................................................................................................................. 117
TMC20: 16-bit timer mode control register 20 ........................................................................................ 116
TMC80: 8-bit timer mode control register 80 .......................................................................................... 118
TXS20: Transmit shift register 20 ........................................................................................................... 166

[W]
WDTM: Watchdog timer mode register .................................................................................................. 132

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to our customers is complete, bug free
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