6th Semester BE (CBCS) EC/TC Model Question Papers

15EC61
Visvesvaraya Technological University, Belagavi

MODEL QUESTION PAPER

6th Semester, B.E (CBCS) EC/TC

Course: 15EC61 - Digital Communication

Max Marks: 80 Time: 3 Hours

Note: (i) Answer Five full questions selecting any one full question from each Module.

(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.

Module 1
1 (a) Define Hilbert Transform. State the properties of it. 4
(b) Define the complex envelope of bandpass signals. Obtain the canonical representation 6
of bandpass signals
(c) Derive the power spectral density of polar NRZ signals and plot the spectrum. 6
OR
2 (a) Define the Pre-envelope. Show the spectral representations of pre-envelopes for low 4
pass signals.
(b) Derive the expression for the complex low pass representation of bandpass systems. 7
(c) Given the data stream 1110010100. Sketch the transmitted sequence of pulses for 5
each of the following line code.
(i) Unipolar NRZ (ii) Polar NRZ (iii) Unipolar RZ (iv) bipolar RZ (v) Manchester
code.
Module 2
3 (a) Explain the Geometric representation of signals and express the energy of the signal 5
in terms of the signal vector.
(b) Explain the Gram-Schmidt orthogonalization procedure. 5
(c) Explain the matched filter receiver with the relevant mathematical theory. 6
OR
4 (a) Obtain the decision rule for Maximum likelihood decoding and explain the correlation 7
receiver.
(b) The waveforms of four signals s1(t), s2(t), s3(t), and s4(t) described below. 9
s1(t) = 1, 0 < t < T/3,
s2(t) = 1, 0 < t < 2T/3,
s3(t) = 1, T/3 < t < T,
 s4(t) = 1, 0 < t < T, and zero otherwise.
Using the Gram-Schmidt orthogonalization procedure, find an orthonormal basis for
this set of signals and construct the corresponding signal-space diagram.
Module 3
5 (a) Define binary phase shift keying. Derive the probability of error of BPSK. 7
(b) Define M-ary QAM. Obtain the constellation of QAM for M=4 and draw the signal 4
space diagram
(c) Given the input binary sequence 1100100001. Sketch the waveforms of the inphase 5
and quadrature components of a modulated wave and next sketch the QPSK signal.
OR
6 (a) Describe the QPSK signal with its signal space characterization. With a neat block 6
diagram explain the generation and detection of QPSK signals.
(b) Obtain the expression probability of symbol error of coherent binary FSK. 7
(c) Illustrate the operation of DPSK for the binary sequence 10010011 3
Module 4
7 (a) With a neat block diagram Explain the digital PAM transmission through bandlimited 5
baseband channels and obtain the expression for ISI.
(b) What are adaptive equalizers? Explain the linear adaptive equalizer based on the MSE 6
criterion.
(c) The binary sequence 10010110010 is the input to the precoder whose output is used to 5
modulate a duobinary transmitting filter. Obtain the precoded sequence, transmitted
amplitude levels, the received signal levels and the decoded sequence.
OR
8 (a) What is eye pattern? What is the Nyquist criterion for zero ISI? Given an example of 5
the pulse with zero ISI.
(b) Explain the design of bandlimited signals with controlled ISI. Describe the time 5
domain and frequency domain characteristics of a duobinary signal.
(c) What is channel equalization? With a neat diagram explain the concept of 6
equalization using a linear transversal filter.
Module 5
9 (a) Draw the 4 stage linear feedback shift register with 1st and 4th stage is connected to 6
Modulo-2 adder. Output of Modulo-2 is connected to 1st stage input. Find the output
PN sequence and obtain the autocorrelation sequence.
(b) With a neat block diagram explain the frequency hopped spread spectrum. 7
(c) Explain the effect of dispreading on narrowband interference. 3
OR
10 (a) Explain the generation of direct sequence spread spectrum signal with the relevant 6
waveforms and spectrums.
(b) With a neat block diagram explain the CDMA system based on IS-95. 7
(c) Write a short note on application of spread spectrum in wireless LANs. 3
 15EC62

Visvesvaraya Technological University, Belagavi

MODEL QUESTION PAPER – Set I
VI Semester, B.E (CBCS) EC/TC
Course: 15EC62 - ARM Microcontroller and Embedded Systems

Note: (i) Answer Five full questions selecting any one full question from each
Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and
2nd question.

Time: 3 hrs Max. Marks: 80

MODULE – 1
1 a Briefly describe the functions of the various units with the architectural block 6
diagram of ARM Cortex M3.
b Explain the applications of Cortex M3. 3
c Discuss the functions of R0 to R15 and other special registers in Cortex M3. 7
OR
2 a Describe the functions of exceptions with a vector table and priorities. 6
b Explain the operation modes of Cortex M3 with diagrams. 3
c Explain two stack model and reset sequence in ARM cortex M3. 7
MODULE -2
3 a Explain the following 16 bit instructions in Cortex M3: ADC, RSB, TST, BL, 7
LDR, MOV, SVC, PUSH
b Write an ALP to find the sum of first 10 integer numbers. 4
c Write the memory map of Cortex M3 and explain briefly bit-band operations. 5
OR
4 a Explain the following 32 bit instructions in Cortex M3: AND, CMN, MLA, 8
SDIV, STR, MRS, MRS, POP
b Write a C language program to toggle an LED with a small delay in Cortex M3. 4
c With a diagram, explain the organization of CMSIS. 4
MODULE - 3
5 a Explain the 6 purposes of Embedded systems with an example for each. 6

b Differentiate between (i) General Computing Systems and Embedded Systems and 4
(ii) RISC and CISC architectures
c Explain the 3 classifications of Embedded systems based on complexity and 3
performance.
d Mention the applications of Embedded systems with an example for each. 3
OR
6 a Explain the functions of Optocoupler and SPI bus with diagrams. 6
b Write a note on Embedded firmware. 4
c Explain SRAM design and features with a diagram. 3
 d Write the architectural block diagram of embedded system and mention the 3
components used.
MODULE – 4
7 a Explain the 6 operational quality attributes of an embedded systems. 5
b Define the 6 characteristics of an embedded system. 5

c With a block diagram, mention the components used in the design of a washing 6
machine and also explain its working.
OR
8 a Compare DFG and CDFG with an example and diagrams. 4
With FSM model, explain the design and operation of automatic tea/coffee
b vending machine. 5

c Explain the assembly language based embedded firmware development with a 7

diagram and mention its advantages and disadvantages.
MODULE – 5
9 a Briefly explain the functions of the operating system, with a diagram. 4
Describe preemptive SJF scheduling. Determine average turn around time and
b average waiting time, if processes P1 P2 and P3 with estimated completion time of 5
10, 5, 7 milliseconds enter ready queue together and later P4 with a completion
time of 2 msec enters ready queue after 2 msec.

c With a state transition diagram, structure and memory organization of a 7

process, describe the process state transitions.
OR
10 a Explain out of circuit and in-system programming methods for integration of 5
hardware and firmware.

b With a diagram, mention the function of the components in an embedded system 5

development environment.
c Explain simulator based debugging and ICE based target debugging techniques. 6

Note: In the updated syllabus ‘Bus Interface’ topic in Module-2 has been replaced with
‘Bit-band operations.
*************
 15EC62
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set II
6th Semester, B.E (CBCS) ECE
Course: 15EC62- ARM Microcontroller and Embedded Systems

Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.

Module-1 Marks
1 a Explain the architecture of ARM Cortex-M3 processor with the help of a neat block 10M
diagram.

b List the applications of ARM Cortex-M3 processor. 06M

OR
2 a Explain ARM Cortex-M3 Program Status Register in detail. 08M

b Explain Stack PUSH and POP operation in Cortex-M3 with the help of a neat diagram. 04M

c Explain reset sequence with the help of memory map. 04M

Module-2
3 a Explain the following instructions with example 08M
i)ASR ii)LSL iii)ROR iv)REV

b List and explain the function of any four data processing and branch instructions in 08M
Cortex- M3 with example.
OR
4 a Write a note on the interface between assembly and C. 04M

b Explain any two methods of accessing memory mapped registers in C. 08M

c List and explain the function of any four commonly used memory access instructions
in Cortex- M3 04M
Module-3
5 a Explain the components of typical Embedded Systems in detail. 08M

b Give the memory classification. Explain the SRAM cell implementation with relevant
 figures. 08M
OR
6 a Explain the different on-board communication interfaces in brief. 08M

b Differentiate between computer system and an Embedded System. 08M

Module-4
7 a Explain the different characteristics of Embedded System in detail. 08M

b What is operational quality attribute? Explain the important non- operational quality
attributes to be considered in any Embedded System design. 08M
OR
8 a Explain the different Embedded firmware design approaches in detail. 08M

b What is Hardware and Software co-design? Explain the fundamental design

approaches in detail. 08M
Module-5
9 a Explain Multi processing, multi tasking and multi programming. 08M

b What the basic functions of real time kernel? Explain each 08M
OR
10 a Explain the Simulator and Emulator. 08M

b Explain the terms process, task and thread 08M

Note: In the updated syllabus ‘Bus Interface’ topic in Module-2 has been replaced with
‘Bit-band operations’.

*********
 15EC63

Visvesvaraya Technological University, Belagavi

MODEL QUESTION PAPER- Set I
6th Semester, B.E (CBCS) ECE
Course: 15EC63- VLSI DESIGN
Time: 3 Hours Max. Marks: 80

Note: (i) Answer five full questions selecting any one full question from each Module.

(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.

Module-1 Marks
a What do you mean by static load inverters? Derive the output voltage for pseudo 8
1 Inverter by discussing its dc characteristics.
b Derive the CMOS inverter DC characteristics graphically from p device and n device 8
characteristics and show all operating regions.
OR
a Explain the nMOS enhancement mode transistor operation for different values of Vgs 6
2 and Vds .
b Explain the fabrication steps of CMOS p-well process with neat diagram and write the 6
mask sequence.
c What are the advantages of BiCMOS process over CMOS technology. 4

Module-2
a Explain λ based design rules with neat diagram. 6
3
b Draw the circuit and stick diagram for nMOS and CMOS implementation of Boolean 10
expression = +
OR
4 a Calculate the capacitance in □Cg for the given metal layer shown in the Fig Q4(a), if
feature size=5µm and relative value of metal to substrate =0.075.

Fig Q4(a)

b Define sheet resistance Rs and standard unit of capacitance (□Cg). Calculate the on 8
resistance of 4:1 nMOS inverter with Rs=10kΩ/□, Zpu=8λ/2λ, Zpd=2λ/2λ. Also
 estimate the total power dissipated if VDD=5V.
Module-3
a Find the scaling factors for: 8
i) Saturation current
ii) Current density
iii) Power dissipation/unit area
5 iv) Maximum operating frequency

b Design a 4 bit ALU to implement addition, subtraction, EX-OR, EX-NOR, OR and 8

AND operations.
OR
a With a neat diagram, explain 4x4 barrel shifter. 8
6
b Describe Manchester Carry-chain. 8
Module-4
a Discuss the architectural issues related to subsystem. 8
7
b Explain Pseudo nMOS logic for NAND gate and Inverter. 8
OR
a Explain Parity generator with basic block diagram and stick diagram. 8
8
b Explain FPGA architectures. 8
Module-5
a Explain 3 transistor dynamic RAM cell. 8
9
b Write a note on testability and testing. 8
OR
a Explain the scan design techniques. 8
10
b Demonstrate write operation & read operation for four transistor dynamic and six 8
transistor static CMOS memory cell.

**********
 15EC63
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER –Set II
6th Semester, B.E (CBCS) EC
Course: 15EC63- VLSI DESIGN
Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.

Module-1 Marks
1 (a) With Suitable diagrams explain the three regions of operation of Enhancement 7
mode NMOS transistor.
(b) Using graphical approach explain the DC characteristics of a CMOS inverter. 5
(c) Differentiate between CMOS and Bipolar technologies. 4
OR
2 (a) With neat sketches explain the CMOS P-well process steps to fabricate a CMOS 6
(b) inverter. 6
Derive a first order expression relating the current and voltage (I-V) for an NMOS
(c) transistor 4
in Linear region.
Explain only two non ideal I-V effects in a MOS device.
Module-2
3 (a) What do you mean by λ-based design rules? List the λ-based design rules for CMOS 7
(b) Technology. 9
Draw the schematic, stick diagram and layout for a CMOS NAND gate.
OR
4 (a) Derive the expression for sheet resistance Rs. 4
(b) Calculate the capacitance of the structure given below in Figure 4(b) 6

Figure 4(b)
(c) Derive an expression for the estimation of CMOS inverter Delay.
6
Module-3
5 (a) Obtain the scaling factor for the following device parameters: 8
(I) Gate Capacitance (II) Gate Area (III) Saturation Current (Idss) (IV) Channel
Resistance (Ron) (V) Max Operating Frequency (fo) (VI) Power Dissipation
per gate (Pg) (VII) Current density (J)
(b) (VIII) Gate delay (Td). 8
With a neat diagram explain 4x4 Barrel shifter.
OR
6 (a) Explain the general arrangement of a 4 bit ALU. 8
(b) Explain in detail any One Adder Enhancement technique. 8
Module-4
7 (a) Discuss the architectural issues to be followed in the design of a VLSI subsystem. 5
(b) Explain in detail the Generic Structure of an FPGA fabric. 7
(c) Explain switch logic implementation of a 4x4 four way multiplexer. 4
OR
8 (a) Explain the Structured Design approach for the implementation of a Parity Generator 8
with
(b) relevant stick diagram. 8
Explain Dynamic CMOS logic with an example.
Module-5
9 (a) Explain 3-Transistor Dynamic RAM cell with Schematic and stick diagram. 6
(b) 4
(c) List the System timing Considerations. 6

Explain any two fault models in combinational circuits.

OR
10 (a) Explain Pseudo-Static RAM cell (CMOS) with schematic and stick diagram. 8
(b) Write short notes on 8
I) Observability and Controllability
II) Built in Self Test (BIST)
 15EC64
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set I
6th Semester, B.E (CBCS) EC/TC
Course: 15EC64– Computer Communication Networks

Time: 3 Hours Max Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or 2nd question.

Module 1

1 (a) Explain the significance of all layers in TCP/IP protocol suite 8

(b) Distinguish Character stuffing and Bit stuffing, with an example 4

(c) Explain four Physical Topologies. 4

OR

2 (a) Discuss the FSM for stop and wait protocol in detail using suitable example 8

(b) Write the format of an ARP packet, and show how ARP sends request and response 8
message with suitable example

Module 2

3 (a) Discuss the behavior of the three persistence methods of CSMA with flow diagram 8

(b) Explain token passing as a controlled aces technique 4

(c) A slotted ALOHA network transmits 200 bit frame on a shared channel of 200 kbps. 4
What is the throughput if the system (all stations together) produces
 (i)1000 frames per second (ii) 500 frames per second (iii)250 frames per second

OR

4 (a) Explain the IEEE frame format of standard Ethernet 6

(b) Explain the standard Ethernet physical layer implementation of (i)10base 2 (ii)10base5 4

(c) With a neat diagram, explain Gigabit Ethernet encoding scheme. 6

Module 3

5 (a) Discuss the characteristics of wireless LAN protocol. 4

(b) Describe the characteristics of VLAN used to group stations and explain them briefly 6

(c) Explain spanning tree algorithm with graphical representation 6

OR

6 (a) Explain the two different approaches of Packet-switched network to route the packet. 8

(b) An organization is granted a block of addresses with the beginning address 8

14.24.74.0/24. The organization needs to have 3 subblocks of addresses to use in its
three subnets: one subblock of 10 addresses, one subblock of 60 addresses, and one
subblock of 120 addresses. Design the subblocks.

Module 4

7 (a) Explain IPv4 datagram format. 8

(b) Explain three phases of Remote host and Mobile host communication 8

OR
8 (a) Explain the operation of External and Internal Border Gateway Protocol 8

(b) Explain Least cost tree using shared link state database with suitable example 8

Module 5

9 (a) Explain connectionless and connection-oriented service represented as FSMs for 8

transport layer

(b) Write outline and explain send window and receive window for selective repeat 8
protocol

OR

10 (a) What are the different TCP services and features? Explain them 8

(b) Explain TCP connection establishment and connection termination using three way 8
handshaking

Note: In the updated syllabus, in Module-3, Routers has been added along with the
Switches.
***************
 15EC64
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set II
6th Semester, B.E (CBCS) EC/TC
Course: 15EC64- Computer Communication Networks
Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a Explain with neat diagrams the basic topologies for a network 06
b Explain with neat diagram the logical connection between layers and its function of 05
TCP/IP Protocol suits.
c Illustrate with an example two types of framing 05
OR
2 a Explain circuit switched and packet switched network 05
b Compare OSI with TCP/IP 06
c Explain ARP operation 05
Module-2
3 a With neat diagrams , Explain persistence methods in CSMA 06
b With neat diagram , Explain Ethernet frame format . 05
c A pure ALOHA network transmits 200 bit Frames on a shared channel of 200kbps. What is 05
the throughput if system produces : (i) 1000 Frames per sec (ii) 250 Frames per sec
OR
4 a Describe polling and Token passing in controlled Access method 06
b Write short notes on 10 Base5 thick Ethernet, 10 Base 2 thin Ethernet 05
c A slotted ALOHA Network transmits 200bit Frames using a shared channel with a 200kbps 05
bandwidth. Find the throughput if the system produces: (i) 1000 Frames per sec (ii) 250
Frames per sec
Module-3
5 a Explain with architecture of two kinds of services in wireless Ethernet 06
b Apply spanning tree algorithm and mark forwarding and blocking ports for a system 06
with 4 LANS and 5 switches.
(i) S1 connects LAN1 and LAN2
(ii) S2 connects LAN1 and LAN3
(iii) S3 connects LAN2, LAN3 and LAN4
(iv) S4 connects LAN2, LAN4
(v) S5 connects LAN3, LAN4

c Explain Network Address Translation (NAT) 04

 OR
6 a With a neat diagram explain two types of Network defined by Bluetooth 06
b Explain VLAN with a neat diagram and also membership and configuration of VLAN 06
c Explain Forwarding process of a router 04
Module-4
7 a With a neat diagram explain IPV4 Datagram format 06
b Explain with neat diagram the three phases in Mobile host communication 06

c With a neat diagram Describe areas in an Autonomous system in OSPF 04

OR
8 a With a neat diagram explain general format of ICMP messages 06
b Apply link state routing for the given Fig. Q.8(b) below and create a least cost tree using 10
Dijkstra Algorithm

2 5
A B C 3 3

3 4 4 G

D E F 1
5 2

Fig. Q. 8(b)
Module-5
9 a Explain why the send window size for Go- Back N must be less than 2m 05
b Explain sending and receiving buffers in TCP 05
c With a neat diagram explain TCP segment format 06
OR
10 a Explain why the size of the send and receiver window in selective repeat can be atmost 05
one half of 2m
b Discuss the general services provided by UDP 05
c Explain with a neat diagram connection establishment using three way handshaking in TCP 06
Note: In the updated syllabus, in Module-3, Routers has been added along with the
Switches.
***************
 15EC651
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER
6th Semester, B.E (CBCS) EC/TC
Course: 15EC651 – Cellular Mobile Communications

Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.

Module-1 Marks
1 a) What are co-channel cells? with a diagram & relevant equations, explain the 8
interference between signals from co-channel cells.

b) Explain how cell splitting is used to improve coverage and capacity in cellular systems 8
with a diagram.
OR
2 a) Explain the three basic propagation mechanisms which impact propagation in a 8
mobile communication system.
b) Explain okumura and hata outdoor propagation models. 8
Module-2
3 a) Explain the impulse response model of a multipath channel with relevant equations. 8
b) Explain the clarke’s model for flat fading with relevant equations. 8
OR
4 a) Consider a transmitter which radiates a sinusoidal carrier frequency of 1850 MHz. 6
For a vehicle moving 60mph, compute the received carrier frequency if the mobile is
moving a) Directly towards the transmitter b) Directly away from the transmitter c)
In a direction which is perpendicular to the direction of arrival of the transmitted
signal.

b) What is small scale fading? explain different types of small-scale fading. 10

Module-3
5 a) What is multiframe in GSM? explain the channel organization in a 51-frame 8
multiframe.
b) With a simplified block diagram, explain the GSM speech coder. 8
OR
6 a) Explain the GSM system architecture with a diagram. 8
b) Explain the GSM protocol architecture for signaling with a diagram.
Module-4
7 a) Explain the GPRS system architecture & interfaces with a diagram 8
 b) Explain the location updating procedure used in GSM. 8
OR
8 a) Explain the Multimedia messaging service network architecture (MMSNA) with a 8
diagram.
b) Explain the effects of EDGE on the GSM system architecture 8
Module-5
9 a) Explain the generation of the CDMA forward traffic/power control channel for 9.6 8
kbps
b) Explain the various states involved in CDMA call establishment 8
OR
10 a) Explain the different types of CDMA handoff with neat diagrams. 8
b) Explain the evolution of CDMA to 3G with a diagram 8
 15EC652
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER
th
6 Semester, B.E (CBCS) EC/TC
Course: 15EC652 - ADAPTIVE SIGNAL PROCESSING
Time: 3 Hours Max. Marks: 80
Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a. Explain the characteristics and applications of adaptive signal processing. 8
b. With a neat diagram explain open and closed loop adaptation. 8
OR
2 a. Discuss about Principle of Orthogonality. 8
b. Derive augmented Wiener-Hopf equation for forward prediction. 8
Module-2
3 a. Explain about Gradient Search methods. 5
b. Discuss about Stability and Rate of convergence Gradient Searching Algorithm 7
OR
4 a. Compare Newton’s & Steepest-descent methods in terms of speed adaptation and 10
mis-adjustment.
b. Discuss about role of Learning curves. 6
Module-3
5 a. Derive LMS adaptive algorithm. 8
b. Compare the LMS and the RLS algorithm 8
OR
6 a. Determine the response of the system given by 6
y(n)=2.5y(n–1)–y(n–2)+x(n)–5x(n–1)+6x(n–1) to a input ( )
b. Prove Correlation properties of lattice Filter. 10
Module-4
7 a. Discuss the working of spread spectrum communication system. 8
b. Explain how adaptive filters can be used for single input system identification 8
OR
8 a. Illustrate how adaptive filters are used to measure earth’s impulse response. 10
b. Express the relevance of the term spread spectrum when information is represented 6
by pseudo random sequence.
Module-5
9 a. Describe the two types of inverse modelling approaches. 8
b. Derive the least-square solution to inverse modelling problem. 8
OR
10 a. Discuss about Cancellation of Echoes in long distance telephone circuits. 10
b. Explain how poles and zeros can be adapted for IIR filter synthesis. 6
 15EC653
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER
6th Semester, B.E (CBCS) EC/TC
Course: 15EC653 - ARITIFICAL NEURAL NETWORKS

Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a. What is Neural Learning? Draw and explain the general neuron model. 8
b. State and explain the Ex-OR problem? Also, explain how to overcome it. 8
OR
2 a. List and explain any three commonly used activation functions in ANN? 8
b. Draw and explain architectural graph of a multi-layer perceptron with two hidden layers. 8
Module-2
3 a. What is termination criterial in perceptron training, if the given samples are 6
not linearly separable?
b. Discuss about Stability and Rate of convergence LMS Algorithm. 10
OR
4 a. What is Back propagation? Explain the Back propagation-training algorithm with the help 10
of a one hidden layer feed forward Network
b. Illustrate how LMS algorithm is used for noise cancellation 6
Module-3
5 a. Derive LMS adaptive algorithm. 8
b. Compare RBF with Multilayer Perceptron. 8
OR
6 a. Describe how RBB networks uses cover’s theorem to solve complex classification problem. 8
b. Define the problem of automated face recognition system and its ANN solution. 8
Module-4
7 a. What is the architecture of Hopfield network? Explain the working principal of 8
Hopfield network with example

b. Explain how BAM can be used as Hetro-associative memory. 8

OR
8 a. Explain how an unsupervised learning mechanism can be adopted to solve supervised 10
learning task using LVQ algorithm.
b. Explain the concept of Simulated annealing. 6
Module-5
9 a. Explain the concept of dimensionality reduction using principal component 8
analysis.
 b. Discuss any two applications of SOM. 8
OR
10 a. Describe Kohonen self-organization map in detail. 10
b. Write a short note on Growing neural GAS algorithm. 6
 15EC654
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set I
6th Semester, B.E (CBCS) EC/TC
Course: 15EC654-Digital Switching System

Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a. Explain in brief the operation of a four wire circuit used in two way transmission. 10

b. Explain in brief regulations, standards in a telecommunication network 6

OR
2 a. Explain in brief PCM primary multiplex group. 8

b. Define the terms dB, dBW and dBm. 3

c. An amplifier has an input resistance of 600Ω and a resistive load of 75 Ω. When it 5

has an r.m.s input voltage if 100mV, the r.m.s output current is 20mA. Find the gain
in dB.
Module-2
3 a. List out the difference between Message and circuit switching 6

b. What is the significance of distribution frames? Explain the operation of distribution 10

frames.
OR
4 a. What are the functions of Switching System? 8
b. Explain the basic call processing in DSS. 8
Module-3
5 a. Derive the Erlang’s second distribution equation in case of switching systems for a 10
finite queue capacity.
b. During the busy hour a group of trunks is offered 100 calls having an average 6
duration
of 3 min; one call fails to find a disengaged trunk. Find the traffic offered to the group
and the traffic carried by the group.
OR
6 a. Find the grade of service when a total of 30E is offered to the 2 stage switching 6
network and the traffic evenly distributed over the 10 outgoing routes. Also find
traffic capacity if B ≤ 0.01.
 b. Define: a) GOS b) Busy hour c) CCR d) BHCA 4
c. Design a 3 stage fully interconnected network for 600 incoming trunks and 100 6
outgoing trunks that will make use of switches of size 5 x 5. Determine the number
of cross points required.
Module-4
7 a. An S-T-S network has 10 incoming and 10 outgoing highways. Each of which 10
conveys 32 PCM channels between incoming and outgoing space switches; there are
20 lines containing time switches. During the busy hour, the network is offered 200E
of traffic and it can be assumed that this is evenly distributed over the outgoing
channel. Estimate the grade of service obtained if,

i) Connection is required to a particular free channel on a selected

outgoing highway (mode 1)
ii) Connection is required to a particular outgoing highway, but any free
Channel on it may be used (mode 2)

b. With flow diagram, discuss call forwarding feature. 6

OR
8 a. With a neat diagram, explain the operation of time switch implementation and 8
bilateral synchronization system.
b. Explain in brief, basic software architecture used in DSS. 8
Module-5
9 a. Explain in brief the software process matrices and describe the defect analysis with 10
an example.
b. Explain the concept of embedded patcher. 6

OR
10 a. Explain in brief system outage and its impact on DSS reliability. 8
b. Explain in brief generic switch hardware architecture. 8
 15EC654
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set II
6th Semester, B.E (CBCS) EC/TC
Course: 15EC654– Digital Switching Systems

Time: 3 Hours Max Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or 2nd question.
Module 1

1 (a) Explain different network structure used in communication. 8

(b) Explain with neat diagram four wire circuit. 8

OR

2 (a) With a block schematic, explain the national telecommunication network. 8

(b) Explain the following power levels in dbm and dbw: 4

( i) 1 mw (ii) 1w (iii) 2 mw (iii) 100 mw

(c) With suitable diagram explain the principle of frequency division multiplexing. 4

Module 2

3 (a) Explain Message switching. 8

(b) Mention the functions of a switching systems 4

(c) Define (i) CCR (ii) BHCA (iii) Busy hour 4

OR

4 (a) Explain the significance of distribution frames, with the help of neat diagram. 8

(b) With a neat diagram, explain basic call process of incoming and outgoing calls 8
through digital switching systems.

Module 3

5 (a) Derive the equation for finite queue capacity. 6

 (b) During the busy hour a group of trunks is offered 100 calls having an average duration 6
of 3 minutes, one of calls fails to find a disengaged trunk. Find the traffic offered to
the group and the traffic carried by the group.

(c) Explain Business Ethics and Corporate Governance. 4

OR

6 (a) Design a grading for connecting 20 trunks to switches having 10 outlets. 8

(b) Explain grading, Explain with a neat diagram, skipped and homogenous grading 8

Module 4

7 (a) With neat sketch, explain space switch and time switch. 6

(b) Write a note on synchronization networks. 4

(c) Explain with a diagram classification of digital switching software 6

OR

8 (a) Explain in brief basic software architecture used in digital switching system. 8

(b) With a neat sketch, explain the operation of a k x m space switch. 8

Module 5

9 (a) Explain briefly with neat diagram of organizational interfaces of a typical digital 8
switching systems central office.

(b) Explain in brief generic switch hardware architecture. 8

OR

10 (a) Explain system outrage and its impact on digital switching system reliability. 6

(b) Write note on recovery strategy 4

(c) Draw a typical problem reporting system and explain function of each block 6
 15EC655
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set I
6th Semester, B.E (CBCS) EC
Course: 15EC655- Microelectronics
Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a With the neat diagram obtain the expression for finite output resistance in 08
saturation region.
b Consider an NMOS transistor fabricated in a 0.18µm process with L = 0.18µm and W 08
= 2µm. The process technology is specified to have Cox =8.6 fF/µm2, µn = 450cm2/Vžs
and Vm = 0.5V.
i. Find VGS and VDS that results in the MOSFET operating at the edge of
saturation with ID = 100µA.
ii. If VGS is kept constant, find VDS that results in ID = 50µA
OR
2 a With the neat diagram obtain the expression for drain current in various regions 08

b Analyze the circuit shown in figure Q.2b to determine the voltages at all nodes and 06
the currents through all branches. Let Vtn = 1 V and kʹn(W/L) = 1 mA/V2. Neglect the
channel length modulation effect.

Fig. Q.2b
Module-2
3 a With the help of neat diagram explain the biasing of MOSFET by Fixing VG with and 10
without source resistance.
b Explain the small signal model of MOSFET and how the T equivalent-circuit model 06
can be obtained.
OR
4 a Explain the operation of MOSFET as an amplifier with necessary diagram 10
 expressions.
b Explain the high frequency model of MOSFET with a neat diagram and internal 06
capacitances.
Module-3
5 a Explain the operation of MOS current steering circuit with necessary diagram and 08
expressions.
b Given VDD = 3V and using IREF = 100µA, design the circuit shown in figure Q.5b to 08
obtain an output current whose nominal value is 100µA. Find R if Q1 and Q2 are
matched and have channel length of 1µm, channel widths of 10µm, Vt = 0.7 V and kʹn
= 200µA/V2. What is the lowest possible value of VO? Assuming that for this process
technology VʹA = 20V/µm, find the output resistance of the current source. Also find
the change in output current resulting from a +1V change in VO.

Fig. Q.5b
OR
6 a With the help of a neat diagram and necessary expressions, explain the characteristic 10
parameters of the common gate amplifier.
b Briefly explain Millers theorem. 06
Module-4
7 a Explain the operation of common source amplifier with constant current load and 08
obtain the necessary expression
b Find the midband gain AM and the upper 3-dB frequency fH of a CS amplifier fed with 08
a signal source having an internal resistance Rsig = 100kΩ. The amplifier has RG =
4.7MΩ, RD = RL = 15kΩ, gm = 1mA/V, ro = 150kΩ, Cgs = 1pF and Cgd = 0.4pF. Also find
the frequency of the transmission zero.
OR
8 a Explain the high frequency response of MOS Cascode amplifier with necessary 08
diagram and expressions.
b Explain the operation of common gate amplifier with constant current load and 08
obtain the necessary expression
Module-5
9 a Explain the operation with a Commom-Mode input voltage of MOS differential pair 08
b Explain the small signal operation of MOS differential pair. 08
OR
10 a Explain the frequency response of the MOS differential amplifier. 08
b Explain a Two stage CMOS Op-Amp. 08
 15EC655
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set II
6th Semester, B.E (CBCS) EC
Course: 15EC655 - Microelectronics

Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
MODULE 1
1 a. Derive the expression of drain current of a MOS device for triode and 6 Marks
saturation region.
b. For the circuit shown in Fig. 1(b) has ID = 0.4mA and VD = 0.5V. The 6 Marks
2
NMOS transistor has Vt = 0.7V, µnCOX = 100µA/V , L = 1µm and W =
32µm. Find the values of Rs and RD. Assume ƛ = 0.

c. Mention the advantages of MOSFETs. 4 Marks

OR
2 a. Explain the operation of enhancement type NMOS transistor in detail. 8 Marks
b. Discus the role of substrate in the MOS with relevant equations. NMOS 8 Marks
transistor has Vto = 0.8V, 2Øf = 0.7V and Ɣ = 0.4V1/2, find Vt when VSB =
3V.
MODULE - 2
3 a. Draw the T – equivalent circuit model for the MOSFET and explain. 6 Marks
b. Explain the biasing of the MOSFET using constant current source. 6 Marks
 c. Derive the expression of AV = -gmRD for the circuit shown in Fig. 3(c). 4 Marks

OR
4 a. For the circuit shown in Fig. 4(a), obtain the expressions of Rin, AV, AVO, 8 Marks
GV and Rout.

b. Explain the role of various internal capacitances in the MOSFET. 8 Marks

MODULE - 3
5 a. For an NMOS transistor with W/L = 10 fabricated in the 0.18µm process, 6 Marks
find the values of VOV and VGS required to operate the device at ID =
100µA. Ignore channel length modulation. Assume µnCOX = 387µA/V2.
b. Explain the operation of a basic MOSFET current mirror. 5 Marks
c. State and prove the Miller’s Theorem. 5 Marks
OR
6 a. Draw and explain the circuit for generating the number of constant 8 Marks
currents of various magnitude of a current steering.
b. Derive the expression for determining the 3-dB frequency (ωH) of an 8 Marks
amplifier.
MODULE - 4
7 a. Draw the circuit diagram of a CMOS Common Source amplifier and 8 Marks
explain its operation with the help of I-V characteristics and transfer
 characteristics.
b. Explain what is Cascode amplifier and the basic idea behind the Cascode 4 Marks
amplifier.
c. Explain the operation of a Double Cascoding. 4 Marks
OR
8 a. Draw the high frequency equivalent circuit model of the common source 8 Marks
amplifier and explain the analysis using open circuit time constants.
b. Explain the effect of source resistance on transconductance and voltage 8 Marks
gain of a CS- amplifier.
MODULE - 5
9 a. Explain the operation of MOS differential pair with a differential input 8 Marks
voltage.
b. Obtain the expression of CMRR of an active loaded MOS differential 8 Marks
amplifier.
OR
10 a. Draw the diagram of a two stage CMOS op-amp circuit and explain its 8 Marks
operation.
b. Draw the frequency response of a differential amplifier due to variation of 8 Marks
common - mode gain, differential gain and CMRR with frequency and
analyse it.

****************
 Telecommunication Engineering Exclusive Model Question Papers

15TE63
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER
6th Semester, B.E (CBCS) Telecommunication Engg.
Course: 15TE63- MICROWAVE THEORY AND ANTENNAS

Time: 3 Hours Max. Marks: 80

Note: (i) Answer five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks

a What are the high frequency limitations of conventional Vacuum Tubes / Transistors?
8
Briefly Explain how these are overcome in Microwave Tubes?
1
b Describe the Structure and Operation of Reflex Klystron Oscillator. 8

OR

a Define Reflection coefficient and Derive the expression for Reflection coefficient at
8
load, in terms of Load and Characteristic impedances.
2
b A load impedance of 73-j80 Ω is required to be matched to a 50 Ω cable having
operating wave length λ = 30 cm. Design a single stub matching section of length ‘l’
8
with position ‘d’ assuming main line and stub are of same type. Simplify using Smith
Chart.

Module-2

a List the properties of S-Parameters. State and Prove the following properties of S-
parameters: 8
3
i) Symmetrical property for Reciprocal Network
ii) Unitary property for a lossless junction
b Explain with a neat diagram, the construction and working of Precision type variable
8
Attenuator.

OR

4 a Stating the characteristic features of E-plane tee junction, derive its S-matrix. 8
 b Describe the characteristic features of a Two-hole waveguide directional coupler and
8
derive its S-matrix.

Module-3

5 a List the various losses that occur in a Microstrip line. Derive the expression for
8
dielectric loss in the Substrate and ohmic loss in the Strip conductor.

b A lossless parallel strip line has a conducting strip width ‘w’, substrate dielectric
separating the two conducting strips has a relative dielectric constant εrd of ‘6’ and a
thickness ‘d’ of 4mm.

Calculate: 8
i) The required widths ‘w’ of the conducting strip in order to have a
Characteristic impedance of 50Ω.
ii) The Strip line Capacitance ‘C’.
iii) The strip line Inductance ‘L’.
iv) The velocity of the wave in the parallel strip line.
OR

a Define the following terms as applied to an Antenna.

6 i) Directivity 6
ii) Beam solid angle
iii) Half Power Beam Width
b The Power received by the receiving Antenna at a distance of 1kM over a free space
at a frequency of 1GHz is 12mW. Calculate the input to the transmitting Antenna if 4
gain of transmitting Antenna and receiving Antenna are 25dB and 35dB respectively.

c Show that the maximum effective aperture of a λ/2 dipole is 0.13 λ2. 6

Module-4

a Derive an expression for Radiation Resistance of a short electric Dipole. 8

7 b Obtain the relative Field Pattern for two Isotropic Point Sources of same Amplitude
8
but opposite Phase spaced λ/2 apart.

OR

a Derive the Field equation for a linear array of n Isotropic Point Sources of equal
8
amplitude and spacing.
8
b Explain the Principle of Pattern Multiplication with an example. 8
 Module-5

a The Diameter of a circular Loop Antenna is 0.04 λ. How many turns of Antenna will
6
give a Radiation Resistance of 36 Ω.
9
b Explain the Features and Practical Design considerations of a Mono-filar Helical
10
Antenna.

OR

a With a neat diagram, explain the operation of Log-periodic Antenna. 8

10 b Obtain the Radiation Resistance of a small loop Antenna. 8

 15TE655
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set I
6th Semester, B.E (CBCS) TC
Course: 15TE655- IMAGE PROCESSING
Time: 3 Hours Max. Marks: 80
Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a. With the help of neat block dig explain the components of a general purpose 10
image processing system.
b. Explain briefly the following terms i) Neighbors ii) Path iii) Connectivity of pixels. 6
OR
2 a. Mention the applications of image processing ? 8
b. Explain the importance of brightness adaptation and discrimination in image processing. 8
Module-2
3 a. Explain the following i) Gray-level slicing ii) Bit plane slicing. 4
b. For the given 4X4 image having gray scale between [0,9] get the histogram 12
equalized image and draw the histogram after and before equalization

2 3 3 2
4 2 4 3
3 2 3 5
2 4 2 4
OR
4 a. Explain how logical operators are used for image enhancement 6
b. Explain the basic concepts of spatial filtering in image enhancement and hence explain the 10
importance of smoothing filters.
Module-3
5 a. Explain any four properties of two dimensional Fourier Transform 8
b. Explain Homomorphic filtering for image enhancement. 8
OR
6 a. Explain any four important noise probability density functions 8
b. Draw and explain image degradation and restoration model 8
Module-4
7 a. Explain in brief inverse filtering approach and its limitation in image restoration 8
 b. Explain how adaptive filters can be used for single input system identification 8
OR
8 a. Explain in brief any two boundary representation schemes and illustrate. 10
b. write short note on i) Hit and Miss transform ii) Dilation and Erosion 6
Module-5
9 a. Explain region based segmentation technique. 8
b. Illustrate and explain how chain code is used for compression of monochrome images. 8
OR
10 a. Explain How polygon approximation approach can be used for morphological shape 8
approximation
b. Explain a boundary tracing algorithm and its applications. 8
 15TE655
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER – Set II
6th Semester, B.E (CBCS) TC
Course: 15TE655- IMAGE PROCESSING

Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a Highlight any 2 different fields in which Digital Image Processing is used? 4
b List the steps involved in digital image processing with Illustration? Briefly 6
Discuss each step.
c What is Digital Image Processing? How do you represent the digital images? 6
Explain about sampling and quantization of an image.
OR
a Define the (i) relationships between pixels.(ii) Neighbors of Pixel . 4
2 b Consider the image segment given in figure Let V={ 3,4}.Compute the lengths 6
of shortest 4,8 and m path between p and q. If the path does not exists,
Explain why.
3 4 1 2 0

0 1 0 4 2 (q)

2 2 3 1 4

(P) 3 0 4 2 1

1 2 0 3 4

c Describe image formation in the eye with brightness adaptation and 6

discrimination.
Module-2
3 a What effect would setting to zero the half of lower-order bit planes have on 4
the Histogram of an image in general.
b Specify the objective of image enhancement technique. Name various 6
arithmetic and logical operations that can be done on Images.
 c Describe Histogram Specification. 6
OR
4 a Discuss the importance of a kernel or mask or window in spatial filtering used 4
for enhancement of a digital image.
b Discuss the limiting effect of repeatedly applying a 3x3 low-pass spatial filter to 6
a digital image. You may ignore border effects. Is this effect different from
applying 5x5 filter? Illustrate.
c Perform Histogram Equalization and Draw new equalized Histogram for the 6
following Image Data.
Gray Level 0 1 2 3 4 5 6 7
No of Pixels 550 900 650 150 300 250 110 90
Module-3
5 a What is meant by image interpolation? Discuss about various interpolation 4
methods.
b Calculate the 2D-DFT of the image segment shown below using matrix 6
0 0 1 4 multiplication method.
(x,y)= 1 1 1 4
1 0 1 0
0 2 0 2
c Identify the filter function for Image Enhancement. Draw neat block diagram 6
of the filtering steps and show how the fH and fL are obtained.

OR
6 a Bring out the differences between Image enhancement and Image Restoration 4
with Illustration.
b Explain the importance of kernel separatility property of 2D-DFT in 6
implementing 2D-FFT.
c Discuss the importance of adaptive filters in image restoration system. 6
Highlight the marking of Adaptive Median filters.
Module-4
7 a Describe the process of image restoration by inverse filtering? 4
b Explain three principle ways to estimate the degradation function for use in
6
image restoration.
c Discuss Structuring elements in Image morphological transformations. 6
 OR
8 a What are the Applications of morphology? 4
b Describe dilation and Erosion morphological transformations on a binary 6
image.
c Write the mask for PreWitt, Sobel and Laplacian operator. 6
Module-5
9 a Discuss about region based segmentation. 4

b What are the derivative operators useful in image segmentation? Explain their 6
role in segmentation.
c What is global, Local and dynamic or adaptive threshold? Describe. 6
OR
10 a How can you control over segmentation problem? Explain. 4
b Segment the Image shown by using the split and Merge procedure. Let 6
Q(Ri)=TRUE if all the pixels in Ri have the same Intensity. Show the Quadtree
corresponding to your segmentation.

c Explain about the Global processing via the Hough Transform for edge linking. 6
 6th Semester BE (CBCS) Open Electives Model Question Papers

15EC661
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER
6th Semester, B.E (CBCS) – Open Elective
Course: 15EC661- DATA STRUCTURE USING C++
Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a Discuss template functions in C++. Write template function to swap two parameters 5
with arguments being two integers or two float values
b Explain how “new” operator is used for dynamic memory allocation in C++. Write a 5
function to allocate memory dynamically to a two dimensional array.
c Briefly explain Recursion. Write recursive function in C++ to find factorial of a 6
number
OR
2 a Write ADT specification for Linear Lists. 7
b Write a C++ program to insert a given element at the indexth position. 6
c Write destructors for chain. 3
Module-2
3 a Write a C++ program to add two matrices. 6
b Explain how parenthesis matching is carried out using stacks. Write C++function for 10
the same.
OR
4 a Write a C++ program to transpose a given Sparse matrix. 10
b Write C++ abstract class for Stacks. 6
Module-3
5 a What is the advantage of circular queue over simple queue? With neat diagrams 9
explain how array length can be doubled in a circular queue
b Explain how overflow condition is eliminated using hashing with chains. Compare 7
with the Linear probing method.
OR
6 a Discuss problem description and solution strategy for rail road car rearrangement 8
b Write short notes on Hashing 8
Module-4
7 a Draw the binary expression trees corresponding to each of the following expressions. 6
1. ((-A)+(X+Y))/((+B)*(C*A))
2. (A+B)/(C-D)+E+G*H/A

b Write functions for 10

1. Pre-order traversal of a Binary tree
2. Determining height of the binary tree
OR
8 a Write short notes on Linked representation of binary trees 10
b Write preorder, inorder and postorder traversals for the tree given below. 6

2 3

3 4 5 6

Module-5
9 a Explain the operations -- insertion and deletion for Max Heaps 8
b Write a function to search for an element in Binary Search Trees. 8
OR
10 a Write a function for Heap-Sort and explain Heap-Sort with neat diagrams. 10
b Discuss Binary Search Trees with duplicates 6

Note: In the updated syllabus, the publisher of the prescribed text book has been changed to
‘Universities Press’, instead of ‘Mc. Graw Hill.’
 Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER
6th Semester, B.E (CBCS) - Open Elective
Course: 15EC662–POWER ELECTRONICS
Time: 3 Hours Max Marks: 80
Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or 2nd question.
Module 1
1 (a) Draw the circuit diagram, and control characteristics of GTO,MCT and TRAIC. 6
(b) What is a converter? How are power converters classified? Explain briefly. 6
With the help of relevant equations and waveforms explain steady state characteristics of
(c) 4
power BJT.
OR
(a) Explain the switching characteristics of power MOSFET with neat diagram. 6
2
(b) What is an IGBT? Compare IGBT with BJT and MOSFET. 6
Give the definition of power electronics. Explain the relationship of power electronics to
(c) 4
power electronics and control. Mention two applications of power electronics.
Module 2
Explain the turn–on mechanism of a thyristor using two transistor analogy and derive an
3 (a) 8
expression for the anode current in terms of transistor parameters.
(b) Explain different operation regions of SCR gate characteristics. 4
(c) Explain dynamic switching characteristics of SCR. 4
OR
(a) With a circuit diagram and waveform explain RC-triggering circuit. 5
4 Differentiate natural and forced commutation? Briefly explain different types of forced
(b) 6
commutation.
Sketch the V-I characteristics of an SCR and explain a) Latching current b) Holding
(c) 5
current c) Break over voltage.
Module 3
With a neat diagram and waveform, explain the principle of single phase full converter
(a) with a purely resistive load. Derive the expression for output voltage and RMS output 6
5 voltage.
(b) What are the advantages of single phase dual convertor operation with circulating current? 5
For a single phase fully has RL load having L=6.5 mH,R=0.5 ohms and E=10v. The input
voltage is Vs= 120v(rms) at 60Hz. Dertermine a)load current at wt=α=60o, b) average
(c) 5
thyristor current IA c)rms thyristor current IR d)rms output current Irms e) average output
current Idc.
OR
 Explain the operation of single phase AC voltage controllerfor inductive load with the help
(a) 6
of circuit diagram and waveform.
Derive an expression for the rms value of the output voltage of the bidirectional AC
(b) 6
voltage controller, employing ON-OFF control.
6 A single–phase half wave AC voltage controller has a resistive load of R= 5Ω and input
voltage Vs=120v,60Hz. The delay angle of thyristor is α = π/3. Find the
(b) i) RMS value of output voltage 4
ii) input power factor
iii) average input current.
Module 4
(a) 6
With relevant equations and waveform explain step-down convertor with R-L load.

(b) Explain step –up converter with resistive load. 5

7 The Buck Regulator has an input voltage of VS= 12v. The required average output voltage
is Va= 5v at R= 500 Ω and the peak to peak output ripple voltage is 20mv. The switching
(c) frequency is 25kHz. If the peak to peak ripple current of the inductor is limited to 0.8A. 5
Determine a) Duty cycle k b) filter inductance L and capacitance c) critical values of L
and C.
OR
Briefly explain how DC convertors are classified depending on the directions of current
(a) and voltage flows. 6
8
(b) With circuit diagram and waveform explain Buck Regulator. 5
A boost regulator has an input voltage of Vs=5v. The average ouput voltage Va=15v and
the average load current Ia= 0.5 A. The switching frequency is 25kHz.If L= 150µH and
(c) 5
C=220 µF, determine duty cycle, ripple current of inductor, peak current of inductor,
ripple voltage of filter capacitor and critical values of L and C.
Module 5
(a) Explain the performance parameters of inverters. 4
9 Explain single phase full-bridge inverter with necessary circuit diagram and waveforms.
(b) 6
Derive the equation for RMS output voltage.
(c) Explain the working of transistorized current source inverter. 6
OR
Explain principle of working of variable DC link inverter. Also mention advantages and
(a) 6
disadvantages.
Explain operation of single phase half-bridge inverter and derive the output voltage
(c) 6
equation of the inverter.
10 The single phase full bridge inverter has a resistive load of R=24 ohms and the DC input
voltage of Vs= 48 v. Determine
(b) i) RMS output voltage at the fundamental frequency. 4
ii) Output power
iii) Peak and average currents of each transistor.
 15EC663
Visvesvaraya Technological University, Belagavi
MODEL QUESTION PAPER
6th Semester, B.E (CBCS) – Open Elective
Course: 15EC663 – DIGITAL SYSTEM DESIGN USING VERILOG

Time: 3 Hours Max. Marks: 80

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1 Marks
1 a What is Digital system? Explain how the Digital circuits are evolved over the times. 5
b Define the terms setup time, hold time and clock-to-output time of a flip-flop and what 5
are the constraints imposed by these parameters on the circuit operations?
c Develop a Verilog model for a 7-segment decoder. Include an additional input, blank, 6
that overrides the BCD input and causes all segments not to be lit.
OR
2 a Develop a test bench model for the 3:8 decoder. 6

b With an example show the distinction between a Moore and Mealy finite-state machine 10
and also draw the corresponding state transition diagram
Module-2
3 a Explain Bidirectional tristate data connections . Design a 64K× 8-bit composite 8
memory using four 16K × 8-bit components using Bidirectional tristate data
connections.
b Develop a Verilog model of the FIFO, which can store up to 256 data items of 16 bits 8
each using 256×16 bit dual port SSRAM for the data storage. The FIFO should provide
status outputs empty and full to indicate the empty and full status of FIFO and FIFO will
not be read when it is empty nor be written when it is full and that the write and the
read port share a common clock.
OR
4 a Design a circuit that computes the function y=ci × x2, where x is a binary-coded input 8
value and ci is a coefficient stored in a flow-through SSRAM. x, ci and y are all signed
fixed-point values with 8 pre binary-point and 12 post-binary-point bits. The index i is
also an input to the circuit, encoded as a 12-bit unsigned integer. Values for x and i arrive
at the input during the cycle when a control input, start, is 1. The circuit should minimize
area by using single multiplier to multiply ci by x and then by x again.
b What is a common cause of soft errors in DRAMs? Compute the 12-bit ECC word 8
corresponding to the 8-bit data word 01100001.
Module-3
a Explain different types of PCB design. How fast does a signal change propagate along a 8
typical PCB trace?
5 b Explain the concept differential signaling .How does differential signaling improve noise 8
immunity?
OR
a Explain signal integrity interconnection issue in PCB design. 6
b What is the benefit of allowing a PLD in a system to be reprogrammed? 5
6
c What distinguishes a platform FPGA from a simple FPGA? 5
Module-4
a Explain Digital-to-Analog Converters using R/2R ladder DAC. 6
b Write a Verilog assignment that represents a tri-state bus driver for 6
7 an 8-bit bus.
c How does the processor determine where to resume program execution on completion 4
of handling an interrupt?
OR
8 a Explain any four serial interface standards. 8
b Design and develop the Verilog code for an input controller that has 8-bit binary-coded 8
input from a sensor. The value can be read from an 8-bit input register. The controller
should interrupt the embedded Gumnut core when the input value changes. The
controller is the only interrupt source in the system.
Module-5
9 a Explain the design flow of hardware/software co-design. 10
b What aspects of the design flow does a verification plan cover? 6
OR
10 a Explain Built-in self test (BIST) techniques. 8
b Explain the terms scan design and boundary scan 8