CA Notes
CA Notes
the number of gates that can be put in a single chip has increased
considerably. The differentiation between those chips that have a few
internal gates and those having hundreds or thousands of gates is
made by a customary reference to a packages as being either a small·,
medium·, or large-scale integration device.
ECL
The emitter-coupled logic (ECL) family provides the highest-speed
digitalcircuits in integrated form. ECL is used in systems such as
supercomputers andsignal processors where high speed is essential.
Decoders
The combinational circuit that changes the binary information into
2N output lines is known as Decoders. The binary information is
passed in the form of N input lines.
Discrete quantities of information are represented in digital computers
with binary codes. A binary code of n bits is capable of representing
up to 2n distinctelements of the coded information. A decoder is a
combinational circuit that converts binary information from the n
coded inputs to a maximum of 2nunique outputs. If the n-bit coded
information has unused bit combinations,the decoder may have less
than 2noutputs.
The logic diagram of a 3-to-8-line decoder, The three data inputs, Ao,
A1, and A2, are decoded into eight outputs, each output representing
one of the combinations of the three binary input variables.
The three inverters provide the complement of the inputs, and each of
the eight AND gates generates one of the binary combinations.
2 to 4 line decoder:
1. A particular application of this decoder is a binary-to-octal
conversion.
Multiplexers (MUX):
The 4-to-1 line multiplexer of Fig. 2-4 has six inputs and one output.
A truth table describing the circuit needs 64 rows since six input
variables can have 26 binary combinations. A more convenient way to
describe the operation of multiplexers is by means of a function table.
The function table for the multiplexer is shownin Table 2-3.
The table demonstrates the relationship between the four data inputs
and the single output as a function of the selection inputs S1 and S0.
The Demultiplexer
1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2
selection lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination
of inputs which are present at the selection lines S 0 and S1, the input be connected to
one of the outputs. The block diagram and the truth table of the 1×4 multiplexer are
given below.