LOW ERROR EFFICIENT APPROXIMATE ADDERS

FOR FPGA’s

PHASE I REPORT

Submitted by

M.KARTHIGA

in partial fulfillment for the award of the degree of

MASTER OF ENGINEERING IN
VLSI DESIGN

SRI VIDYA COLLEGE OF ENGINEERING

&TECHNOLOGY
VIRUDHUNAGAR
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
ANNA UNIVERSITY, CHENNAI
 NOV – DEC 2021

ANNA UNIVERSITY, CHENNAI

BONAFIDE CERTIFICATE

Certified that this Report titled “LOW ERROR APPROXIMATE

ADDERS FOR FPGA’S” is the bonafide work of M.KARTHIGA (Reg no:

922020419003) who carried out the work under my supervision. Certified further

that to the best of my knowledge the work reported herein does not form part of any

other thesis or dissertation on the basis of which a degree or award was conferred on

an earlier occasion on this or any other candidate

Signature Signature
DR.MOHIDEENABDULKADER. Mrs.S.PRIYADHARSINI
M.E.,Ph.D., M.E.,

Professor and Head Supervisor,

DepartmentOfECE, DepartmentOfECE,
SriVidyaCollegeOfEnggAndTech
SriVidyaCollegeOfEnggAndTech
Virudhunagar-626001. Virudhunagar-626001.

Submitted for the Viva-Voice on VL5311 Project work (Phase I)

Report held at Sri Vidya College of Engineering & Technology,
Virudhunagar
On …………………….

Internal Examiner External Examiner

Abstract:
In this project, a methodology for designing low error efficient approximate adders has
been proposed. The proposed methodology utilizes FPGA resources efficiently to reduce
the error of approximate adders. We propose two approximate adders for FPGAs using our
methodology: low error and area efficient approximate adder (LEADx), and area and
power efficient approximate adder (APEx). Both approximate adders are composed of an
accurate and an approximate part. The approximate parts of these adders are designed in a
systematic way to minimize the mean square error (MSE). LEADx has lower MSE than
the approximate adders in the literature. APEx has smaller area and lower power
consumption than the other approximate adders than the existing adders. As a case study,
the approximate adders are used in video encoding application. LEADx provided better
quality than the other approximate adders for video encoding application. Therefore, our
proposed approximate adders can be used for efficient FPGA implementations of error
tolerant applications. The effectiveness of the proposed method is synthesized and
simulated using Xilinx ISE 14.7.
Keywords:- Approximate computing, approximate adder, FPGA, low error, low power,
LUT
 ACKNOWLEDGEMENT

I take this opportunity to express my gratitude to all those

who helped tocompletemy projectsuccessfully.

First, I would like to thank God almighty for having helped

me in all phases ofourendeavoursinthecompletionofthisprojectwork.

IexpressmyindebtednesstoourChairmanEr.R.THIRUVENG
ADARAMANUJA DOSS, B.E., and Vice Chairman Er. T.
VENKATESH, B.E., forallowingdoing my M.E.Degree
inthisesteemedinstitution.

I would like to express my sincere thanks to Dr.T. LOUIE

FRANGO, M.E.,Ph.d., Principal, Sri Vidya College of Engineering
and Technology, Virudhunagar
forhisencouragementandforgivingachanceofknowingtheexcellence.

I owe gratitude toDr.MOHIDEEN ABDUL KHADER,

M.E.,PH.D., Head of the Department,
forhisguidanceandvaluablesuggestions.

I would like to thank my guide and also Project Co-

ordinatorMrs.S.Priyadharsini, M.E.,Embedded System for her
valuable suggestions,
persistentdiscussion,andkindadvicethroughoutmyprojectwork.
 I also wish to express my sincere thanks to all staff members
and supportingstafffortheirselflesssupportandcooperation

M.KARTHIGA

TABLE OF CONTENTS

CHAPTER NO. TITLE PAGE NO.

ABSTRACT iii
LIST OF TABLES viii
LIST OF FIGURES ix
1 INTRODUCTION
1.1 General 11
1.2 Need for the Study 15
1.3 Objectives of the Study 16
2 REVIEW OF LITERATURE 17
3 EXISTING METHOD
3.1 Half Adder 25
3.2 Full Adder 26
3.3 Ripple Carry Adder 26
3.4 Parallel Prefix Adder 27
3.5 Disadvantages 30
4 PROPOSED METHOD
4.1 Proposed Approximate Adder 32
4.2 LEADx Approximate Adder 34
4.3 APEx Approximate Adder 34
5 ADVANTAGES & APPLICATIONS
5.1 Advantages 36
5.2 Applications 36
6 SOFTWARE USED XILINX AND VERILOG HDL
6.1 History of verilog
6.1.1 Introduction 37
6.1.2 Design Styles 38
6.1.3 Features of Verilog HDL 38
6.2 VLSI Design Flow
6.2.1 System Specification 39
6.2.2 Architectural Design 39
6.2.3 Behavioral or Functional Design 40
6.2.4 Logic Design 40
6.2.5 Circuit Design 40
6.2.6 Physical Design 40
6.2.7 Layout Verification 41
6.2.8 Fabrication & Testing 41
6.3 Module
6.3.1 Instances 41
6.3.2 Ports 41
6.3.3 Identifiers 42
6.3.4 Keywords 42
6.3.5 Data Type 42
6.3.6 Register Data Type 42
6.4 Modeling Concepts
6.4.1 Behavioral or algorithmic level 43
6.4.2 Register – Transfer level 43
6.4.3 Gate level 43
6.4.4 Switch level 44
6.5 Operators
 6.5.1 Arithmetic Operators 44
6.5.2 Relational Operators 45
6.5.3 Bit-wise Operators 45
6.5.4 Logical Operators 46
6.5.5 Reduction Operators 47
6.5.6 Shift Operators 47
6.5.7 Concatenation Operators 47
6.5.8 Operator Precedence 48
6.6 Xilinx Verilog HDL Tutorial
6.6.1 Getting Started 48
6.6.2 Introduction 48
6.6.3 Creating a New Project 49
6.6.4 Opening a Project 50
6.6.5 Creating a Verilog HDL Input file for a
combinational logic design 53
6.6.6 Synthesis and implementation
of the design 56
6.7 Xilinix Simulation Procedure 59
7 RESULTS
7.1 RTL Schematic 61
7.2 Technology Schematic 61
7.3 Simulation Results 62
7.4 Area 62
7.5 Delay 63
7.6 Evaluation Table 63
8 CONCLUSION
8.1 Conclusion 64
8.2 Future Scope 64
9 REFERENCES 65
 LISTOFTABLES

TABLENO. DESCRIPTION PAGENO.

1. Half Adder Truth Table 25

2. AAd2 33
3. Relational Operators 45
4. Bit-wise Operators 46
5. Logical Operators 46
6. Reduction Operators 47
7. Shift Operators 47
8. Operator Precendence 48
9. Evaluation Table 63
 LISTOFFIGURES

FIGURENO DESCRIPTION PAGE NO

1. Generalized Approximate Adder 15

1 W/CRatioVsCompressivestrength41 W/CRatioVs1
2. Half Adder 25
3. Full Adder 26
4. Ripple Carry Adder 27
5. Generalised PPA 28
6. LOA Approximate Adder 30
7. Proposed Approximate Adder 32
8. Add1 33
9. LEADx 34
10. APEx 35
11. VLSI Design Flow 39
12. Xilinx Project Navigator Window 50
13. Create New Project Window 51
14. Device Properties Window 51
15. Create New Source Window 52
16. Select Source Type Window 53
17. Define Verilog Source Window 54
18. New Project Information Window 55
19. Verilog Source Code Editor Window 56
20. Implementing the Design 57
21. Top Level Hierarchy of the Design 58
22. Realised Internal Logic 58
23. Xilinx Simulation 59
24. ISim Simulator 59
25. Simulation Window 60
26. Output Waveforms 60
27. RTL Schematic 61
28. Technology Schematic 61
29. Simulation Results 62
30. Area 62
31. Delay 63