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Exp 4

Here are the key steps to implement and verify an adder/subtractor circuit in FPGA using Verilog HDL: 1. Design the Verilog module for an n-bit adder/subtractor circuit using primitives like full adder, half adder. 2. Write testbench code with different input test cases and expected outputs to verify the design functionality. 3. Compile and synthesize the design using a synthesis tool like Vivado/Quartus. 4. Generate the programming file (.bit/.sof) and program the targeted FPGA board. 5. Implement the design on FPGA board by assigning inputs to pins, mapping outputs to pins in constraints file. 6.

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Pravin
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29 views

Exp 4

Here are the key steps to implement and verify an adder/subtractor circuit in FPGA using Verilog HDL: 1. Design the Verilog module for an n-bit adder/subtractor circuit using primitives like full adder, half adder. 2. Write testbench code with different input test cases and expected outputs to verify the design functionality. 3. Compile and synthesize the design using a synthesis tool like Vivado/Quartus. 4. Generate the programming file (.bit/.sof) and program the targeted FPGA board. 5. Implement the design on FPGA board by assigning inputs to pins, mapping outputs to pins in constraints file. 6.

Uploaded by

Pravin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EX.

NO:04 DESIGN AND IMPLEMENTATION OF 8-BIT ADDERS USING FPGA


DATE:

Aim
To design, simulate and implement 8 bit simple and ripple carry adders circuit in FPGA using
Verilog HDL

Software Required
 Vivado 2014.4

Hardware Required
 Nexys A7: FPGA Trainer Board

Theory

Adders are the combinatorial circuits which are used to add two binary numbers. The nature of
the adders chosen depends on the characteristics of the binary numbers which need to be added. Say for
example, if one needs to add two single bit binary digits, then one can use half adder while if there is an
additional carry which needs to be added along with them, then one may resort to the use of full adder.
However what if we want to add a binary number which has multiple bits in it. In such a case, the need
arises to use a parallel adder.

Parallel adder is nothing but a cascade of several full adders. The number of full adders used will
depend on the number of bits in the binary digits which require to be added. Such a n-bit adder formed by
cascading n full adders (FA1 to FAn)

From the discussion presented we can say that in the case of n-bit parallel adder, each adder has
to wait for the carry term to be generated from its preceding adder in order to finish its task of adding.
This can be visualized as if the carry term propagates along the chain in the fashion of a ripple. Thus these
kind of adders are even referred to as ripple carry adders. Further, the delay associated with the travelling
of carry bit is called carry propagation delay and is found to worsen with an increase in the length of the
binary numbers which require to be added. For example, if each full adder is considered to have a delay
of 10 ns, then the total delay to produce the output of a 4-bit parallel adder would be 4×10=40 ns.
8-Bit Simple Adder

Logic Diagram Truth Table

A B Sum
0101 0001 0011 0110 1000 0111
0000 0010 1000 0011 1000 0101

Program Testbench Program


module ad(a,b,sum); module tb_ad();
input [7:0]a,b; reg [7:0]t_a,t_b;
output [7:0]sum; wire [7:0]t_sum;
assign sum=a+b; ad dut (.a(t_a),.b(t_b),.sum(t_sum));
endmodule initial begin
t_a=8'b00000000; t_b=8'b10100000; #10
t_a=8'b11110000; t_b=8'b00001111; #10
$stop; end
endmodule
RTL Schematic Output

Implemented Simple Adder


in Nexys A7: FPGA Trainer
Board

Output Sum: 1111 1111


Input a: 1111 0000
b: 0000 1111
Procedure

1. Double Click on “ vivado2014.4”


2. Clickcreate new project
3. Clicknext
4. Enter your project name,and click, next.,
5. Select “RTL project” and click next.,
6. Click create file
7. Select your file type as Verilog
8. Enter your “file name” and click ok.,
9. Clicknext.,
10. Click next.,
11. Create xdc file
11.a, Clickcreate file.,
11.b. Enter your “xdc name” and click ok.,
12. Clicknext.,
13. Select your ic details.,(ex:Nexys A7” xc7a100tcpg324-1”)
14. Click finish.,
15. Enter your input and output details and click ok, else click cancel directly enter your program and
declare your input output
16. Goto project manager and click your verilog file under Design Sources.,
17. Enter your program and save file.,

Steps for Test bench creation

18. Goto project manager  right click on Simulation SourcesSelect Add or create simulation sources,
19. Click on Create File  Select your file type as Verilog
20. Enter your “file name” and click Finish.,
21. Goto project manager and click your verilog file under Simulation Sources.,
22. Enter your program and save file.,
23. Click on”run synthesis”
24. Running synthesis.,

Steps for Simulation

25. After successful synthesis completion, close the pop-up window and select Simulation  Run
Behavioural Simulation is enough to see output waveform If we run through testbench program.
26. Else After the Run Behavioral Simulation, Force the value for inputs by Force Constant option and
save the waveform
27. Run the simulation by clicking on Run for amount of time previously set
28. Output of simulation is verified with the help of waveform
8-Bit Ripple Carry Adder

Logic Diagram

Program Test bench Program


module ripple_8adder( module tb_ripple_8adder();
input [7:0] a, reg [7:0] t_a,t_b;
input [7:0] b, reg t_cin;
input cin, wire [7:0] t_sum;
output [7:0] sum, output carry ); wire t_carry;
wire [6:0]c; ripple_8adder
fulladder fa1(sum[0],c[0],a[0],b[0],cin); dut(.a(t_a),.b(t_b),.cin(t_cin),.sum(t_sum),
fulladder fa2(sum[1],c[1],a[1],b[1],c[0]); .carry(t_carry));
fulladder fa3(sum[2],c[2],a[2],b[2],c[1]); initial begin
fulladder fa4(sum[3],c[3],a[3],b[3],c[2]); t_a=8'b00000000; t_b=8'b11110000; t_cin=0;
fulladder fa5(sum[4],c[4],a[4],b[4],c[3]); #10
fulladder fa6(sum[5],c[5],a[5],b[5],c[4]); t_a=8'b11110000; t_b=8'b00001111; t_cin=0;
fulladder fa7(sum[6],c[6],a[6],b[6],c[5]); #10
fulladder fa8(sum[7],carry,a[7],b[7],c[6]); $stop;
endmodule end
Sub-Program endmodule
module fulladder(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
assign s = a^b^cin;
assign cout = (a&b)|(a&cin)|(b&cin);
endmodule

TruthTable

A B Sum
0101 0001 0011 0110 1000 0111
0000 0010 1000 0011 1000 0101
Steps for Implementation

1. Click open synthesis design and click ok.,


2. Create floor plan details
a. Clickconstraints wizard
b. Click define target
c. Select your xdc file and click ok.,
d. Click schematic(F4)
e. ClickI/O Ports
f. Enter your pin details.,
g. Select I/O STDLVCMOS33
h. Clicksave, and yes,
3. Clickrun implementation
4. ClickGenerate Bitstream and click “open target”
5. Opentargetopen new target.,
6. ClickAuto connect.,
7. Clickprogram deviceselect your device
8. Clickprogram
RTL Schematic Output – Ripple Carry Adder

Implemented Ripple Carry


Adder in Nexys A7: FPGA
Trainer Board

Output Sum: 1000 0111

Input a: 0101 0001


b: 0011 0110

a b
Result
Thus the simulation of simple and ripple carry adders were done, implemented in Nexys A7
FPGA Trainer Board and outputs were verified

Inference from the Result:

Practice Question

Implement and verify adder/ subtractor circuit in FPGA using Verilog HDL

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