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ISO1176T
SLLSE28G – OCTOBER 2010 – REVISED OCTOBER 2015

ISO1176T Isolated Profibus RS-485 Transceiver with Integrated Transformer Driver

1 Features The galvanically isolated differential bus transceiver is
an integrated circuit designed for bi-directional data
1• Meets or Exceeds the Requirements of EN 50170 communication on multipoint bus-transmission lines.
and TIA/EIA-485-A The transceiver combines a galvanically isolated
• Signaling Rates up to 40 Mbps differential line driver and differential input line
• Easy Isolated Power Design with Integrated receiver. The driver has an active-high enable with
Transformer Driver isolated enable-state output on the ISODE pin (pin
10) to facilitate direction control. The driver differential
• Typical Efficiency > 60% (ILOAD = 100 mA) - see outputs and the receiver differential inputs connect
SLUU471 internally to form a differential input/output (I/O) bus
• Differential Output exceeds 2.1 V (54-Ω Load) port that is designed to offer minimum loading to the
• Low Bus Capacitance 10 pF (Maximum) bus whenever the driver is disabled or VCC2 = 0.
• Fail-safe Receiver for Bus Open, Short, or Idle Any cabled I/O can be subjected to electrical noise
• 50-kV/µs Typical Transient Immunity transients from various sources. These noise
transients can cause damage to the transceiver
• Safety and Regulatory Approvals and/or near-by sensitive circuitry if they are of
– 4242 VPK Basic Insulation per DIN V VDE V sufficient magnitude and duration. The ISO1176T can
0884-10 and DIN EN 61010-1 significantly reduce the risk of data corruption and
– 2500 VRMS Isolation for 1 minute per UL 1577 damage to expensive control circuits.
– CSA Component Acceptance Notice 5A, IEC The device is characterized for operation over the
60950-1 and IEC 61010-1 Standards ambient temperature range of –40°C to 85°C.
•
Device Information(1)
2 Applications
PART NUMBER PACKAGE BODY SIZE (NOM)
• Profibus® ISO1176T SOIC (16) 10.30 mm × 7.50 mm
• Factory Automation
(1) For all available packages, see the orderable addendum at
• Networked Sensors the end of the datasheet.
• Motor/motion Control
Typical Application
• HVAC and Building Automation Networks
X-FMR LDO
• Networked Security Stations 4 8
D1 1
IN OUT
5

3 7 C4 C5 3 C6
EN
3 Description C1
2 6
2
GND NC
4
1 5
The ISO1176T is an isolated differential line D2
transceiver with integrated oscillator outputs that
1 16
provide the primary voltage for an isolation D1 VCC2
C3
transformer. The device is ideal for long transmission 2
D2 Isolated Supply to
lines because the ground loop is broken to allow the 4
VCC1
other Components
13
device to operate with a much larger common-mode C2 3
GND1
B
12 Profibus
voltage range. 5 A Interface
R 10
6 ISODE
The symmetrical isolation barrier of each device is Control RE
tested to provide 4242VPK of isolation per VDE for 60 Circuitry 7
DE GND2
14, 15

seconds between the line transceiver and the logic- 8

GND2
9, 11
D
level interface.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 17
2 Applications ........................................................... 1 8.1 Overview ................................................................. 17
3 Description ............................................................. 1 8.2 Functional Block Diagram ....................................... 17
4 Revision History..................................................... 2 8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 20
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 4 9 Application and Implementation ........................ 23
9.1 Application Information............................................ 23
6.1 Absolute Maximum Ratings ...................................... 4
9.2 Typical Application ................................................. 23
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5 10 Power Supply Recommendations ..................... 26
6.4 Thermal Information .................................................. 5 11 Layout................................................................... 26
6.5 Electrical Characteristics: Power Rating ................... 5 11.1 Layout Guidelines ................................................. 26
6.6 Electrical Characteristics: ISODE-Pin ....................... 6 11.2 Layout Example .................................................... 27
6.7 Electrical Characteristics: RS-485 Driver.................. 6 12 Device and Documentation Support ................. 28
6.8 Electrical Characteristics: Receiver .......................... 7 12.1 Documentation Support ........................................ 28
6.9 Supply Current .......................................................... 7 12.2 Community Resources.......................................... 28
6.10 Transformer Driver Characteristics ......................... 8 12.3 Trademarks ........................................................... 28
6.11 Switching Characteristics: RS-485 Driver ............... 9 12.4 Electrostatic Discharge Caution ............................ 28
6.12 Switching Characteristics: Receiver........................ 9 12.5 Glossary ................................................................ 28
6.13 Typical Characteristics .......................................... 10 13 Mechanical, Packaging, and Orderable
7 Parameter Measurement Information ................ 12 Information ........................................................... 28

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (October 2012) to Revision G Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1
• Added Maximum Device Power Dissipation to Power Rating Table. .................................................................................... 5

Changes from Revision E (August 2011) to Revision F Page

• Changed From "ISO1176T Reference Design SLLU471" To: "ISO1176T Reference Design SLUU471"........................... 28

Changes from Revision D (May 2011) to Revision E Page

• Deleted the MIN and MAX values for tr_D, tf_D and tBBM specifications in the Transformer Driver Characteristics table. ....... 8
• Changed test conditions from 1.9 V to 2.4 V, and changed TYP value from 230 to 350 for fSt specification in the
Transformer Driver Characteristics table................................................................................................................................ 8

Changes from Revision C (February 2011) to Revision D Page

• Added Figure 33 ..................................................................................................................................................................... 1

• Moved the Pin Description closer to the Pin drawing............................................................................................................. 4

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Changes from Revision B (December 2010) to Revision C Page

• Deleted ROFF from the TRANSFORMER DRIVER CHARACTERISTICS table ..................................................................... 8

• Added a Typ value of 23ns to Prop delay time for VCC1 = 5V in the RS-485 DRIVER SWITCHING
CHARACTERISTIC table ....................................................................................................................................................... 9
• Added a Typ value of 25ns to Prop delay time for VCC1 = 3.3V in the RS-485 DRIVER SWITCHING
CHARACTERISTIC table ....................................................................................................................................................... 9
• Changed θJA = 212°C/W To: θJA = 76°C/W, Changed the IS Max value From: 128mA To: 347mA, and changed
paragraph two in the IEC SAFETY LIMITING VALUES section .......................................................................................... 19
• Changed Figure 29............................................................................................................................................................... 19

Changes from Revision A (December 2010) to Revision B Page

• Changed the Steady-state short-circuit output current - Test Conditions and values............................................................ 6
• Changed the Oscillator frequency values............................................................................................................................... 8
• Changed the D1, D2 output rise time values ......................................................................................................................... 8

Changes from Revision initial (October 2010) to Revision A Page

• Updated transformer driver characteristics............................................................................................................................. 8

• Added Thermal Table data ................................................................................................................................................... 19

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5 Pin Configuration and Functions

DW Package
16-Pin SOIC
Top View

D1 1 16 VCC2
D2 2 15 GND2
GND1 3 14 GND2
VCC1 4 13 B
R 5 12 A
RE 6 11 GND2
DE 7 10 ISODE
D 8 9 GND2

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
A 12 I/O Non-inverting Driver Output / Receiver Input
B 13 I/O Inverting Driver Output / Receiver Input
D 8 I Driver Input
D1 1 O Transformer Driver Terminal 1, Open Drain Output
D2 2 O Transformer Driver Terminal 2, Open Drain Output
DE 7 I Driver Enable Input
GND1 3 — Logic-side Ground
GND2 9, 11, 14, 15 — Bus-side Ground. All pins are internally connected.
ISODE 10 O Bus-side Driver Enable Output Status
R 5 O Receiver Output
RE 6 I Receiver Enable Input. This pin has complementary logic.
VCC1 4 — Logic-side Power Supply
VCC2 16 — Bus-side Power Supply

6 Specifications
6.1 Absolute Maximum Ratings
(1)
See
MIN MAX UNIT
VCC1, (2)
Input supply voltage –0.5 7 V
VCC2
Voltage at any bus I/O terminal –9 14 V
VO
Voltage at D1, D2 14 V
VI Voltage input at D, DE or RE terminal –0.5 7 V
IO Receiver output current –10 10 mA
ID1, ID2 Transformer Driver Output Current 450 mA
TJ Maximum junction temperature 170 °C
TSTG Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the referenced network ground terminal and are peak voltage
values.

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6.2 ESD Ratings

VALUE UNIT
Bus pins to GND1 ±6000
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
Bus pins to GND2 ±10000
001 (1)
Electrostatic
V(ESD) All pins ±4000 V
discharge
(2)
Charged-device model (CDM), per JEDEC specification JESD22-C101 ±1500
Machine model (MM), ANSI/ESDS5.2-1996 ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Logic side supply voltage, VCC1 (with respect to GND1) 3 5.5
VCC V
Bus side supply voltage, VCC2 (with respect to GND2) 4.75 5.25
VCM Voltage at either bus I/O terminal A, B –7 12 V
RE 2 VCC1
VIH High-level input voltage V
D, DE 0.7 VCC1
RE 0 0.8
VIL Low-level input voltage V
D, DE 0.3 VCC1
VID Differential input voltage A with respect to B –12 12 V
RS-485 driver –70 70
IO Output Current mA
Receiver –8 8
TA Ambient temperature -40 85 °C
TJ Operating junction temperature 150 °C
1 / tUI Signaling Rate 40 Mbps

6.4 Thermal Information

ISO1176T
THERMAL METRIC (1) DW (SOIC) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 76 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 37.9 °C/W
RθJB Junction-to-board thermal resistance 44.6 °C/W
ψJT Junction-to-top characterization parameter 12.1 °C/W
ψJB Junction-to-board characterization parameter 37.9 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: Power Rating

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
VCC1 = 5.5 V, VCC2 = 5.25 V, TJ = 150°C, CL =
PD Maximum device power dissipation 50 pf, RL = 54 Ω 719 mW
Input a 20 MHz 50% duty cycle square wave

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6.6 Electrical Characteristics: ISODE-Pin

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = –8mA VCC2 – 0.8 4.6
VOH High-level output voltage V
IOH = –20µA VCC2 – 0.1 5
IOL = 8mA 0.2 0.4
VOL Low-level output voltage V
IOL = 20µA 0 0.1

6.7 Electrical Characteristics: RS-485 Driver

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOD Open-circuit differential output voltage |VA – VB|, See Figure 9 1.5 VCC2 V
See Figure 10 and Figure 14 2.1
Steady-state differential output voltage
|VOD(SS)| See Figure 11, Common-mode loading V
magnitude 2.1
with Vtest from –7 V to +12 V
Change in steady-state differential output
|ΔVOD(SS)| See Figure 12 and Figure 13, RL = 54 Ω -0.2 0.2 V
voltage between logic states
Steady-state common-mode output
VOC(SS) See Figure 12 and Figure 13, RL = 54 Ω 2 3
voltage
Change in steady-state common-mode
ΔVOC(SS) See Figure 12 and Figure 13, RL = 54 Ω –0.2 0.2 V
output voltage
Peak-to-peak common-mode output
VOC(pp) See Figure 12 and Figure 13, RL = 54 Ω 0.5
voltage
Differential output voltage over and under
VOD(ring) See Figure 14 and Figure 17 10% VOD(pp)
shoot
II Input current D, DE at 0 V or VCC1 –10 10 µA
IO(OFF) Power-off output current VCC2 = 0 V See receiver input current
IOZ High-impedance output current DE at 0 V See receiver input current
IOS(P) Peak short-circuit output current VOS = –7 V to 12 V –250 250 mA
See
Figure 16, VOS = 12 V, D at GND1 135
IOS(SS) Steady-state short-circuit output current DE at VCC1 mA
VOS = –7 V, D at VCC1 –135
COD Differential output capacitance See receiver CIN
CMTI Common-mode transient immunity See Figure 27 25 kV/µs

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6.8 Electrical Characteristics: Receiver

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT(+) Positive-going input threshold voltage IO = –8mA –80 –10 mV
See Figure 23
VIT(–) Negative-going input threshold voltage IO = 8mA –200 –120 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 25 mV
VCC1 = 3.3 V ± 10% IOH = –8 mA VCC1 – 0.4 3
VID = 200 mV,
VOH High-level output voltage and VCC2 = 5 V ± V
See Figure 23 IOH = –20 µA VCC1 – 0.1 3.3
5%

VID = –200 mV, IOL = 8 mA 0.2 0.4

VOL Low-level output voltage V
See Figure 23 IOL = 20 µA 0 0.1
VCC1 = 5 V ± 10% IOH = –8 mA VCC1 – 0.8 4.6
VID = 200 mV,
VOH High-level output voltage and VCC2 = 5 V ± V
See Figure 23 IOH = –20 µA VCC1 – 0.1 5
5%
VID = –200 mV,
IOL = 8 mA 0.2 0.4
VOL Low-level output voltage See Figure 23 V
IOL = 20 µA 0 0.1
VCC2 = 4.75 V
IA, IB
or 5.25 V
Bus pin input current VI = –7 or 12 V, Other input = 0 V –160 200 µA
IA(off),
VCC2 = 0 V
IB(off)
II Receiver enable input current RE = 0 V –50 50 µA
IOZ High-impedance state output current RE = VCC1 –1 1 µA
RID Differential input resistance A, B 60 kΩ
Test input signal is a 1-MHz sine wave with 1-Vpp
CID Differential input capacitance 7 10 pF
amplitude. CD is measured across A and B.
CMR Common mode rejection See Figure 26 4 V

6.9 Supply Current

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 = 3.3 V ± 10%, DE, RE = 0V or VCC1,
4.5 8 mA
(1) Logic-side quiescent supply No load
ICC1
current VCC1 = 5 V ± 10%, DE, RE = 0V or VCC1, No
7 11 mA
load
VCC2 = 5 V ± 5%, DE, RE = 0V or VCC1, No
ICC2 (1) Bus-side quiescent supply current 13.5 18 mA
load

(1) ICC1 and ICC2 are measured when device is connected to external power supplies. D1 and D2 are disconnected from external
transformer.

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6.10 Transformer Driver Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 = 5 V ± 10%, D1 and D2 connected to
350 450 610
Transformer
fOSC Oscillator frequency kHz
VCC1 = 3.3 V ± 10%, D1 and D2 connected to
300 400 550
Transformer
RON Switch on resistance D1 and D2 connected to 50Ω pullup resistors 1 2.5 Ω
VCC1 = 5 V ± 10%, See Figure 28, D1 and D2
80
connected to 50-Ω pullup resistors
tr_D D1, D2 output rise time ns
VCC1 = 3.3 V ± 10%, See Figure 28, D1 and
70
D2 connected to 50-Ω pullup resistors
VCC1 = 5 V ± 10%, See Figure 28, D1 and D2
55
connected to 50-Ω pullup resistors
tf_D D1, D2 output fall time ns
VCC1 = 3.3 V ± 10%, See Figure 28, D1 and
80
D2 connected to 50-Ω pullup resistors
VCC1 = 2.4 V, D1 and D2 connected to
fSt Startup frequency 350 kHz
Transformer
VCC1 = 5 V ± 10%, See Figure 28, D1 and D2
38
connected to 50-Ω pullup resistors
tBBM Break before make time delay ns
VCC1 = 3.3 V ± 10%, See Figure 28, D1 and
140
D2 connected to 50-Ω pullup resistors

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6.11 Switching Characteristics: RS-485 Driver

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Prop delay time See Figure 17 23 35 ns
VCC1 = 5V ± 10%,
tsk(p) Pulse skew (|tPHL – tPLH|) VCC2 = 5V ± 5% 2 5 ns
tPLH, tPHL Prop delay time See Figure 17 25 40 ns
VCC1 = 3.3V ± 10%,
tsk(p) Pulse skew (|tPHL – tPLH|) VCC2 = 5V ± 5% 2 5 ns
tr Differential output signal rise time See Figure 17 2 3 7.5 ns
tf Differential output signal fall time See Figure 17 2 3 7.5 ns
tpDE DE to ISODE prop delay See Figure 21 30 ns
tt(MLH) , tt(MHL) Output transition skew See Figure 18 1 ns
tp(AZH), tp(BZH), Propagation delay, high-impedance-to-active
80 ns
tp(AZL), tp(BZL) output See Figure 19 and Figure 20,
tp(AHZ), tp(BHZ), Propagation delay, active-to-high-impedance CL = 50pf, RE at 0 V
80 ns
tp(ALZ), tp(BLZ) output
| tp(AZL) – tp(BZH) |
Enable skew time 0.55 1.5 ns
| tp(AZH) – tp(BZL) |
Time from application of short-circuit to
t(CFB) See Figure 16 0.5 µs
current fold back
Time from application of short-circuit to
t(TSD) See Figure 16, TA = 25°C 100 µs
thermal shutdown

6.12 Switching Characteristics: Receiver

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 23 50 65 ns
VCC1 = 5 V ± 10%,
tsk(p) Pulse skew (|tPHL – tPLH|) VCC2 = 5 V ± 5% 2 5 ns
tPLH, tPHL Propagation delay time See Figure 23 53 70 ns
VCC1 = 3.3 V ± 10%,
tsk(p) Pulse skew (|tpHL - tpLH|) VCC2 = 5 V ± 5% 2 5 ns
tr Output signal rise time 2 4 ns
tf Output signal fall time 2 4 ns
Propagation delay, high-impedance-to-high-
tPZH 13 25 ns
level output
DE at VCC1, See Figure 24
Propagation delay, high-level-to-high-
tPHZ 13 25 ns
impedance output
Propagation delay, high-impedance-to-low-
tPZL 13 25 ns
level output
DE at VCC1, See Figure 25
Propagation delay, low-level-to-high-
tPLZ 13 25 ns
impedance output

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6.13 Typical Characteristics

35 90
No Load ICC2 @ 5 V
TA = 25°C 80
30
70 RL = 54 W,
ICC - Supply Current - mA

ICC - Supply Current - mA

25 ICC2 @ 5 V CL = 50 pF,
60 TA = 25°C

20 50

40
15
ICC1 @ 5 V ICC1 @ 3.3 V
30
10
20 ICC1 @ 5 V ICC1 @ 3.3 V

5
10

0 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Data Rate - Mbps Data Rate - Mbps

Figure 1. RMS Supply Current (ICC1 and ICC2) vs Signaling Figure 2. RMS Supply Current (ICC1 and ICC2) vs Signaling
Rate With No Load Rate With Load
5 -99
VCC2 = 5 V 15 pF Load
4.5 -89 TA = 25°C
VCC2 = 5.25 V 100 Ω
VOD − Differential Output Voltage − V

4 -79

IO - Output Current - mA
3.5 -69
50 Ω
3 VCC2 = 4.75 V -59

2.5 -49

2 -39

1.5 -29

1 -19

0.5 -9
TA = 25 C
0 1
0 20 40 60 80 0 1 2 3 4 5
IL − Load Current − mA VO - Output Voltage - V
Figure 3. Differential Output Voltage vs Load Current Figure 4. Receiver High-Level Output Voltage Vs High-Level
Output Current
110 0.7
15 pF Load
100 TA = 25°C VCC = 4.75 V
0.6
90
IO - Output Current - mA

Driver Enable Skew − ns

80 0.5
70
VCC = 5.25 V
0.4
60
VCC = 5 V
50 0.3
40
0.2
30

20
0.1
RL = 110 Ω,
10 CL = 50 pF
0
0 −40 −15 10 35 60 85
0 1 2 3 4 5
VO - Output Voltage - V TA − Free-Air Temperature − °C

Figure 5. Receiver Low-Level Output Voltage vs Low-Level Figure 6. Driver Enable Skew vs Free-Air Temperature
Output Current

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Typical Characteristics (continued)

28 58
CL = 15 pH, tPHL (VCC1 = 3.3 V)
tPHL (VCC1 = 3.3 V)
56 VCC2 = 5 V

26

Receiver Propagation Delay - ns

Driver Propagation Delay - ns

54 tPLH (VCC1 = 3.3 V)

tPLH (VCC1 = 3.3 V)

52
24

50

22
48
tPHL (VCC1 = 5 V) tPHL (VCC1 = 5 V)
46
20 tPHL (VCC1 = 5 V) tPLH (VCC1 = 5 V)
44

18 42
-40 -15 10 35 60 85 -40 -15 10 35 60 85
TA - Free-Air Temperature - °C TA - Free-Air Temperature - °C
Figure 7. Driver Propagation Delay vs Free-Air Temperature Figure 8. Receiver Propagation Delay vs Free-Air
Temperature

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7 Parameter Measurement Information

VCC1 VCC1
IOA IOA
DE DE
A A
0 or II 0 or II
VCC1 VOD VCC1 VOD 54 W
D B D B

GND1 GND2 IOB GND1 GND2 IOB

VI VI
VOB VOA VOA
VOB
GND1 GND2
GND 1 GND2

Figure 9. Open Circuit Voltage Test Circuit Figure 10. VOD Test Circuit

VCC2 VCC1
IOA RL
DE
DE 375 W 2
A
A
D + 0 or II
0 or 3 V . 60 W VCC1 VOD
B VOD D
- 7 V to12 V B
-
RL
GND1 2
GND2 IOB
GND2 375 W VI

VOB VOA VOC

GND1 GND2
Figure 11. Driver VOD with Common-mode
Loading Test Circuit Figure 12. Driver VOD and VOC Without Common-
Mode Loading Test Circuit

VCC1
IOA RL
DE A VA
2
A
II
Input VOD B VB
D
B
RL
VOC
Input GND1 GND2 IOB 2
Generator : PRR = 500 kHz , 50 % duty VOC(p-p)
cycle, t r < 6 ns , t f < 6 ns , ZO = 50 W
VI

VOB VOA VOC VOC (SS )

GND1 GND2

Figure 13. Steady-State Output Voltage Test Circuit and Voltage Waveforms

VOD(RING )
VOD (SS )
VOD ( pp)
0V differential

Figure 14. VOD(RING) Waveform and Definitions

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VCC1
DE IOA
A
0 or II 54 W
VCC1 V OD
D B

GND 2 IOB
GND 1
VI
V OB V OA
GND 1 GND 2

Figure 15. Input Voltage Hysteresis Test Circuit

DE
IOS 250

Output Current - mA
A

D
135
IOS
B
+ 60
V_
OS
GND1 GND2
t(CFB) time
t(TSD)

Figure 16. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t=0)

3V
VCC1 DE
A 1.5 V 1.5 V
VI
D VOD
R L = 54 W C L = 50 pF
±1 % tpLH tpHL
Input B ± 20% VOD(H)
Generator VI 90% 90%
50 W
0V 0V
C L includes fixture and VOD
GND1 10 % 10%
instrumentation capacitance
Generator: PRR= 500 kHz , 50 % duty tr tf VOD(L)
cycle, t r < 6ns , t f < 6 ns ,ZO = 50 W

Figure 17. Driver Switching Test Circuit and Waveforms

DE
VCC1
A
50 % 50 %
D
A
Input B RL= 54 W CL = 50pF
Generator VI ±1% ± 20% VO B tt(MHL) tt(MLH)
50 W
GND1 GND2 V
OA VOB 50 % 50 %
Generator : PRR= 500 kHz, 50 % duty
cycle, t r< 6ns , t f <6 ns ,ZO = 50 W
CL includes fixture and
instrumentation capacitance

Figure 18. Driver Output Transition Skew Test Circuit and Waveforms

RL= 110 W
VCC2
A CL = 50 pF DE 1.5 V

D t(AZL) t(ALZ)
V IN = 0V
B A 50% VOL+ 0.5V
DE RL= 110 W
0V t(BZH) t(BHZ)
Signal CL = 50 pF
50 W VOA VOB B VOH - 0.5 V
Generator 50%
GND 1 GND 2

Figure 19. Driver Enable/Disable Test, D at Logic Low Test Circuit and Waveforms

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RL= 110 W
0V
A CL = 50 pF DE 1.5 V
D
VIN = 3. 0V t(AZH) t(AHZ)
B R = 110 W VOH -0.5 V
DE A
VCC2 50 %
Signal t(BZL) t(BLZ)
50 W VOA VOB C L = 50 pF
Generator
B 50 % VOL 0.5 V
GND 1 GND 2

Figure 20. Driver Enable/Disable Test, D at Logic High Test Circuit and Waveforms

VCC1 VCC2
GALVANIC ISOLATION

DE 50 % 50 %
D ISODE
VIN = VCC1
tpDE_LH tpDE_HL
CL = 15 pF
DE
± 20% 50 %
50 %
Signal ISODE
50 W
Generator

GND 1 GND 2

Figure 21. DE to ISODE Prop Delay Test Circuit and Waveforms

IO
V ID

VO

Figure 22. Receiver DC Parameter Definitions

Signal Input B
50 W 1.5 V
Generator
A 50%
IO
R Input A
PRR=100 kHz, 50% duty cycle, VID 0V
t r <6ns, t f <6ns, ZO = 50 W tpLH tpHL
B VO
C L = 15 pF V OH
Signal 90%
50 W (includes probe and 1.5 V
Generator jig capacitance) Output 10%
V OL
tr tf

Figure 23. Receiver Switching Test Circuit and Waveforms

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VCC D
VCC DE

A RE 3V

54 W 1.5 V 1.5 V
B
0V

tpZH tpHZ
R 1 kW
0V VO
VOH -0.5 V
C L = 15 pF 1.5 V
(includes probe and
RE jig capacitance)
R GND
Signal 50 W
Generator PRR=100 kHz, 50% duty cycle,
tr<6ns, t f <6ns, ZO = 50 W

Figure 24. Receiver Enable Test Circuit and Waveforms, Data Output High

0V D
VCC DE

A RE 3V

54 W 1.5 V 1.5 V
B
0V
tpZL tpLZ
R 1 kW VOH
VCC1 R

C L = 15 pF 1.5 V
(includes probe and VOL +0.5 V
RE jig capacitance) VOL
Signal 50 W
Generator PRR=100 kHz, 50% duty cycle,
tr<6ns, t f <6ns, Z O = 50 W

Figure 25. Receiver Enable Test Circuit and Waveforms, Data Output Low

A
VINPUT 100 nF 470 nF
50 W R
freq = 1 to 50 MHz
ampl. = ±5 V
B RE
2.2 kW V
50 W
R Scope
DE
2.2 kW

VOFFSET
Scope
= -2V to7V GND VCC
100 nF

Figure 26. Common-Mode Rejection Test Circuit

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2.0V C = 0.1 mF VCC1 VCC2

±1% C = 0.1 mF ±1%
A
DE
GND 1 D
S1 54 W
VOH or VOL
B

0.8V
R Success / fail criterion :
stabile VOH or V OL outputs.
RE
VOH or VOL 1 kW
GND1 GND2
CL=15 pF
(includes probe and
jig capacitance)

VTEST

Figure 27. Common-Mode Transient Immunity Test Circuit

tr_D tf_D
90%

D1 10%
tBBM tBBM
90 %
D2
10 %
tf_D tr_D

Figure 28. Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs

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8 Detailed Description

8.1 Overview
The ISO1176T is an isolated half-duplex differential line transceiver that meets the requirements of EN 50170
and TIA/EIA 485/422 applications. It has integrated transformer driver for convenient secondary power supply
design. The device is rated to provide galvanic isolation of up to 4242 VPK per VDE and 2500 VRMS per UL 1577.
The device has active-high driver enable and active-low receiver enable functions to control the data flow. It has
maximum data transmission speed of 40 Mbps.
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined
as VOD = V(A) – V(B) is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD
is negative. When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant.
The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled (high-
impedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is
enabled, output A turns high and B turns low.
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT– , the receiver output, R, turns
low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic high or left open, the receiver
output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver
inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the
bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).

8.2 Functional Block Diagram

1
D1
OSC
2
D2
GALVANIC ISOLATIO N

13
5 B
R 12
6 A
RE
8
D

7 10
DE ISODE

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8.3 Feature Description

8.3.1 Insulation and Safety-Related Specifications for 16-DW Package
over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

L(I01) Minimum air gap (Clearance) (1) Shortest terminal to terminal distance through air 8 mm
Shortest terminal to terminal distance across the
L(I02) Minimum external tracking (Creepage) (1) 8 mm
package surface
Comparative Tracking Index (Tracking
CTI DIN EN 60112 (VDE 0303-11); IEC 60112 400 V
resistance)
DTI Distance through the insulation Minimum Internal Gap (Internal Clearance) 0.008 mm
Input to output, VIO = 500 V, all pins on each side
RIO Isolation resistance of the barrier tied together creating a two-terminal >1012 Ω
device, TA = 25 °C
CIO Barrier capacitance Input to output VIO = VCC/2 + 0.4 sin (2πft), f = 1MHz, VCC = 5 V 2 pF
CI Input capacitance to ground VI = 0.4 sin (2πft), f = 1MHz 2 pF

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to make sure that the mounting pads of the isolator
on the printed circuit board do not reduce this distance. Techniques such as inserting grooves and/or ribs on a printed circuit board are
used to help increase these specifications.

8.3.2 IEC 60664-1 Ratings Table

PARAMETER TEST CONDITIONS SPECIFICATION

Material group II
Overvoltage category / Installation Rated mains voltage ≤ 150Vrms I-IV
classification for basic insulation Rated mains voltage ≤ 300Vrms I-III

8.3.3 DIN V VDE V 0884-10 Insulation Characteristics (1)

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS SPECIFICATION UNIT

VIORM Maximum working isolation voltage 566 VPK
VPR Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1s, 1062
Partial discharge < 5pC
Input to output test voltage Method a, After environmental tests subgroup 1, VPK
906
VPR = VIORM × 1.6, t = 10s, Partial discharge < 5pC
After Input/Output Safety Test Subgroup 2/3,
680
VPR = VIORM x 1.2, t = 10s, Partial discharge < 5pC
VIOTM t = 60s (qualification),
Maximum transient isolation voltage 4242 VPK
t = 1s (100% production)
VIOSM Tested per IEC 60065, 1.2/50 µs waveform,
Maximum surge isolation voltage 3077 VPK
VTEST = 1.3 x VIOSM = 4000 VPK (Qualification Test)
RS Insulation resistance VIO = 500V at TS = 150°C > 109 Ω
Pollution degree 2

(1) Climatic Classification 40/125/21

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8.3.4 Regulatory Information

VDE CSA UL
Certified according to DIN V VDE V 0884- Approved according to CSA Component Approved under UL 1577 Component
10 (VDE V 0884-10):2006-12 Acceptance Notice 5A, IEC 60950-1 and IEC Recognition Program
61010-1
Basic Insulation 3000 VRMS Isolation Rating; Single Protection, 2500 VRMS (1)
Maximum Transient Isolation Voltage, Reinforced insulation per CSA 61010-1-04 and
4242 VPK IEC 61010-1 2nd Ed. 150 VRMS working
Maximum Surge Isolation Voltage, 3077 voltage;
VPK Basic insulation per CSA 61010-1-04 and IEC
Maximum Working Voltage, 566 VPK 61010-1 2nd Ed. 600 VRMS working voltage;
Basic insulation per CSA 60950-1-07 and IEC
60950-1 2nd Ed. 760 VRMS working voltage
Certificate Number: 40016131 Master Contract Number: 220991 File Number: E181974

(1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.

8.3.5 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Safety input, output, or supply
IS DW-16 θJA = 76°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 347 mA
current
TS Maximum safety temperature DW-16 150 °C

The safety-limiting constraint is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is
that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the
recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
400
VCC1 = VCC2 = 5.5 V
350
Safety Limiting Current - mA

300

250

200

150

100

50

0 50 100 150 200

Temperature - °C

Figure 29. Thermal Derating Curve per VDE

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8.4 Device Functional Modes

Table 1 and Table 2 are the function tables for the ISO1176T driver and receiver.

Table 1. Driver Function Table (1)

ENABLE OUTPUTS
INPUT ENABLE INPUT
VCC1 VCC2 OUTPUT
(D) (DE) A B
(ISODE)
PU PU H H H H L
PU PU L H H L H
PU PU X L L Z Z
PU PU X open L Z Z
PU PU open H H H L
PD PU X X L Z Z
PU PD X X L Z Z
PD PD X X L Z Z

(1) PU = Powered Up, PD = Powered Down, H = High Level, L= Low Level, X = Don't Care, Z = High
Impedance (off)

Table 2. Receiver Function Table (1)

DIFFERENTIAL
VCC1 VCC2 INPUT ENABLE (RE) OUTPUT (R)
VID = (VA – VB)
PU PU –0.01V ≤ VID L H
-0.2V < VID <
PU PU L ?
–0.01V
PU PU VID ≤ –0.2V L L
PU PU X H Z
PU PU X open Z
PU PU Open circuit L H
PU PU Short Circuit L H
Idle (terminated)
PU PU L H
bus
PD PU X X Z
PU PD X L H
PD PD X X Z

(1) PU = Powered Up, PD = Powered Down, H = High Level, L= Low Level, X = Don’t Care, Z = High
Impedance (off), ? = Indeterminate

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8.4.1 Device I/O Schematics

D , RE Input DE Input

V CC1 V CC1 V CC1 V CC1 V CC1

1 MW
500 W 500 W

1 MW

ISODE Output 3 .3 -V R Output

V CC2 V CC1

5.5 W 4W

11 W 6.4 W

5 -V R Output
V CC1

5.5 W

11 W

Figure 30. Equivalent Circuit Schematics

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A Input B Input
V CC2 V CC2

16V 18 k W 16V 18 kW

90 kW 90 kW
Input Input

16V 18 kW 16V 18 kW

A and B Outputs

V CC2

16V

Output

16V

Figure 31. Equivalent Circuit Schematics

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO1176T device consists of a RS-485 transceiver, commonly used for asynchronous data transmissions.
For half-duplex transmission, only one pair is shared for both transmission and reception of data. To eliminate
line reflections, each cable end is terminated with a termination resistor, R(T), whose value matches the
characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data
rates over longer cable length.

R R R
R R R
RE A RE A RE A
DE B DE B DE B
D D D
D D D

a) Independent driver and b) Combined enable signals for c) Receiver always on

receiver enable signals use as directional control pin
Figure 32. Half-Duplex Transceiver Configurations

9.2 Typical Application

X-FMR LDO
D1 1
4 8 5
IN OUT
3 7 C4 C5 3 C6
EN
2 6
C1 2 4
GND NC
1 5
D2

1 16
D1 VCC2
2 C3
D2 Isolated Supply to
4 other Components
VCC1 13
C2 3 B
GND1 12 Profibus
5 A Interface
R 10
6 ISODE
Control RE
Circuitry 7 14, 15
DE GND2
8 9, 11
D GND2

Figure 33. Typical Application

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Typical Application (continued)

9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.

Table 3. Design Parameters

PARAMETER VALUE
Pullup and Pulldown Resistors 1 kΩ to 10 kΩ
Decoupling Capacitors 100 nF

9.2.2 Detailed Design Procedure

9.2.2.1 Transient Voltages

Isolation of a circuit insulates it from other circuits and earth so that noise develops across the insulation rather
than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical fast
transients that occur after installation and the transient ratings of ISO1176T are sufficient for all but the most
severe installations. However, some equipment manufacturers use their ESD generators to test transient
susceptibility of their equipment and can exceed insulation ratings. ESD generators simulate static discharges
that may occur during device or equipment handling with low-energy but high voltage transients.
Figure 34 models the ISO1176T bus IO connected to a noise generator. CIN and RIN is the device and any other
stray or added capacitance or resistance across the A or B pin to GND2, CISO and RISO is the capacitance and
resistance between GND1 and GND2 of ISO1176T plus those of any other insulation (transformer, or similar),
and we assume stray inductance negligible. From this model, the voltage at the isolated bus return is shown in
Equation 1:
Z ISO
vGND2 = vN
ZISO + ZIN (1)
and will always be less than 16 V from VN. If ISO1176T is tested as a stand-alone device, RIN = 6 × 104Ω, CIN =
16 × 10-12 F, RISO = 109Ω and CISO = 10-12 F.
SPACER
Note from Figure 34 that the resistor ratio determines the voltage ratio at low frequency and it is the inverse
capacitance ratio at high frequency. In the stand-alone case and for low frequency, as shown in Equation 2,
vGND2 RISO 109
= =
vN RISO + RIN 109 + 6 ´ 104 (2)
or essentially all of noise appears across the barrier. At high frequency, as shown in Equation 3,
1
v GND2 CISO 1 1
= = = = 0.94
vN 1 1 CISO 1
+ 1+ 1+
CISO CIN CIN 16
(3)
and 94% of VN appears across the barrier. As long as RISO is greater than RIN and CISO is less than CIN, most of
transient noise appears across the isolation barrier, as it should.
We recommend the reader not test equipment transient susceptibility with ESD generators or consider product
claims of ESD ratings above the barrier transient ratings of an isolated interface. ESD is best managed through
recessing or covering connector pins in a conductive connector shell and installer training.

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A,B, Y, or Z

C IN R IN 16 V

VN Bus Return(GND2)

C ISO R ISO

System Ground (GND1)

Figure 34. Noise Model

9.2.3 Application Curve

At maximum working voltage, ISO1176T isolation barrier has more than 28 years of life.

100
WORKING LIFE -- YEARS

VIORM at 566 VPK

28

10
0 120 250 500 750 880 1000
WORKING VOLTAGE (V IORM ) -- VPK

Figure 35. Time-Dependent Dielectric Breakdown Test Results

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10 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, TI recommends a 0.1-µF bypass capacitor at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. This device is used in applications where only a single primary-side power supply is available. Isolated
power can be generated for the secondary-side with the help of integrated transformer driver.

11 Layout

11.1 Layout Guidelines

ON-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the
use of external transient protection devices. Because ESD and EFT transients have a wide frequency bandwidth
from approximately 3-MHz to 3-GHz, high-frequency layout techniques must be applied during PCB design. A
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 36).
• Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power
plane, and low-frequency signal layer.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
• Use VCC and ground planes to provide low-inductance. High-frequency currents might follow the path of least
inductance and not necessarily the path of least resistance.
• Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
• Apply 0.1-µF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, and controller ICs
on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
• Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
• Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.

NOTE
For detailed layout recommendations, see Application Note Digital Isolator Design Guide,
SLLA284.

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11.2 Layout Example

High-speed traces
10 mils
Ground plane
Keep this
space free FR-4
40 mils from planes, 0r ~ 4.5
traces, pads,
and vias
Power plane
10 mils
Low-speed traces
Figure 36. Recommended Layer Stack

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
• Isolated, 40-Mbps, 3.3-V to 5-V Profibus Interface (SLUU471)
• Digital Isolator Design Guide (SLLA284)
• Isolation Glossary (SLLA353)

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
Profibus is a registered trademark of Profibus International.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISO1176TDW LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ISO1176T
ISO1176TDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ISO1176T Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1176TDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO1176TDWR SOIC DW 16 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ISO1176TDW DW SOIC 16 40 506.98 12.7 4826 6.6

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
 PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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