10 Memory
10 Memory
: PPT/2K804/04
PPT/2K403/02
Memory
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Classification
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Classification (contd.)
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– ROMs use very little power, are extremely reliable and, contain all
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PROM
• It is basically a blank ROM chip that can be written to, but only
once.
• It is much like a CD-R drive that burns the data into the CD.
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EPROM
• It is just like PROM, except that you can erase the ROM by
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EEPROM
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Flash Memory
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RAM Basics
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Writing Operation
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Form Factor
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• 386 and 486-SX used 30 pin SIMMs, 486-DX PCI chipset and
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Memory Speed
access time.
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Example
• The memory controller requests data from memory and
memory reacts to the request in 70ns.
• The CPU receives the data in approximately 125ns.
• The total time from when the CPU first requests
information to when it actually receives the information
can be up to 195ns using a 70ns memory module.
• It takes time for the memory controller to manage the
information flow, and the information needs to travel from
the memory module to the CPU on the bus
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Types of RAM
– Two categories
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DRAM
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• A type of RAM that allows faster access if the data being called
• First memory chips to use the burst mode timing, wherein data
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EDORAM
• This RAM is used from 80286 class machine till Pentium class
machines.
• It works at 3.3V.
pins.
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SDRAM
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ECC DRAM
• NON-ECC RAM checks out for any error occurred in parity bit,
but does not correct it, which is performed by ECC
• ECC detects problems in RAM quite well and can fix most of
them on the fly.
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SDRAM
frequency.
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DDR working
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• Since the rising edge gets all the data, the falling edge
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DDR vs SDRAM
• DDR memory also fits into DIMM (Dual In-line Memory Module)
slots, although the pin count is different.
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• This lets several users share the same system, and at the
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RD RAM (contd.)
• RDRAM RIMMs comes in 2 sizes: 184 pin for desktops and 160
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SGRAM
SRAM
• It is expensive to fabricate.
• No refreshing required
• Classified as
• Core RAM
• Cache RAM
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Cache Memory
CPU.
using it.
• There are two levels of cache built right into the CPU.
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Layers Of Cache
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• Used to catch recent accesses that are not caught by the level
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• The cache controller will keep track of which data is stale and
performance as well.
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