Received December 19, 2018, accepted January 7, 2019, date of publication January 11, 2019, date of current version

January 29, 2019.

Digital Object Identifier 10.1109/ACCESS.2019.2892308

Scalable Hardware-Based On-Board Processing

for Run-Time Adaptive Lossless
Hyperspectral Compression
ALFONSO RODRÍGUEZ 1, (Student Member, IEEE), LUCANA SANTOS 2,

ROBERTO SARMIENTO 3, AND EDUARDO DE LA TORRE 1

1 Centro de Electrónica Industrial, Universidad Politécnica de Madrid, 28006 Madrid, Spain
2 Moltek Ltd. for European Space Agency, 2201 AZ Noordwijk, The Netherlands
3 Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, 35001 Las Palmas, Spain
Corresponding author: Alfonso Rodríguez ([email protected])
This work has been conducted within the ENABLE-S3 project that has received funding from the ECSEL Joint Undertaking under grant
agreement No 692455. This Joint Undertaking receives support from the European Union’s Horizon 2020 research and innovation
programme and Austria, Denmark, Germany, Finland, Czech Republic, Italy, Spain, Portugal, Poland, Ireland, Belgium, France,
Netherlands, United Kingdom, Slovakia, Norway. This work has also been supported by the Spanish R&D programme under grant
PCIN-2015-254. The authors would like to thank the Spanish Ministry of Education, Culture and Sport for its support under the FPU grant
program.

ABSTRACT Hyperspectral data processing is a computationally intensive task that is usually performed
in high-performance computing clusters. However, in remote sensing scenarios, where communications are
expensive, a compression stage is required at the edge of data acquisition before transmitting information to
ground stations for further processing. Moreover, hyperspectral image compressors need to meet minimum
performance and energy-efficiency levels to cope with the real-time requirements imposed by the sensors
and the available power budget. Hence, they are usually implemented as dedicated hardware accelerators in
expensive space-grade electronic devices. In recent years though, these devices have started to coexist with
low-cost commercial alternatives in which unconventional techniques, such as run-time hardware recon-
figuration are evaluated within research-oriented space missions (e.g., CubeSats). In this paper, a run-time
reconfigurable implementation of a low-complexity lossless hyperspectral compressor (i.e., CCSDS 123) on
a commercial off-the-shelf device is presented. The proposed approach leverages an FPGA-based on-board
processing architecture with a data-parallel execution model to transparently manage a configurable number
of resource-efficient hardware cores, dynamically adapting both throughput and energy efficiency. The
experimental results show that this solution is competitive when compared with the current state-of-the-
art hyperspectral compressors and that the impact of the parallelization scheme on the compression rate is
acceptable when considering the improvements in terms of performance and energy consumption. Moreover,
scalability tests prove that run-time adaptation of the compression throughput and energy efficiency can be
achieved by modifying the number of hardware accelerators, a feature that can be useful in space scenarios,
where requirements change over time (e.g., communication bandwidth or power budget).

INDEX TERMS Data compression, dynamic and partial reconfiguration, FPGAs, high-performance
embedded computing, hyperspectral images, on-board processing.

I. INTRODUCTION ited communication bandwidth between satellites and ground

The use of hyperspectral imaging is already consolidated as stations, motivates the use of high-efficiency on-board data
a key enabling technology in remote sensing applications. compression.
However, the continuous improvements in the field still pose Hyperspectral compression algorithms are usually imple-
several challenges at multiple levels. For instance, enhanced mented in hardware fabrics (e.g., ASICs or radiation-
sensor resolution means more data to be processed and/or hardened FPGAs), since they provide high-performance and
stored, which in turn increases both computing and memory low-energy solutions [1]. However, these approaches present
requirements in the systems. This, together with the lim- several drawbacks: on the one hand, they lack flexibility
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A. Rodríguez et al.: Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

once deployed, since it is impossible to make modifications the proposed image partitioning scheme can complement
in the implemented circuit; on the other hand, they rely on the inherent redundant operation available in ARTICo3 to
expensive space-qualified devices to ensure correct behavior increase the fault tolerance of the compressor (i.e., a single
during mission time. error in one of the compressed bitstreams only prevents that
Recently, the appearance of CubeSats has enabled the subimage from decoding from that point onwards, instead of
use of low-cost technology, usually based upon commercial compromising the whole input image).
off-the-shelf components, in small satellite deployments [2]. The ARTICo3 -based HyLoC compressor differs from all
One of the main benefits of this is that CubeSats can be hardware-based alternatives available in the literature, which
used as testbeds for non-conventional developments target- typically rely on the use of a single and highly opti-
ing space applications. For instance, they allow the eval- mized accelerator. These implementations can achieve high
uation of dynamically and partially reconfigurable FPGAs throughput (ideally, 1 compressed sample per clock cycle)
as a possible replacement for traditional radiation-hardened in BIP mode with an optimized pipeline, although data
alternatives [3]. This evaluation includes the use of Dynamic dependencies force the compressor to run slower in BSQ or
and Partial Reconfiguration (DPR) of SRAM-based fabrics BIL modes. However, resource utilization grows significantly
with a twofold objective: on the one hand, to support func- when optimizing the cores, due to the amount of internal
tional adaptation with software-like flexibility but hardware- storage required. Moreover, the throughput may be severely
like performance; on the other hand, to implement run-time affected if internal resources are not enough and storage needs
fault mitigation mechanisms such as module relocation or to be outsourced (e.g., to an external memory attached to
configuration memory scrubbing [4]. the FPGA). Although this last problem cannot be avoided,
In this paper, a run-time scalable hardware-based imple- the parallel execution of several resource-constrained hard-
mentation of a lossless hyperspectral data compression ware accelerators mitigates the impact on execution perfor-
algorithm is presented. The proposed approach relies mance without increasing area overhead drastically.
on a configurable number of low-complexity compressor The rest of this paper is organized as follows. Section II
cores (HyLoC) managed by a DPR-enabled hardware pro- presents the building blocks used in this work. A discussion
cessing architecture (ARTICo3 ) operating in the recon- on the parallelization approach used to deploy the hyper-
figurable part of a commercial System on Programmable spectral image compressor on the hardware-based process-
Chip (SoPC). ing architecture is presented in Section III. The proposed
HyLoC [5] is a hardware-based implementation of the implementation is assessed in Section IV, and the conclusions
Consultative Committee for Space Data Systems (CCSDS) drawn from the results are presented in Section V.
123 standard that targets resource-constrained systems,
where limiting area overhead is more important than achiev-
ing high compression throughput. As such, it has a reduced II. TECHNOLOGY BACKGROUND
footprint and features low-power execution at the expense A. HYLOC: A LOW-COMPLEXITY IMPLEMENTATION
of limited performance. ARTICo3 [6], on the other hand, OF THE CCSDS 123 STANDARD
is a hardware-based processing architecture that benefits from The CCSDS 123 standard [7] describes a compression algo-
a multi-accelerator computing scheme to create a run-time rithm divided in two stages: a predictor and an entropy
adaptive solution space for data-parallel algorithms. This coder. The algorithm takes a multispectral or hyperspectral
solution space is defined by a tradeoff between computing image (i.e., a three-dimensional array of integer samples) as
performance, energy consumption and fault tolerance. input, and exploits redundancies in both spatial and spec-
The HyLoC compressor is sequential in nature. In order to tral domains to reduce data volume without compromising
make it compatible with the ARTICo3 execution model, input its integrity (i.e., the compression is lossless). As a result,
images are split in fixed-size subimages that are compressed the original input samples can be completely recovered from
independently. Hence, the implementation is provided with the encoded bitstream that is produced as output.
data-level parallelism and can fully benefit from a config- A simplified flowchart of the algorithm is presented in
urable number of accelerators to achieve better performance Figure 1. The predicted sample ŝz,y,x , which corresponds to
(one order of magnitude) at a very low cost in terms of power the actual sample sz,y,x , is computed using the previously
consumption, logic resources and design/verification times. processed samples in a three-dimensional neighborhood that
To the best of the authors’ knowledge, this is the first spans the current spectral band as well as the P previous bands
implementation of a lossless hyperspectral compressor with (see Figure 2). P is a user-defined parameter that can range
multiple SIMD-like hardware accelerators that renders run- between 0 (i.e., no information from previous bands is used
time adaptive throughput and energy consumption, while for prediction) and 15.
still being competitive with alternative state-of-the-art solu- The steps of the algorithm are as follows. First, a local
tions. This novel approach allows the system to compress sum (i.e., σz,y,x ) of the neighboring samples of sz,y,x in the
faster or slower depending on the availability of the down- current band is computed. Users can select how this local
link bandwidth or the urgency to receive, in the ground sum is computed from two alternatives: neighbor-oriented
station, the information contained in the image. In addition, and column-oriented (see Table 1). Then, the local sums are

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TABLE 2. Equations to calculate the elements of the local differences

vector Uz,y ,x . For reduced prediction, only central local differences are
used; for full prediction, both central and directional local differences
are used.

FIGURE 1. Flowchart of the CCSDS 123 standard algorithm for

multispectral and hyperspectral data compression.

FIGURE 2. Three-dimensional neighborhood used for prediction in the

CCSDS 123 standard.
FIGURE 3. Block diagram of the HyLoC IP Core.
TABLE 1. Equations to calculate the local sum σz,y ,x .

The CCSDS 123 standard offers two options for entropy

coding: a sample-adaptive and a block-adaptive encoder.
HyLoC [5] is a low complexity VHDL implementation
of the CCSDS 123 lossless compressor for multispectral
and hyperspectral images that fits in a small space-qualified
used to calculate the local differences vector (i.e., Uz,y,x ). FPGA. It performs the compression in BSQ order with
The elements of this vector depend on the prediction mode, sample-adaptive entropy coding only, and serializes the com-
which is also a user-defined parameter. Hence, for reduced putation of the local differences and weight vectors to reduce
prediction, only central local differences (i.e., dz,y,x ) are complexity as much as possible. It is fully compliant with the
used; for full prediction, on the other hand, both central standard and allows for tuning the the CCSDS 123 parameters
N , d W and d NW )
and directional local differences (i.e., dz,y,x at compile time. A simplified block diagram of the HyLoC
z,y,x z,y,x
are required. The exact equations to obtain all values are compressor IP core is presented in Figure 3.
shown in Table 2. During the HyLoC development, the tradeoffs between
The predicted sample ŝz,y,x is calculated by performing the compression efficiency and hardware complexity of the
dot product of the local differences vector Uz,y,x and a weight implementation were analyzed under several compression
vector Wz,y,x that is updated according to the resulting predic- scenarios (i.e., exploring using different user-defined param-
tion error (i.e., the difference between prediction and actual eters). The final hardware architecture designed for HyLoC
sample). Finally, the prediction residuals are mapped to posi- makes it possible to compress any image in BSQ order with-
tive integer values δz,y,x that are subsequently entropy coded. out requiring an additional external data memory to store

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the local differences vector, and it also features the lowest

complexity in terms of necessary logic to compute the math-
ematical operations at the prediction stage. The price to be
paid in return for the reduced complexity is an increased
latency, as the computation of the dot product between
the local differences and the weight vectors is serialized.
Nevertheless, the low complexity of the IP core allows for
several instances to co-exist in the same FPGA and conse-
quently scale up the throughput. As it will be shown in the
following sections, this is one of the main contributions of
this paper.
The VHDL description of HyLoC was validated against
reference software implementations from ESA [8] and
UAB [9]. Moreover, it was synthesized for anti-fuse
and SRAM FPGA technologies, including space-qualified
devices such as the RTAX1000S. When implemented on
a Virtex-5 FX130, the maximum occupancy of resources
was 10%, demonstrating its low-complexity nature, and the
maximum operating frequency was 134 MHz, providing a
throughput of 11.3 MSamples/s.
FIGURE 5. ARTICo3 execution model. User applications offload a global
workload to a reconfigurable number of hardware accelerators, each one
being capable of processing a local workload. Black boxes represent DMA
transfers to (Write) or from (Read) accelerators.

In addition, the internal datapath of the architecture can be

configured at run time to support different operation modes.
Hence, several instances of the same hardware accelerator
can be used to execute a kernel in SIMD-like fashion, in a
fault-tolerant manner using module redundancy and a voter
unit, or in a combination of both modes. This configurability
creates, for each kernel, a dynamic solution space defined
by run-time tradeoffs between not only computing perfor-
mance and fault tolerance, but also energy consumption.
Furthermore, and given the data-parallel nature of the ker-
nels, the architecture provides transparent performance scal-
ability when dynamically changing the number of effective
kernel-specific accelerator instances operating in SIMD-like
fashion. An effective accelerator instance is either a single
accelerator operating in non-redundant mode or a group of
FIGURE 4. Top-level block diagram of the ARTICo3 architecture.
accelerators operating in redundant mode (i.e., 2 in DMR,
3 in TMR). Figure 5 illustrates performance scalability in
the ARTICo3 execution model: given a global workload,
B. ARTICo3 : A FRAMEWORK FOR HARDWARE-BASED which is defined in the user application running in the host
HIGH-PERFORMANCE EMBEDDED COMPUTING microprocessor, the time it takes for the offloaded computa-
ARTICo3 [6] is a DPR-enabled hardware-based processing tion to finish depends on the number of effective accelera-
architecture for high-performance embedded systems (see tor instances and their processing capabilities (i.e., the local
Figure 4 for a top-level block diagram). Its execution model workload they can accept). In the example, a global workload
follows a processor-coprocessor approach, where computa- of 4 units requires 1 execution round with 4 accelerators,
tionally intensive tasks with explicit data-level parallelism 2 execution rounds with 2 accelerators, or 4 execution rounds
(called kernels) are offloaded to hardware accelerators. More- with 1 accelerator.
over, one of the main features of ARTICo3 -based process- The ARTICo3 framework uses the architecture as its
ing is that the pool of hardware accelerators is dynamic: core element, but provides additional components at both
DPR can be used to either achieve flexible functional adap- design and run time. At design time, the ARTICo3 toolchain
tation (i.e., time-multiplexing application-specific logic in eases the integration of user-defined accelerator logic into
the FPGA), or to enable module replication (i.e., loading one a run-time reconfigurable computing system. An automated
or more copies of the same accelerator). flow builds the multi-accelerator setup and generates the

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required FPGA configuration files from the kernel spec- document mentions certain tradeoffs that need to be taken into
ifications provided by the developer. These descriptions account when applying partitioning. These tradeoffs involve
can be done either in low-level RTL code (e.g., VHDL, sacrificing the compression rate to, for instance, achieve fault
Verilog) or in high-level C/C++ code. Hence, hard- tolerance (e.g., minimize the effects of data corruption in
ware engineers can work with performance-oriented and communication links), or to limit the maximum size of each
resource-efficient accelerators, whereas software engineers compressed image [7]. By using ARTICo3 , computing per-
can also work with ARTICo3 by leveraging High-Level formance (algorithm speedup) and energy efficiency become
Synthesis (HLS) engines. At run time, the ARTICo3 runtime part of these tradeoffs, since they are also considered when
library makes both reconfiguration and execution manage- deciding the size and number of segments that are to be
ment transparent for developers, relying on a user-friendly compressed independently.
API called from the code running on the host processor. The In any case, hyperspectral image partitioning usually leads
application executable is also built by the ARTICo3 toolchain to a reduction in the compression rate for several reasons:
from a C/C++ specification, making it mandatory to pro- • Each segment requires a header, since it is handled as an
vide an already partitioned hardware/software application as independent image.
input. • Prediction is limited at the boundaries between segments
(less neighbors).
III. PARALLELIZATION APPROACH • Small segments mean less data to ‘‘learn’’ from and
The original HyLoC compressor was conceived to have a therefore, less adaptivity in the compressor.
small footprint in terms of logic resources and, as a result, Although the limits might change depending on the appli-
its normal operation is eminently sequential. Moreover, and cation scenario, variations in the compression rate need to
due to the adaptive nature of the compression algorithm be bounded. It is important to analyze the whole constraint
itself, it was meant to compress relatively large hyperspectral set in order to assess the feasibility of any given partitioning.
images. This approach, although reasonable in some contexts This is even more important in the proposed approach, where
(e.g., small rad-hard FPGAs or expensive ASICs), is no low-level, physical restrictions derived from the DPR-based
longer valid in an ARTICo3 -based implementation, because design flow are present. For this reason, an in-depth analy-
no data-level parallelism can be extracted and exploited. sis on the impact of different partitioning strategies on the
According to Section 2.1 of the CCSDS 123.0 Recom- compression rate is presented below. It is important to high-
mended Standard [7]: A user may choose to partition the light that, although this analysis is particularized through-
output of an imaging instrument into smaller images that are out the discussion to the data-parallel implementation of
separately compressed (. . .). This Recommended Standard HyLoC in ARTICo3 , the proposed partitioning strategies
does not address such partitioning or the tradeoffs associ- are platform-agnostic and hold valid for CPUs, GPUs and
ated with selecting the size of images produced under such hardware accelerators on FPGAs.
partitioning. This is further described in Section 5.3.2 of the
CCSDS 120.2 Informational Report [10]: The Recommended TABLE 3. CCSDS 123 compressor configuration.

Standard does not directly address such image segmentation;

the term ‘‘segment’’ is not part of the standard. In the view
of the Recommended Standard, each such image segment is
simply a separate image.

The configuration parameters used in the CCSDS 123

compressor for all tests can be found in Table 3. Although
the HyLoC core supports more customization parameters,
only these have an actual impact on compression performance
and area overhead [5]. With this setup, two schemes have
been evaluated using a calibrated AVIRIS [11] image with
224 spectral bands and different spatial dimensions: on the
FIGURE 6. Extracted data-level parallelism (from CCSDS one hand, a strip-based partitioning over the y-axis; on the
120.2 Informational Report [10]). In this example, image segments are other hand, a square-based partitioning over both x-axis and
produced by partitioning a larger image along the y-axis. This is a
natural approach for imagers that produce data in BIP or BIL order, but
y-axis.
other partitioning approaches could also be used. The strip-based partitioning (see Figure 7), which is the
same one presented in [10], shows convergence in the com-
Hence, extracting data-level parallelism by splitting the pression rate for subimages that are fairly large. Small images
image in several segments (as shown in Figure 6) is compli- render worse compression rates, especially when partitioned,
ant with the reference standard, as long as each partition is since the compression algorithm does not have enough input
handled as an independent image. Notice, however, that the samples to fully exploit its adaptive core. This partitioning

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hardware infrastructure. Within this wrapper, the user logic

is attached to a local memory with a size of up to 64 KiB.
The dashed line in both Figure 7 and Figure 8 represents
this resource limitation for both partitioning schemes (points
above the line denote realizable solutions). Note that, due
to its lack of scalability, the strip-based approach becomes
no longer feasible in the region where better compression
results are achieved. As a result, the square-based partitioning
scheme, which provides bounded results regardless of the
input image and thus favors scalability, has been selected for
implementation in an ARTICo3 -based deployment.

TABLE 4. Compression Rate: single image versus parallel partitioning. All

reference images are calibrated AVIRIS samples. The size of all subimage
blocks is 224 × 8 × 8.
FIGURE 7. Compression Rate: evaluation when dividing the original
image (calibrated AVIRIS image with 224 bands, different spatial
dimensions) in strips.

At this point, it is important to highlight that compression

effectiveness is data-dependent (i.e., is not only affected by
the specific partitioning of the hyperspectral image, but also
by the image itself). This is due to the adaptive nature of
the compression algorithm, and further discussion in this
regard can be found in [10], where it is also possible to see
certain convergence in the compression effectiveness pro-
vided that subimages are large enough. Hence, additional
tests have been carried out using well-known datasets as input
images (i.e., Indian Pines [12], Yellowstone Scenes [13]).
FIGURE 8. Compression Rate: evaluation when dividing the original
image (calibrated AVIRIS image with 224 bands, different spatial Table 4 presents the compression rates achieved using subim-
dimensions) in squares. age blocks of 224 × 8 × 8, which is the maximum size
for ARTICo3 -based implementations. Please note that spatial
scheme is not uniform, since the subimage size changes from dimensions have been extended (Indian Pines) or reduced
smaller images to larger ones. (Yellowstone Scenes) to achieve correct partitioning with an
The square-based partitioning (see Figure 8), on the other integer number of blocks. Results show that the worst case
hand, shows strong deviations in the compression effective- only incurs in 28% overhead in the compression rate for a
ness due to the partitioning being uniform (i.e., subimages spatial resolution of 8 × 8 pixels, a value that is consistent
have fixed size regardless of the actual input image size). with the previous tests.
In this scenario, the impact of small subimages is larger,
since there are even less input samples for the compression IV. EXPERIMENTAL RESULTS
algorithm to reach efficient results. However, the deviation Once the feasibility of the data-parallel approach has been
in the compression rate remains within an acceptable range assessed, the next step is to evaluate the run-time adaptation
when the size of the subimages is increased (e.g., from and scalability features of the ARTICo3 -based HyLoC imple-
4.022 to 5.015, around 25%, for a spatial resolution of 8 × mentation. To this end, a Zynq MMP development board
8 pixels). featuring an XC7Z100-2FFG900 Zynq-7000 device has been
Although the strip-based partitioning is better than the used. This decision has been motivated by two key factors:
square-based one when compressing large input images, on the one hand, Zynq-7000 devices provide better embed-
its implementation leads to increased memory footprints that ded processor performance than any other Xilinx FPGA
are incompatible with ARTICo3 accelerators. Before building (dual-core ARM Cortex-A9 versus single-core MicroBlaze);
the reconfigurable system, the ARTICo3 toolchain takes the on the other hand, the selected device features the largest
input kernel specifications and places them in a parametric number of logic resources in the family, which allows for
wrapper that provides seamless integration with the rest of the better accelerator scalability. A hardware template has been

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TABLE 6. Estimated power consumption.

the number of HyLoC accelerator instances, the ARTICo3

infrastructure becomes a small fraction of the overall resource
utilization (e.g., 8% with 16 accelerators).
The Zynq MMP development board does not have power
measurement circuitry and therefore, only estimated values
have been used to evaluate the energy efficiency of the pro-
posed implementation. However, the values obtained using
Vivado power estimator are coherent with actual power traces
obtained in other ARTICo3 deployments where on-board
measuring capabilities were present [6]. Table 6 reports
the estimated power consumption values for both individual
components and complete system.
The evaluation of computing performance, execution scal-
ability and energy efficiency of the ARTICo3 -based HyLoC
implementation has been done using as input hyperspectral
image a calibrated AVIRIS capture with 224 bands, 512 lines
and 512 samples. Each of the hardware accelerators has been
FIGURE 9. Experimental setup: 16 HyLoC accelerators (green) connected
to the ARTICo3 infrastructure (black). Reconfigurable slots have been configured with the maximum subimage size (as discussed
highlighted in red for clarification. in Section III), which is 224 bands, 8 lines and 8 samples,
and operates at a clock frequency of 100 MHz. Table 7 shows
TABLE 5. Resource Utilization: ARTICo3 infrastructure, HyLoC kernel, and the theoretical results (i.e., assuming zero on-chip communi-
reference implementation.
cation and memory access overheads, and knowing that one
ARTICo3 -compliant HyLoC takes 185555 clock cycles to
compress one subimage), and the values obtained when using
DPR to dynamically change the pool of available processing
cores in a real implementation. These results correspond to a
scenario where no module redundancy is used, but the same
values would be obtained when using the same number of
effective accelerator instances. In this context, execution time
shows almost linear scalability when using up to 8 accel-
erators, proving that they operate in a computing-bounded
defined to support this board in the ARTICo3 toolchain, region (i.e., accelerator execution takes more time than data
enabling up to 16 reconfigurable slots to load kernel-specific transfers between memories), which is the preferred scenario
hardware accelerators. Figure 9 shows the FPGA layout to fully benefit from ARTICo3 -based acceleration. However,
after implementation, with the ARTICo3 architecture and all using 16 accelerators only renders 9.7× speedup, which
HyLoC instances. Moreover, an ad-hoc port of the ARTICo3 indicates that the system is entering the memory-bounded
runtime library for bare-metal applications has been used region (i.e., memory bandwidth reaches its saturation point).
instead of the standard Linux-based version, aiming at In any case, all configurations are compliant with the CCSDS
improving computing performance and execution scalability specification in terms of energy efficiency, even though some
by reducing memory management overheads. of them are below the required threshold for compression
Table 5 shows the resource utilization of the ARTICo3 throughput. Please bear in mind that the specification states
infrastructure, one instance of a HyLoC kernel, and the refer- that a compressor should reach 20 MSamples/s at less than
ence implementation [5]. Notice that, although the synthesis 0.5 W/(MSamples/s) [10].
tool (ISE versus Vivado) and the FPGA used (Virtex-5 versus Finally, Table 8 shows a comparison of the proposed
Zynq-7000) are not the same, the area overhead introduced implementation with different alternatives from the state of
by the ARTICo3 wrapper is almost negligible (except for the art. In addition, reference values for AVIRIS sensors
the local memory storage). Also note that, when scaling up and the CCSDS reference standard are also included in the

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TABLE 7. Compression throughput and energy efficiency when compressing a calibrated AVIRIS image with 224 bands, 512 lines and 512 samples using
ARTICo3 and a variable number of HyLoC accelerators (configured to compress subimage blocks of 224 bands, 8 lines and 8 samples,
FPGA fabric @ 100 MHz).

TABLE 8. Comparison of CCSDS 123 implementations according to the encoding order, bands used for prediction (P), target device, maximum operating
frequency, throughput and energy efficiency.

list to highlight real-time processing conditions. Since some V. CONCLUSIONS

solutions do not consider the communication and memory In this paper, a novel run-time scalable implementation of
access overheads to calculate the throughput, both actual and the CCSDS 123 standard has been presented. As opposed to
theoretical values are provided for the proposed approach other alternatives from the literature, the proposed approach
(for the latter, the maximum operating frequency of a single relies on a DPR-enabled multi-accelerator approach, where a
HyLoC instance has been used). It is possible to see that configurable number of low-complexity and resource-
the ARTICo3 -based HyLoC compressor renders results in efficient compressor cores operate in SIMD-like fashion,
the range of the rest of implementations, being only 3.2× exploiting data-level parallelism to achieve competitive
slower (considering actual throughput values) than the fastest performance values.
solution but flexible at run time, a unique feature of this The proposed parallelization approach is supported by a
work. The GPU-based implementation presented in [18] is platform-agnostic hyperspectral image partitioning scheme
the only one that also uses input image partitioning (referred that is compatible with the reference standard. Moreover,
to as tiling). However, the implemented partitioning scheme the impact of this partitioning on the compression rate is
is the strip-based one, and the execution is performed using a acceptable even if additional low-level constraints derived
fixed number of processing elements (GPUs cannot dynam- from the hardware implementation are taken into account
ically change its computing resources). Therefore, it cannot (e.g., compression rate does not exceed a 30% overhead
dynamically adapt its performance to changing requirements when using subimage sizes of 224 bands, 8 lines and
as the implementation proposed in this work. Regarding other 8 samples).
hardware-based alternatives in the literature, the most com- Experimental results show that adaptation is supported at
mon approach is to generate highly optimized application- run time, enabling different performance/energy levels by
specific accelerators, as opposed to ARTICo3 , which has switching the number of hardware accelerators. Performance
a more general purpose (i.e., the same architecture can be scalability is almost linear until memory bandwidth starts
used to accelerate different algorithms). For instance, in [1], to saturate (e.g., using 16 accelerators reduces compression
a combination of task-level parallelism and a reconfigurable time around 10×), and although some configurations do
fine-grained pipeline is used to achieve one of the fastest not meet the reference standard requirements in terms of
implementations of the CCSDS 123 standard up to date. throughput, energy efficiency is always below the required
In addition, these implementations usually rely on design- threshold.
time customization of the hardware accelerators, as opposed Furthermore, the competitiveness of the proposed imple-
to ARTICo3 , where DPR allows dynamic changes at run mentation when compared with other alternatives from
time. This can be seen in [15], where the authors hint that the literature encourages the increase of research activ-
several logic synthesis iterations can be run to fine-tune the ity around the use of commercial off-the-shelf devices
parameters of the compressor to the hyperspectral sensor that with run-time reconfiguration capabilities in low-cost space
is used. applications.

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 A. Rodríguez et al.: Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

REFERENCES LUCANA SANTOS received the telecommunica-

[1] A. Tsigkanos, N. Kranitis, G. A. Theodorou, and A. Paschalis, tion engineering degree from the University of
‘‘A 3.3 Gbps CCSDS 123.0-B-1 multispectral & Hyperspectral Las Palmas de Gran Canaria, in 2008, and the
image compression hardware accelerator on a space-grade SRAM Ph.D. degree from the Integrated System Design
FPGA,’’ IEEE Trans. Emerg. Topics Comput., to be published, doi: Division, IUMA, in 2014.
10.1109/TETC.2018.2854412. She was a Visiting Researcher with the
[2] M. N. Sweeting, ‘‘Modern small satellites-changing the economics of European Space Research and Technology Cen-
space,’’ Proc. IEEE, vol. 106, no. 3, pp. 343–361, Mar. 2018. tre, The Netherlands. Since 2018, she has been
[3] A. D. George and C. M. Wilson, ‘‘Onboard processing with hybrid and with the Data Systems and Microelectronics Divi-
reconfigurable computing on small satellites,’’ Proc. IEEE, vol. 106, no. 3,
sion, European Space Agency. She is currently
pp. 458–470, Mar. 2018.
[4] A. Pérez, L. Suriano, A. Otero, and E. de la Torre, ‘‘Dynamic reconfig-
a member of the CCSDS Multispectral/Hyperspectral Data Compression
uration under RTEMS for fault mitigation and functional adaptation in working group. She has participated actively in industrial projects in the
SRAM-based SoPCs for space systems,’’ in Proc. NASA/ESA Conf. Adapt. field of hardware architectures for hyperspectral and multispectral image
Hardw. Syst. (AHS), Jul. 2017, pp. 40–47. compression on GPUs and FPGAs for Thales Alenia Space España and the
[5] L. Santos, L. Berrojo, J. Moreno. J. F. López, and R. Sarmiento, ‘‘Mul- European Space Agency. She has co-authored several scientific papers and
tispectral and hyperspectral lossless compressor for space applications has been a Reviewer of major international journals in her research areas. Her
(HyLoC): A low-complexity FPGA implementation of the CCSDS 123 current research interests include hardware architectures for on-board data
standard,’’ IEEE J. Sel. Topics Appl. Earth Observ. Remote Sens., vol. 9, processing, reconfigurable architectures, and hardware/software co-design
no. 2, pp. 757–770, Feb. 2016. methodologies.
[6] A. Rodríguez, J. Valverde, J. Portilla, A. Otero, T. Riesgo, and
E. de la Torre, ‘‘FPGA-based high-performance embedded systems for
adaptive edge computing in cyber-physical systems: The ARTICo3 frame-
work,’’ Sensors, vol. 18, no. 6, p. E1877, 2018.
[7] Lossless Multispectral and Hyperspectral Image Compression,
Recommended Standard CCSDS 123.0-B-1, Consultative Committee for
Space Data Systems (CCSDS), May 2012.
[8] European Space Agency. Data Compression Tools. Accessed:
Nov. 14, 2018. [Online]. Available: https://www.esa.int
[9] Group on Interactive Coding of Images, Universitat Autònoma de
Barcelona. Emporda. Accessed: Nov. 14, 2018. [Online]. Available:
ROBERTO SARMIENTO is currently a Full Pro-
http://www.gici.uab.es
[10] ‘‘Lossless multispectral and hyperspectral image compression,’’ Consulta- fessor of electronic engineering with the Electron-
tive Committee Space Data Syst., Inf. Rep. CCSDS 120.2-G-1, Dec. 2015. ics and Telecommunication Engineering School,
[11] NASA. Airborne Visible InfraRed Imaging Spectrometer. Accessed: University of Las Palmas de Gran Canaria, Spain.
Nov. 14, 2018. [Online]. Available: https://aviris.jpl.nasa.gov He contributed to set the Electronics and Telecom-
[12] M. F. Baumgardner, L. L. Biehl, and D. A. Landgrebe. (Sep. 2015). munication Engineering School, where he was the
220 Band AVIRIS Hyperspectral Image Data Set: June 12, 1992 Indian Dean of the Faculty, from 1994 to 1998, and was
Pine Test Site 3. [Online]. Available: https://purr.purdue.edu/publications/ the Vice Chancellor for Academic Affairs and
1947/1 Staff with ULPGC, from 1998 to 2003. He is a
[13] A. B. Kiely and M. A. Klimesh, ‘‘Exploiting calibration-induced artifacts co-founder of the Research Institute for Applied
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Design Division. He has published more than 70 journal papers and more
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ng.jpl.nasa.gov research programmes funded by public and private organizations. His current
[15] D. Báscones, C. González, and D. Mozos, ‘‘FPGA implementation of the research interest includes electronics system on-board satellites. He received
CCSDS 1.2.3 standard for real-time hyperspectral lossless compression,’’ five six-year research periods from the National Agency for the Research
IEEE J. Sel. Topics Appl. Earth Observ. Remote Sens., vol. 11, no. 4, Activity Evaluation in Spain.
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[16] Universidad de Las Palmas de Gran Canaria. (2017). SHyLoC IP Core.
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spectral images,’’ IEEE J. Sel. Topics Appl. Earth Observ. Remote Sens.,
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EDUARDO DE LA TORRE received the Ph.D.
ALFONSO RODRÍGUEZ (S’15) received the degree in electrical engineering from Universi-
B.Sc. degree in industrial engineering and the dad Politécnica de Madrid (UPM), in 2000. He is
M.Sc. degree in industrial electronics from currently an Associate Professor in electronics
the Universidad Politécnica de Madrid (UPM), with UPM, Spain, doing research with the Cen-
Madrid, Spain, in 2012 and 2014, respectively. tre of Industrial Electronics. He has participated
He is currently pursuing the Ph.D. degree in in more than 40 projects, eleven of them being
industrial electronics with the Centro de Elec- EU funded projects and, overall, in nine funded
trónica Industrial, UPM, where he is currently projects related with reconfigurable systems. His
a Full-Time Researcher. Under a HiPEAC col- main expertise is in FPGA design, embedded sys-
laboration grant, he was a Visiting Researcher tems design, HW acceleration, signal processing, and partial and dynamic
with the Computer Engineering Group, Universität Paderborn, where he reconfiguration of digital systems. He has been the Program Chair of ReCon-
worked on operating systems for reconfigurable computing. His current Fig and the General Chair of ReCoSoC, two conferences with strong interest
research interests include artificial intelligence, high-performance embedded in hardware reconfiguration.
systems, and reconfigurable computing.

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