Simplified SVPWM Method for the Vienna

Rectifier
Ali Sunbul Vijay K. Sood
Department of Electrical, Computer and Software Engineering Department of Electrical, Computer and Software Engineering
University of Ontario Institute of Technology (UOIT) University of Ontario Institute of Technology (UOIT)
Ontario, Canada Ontario, Canada
[email protected] [email protected]

Abstract— In this paper, a simplified Space Vector Pulse

Width Modulation (SVPWM) technique for the Vienna rectifier
is presented. Furthermore, the robustness of this modulation
technique is tested under various faults. A MATLAB/Simulink
model for the 70 kW Vienna rectifier model is implemented and
the results are provided. A low Total Harmonic Distortion
(THD) and unity Power Factor (PF) are achieved. The
simplified SVPWM provides effective capacitor voltage
balancing even under extreme faults.

Keywords— Vienna Rectifier, SVPWM, THD, power factor,

PFC, capacitor voltage balancing

I. INTRODUCTION
The 3-phase, 3-switch, 3-level and boost Vienna rectifier Fig. 1. Schematic of the Vienna rectifier
(Fig. 1) is one of the most popular Power Factor Correction simplified technique has not been implemented and its results
(PFC) topologies due to its high power density, low Total have not been reported in the literature. Moreover, in this
Harmonic Distortion (THD) and low switch voltage stress. It paper the modulation technique is tested under different faults
is widely used in several applications i.e. telecommunication to check its capability and the limitations.
supplies and off-board Electric Vehicle (EV) charging etc. [1 MATLAB/Simulink simulation results of the Vienna rectifier
- 2]. Vienna rectifier is a 3-phase system with voltages (Va, using the simplified SVPWM technique are provided.
Vb and Vc), it has three boost inductors (La, Lb and Lc), six
diodes (D1 to D6), three bidirectional active switches (Sa, Sb II. THE OPERATION OF THE VIENNA RECTIFIER
and Sc) and two capacitors (C1 and C2). For applications in Since the Vienna rectifier is a 3-switch rectifier, it has
the range of several kilowatts, the Vienna rectifier is able to eight possible switching states. However, it is a 3-phase
function well above 100 kHz switching frequency depending system, which means that there are six possible sectors based
on electromagnetic compatibility (EMC) requirements [3]. on the polarity of the grid. The operation of this rectifier can
Several researchers have employed sinusoidal PWM and be explained as follows. For example, in phase a, when the
hysteresis modulators to improve the performance of the bidirectional active switch (Sa) is OFF, the phase current
Vienna rectifier which is easily built using simple analog travels through one of the two diodes D1 or D2, depending on
circuits [4 - 5]. On the other hand, these type of modulators its polarity, and charges the two output capacitive filters C1
increase the THD since they operate in a variable switching and C2. On the other hand, the boost inductors are charged
frequency. To reduce the THD, digital controllers based on when the rectifier input is connected to the capacitor mid-point
Field Programmable Gate Arrays (FPGAs) and Digital Signal through one of the bidirectional active switches. Fig. 2 depicts
Processors (DSPs) are used with constant switching frequency the operation when the same switching state is applied in two
[6 - 7]. Although several modulation techniques have been different sectors. In both circuits, the switching state (010) is
applied to the Vienna rectifier, the Space Vector Pulse Width applied in Sectors 1 and 4. The switching state (010) means
Modulation (SVPWM) method has shown an excellent the switches (Sa) and (Sc) are OFF while the switch (Sb) is
performance. Another advantage of the SVPWM is the ability ON. The figure illustrates how one switching state can result
to modify the location and timing of the pulses which is an in different mode of operations and produce different voltage
important factor for eliminating certain harmonics. Using levels.
SVPWM for the Vienna rectifier provides an extra advantage
of balancing the DC-link’s voltage by changing the time ratio III. SPACE VECTOR PULSE WIDTH MODULATION (SVPWM)
of the two redundant switching states [8 - 9]. Numerous FOR THE VIENNA RECTIFIER
researches have employed SVPWM for this rectifier; some Unlike conventional PWM techniques, SVPWM is a
focused on neutral point balancing [10], and others proposed modulation technique that provides the ability to control the
methods to improve the zero crossing distortion [11]. pulse placement which gives the ability to reduce the THD
SPVPWM is also tested under unbalanced load conditions [12 SVPWM for the Vienna rectifier differs from conventional 3-
- 13]. However, few researchers focused on improving the level SVPWM method due to different reasons. The main
main disadvantage of this modulation technique which is the reason is that the degree of freedom in the Vienna rectifier is
high complexity and the high computational requirement such different than conventional converters. The conventional SV
as [3], [14 - 15]. In this paper, a further simplified SVPWM method considers the voltage vector as the primary vector
technique, first proposed in [16], is analysed and explained in which is used to locate the nearest switching states for the
detail. This method shows a significant reduction in the
complexity and computational requirements. However, this

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 Fig. 3. 3-level space vector diagram

The controller of the Vienna rectifier generates the

required voltage reference vector in dq-coordinates which is
transferred into Alpha-Beta coordinates in the Space Vector
(SV) modulation technique. In a further step, the magnitude
(|Vref|) and the angle (θ) of the reference vector are extracted
to pursue further in the simplified SVPWM technique as
follows:
Fig. 2. Current’s flow when the switching state is (010) and the phase
polarity are (+ - -) and (- + +) respectively A. Sector Identification
A significant step in SVPWM is to identify which sector
purpose of synthesizing the reference vector. Using the
the voltage and current vectors lie in. This can be done using
conventional SVPWM for the Vienna rectifier leads to a
simple comparators to determine the polarity of the phases.
wrong selection of the nearest switching states since the
polarity of the phase currents choose which voltage level is to
be applied. In other words, when applying the conventional Fig. 4 depicts the procedure of sector identification. The
SV method, not all voltage space vectors are visible at a given boundary of Sector 1 of the 3-level SV diagram is depicted in
time because the direction of the phase current limits the Fig. 3. It also shows that Sector 1 intersects with Sector 2 and
applicable voltage space vectors. Therefore, the SVPWM for 6. The rest of the sectors can be explained in the same manner.
the Vienna rectifier uses the current vector as the primary In the case where the voltage and current vectors are not in-
vector. phase, the voltage vector might lie in one of the intersected
areas. However, the location of the current sector decides
Equations (1) to (7) illustrate the mathematical derivation of which sector the sub-vectors’ calculation should be based on.
the available voltage space vectors for the Vienna rectifier.
Si = sign(ii ) [1 – SSi ] Fig. 5 depicts the location of the six sectors in the ideal
(1)
case where the polarity of both voltage and current vectors
Where i ϵ {a, b, c,} and SSi is the switching state ϵ {0, 1} are identical. In this case, the voltage vector cannot lie on the
intersected areas since both vectors are moving together
= (2) around the SV diagram.

= ( + + ) (3)

= – (4)

= [ + + ] (5)

= [ + + ] (6)

= [ + + ] (7)

Substituting all the possible switching states (Si) in (7) results

in 19 different vectors (6 are called short vectors, 6 are
medium vectors, 6 are long vectors and one is called the zero Fig. 4. Location of the six sectors in the 3-phase waveform
vector). All the resultant vectors are plotted in Fig. 3.

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 D
OL
_
ref
Fig. 5. Sectors in the 3-level space vector diagram
Fig. 6. Example of angle normalization

B. Angle Normalization
Normalizing the angle (Ф) (defined in eq. (8) and also
shown in Fig. 6) is a significant step to simplify the SVPWM
for the Vienna rectifier. The main idea of angle normalization
is to rotate the voltage vector, which is located in Sectors 2 to
6, to Sector 1; then, the calculations are performed on the basis
of Sector 1 despite the location of the reference vector.
Equation (8) illustrates the mathematical explanation of angle
normalization.
Ф= − ( ) − 1 ∗ 60 (8)
Note: Sector (I) is the current sector.
Fig 6 depicts the rotation of the reference vector on the 3-
level SV diagram to lie in Sector 1. As illustrated in Fig. 6, the
Fig. 7. A zoomed-in view of Sector 1 in the 3-level space vector diagram
reference vector ( Vref_OLD ) is located in Sector 2; then, the
normalization method is used to shift the reference vector to If (9) is satisfied, it means the reference vector is located
Sector 1 (shaded in pink). The result of the normalization in the inner triangle (colored in green) as shown in Fig.
method is the new vector ( Vref ). Ideally, the range of the 8. On the other hand, the reference vector lies in the
normalized angle (Ф) is between 30 to -30 degree. outer triangle (colored in blue) if (10) is satisfied as
shown in Fig. 8. However, if neither (9) nor (10) are
C. Sub-vector Calculations satisfied, the location of the reference vector is in the
In SVPWM, the reference vector is synthesized by the middle triangle (colored in white). Fig. 8 depicts the
nearest three vectors. In order to do that, the location of the three triangles that are located in the upper half of Sector
reference vector within Sector 1 must be specified via three 1. Since the absolute value of the normalized angle is
steps: used in the calculations, the three triangles are enough
1- The location of the reference vector is determined to calculate the sub-vectors at any location in the 3-level
whether it is in the upper or lower half of Sector 1. SV diagram. This illustrates the significant
Fig. 7 depicts a zoomed-in picture of Sector 1, where simplification attained by the provided SVPWM
the location of the reference vector is determined based method.
on the polarity of the normalized angle ( Ф ). For
instance, if the normalized angle is positive, the
reference vector is located in the upper half of the
hexagon (colored in blue).
2- The triangle, which the reference vector lies in, is
identified by using the following equations:

( ) (9)
| | ≤
( |Ф|)
( ) (10)
| | ≥ Fig. 8. Upper half of Sector 1 in the 3-level space vector diagram
( |Ф|)

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Fig. 9. Location of the sub-vectors in each triangle

Fig. 10. Examples of shortening sub-vectors

3- Calculating the sub-vectors V1, V2, V0 vector in the outer and the inner triangle while it is applied to
Equations (11) and (12) are used to calculate the sub- the shorter sub-vector in the middle triangle.
vectors V1 and V2 when the reference vector is located
in the inner triangle. E. Pulse Generation
The last step in the simplified SVPWM technique is
( |Ф|) (11)
1 = 1 − | | generating the pulses. This step uses the results of the previous
( )
sections. As illustrated in Fig. 11, each triangle has a unique
2 = | |
(|Ф|) (12) switching pattern; therefore, a lookup table is needed to
( ) retrieve the switching pattern of each triangle. In the lookup
If the reference vector is located in the middle triangle; table, each triangle is represented by a number called (S),
then, (13) and (14) are required to determine the sub- where S is a sum of several numbers. In section A, the sector
vectors. is identified and a number is added to S as illustrated in (18).
( |Ф|) = ( ) − 1 (18)
V1 = | | − 1 (13)
( )
Then, the number 18 is added to S if the reference vector lies
2 = 1 − | |
( |Ф|) (14) in the negative half of the sector while nothing is added to S
( ) when the reference vector falls in the positive half of the
Finally, (15) and (16) are needed to calculate the sub- sector. Finally, the numbers 1, 7 and 13 are added to S if the
vectors when the reference vector is located in the outer reference vector lies in the outer, middle and inner triangles
triangle. respectively. Fig. 11 also depicts the directions of the
switching patterns in each triangle which minimize the
( |Ф|) (15) number of turning ON and OFF for the switches and reduces
1 = | | − 1
( ) the switching losses when the reference vector travels from a
|Ф| (16) triangle to another. In addition, it is illustrated that each
2 = | | triangle is represented by a unique number to be able to
( )
retrieve the switching pattern of each triangle easily.
Note: Equations (11) to (16) calculate the sub-vectors
based on the new center point of Sector 1 and the
redundant vector for all triangles is provided in (17).
0 = 1 − 2 − 1 (17)
Fig. 9 depicts the axis locations of the sub-vectors
when the reference vector lies in one of the three
triangles. It also shows that the center of the hexagon is
shifted from the center of the 3-level SV diagram to the
center of Sector 1.
D. Shortening Sub-vectors
The simplified SVPWM method provides an optimized
selection of sub-vector reduction to minimize the error. The
values of the sub-vectors represent the percentage of each
switching states in a given switching cycle; therefore, they are
required to be shortened when their sum is greater than one.
Fig. 10 depicts the procedure of shortening the sub-vectors. It
illustrates that shortening is performed for the longer sub- Fig. 11. Directions of the switching states in 3-level SVPWM diagram

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 IV. SIMULATION RESULTS
In order to verify the functionality of the simplified
SVPWM method, a simulation model has been designed and
implemented in MATLAB/Simulink and the results are
discussed below. To check the robustness of the analysed
modulation technique, different faults have been applied. The
model is tested under an unbalanced capacitor voltages,
capacitor mismatch, capacitor short-circuit and sudden load
change.
Fig. 13 depicts the voltage and current sectors attained in
the simplified SVPWM. It is clear that the modulation
technique successfully derived the voltage and current vectors
to be in-phase.
Fig. 14 to 18 depict the simulation results for the ideal case
(no fault is applied) where the results illustrate a sinusoidal
input current, a low THD (less than 1%), a low ripple output
voltage, a well-balanced capacitor’s voltage and unity Power
Factor (PF).

Fig. 12. Example of pulse generation when Vref falls in Triangle 1

Fig. 12 depicts how the switching sequence is produced
when the reference vector falls in Triangle 1 (S=1). It
illustrates that the resultant sub-vectors are compared to a
triangular wave which then generates a 7-segment switching
pattern.
F. Capacitor Voltage Balancing
At the center of each sector, there are vectors that can be Fig. 13. Current and voltage sectors
applied using two different switching states; these vectors are
known as the redundant vectors. Although the two switching
states result in the same voltage vector, their effect on the
capacitor mid-point is the opposite. For example, if the
redundant state “100” charges capacitor C1; then, the
redundant state “011” charges capacitor C2. In order to
balance the capacitors’ voltages, a PI controller is used to
generate the required ratio for the two redundant states as
shown in (19) and (20).
01 = 0∗ (19)
02 = 0 − 01 (20)
Where k is the output of the PI controller.
Fig. 14. Input current of the rectifier
Table I illustrates the effect of the redundant states on the
capacitor mid-point.

TABLE I. IMPACT OF EACH SWITCHING STATE ON THE NEUTRAL POINT (N)

Switching State Current in Capacitor mid-point (io)
000 0

100 ia

001 ic

101 -ib

010 ib
Fig. 15. Input current's Total Harmonic Distortion (THD)
110 -ic

011 -ia

111 0

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 A. Capacitors Voltage Balance Under Fault Condition
In this test, a fault resistor is connected in parallel with one
of the capacitors (C1) to check the capability of the
modulation method. Fig. 19 depicts the resultant THD, PF,
output peak to peak voltage ripple and capacitor peak to peak
voltage ripple at different levels of faults. The fault is
represented by the ratio Rf/RL, where Rf is the fault resistor
and RL is the load resistor. The THD reaches around 4% when
the maximum fault is applied while it decays to less than 1%
as the fault is reduced, as shown in Fig. 19 (a). Fig. 19 (b)
depicts the change in PF as the fault is changing. The
Fig. 16. Output voltage of the rectifier
minimum PF is 0.9987 which is gained at the maximum
applied fault. Besides, the PF reaches up to 0.9999 as the fault
is decreased. Fig. 19 (c) shows that the output voltage ripple
reaches 14.7 V when the maximum fault is applied. However,
the capacitors voltage ripple are highly affected by this test as
shown in Fig. 19 (d). The voltage ripple is raised to around 60
V for both capacitors at the maximum applied fault while
reduces to less than 20 V at the fault is decreased. In general,
the modulation method is able to keep the capacitors’ voltage
balanced and to draw approximately sinusoidal input current
for this test.
B. Capacitors Mismatch Test
The second test is changing the value of the output
Fig. 17. Capacitor voltages of the rectifier
capacitor (C1) to illustrate the response of the explained
modulation technique. In Fig. 20, it is illustrated how
changing the capacitor values effects THD, PF, output peak to
peak voltage ripple and capacitor peak to peak voltage ripple.
Fig. 20 (a) illustrates the effect on the THD when the
capacitors are mismatched. It also shows that the THD reaches
5.25% when (C1) is reduced to half of (C2). As the value of
(C1) increases to be equal to (C2), the THD drops down to
0.98%. In Fig. 20 (b), the effect on PF is illustrated where the
PF is improving as the similarity of both capacitors is
increasing. In addition, reducing C1 to be half of C2 increases
the output voltage ripple to 25 V as illustrated in Fig. 20 (c).
Also, the voltage ripple in the capacitors is illustrated in Fig.
Fig. 18. Power Factor (PF) of the rectifier 20 (d) as reducing the C1 value to half of C2 increases the
voltage ripple on C1 to 40 V while it reduces the voltage ripple
on C2 to 15 V

Fig. 19. Results of the capacitors unbalanced voltage test

Fig. 20. Results of the capacitors mismatch test

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C. Capacitor’s Short-circuit Test
In this test, the capacitor (C1) is short-circuited for 20
switching cycles (2 ms) at t = 0.2 s (f = 50 Hz). Fig. 21 shows
the response of the rectifier’s input current while Fig. 22 and
23 depict the response in the output voltage and capacitor
voltages respectively. Both figures show that the output
voltage and input current reached steady-state in 60 ms.
D. Load Step Change Test
A sudden increment of 100% in the load is applied at t =
0.2 s in this test. Fig. 24 depicts the response of the input
current during this increment which reaches steady state in Fig. 24. Input current in a sudden load change test
less than 2 ms. In the other hand, the response of the output
voltage during this increment is shown in Fig. 25 while Fig.
26 shows the response of the capacitor voltages. It is
illustrated that the output voltage and the capacitor voltages
need around 50 ms to reach steady-state.

Fig. 25. Output voltage in a sudden load change test

Fig. 21. Input current when a capacitor is short-circuited temporarly

Fig. 26. Capacitor voltages in a sudden load change test

The simulation results illustrate the robustness of the
simplified modulation technique explained in this paper. The
simplified SVPWM shows excellent performance when
applying extreme faults such as unbalanced capacitor
voltages, mismatched capacitors, short-circuited capacitor and
sudden load change.
Fig. 22. Output voltage when a capacitor is short-circuited temporarly V. CONCLUSION
The simplified SVPWM for the Vienna rectifier is
explained in detail. The details for the duty ratio (sub-vectors)
calculation and synthesizing the reference vector are analyzed.
A MATLAB/Simulink model of the Vienna rectifier using the
simplified SVPWM at 70 kW nominal power is implemented.
The model is examined under several fault conditions. The
simulation results illustrated the robustness of the provided
modulation method as less than 1% THD, unity PF and well-
balanced capacitors voltage are attained. Furthermore, the
proposed modulation technique is shown to operate
successfully and balance capacitor voltages under the four
following tests:
Fig. 23. Capacitor voltages when a capacitor is short-circuited • Capacitor mismatch test
temporarly
• Sudden load change test
• Capacitor short-circuit test
• Capacitor voltage unbalance test.

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