Analog Physical Design
Analog Basic Building Blocks
Mostafa Nashaat
Feb 2019
Content
• Analog Building Blocks
– Passive devices
– Active devices
• Resistors
• Capacitors
• BJTs
• BULK CMOS
• MOS SOI
• FinFET
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Analog Building Blocks
Difference between Active and Passive Devices
• Active Devices
– An active device is any type of circuit component with the ability to electrically control electron
flow (electricity controlling electricity).
– Examples:
NMOS
PMOS
BJT
• Passive Devices
– Components incapable of controlling current by means of another electrical signal.
– Examples:
Resistors
Capacitors
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Resistors
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Resistors
Idea
• A Resistor is made of a strip of resistive layer
• Endings of the resistor can be significant so we should care about it
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Reistors
Diffusion Resistor
a) Diffused resistance c) N-well(or p-well) resistance
b) Diffused resistance into well d) Pinched n-well or (p-well) resistance
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Resistor
Poly Resistor
a) Poly Resistor
b) Poly Resistor with N-well Sheilding
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Resistor
Metal Resistors
• Metal Resistors are commonly used in
advanced technologies (FinFet)
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Capacitors
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MOS Capacitors
MOS-Cap Layout
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MOS Capacitors
• MOS Capacitors Pros/Cons
☹ They are highly nonlinear.
☹ Need a dc bias voltage.
☹ High sensitivity to process variations.
☹ Poor quality factor.
☹ Large temperature coefficient limit their use in many applications.
☺ High Density
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Capacitors
Poly Insulator Poly (PIP)
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Capacitors
Metal Insulator Metal (MIM)
• Pros and Cons
– Linear
– Have high Q.
– Exhibit very small temperature variations.
– Needs additional Mask.
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Capacitors
Metal Oxide Metal (MOM)
• Pros and Cons
– Linear
– Have high Q.
– Exhibit very small temperature variations.
– Low Density due to the relatively thick inter-level
oxide layers
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Capacitor Properties
• Voltage Coefficient directly affects the linearity
• Voltage Coefficient
– Poly Insulator poly : typically less than -100 ppm/v
– Metal Insulator metal :typically less than -100 ppm/v
– Dual MIM : typically less than -500 ppm/v
– MOS CAP : Not preferred to be used in precision applications
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BJT
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BJT
• BJT in CMOS process
– PNP
Emitter “E”
Base “B”
Collector “C”
• How can we make NPN ?
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BULK CMOS
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BULK CMOS
CROSS SECTION
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BULK CMOS
NMOS and PMOS
S D
S D
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BULK CMOS
NMOS and PMOS
Width
Length
Width
Length
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BULK CMOS
Native Device
• Native NMOS Transistor :
– A transistor that has not undergone the channel doping process.
– It has a lower threshold voltage because it must rely on the intrinsic background or body of the
transistor to set the threshold voltage.
– The typical native transistor threshold voltage can range from 0.1V to 0.3V.
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BULK CMOS
Fingers and Multipliers
Fingers Multipliers
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BULK CMOS
Fingers and Multiple
• Example:
– Fingers=2
– Multipliers=4 f1 f2
M1a M1b
M1c M1d
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BULK CMOS
Multi Fingers
• Could we use Multi fingers?
• What are the enhancements to use Multi-finger?
w = 8 um
l = 0.5 um
nf = 1 w = 2 um
l = 0.5 um
nf = 4
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MOS-SOI
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MOS-SOI
General Infromation
• When transistors are constructed in a very thin layer of
silicon, deposited on top of a thick layer of insulating SiO2.
• This process is called SOI “Silicon On Insulator”.
• The top Silicon layer is used for active devices while the
bottom bulk Silicon substrate acts as a mechanical support.
• Choosing insulator type depends on the application;
Sapphire (Aluminum Oxide) is used for radio frequency
applications (RF) while Silicon Dioxide is used for
diminished short channel effects in microelectronics
devices
• All other proceeding MOSFET steps remain the same.
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MOS-SOI
CROSS SECTION
Bulk CMOS SOI CMOS
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MOS-SOI
Types of SOI MOSFETs
• There are two type of SOI devices: PDSOI (Partially Depleted SOI) and FDSOI (Fully
Depleted SOI) MOSFETs.
• PD-SOI refers to a partially depleted • FD-SOI is the opposite of PD-SOI, where
channel; i.e. the Silicon film deposited the Silicon film is thin enough, so the
over the insulator is thick. Thus, the SOI channel is completely depleted of the
layer thickness is thicker than the majority carriers. Hence, the SOI layer is
maximum depletion width of the gate. much smaller than the depletion width
of the device and is tightly controlled by
the gate .
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Latch-Up Free Operation
• Due to the presence of buried oxide as an insulator, SOI technology ensures the devices operate in a Latch
Up-Free operation.
Top view of N+/PW and P+/NW STI diode
Bulk CMOS SOI CMOS
FinFET
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FinFET
Motivation to use FinFETS :
As gate lengths are reduced ,Short channel effects should be considered as it has a great
impact on the performance of the IC .
As the drain voltage increase ,threshold voltage decrease and off-Current Increase and
the channel become uncontrollable by the gate
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FinFET
Cross Section
Tsi : The thickness of the Fin.
h : Fin Height
2nh : Effective Gate Width
P : Fin pitch(minimum pitch between
adjacent fins allowed by lithography at a
particular technology node)
In Fig(a):Shorted Gate, This can serve as a
direct replacement for the conventional
bulk-CMOS devices
In Fig(b):Independent Gate, the top part of
the gate is etched out, giving way to two
independent gates. Because the two
independent gates can be controlled
separately, IG-mode FinFETs offer more
design options
Types of FinFET
Thank You
