5.2 Flip-flops Practical synchronous sequential systems use fixed amplitudes such as voltage levels for binary signals. The synchronization is achieved by a timing device called.a master-clock generator, which generates a train of clock pulses. The synchronous sequential circuits that use clock pulses in the inputs of memory elements are called clocked sequential circuits. The memory elements used in A flip-flop circuit has 2 inputs: one for normal value and one for complement “Value of the bit information, Binary information can enter a flip-flop in a number of ways. A flip-flop circuit can maintain a particular binary state indefinately as long as power is delivered to the circuit, until directed by an input signal to switch States. Flip-flops are of various types and each differ from the other in the Digital Systems Page No.: 137.chronous Sequential Lo; 7 ae AUS MEYH Units number of inputs they possess and also in the manner in which the inputs affect the binary state. 5.2.1 Basic Flip-flop Circuit A flip-flop cirouit can be constructed either using 2 NAND gates or 2 NOR gates, The flip-flop has two inputs, set and reset, and has 2 outputs Q and Q'. This type of flip-flop is also called as an RS latch. The fig. 5.2.1 below shows the basic flip-tlop circuit using NOR gates :! R __ srjal a 0 (reset) Q 00 | no |change 4 la Lo 01 1 O ico ni O10 | 4 S (set) 2 —9 a8 oO 1 £ Fig. 5.2.14 Initially assume that S = 1 and R = 0. We know that the output of a NOR gate is 0 aif any input is 1, while the output is 1 only when all the inputs are 0. As a result, G = 0 which is now one of the inputs to gate 1. Both inputs to gate 1 are 0, output Q= 1. When the set input S of gate 2 is made 0, with Q=1, the output of gate 2, Q = 0. The two inputs to gate 1 are 0 and 0, while the output of gate1, Q=1 with $= 0, if R=1 then Q=0 while Q = 1. When a 1 is applied to both the set and reset inputs, both Q and Q outputs go to 0. This condition violates the fact that outputs Q and Q are complements of each other. In normal operation, this condition must be avoided by making sure that 1's are not applied to both inputs simultaneously.‘synchronous Sequential Logic Unit 5 ‘The fig. 5.2.10 below shows the basic flip-flop circuit using NAND gates. sRrjaa el a 10 fo 4 11 Jo 1 | Sters=tR=0) 0 1 11 | (afterS=oR=1) tee ese a oof]14 R Fig. 5.2.1b ‘The above NAND gate basic flip-flop circuit operates with both inputs normally at 1 unless the state of the flip-flop has to be changed. With the set input made 0, Q=1 with Q = 0, thus making the flip-flop go into the set state. After the set input returns to 1, 0 to the reset input causes a transition to the clear set. When both inputs go to 0, both outputs go to 1 —a condition which is to be avoided in normal flip-flop operation. 5.2.2. RS Flip-flop The RS latch discussed in 5.2.1 responds to pulses applied to their set or reset inputs. In digital systems events such as these must be synchronized, so that they all occur at the same time under the control of clock. In such synchronous systems, RS latches change state only when a clock pulse is applied to them. The modified circuit called a clocked or synchronous RS latch is as shown below: R— 5 Q [Qa R_S| Qui || RS | Qn LJ 0 0 of 0 |{00]a o oi 14 o1}1 ooo o 10} 0 |{10 jo _ 1 00 1 Function Table PNY A) 1 Omelet ee P ia.hol_o State Table Page No.: 139 Digital SystemsSynchronous Sequential Logic Aismest Unit 5 In the above circuit, when the clock is low the output of both AND gates is 0, Therefore the NOR gate inputs are both 0, which is the no change condition, Thus the latch cannot change state when the clock is low, regardless of how the R and S inputs to the AND gates change. When the clock is high, the output of each AND gate is the same as its R or S input. In the truth table shown above, Q, is called the present state i.e., state of the flip-flop before the arrival of the next clock pulse. Qn. is the next state, the state that results from the clocking action. In the function table shown above, Qh.: is the same as Qn when R = S = 0 (no change) and that Q,.; is 1 or 0 otherwise, depending on R and S. 5.2.3 D Flip-flop The undesirable condition of RS flip-flop i.e., R = S = 1 at the same time can be eliminated in the D flip-flop as shown below: aD [Om . [?>—f" Q 00 | 0 ei i 10 | 0 cP 11 1 ol : >, ‘As shown above, the D flip-flop has only two inputs: D and CP. The D input goes directly to the S input and its complement is given to the R input. A long as the pulse input is at 0, the outputs of gates 3 and 4 are at level 1 and the circuit cannot change state regardless of the value of D. The D input is sampled when CP= output Q goes to 0 when the circuit goes to the clear state. The characteristic - If D=1, Q output goes to 1, making the circuit goes to the set state. If D=0, table for the D flip-flop is also shown above and it can be seen that the next state of the flip-flop ‘Q,.1 is independent of the present state Q. Since Q,,.; is equal to the input D whether Q is equal to 0 or 1. This means that an input pulse willgynctronous Sequential Logie Unis sypetvonous Seay sfer the value of the input D on to the output of the flip-top independent tran the value of the output before the pulse was applied 5.2.4 JK Flip-flop ; . JK flip-flop is a refinement of the AS tliption ie. the indeterminate state of thg AS type is defined in the JK flip-lop. The two inputs t0 the JK tlipslop ie. Jig 4g, get and K is for reset. When both the inputs J and K are equal 80 1, the tps, gwitches its complement state ie., if Q=1 then it switches to Q=0 and vice vers, AJ fliptlop built with two NOR gates and two AND gates is as shown: below. Qu Kia 0 0 0} 9 0 oO 1/9 0-10 4 Orig | 20: OF 7 104) 9 1ailo ‘The output Q is AND ed with K and CP inputs so that the flip-top is cleareg during a clock pulse only if Q was previously 1. In a similar manner, output 0 ig AND ed with J and CP inputs so that the flip-flop is set with a clock pulse only when @ was previously 1. When both J and K are 1, the input puise is transmitted through one AND gate only: the one whose input is connected tothe flip-flop output that is presently equal to 1. Thus if Q=1, the output of the upper ‘AND gate becomes 1 upon the application of the clock pulse, and the fipop is cleared. If Q=1, the output of the lower AND gate becomes 1 and the flip {lop is set. In either case, the output state of the flip-flop is complemented. Because of the feedback connection made in the JK flip-flop, a CP pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement) again. The complementing goes on until the pulse goes back to 0. To avoid this] Digital Systems Page No. 141synchronous Sequential Logic mays ey _ cies undesirable operation, the clock pulse must have tune duration, which is shorter than the propagation delay tune of the flip-flop. This is a restrictive requirement, since the operation of the circuit depends on the width of the pulse. For this reason, JK flip-flops are never constructed as shown above. The restriction on ine pulse width can be eliminated with a master-slave or edge triggered construction.5.3.1 Master Slave Flip-flop A master slave flip-flop can be constructed from two separate flip-tlops. One circuit serves as the master while the other acts as the slave and the overal circuit is referred to as the master salve flip-flop. cP peels ae ea +> y | s S —a C Master am Sate | ¥ | R R + _@ | aid] The logical diagram of an RS master slave flip-flop is shown above. As shown above, its consists of a master flip-flop, a slave flip-flop and an inverter. Wh clock pulse CP is 0, the output of the inverter is 1. Since the clock input of theSynchronous Sequential Logic A\Sn € 1A Unit 5 slave is 1, the flip-flop is enabled and the output Q is equal to Y, while Qis equal to Y. When the pulse becomes 1, the information at the external R and S inputs is transmitted to the master flip-flop. The slave flip-flop is isolated as long as it is at 1 level, because the inverter output is 0. When the pulse returns to 0, the master flip-flop is isolated, which prevents the external inputs from affecting it The slave flip-flop then goes to the same state as the master flip-flop. The master slave combination can be constructed for any type of flip-tlop by adding a clocked RS flip-flop with an inverted clock to form the slave. A master slave JK flip-flop constructed with NAND gates is as shown below. J 3). cp. : As shown above, it consists of two flip-flops: gates 1 to 4 form the master flip-flop and gates 5 to 8 form the slave flip-flop. The information present at the J and K inputs is transmitted to the master flip-flop on the positive edge of a clock pulse and is held until the negative edge of the clock pulse occurs, after which it is allowed to pass through to the slave flip-flop. The clock input is normally 0, which keeps the outputs of gates 1 and 2 at the 1 level. This prevents the J and K inputs from affecting the master flip-flop. The slave flip-flop is a clocked RS type, with the master flip-flop supplying the inputs and the clock input being inverted by gate 9. When the input is 0, output Q is equal to Y and Q is equal to Y. When positive edge of a clock pulse occurs, master flip-flop affected and may switch Digital Systems ‘ Page No.: 144states. The slave flip-flop is isolated as long as the clock is at level 1, because the output of gate 9 provides a 1 to both inputs of the NAND basic flip-flops of gates 7 and 8. When the clock input returns to 0, master flip-flop is isolated from the J & K inputs while the slave flip-flop goes to the same state as the master — flip-flop.