Institute of Technology of Cambodia I3-GEE-B Digital Electronics and Microprocessor

Exam: Combinational Logic Design

1. Problem
Problem1: Derive the Boolean equation for the circuit below. The switches are inputs (K1,
K2, and K3). The lamp L is the output. (K1 is close when K1 =1; K1 is opened when K1 =0 )
(L = 1 when light is ON, L = 0 when light is OFF)

Problem2: What is the Boolean expression of Y?

Problem 3: A majority gate produces a TRUE output if and only if more than half of its inputs
are TRUE.
• Complete a truth table for the 5-inputs majority gate.

Problem 4: A parity bit is extra bit included with a binary message to make the number of
1’s ether odd or even. The message, including the parity bit, is transmitted and then checked
at the receiving end for errors. An error is detected if the checked parity does not correspond
with the one transmitted.
Consider a 4-bit message, design a logic circuit that generates the even parity bit. The inputs
are m0, m1, m2 and m3. The output is the parity bit P.
• Draw a truth table for the circuit.
• Using K-map to derive the minimal expression of P.
• Draw the design of the circuit using logic gates.

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2. Solution
2.1 Problem 1
For the given system and conditions, we can develop the truth table of the circuit as,

Truth Table:

K1 K2 K3 L
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Now we can make k-map and then derive the Boolean function of the circuit.

So the logic function is,

𝐿𝐿 = 𝐾𝐾1 𝐾𝐾2 + 𝐾𝐾1 𝐾𝐾3
⟹ 𝐿𝐿 = 𝐾𝐾1 (𝐾𝐾2 + 𝐾𝐾3 )
For the lamp to glow, K1 is mandatory to be closed and either or both of K2 and K3 to be closed.
Required Boolean equation for the circuit is,
𝐿𝐿 = 𝐾𝐾1 (𝐾𝐾2 + 𝐾𝐾3 )

Thus: From the circuit above we can derive the Boolean equation to 𝐿𝐿 = 𝐾𝐾1 (𝐾𝐾2 + 𝐾𝐾3 )

2.2 Problem 2

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From the circuit logic gate above we got:

𝑎𝑎 = (𝐵𝐵𝐵𝐵)′
𝑏𝑏 = (𝐷𝐷𝐷𝐷)′
𝑐𝑐 = 𝑎𝑎 + 𝑏𝑏 = [(𝐵𝐵𝐵𝐵)′ ]′ + [(𝐷𝐷𝐷𝐷)′ ]′
′ ′

⇒ 𝑌𝑌 = 𝐴𝐴𝐴𝐴 = 𝐴𝐴(𝐵𝐵𝐵𝐵 + 𝐷𝐷𝐷𝐷)

Thus: From the circuit logic gate above we can derive the Boolean expression of 𝑌𝑌 is
𝑌𝑌 = 𝐴𝐴(𝐵𝐵𝐵𝐵 + 𝐷𝐷𝐷𝐷)

2.3 Problem 3
• Determine the truth table for 5-input majority gate:

Input Output
A B C D E Y
0 0 0 0 0 0
0 0 0 0 1 0
0 0 0 1 0 0
0 0 0 1 1 0
0 0 1 0 0 0
0 0 1 0 1 0
0 0 1 1 0 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 1 0
0 1 0 1 0 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 1 1
0 1 1 1 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 0 1 1
1 0 1 1 0 1
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 1 1
1 1 0 1 0 1

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1 1 0 1 1 1
1 1 1 0 0 1
1 1 1 0 1 1
1 1 1 1 0 1
1 1 1 1 1 1

2.4 Problem 4
Draw a truth table for the circuit
𝑚𝑚0 𝑚𝑚1 𝑚𝑚2 𝑚𝑚3 𝑚𝑚0 ⨁𝑚𝑚1 𝑚𝑚2 ⨁𝑚𝑚3 𝑃𝑃
0 0 0 0 0 0 0
0 0 0 1 0 1 1
0 0 1 0 0 1 1
0 0 1 1 0 0 0
0 1 0 0 1 0 1
0 1 0 1 1 1 0
0 1 1 0 1 1 0
0 1 1 1 1 0 1
1 0 0 0 1 0 1
1 0 0 1 1 1 0
1 0 1 0 1 1 0
1 0 1 1 1 0 1
1 1 0 0 0 0 0
1 1 0 1 0 1 1
1 1 1 0 0 1 1
1 1 1 1 0 0 0

• Using K-Map to derive the minimal expression of 𝑃𝑃

𝑚𝑚2 𝑚𝑚3
𝑚𝑚0 𝑚𝑚1 00 01 11 10
0 1 0 1
00
1 0 1 0
01
11 0 1 0 1

10 1 0 1 0

Form the K-Map above we can derive the Boolean expression as:
𝑃𝑃 = (𝑚𝑚2′ 𝑚𝑚3 )(𝑚𝑚0′ 𝑚𝑚1 + 𝑚𝑚0 𝑚𝑚1′ ) + (𝑚𝑚2′ 𝑚𝑚3 )(𝑚𝑚0′ 𝑚𝑚1′ + 𝑚𝑚0 𝑚𝑚1 ) + (𝑚𝑚2 𝑚𝑚3 )(𝑚𝑚0′ 𝑚𝑚1′ + 𝑚𝑚0 𝑚𝑚1 )

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But by the formula:

(𝐴𝐴′ 𝐵𝐵′ + 𝐴𝐴𝐴𝐴) = (𝐴𝐴 ⊕ 𝐵𝐵)′ (1)
(𝐴𝐴′ 𝐵𝐵 + 𝐴𝐴𝐵𝐵′ ) = 𝐴𝐴 ⊕ 𝐵𝐵 (2)

Thus: The Boolean expression of 𝑃𝑃 = 𝑚𝑚0 ⊕ 𝑚𝑚1 ⊕ 𝑚𝑚2 ⊕ 𝑚𝑚3

• Draw the design of the circuit using logic gates.

m0
Inst2
m1
P
m2

m3

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