MICRO ROCESSO S

A mi r proc ssor i a I ullipurpo e p · r, 1nn1abl , I cl -dri n r ister- a eel I ctr nic

devi th< l r ad bin ry it struction fr 111 , l rag d i e all d m mo,: \ ac pt bin ry
t a~ input and pru . . . . . ..,. .~s t.lata a cor lin to thos in tr 1 tion , n<l pr id r ult , ut-

- - Me mor 1

Mi r J-
proc :-.sor Input

utpuL

microcontrollers

that include all the components shown in Figure

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

Organization of a Microprocessor-Based System

Microprocessor

l/0
I
Input/ Output
A U I Register
I Array
I System Bus
_ _ _ j_ _ _ ,-----~ ~----✓

Memory
Conlrol
.---R-OM~I I.---R/WM------.,

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

Arithmetic/Logic Unit This i th ar a of the n1icroproccssor whcr anous ornputing
function. ar perform d n lat . Th AL unit performs such arithn1 tic op rations as
addition and subtraction, and uch logic op rati n as AND, OR, and cxclusi e OR.

Register Arra. This area of th microprocessor con i t of vari I reg· ters identified
by I tters su ·h as B, C, , , H, and L. h s r oi t r.., are pri11 rily u e I to tore data
L mporarily durin the , e uti n fa pr gran1 and are ace ssibl lo the user through in-
struction . .

Control Unit The control unit provide the nece. ary tin1ing m d c ntrol ~ ignal l all
th perati ns in th microcomputer. ll c ntroL th fl \ f da c betwe n the mi ro-
proc . or anc.J m ·mory and p riph ral. .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

I/0 (INPUT/OUTPUT)
The Lhird mpon nl f ( r icr races or-ba d y t n i I/0 input/ ulpul · it co1nmu-
nicates with the outsjd world. VO includ two typ s of d vices: inp 1t and utput; thes
1/0 de ice are also known a p ripherals.

SYSTEM BUS
Th system bus is a con11nunication pa h betwe n the 1nicroproc sso · and pe ·ipherals; it
i nothin but a g ·oup f wires t carry bits. ln fact , ther are s veraJ bu e in the y ten1
that wHl be is us in the ne t chapt r. All p ·ipherals and memory ha· th 1ne
bu ; how ver, th t 1icr proc sor cornn1l111·cate. ith only one periphe ·al at a ti11e. The
f 1ning i provided by th contro unit of the 1nicrop ·oc ssor.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

Mic oprocessor- nJ'ated Operations and 8085 Bus
Organiza ion

Th MP performs primarily four operations:*

l. M mor R •ad· Read,; lata ( r in trn tion. ) from m m r .
2. Memory Write : W1i tc data (or instruction ) into m mor .
3. 1/0 Read : Accept data fro n input d vice .
4. TIO Writ : Pntl.., data o u1pu1 <l vie •s.

A,, t - - - - - - - - - - - - - - - - - - - - - - -
1\i t------~

Memo1y
8085
Real
MPU World

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

ADDRESS BUS
Th address bus is a group of 16 line general ly identifi ed a A0 to A 1 • The addre bu
i unidirectional: hit flm in on di rion- rron Ih to I ·riph ·ni l <I· i · .._, 'I h
PU u1; . lh ~1<lclr s, "" lo pc rfiwni th 1r ·t un ·ti n: ide ntif ring a J riph rnl r a
m mory locati n St p 1 .
In a c puter ystem, each eriph ral I Ill Ill< r I ·nti n i'i id nttf1 . I b a bin, ry
nun her, ·allc.:d ml addr , an I th addr ·s bu· is LIS'd l ·any a 16-bit a dr s ·. This is ·im-

capacity to identify different memory tocati.ons (or peri.ph r.:ils) . The 8085 MP with ilS 16
add1~ s li nes i. capable of add res.! ing 2 1n = 65,536 (generally known as 64K) tuemory oca-

DATA BUS
he data u. i. a roup of ei ht lines used for data flow (Figure 3.1).* Th se line· ar
bidir tionn l da1a It l m b th ir rion. h twten the MPO nd me, my nd pel'iph -
ra l devices. Th PU u - s the da ta bu · to p r~ rm th cond fun 1ion: 1ran. fi rrin bi -
nary in formation Step_ .
Th ci hl ti rn linec;; n ble th MPU to manipu late 8-hit darn ran in from 00 to FF
(28 = 256 number.-}. The larg sl numb ' r thm ca pp d' on th la1a bus i I l l l l 11 J
l

(255 10). The 8085 is knm: n as an 8-bil microprocessor. Mi ·r pro ·es ·ors ·uch as lh lnL I
8086, Zilo Z8000. and otorol, 68000 have 16 daLa lines; thus they m· known as 16-
bit micr p1 ·e·· 1 ·. h~ Jnt 180386/486hrw· . 1 data lin s~ Ihus1 h la.. ifi I~
2-biL microprocess r .

CONT - 01 BUS
Th conrr 1 bus js comprised of ·11arious single lines thal carry synchronization signal.s.
h J\.llPU u es ·tu h Jines top rf rm ~h third f u11cl ion: pmvirliner Ii,; ·ITT:. si nals , S1ep 3).

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

Memor y Read Oper ho

A151--1 - - - - - - - - - - - - - - ------
-Bit Memory Address Address us
Ao ,---------------
Memory C 1p
06 = 0 00 0110 2000
78 :e: 0 I I 1 I 000 2001
8085
3 =0011 11 10 2002
MPU D7 F2-1111 0010 2003
8 ?004
0 2005
200

0 t Bus

MEMA Memory Read

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

The 8085 Pmgnrrnmao]e Regi~ters

.I
I .. I
I , I I I
Accumulator A (8) fla~ Register

B (8) (8)
D (8) (8)
H (R) L (8)
Stack Poin11:r (SP) (16)

Program ounter(PC) ( 16)

Address Bus

Bidir ct iona l Un id,rcctional

z AC p CY

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 E IS
he 8085 has six genernl- pll rpo. r i, Lers to stor> 8-bil <lata; tl1ese a1 identified as B.
, D, E, I }loci L. as . hown in Figure 2. I(b}. They can be com bin 'd as re ister l)airs-
BC, DE. and H - tu I , for m some 16- i l operations. The pt grammer can LI th e re -
i t r. 10 store or copy c.laLa iul the re isters by using data copy instructions.

ACCUMULAT O
'lh n llmulator is Ill 8-bil re 'stcr t .il ii; pa 'I of U1 arilhmeti ·/1 gi · unit {A l U). This reg-
ister is used lo tor 8-bil data and Lo p rfonn milh1netic and logical opernli ns. The result
of an OJ eration is ·t y; in th ri u1 ml or. Th "' a<.: ·umulator i. lso identified as r gist 'f .

ROGRAM C UNTER (PC) AND STACK POlN E {SP)*

Th s • ar tw l 6-bit rcgi ·1 rs u ed Lo hold memory adcll'es. . Th ·iz, of the. e r ·gi ·Ler.
i 16 bits becnusc the memor, lclr s es are J6 hits.
The 111 i ropro e .. 01 use th PC re2istcr lo · quence Lhe exc , 1Iio n of the instruc-
tions. h func tion f th pr gram co u1Hcr is c poi nl 10 lhc n, mory addres. fron which
rhe n L byte i. to b ~t hed. When a byte (machine cod ) is being fe tched, th program
· unter is iu 'I' ment d by one to point L the I c, I m mory lo at ion.
h ~lack pointer i. also a 16-bit n:: •i l -r used , s a m ~111 r p inter. It points t a
111 •mni·y locati n in R/W memory, 'Qll ·u the stack. Tin; b ~ginn ing or th swck i; <l fined
b load in e. a 16-bil add re.. in th· . la k poinl r. ' he ·tu ·k concept is , plniuetl in Chapter
9. ''Stnt·k aud ubrnutines."

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

FLAGS
The AL in huJc.s five flip-flops, wl1kh m· · s ·1 or r set after an operation accordin to
data condition · of lht! r' ult in the nccumulal r and otl r I egisters. TI1 y are call · I Zero
Z), C rry (CY), Sign (S , Parily , rrnd Auxiliary Carry { ) Ha ~: lhey are list d in
Table 2.1 aml th ir hi1 positions in th llc:1 r gister are. hown in H gur · .... l(c). The rnosl
commonly us d Hag-; nr Zero, Carry. and Sign. ,e 11icrnpmces. or use thes lla 0 to
w:1 li,w conditions.

D Z Zero: ,'h Z r I-tag is set to 1 , hen the re. ull i · zero: otht:rwise ii i.· r ~et.
0 C ·1rry: Ir an al'ithnu.:1ic opernlin n re. ults in a c:my, th C llug is ct: otherwise it is re
<; I.
D -Sign: TI1~ Sig11 llag h set if biL D7 or th t , ult= I; othcrwis it is sec.
D P - Pari t 1 : If the resu lt hH, an even number or Is. the flag is set: for nn ocld m1111bcr of I s, the
Llag i~ reset.
0 C-Auxiliary an l11 au arit llln tic p ratio11. vhen a c;m, i ge nerakd by digit f) 1 a11d
1:

pt11-sed L digi l D.1, the> C nag is set. Th i. f!.,g is used internally ~ r BCD bi11ar coded <.I ci-
mal} orera1 iou,; thc1 • is 11 Jump instruct ion a, sociated \ ith thL AalT ,

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

Memory Map and Addresses

Typically, in an 8-hil micropr c s ,· system. 16 a<ldr lin . r available f r in mory.

Thi means il i a uumb ring y ·t m or l binary bits and i pable of ide ntifyin, 2u
(6 ,536) memory regi t rs, each r gi ·ter wi h a 16-hiL addre h 1H i1 e m mory ad•
dresses can ra n e from U 00 lo Fr • • in I lex. A 111 mory map ii; a pictorial r pr :-. ntation
in which memory devices 31-; locat ·din lh ntire range of ad r's. es. Memory addr sses
provide lhe l ali n. of v. rious memory devic . in the syste , and the interfacing logic
defin s th range of m mory acldre ses for ea h me111 ry de ice. ·1h cuu cpl of me mory
ma and m rnory addresses can b ill ustrar ci wit h an analogy f id ntical hou · · uilt in
s quence and th ir p stal ddr sse , or m11n r. .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

THE 8085 MPU

10

OL1

The low-mder address bus of rhc 8085 micropmc essor is tJmEtiplexed (tjme-shared)
with the data bus. The bu · s n ~eu o be demu ltiplexed.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

The 8085 Microprocess or

The 8085 co11111101il known as the 808 ) ii-. an 8 bit general-pu q o. t.: micr proce,. OI'
capable.: J' adclr ssmg ( I< of rncmm . Tli device has fo11y pins, r quir s a +5 V single
power ~upply. and can 01 rate with a 3-MI 11 in°1 -phasv cit ·k. 'I he 8085A-2 version
, n pc1ate at th~ lllaximum frequency of 5 MHz. he 8085 is an e nhanc d v rsinn ol its
p1\:dc<.: ,~ r. the 8080A: it ins(ruction set 1s upward-compatihlc wilh thaL of the 8080A,
111 ,ming that the 085 1n-.,t1 11 ·tion · I includes all the 8080 in tI uc.:tions plus ,omc adcli
tional ones .
f,'i 0 ur 4. r sh w, Lh logic: pint 111 ul th · 8085 nucruprocessor. II the signals can be
classified int l six group : (I) addr ·ss bu . (2) data bus. (3) control and srntus si nal.s, {4)
ower supply a11cl frcq11 •nc "ignat,. (5) exkrnnlly 111itial · I signal • and (6) c.;erial I/ pons.

A DRF.SS BUS
Tile 808. ha 16 signal linec.; (pins) th;11 ar' used as the address h11s: hnwcv r. these lines
,Ir·-;pJit into two segment,: ,., As anc.l A 7 - AD 0 . Th~ {ighl ,ignal Imes. 1s- s, arc

unidirectio n, I and u:cd for the mo. t . i!!nificaur bib. called !he hi h~ord r utldr •s-;, fa
16~hil ad tJ r, ·\. h signal lin . AD 1 D11 ar used for a dual puq> '. as explajned in the
11 .. ' ( s ct ion.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

 MULTIPL XED AD RESS/DATA B S
The signal lin AD I D0 ar bidirectional: th' rv • a dual purpose. h y ar' LI ·cd as
I he low-ord 1· address bus as well , s I h · data bus. In execuli 11° au im,tru<.:tion. during the
l.!arli "r part f the cycle, the. Jin·:-. are used as the low-order ,1dtl1 ·s bus. During the I rer
part of th ycle, lh s-- Ji n s are use as the data bu . (This i: nls known a: 1nultiplc ng
the bu. . ) Ho\ "Ver. th low-order addre . . hlt 'an be ~ parated from the e signals b us-
i11) · lat ·h.

CONT OL AND STATUS SI NAL

This gl'Ot1p of signals includes l Wo <.:Onlrol signals (RD and WR . thr"' ,;;tatus signals
tlC)/- . S 1• und S41 ) Ll> id nLil'y the nature f the opt!ralion, and one special ignal (A E.)
to intli<.:al, th beginnin or Lhe p I tion . Th, , signals are o. foli o,; s:

D ALF Addi •ss luLch Enable: Thi. i. a positive going pul. e gen rateu ever time Lhe
8085 begins an )pcnit im1 (machine cycle ; it indicate. that lh hit~ on AD 7 - AD 0 aie
acldres.s hit. . Th i~ . i •1ml is used 11ri111arily to lal h th low-order ilddress fr m lb mul-
l i ple,, cd bus m1<l generate a s pn1. t" -;cl of ighl address Ii ne , 7- 11.
D R - cml: This is a Read control si0 nal (aclive low . This . if nal ind i ·ates that the se-
1 cl tl l/ or memory d vi ' i,;; to read and data ore a Hi lnble on lhe data bu..
WR- Write: hi .s is a Write control si nal (act iv JnwJ. This signal indicate.s tha t the
dat~ n the datu bu · are to I e wri1tc1 i11lo n s •l ·ted memory ol' [/0 I > ·:1lion.
D IO/ : ,is i: a slalll~ . ignul w,"'U lo <lifferentiat bet, een T/0 ind memory operations.
hen it is 1111::,h, il i11<li ·at s an 1/0 operat ion: wh nit LJ_ w, it indicares a memory op-
erati n, his ·ignal 1s omhined wi11l Rr> (Reau) and WR (Wi itc) 10 gc 11cratc 1/0 and
111cm r I control signals.
D •1 and S0 : The. c st.illls signal , . imilar to 10/M. ·:ui it.I 111ify various ren1tions, hul
the I re rnrdy lls~d in s mall s , Lem. , ( 11 the operations and thcii- a-.;<.;ocialeu slulus
. i, 11ah m' listed in Table 4. I fur r ·foren .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

POWER SUPP ~ AND C:10CI{ FR QUENCY
The power supJ>ly and frequency s ign Is are as fol low.s:

D Vcc: +5 V power supply.

D V.i;s: GrnumJ Refere11ce .
D X 1, X::!: A crysrnl (rn- RC. LC nehvurk) is con nec ted ar lhcsc lw pins. T he fre~ue ncy
is in ternally di vitl d by fwu; therefore, to operate r1system at J Mllz. tile crysr l sho ul d
lrnve a 1"1 lJUt:11cy of 6 MHz ..
D CU( (OUT)- 'lock On1put: Thi· sig nal c-an be used as rhe :s ste m clock for other
devices.

EXTERNALLY INITIA ED SIGNJ\LS, INCLUDING N'l'ERRUPTS

T he 8085 has fi\'" int l'l'Upt 5ignals .- Tab! · 4.2) lhat can he LL ed lo imerrupl a p1ogram
xec utio n. One ol the sigmds, INTR (I nterrup t Requ' I), is identica l to the 8080 mi ro
pro 'SS r in tem tp l signal (1 T); the ot hers are enhan emcnt · to th 8080 . he micro-
processor acknuwle<lge. an interrupt I qu ' t by the INTA (Interrupt Acknowlcrl 0 c) ~ig-
nal. (T he interru pt pro 'l:~s is di. cussed in Chapter 12.
In dd ition t the mter ni pt , 111t'ee pin s-RES T. H D, ,inti RE DY- acce pt th
ex ternally in itiatecl si nal. a. mp ut ,_ To 1 • p 11d I the 110 D requesl, th 085 hm, one

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

0 IN Input Interrupt Reque t: This i. u:Ld as a •cncral pu1 po e inte11 up1, it is i.in11 •
lat lo th · (N ,ig nal o th 8080 .
D A (Outpul) ]nt ~rr11pt Ad.nowll.:dg ·: Tl ui. b u etl lo n ·knowl d~c an intcnupl.
0 RST 7.5 clnplll J Restart lnlc1rupl. : J he ·e nre ve · to red int ~rrupl s th.it l1,m:.. lcr the pro-
R "f 6 !nllll co ntr 1 to ,p·cific memory lm:mi 11:... They ha, hi~h r pri ri ti • ·
RST 5.5 tha11 111 1 R int rrupl. Among the c lh t • • the pnorny orJcr 1s 7.5
6.5. anrl • .5.
TR P ( Input ) ' h i, is a nonma I ub k u1te11 upt aml ha s th hi 0 hc,t p1101ily.
0 II 1) ( l11p 11 ) 1i ignal indicates that a p,•riphe ral -; uch a· a D 1 1• mo1
Acee:..~) 1,; ntr II r i, request in the me ol' lh ~ ad I ,
0 HLDA (Out rut I Hol c no,1. ledre: tm. signal Jdllrn\ kJ g 'S th HOJ
R , D (Input) hi s1 •nal i~ u, d to ut.:la , t 1c 111i ·wp10 '"°' Read or n lc q 1de, 1111-
111 a Im rc-.po11<l111 p ·n 1IP tal 1s r ady 10 · •ntl or m:cept datu \Vfpn
this s1gm1l gne I lw, 1he microprocc. sor watl\ l , ait ltllcg1,1I 1111111 ·r
,t clod, ~- ,• ·ll · 1ml ii it ,c ·:, high.

signal c·,llec HLDA (T old Acknowledge). The functi 1 s of th se ~ignals were previously
dhcL1ssed in Sec tion 3 .. 3. he RESET is gain d cribed below, and otl ers a ·· Ii ted in
Table 4.2 I~ r l' .r ·rence .

RESET I : W hen lh "' · gnal on thi s pin goes low, the program counter · t to zero,
the bus s at t i-st. teJ, and the MPU is res t.
D S TOUT: his signal ind ' at-s thal the MP is being cset. , he signal can u d
tu reset other d v i

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

SERIAL 1/0 PORTS
The 80 5 has lwo signals to imp] rn nt the ·erial transmi. sion: SID S rial Input Data)
amJ SOD (Serial Output D la). In serial transmission, dat.i bit ar sent over a sinol · lin ,
one bit at a tim such as the lransrni. si o11 v r I l phone lines. Thi. wi ll be discussed in
Chaptel' 16 on s'riaJ 1/0.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

Microprocessor Communication and Bus Timings

Data Bus

Memory
B C
2000
ALU In. rru lion D
Decoder
H L
2004
S1ack
4F 200S
Pointer
Program
Coun1 r

Con1rol
2005
Logic Addres Bus

4F
RD

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

Step l: The 111icroprocessor pla "s the 16-bit memory addre -s frotr lhe pro •t m
'Oll nrc.;r PC on th, mklr ss bu~ (Figure 4.2). In ou1 an,ll ogy, thi, is 1hc quiva-
l •111 nf our cou1ier gellmg on the road to find th address.

Ste() l: Til1e co11trol. un i[ s nds the control sig1 al RD t enable the mer ory c hip (Figm·,
4.2). This is similar co l'ingi. ng the doorbell in our analogy of .-1 package pickup.

Step 3: The byte fro1 lh memory location is plaoed on lhe data bus.

Step 4: The byle i::; plm;ecJ in the instn1ction d,:!eoder of the microprocessor, and the
la ·k i::; carried out accorrlin ° ro th . instruction.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

 Opc:od Felch

CLK

Low-Order
AD1 ""'•----- -----~
0511 4FH Opcode

ALE

IOtM
Stalus (OfM = 0, Su ;; I . S , - I

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

Demultiplexin g the B s AD'7 -AD 0

0 A,~
Ats
0
A 14
• I An
0 A1! High-Ord r

R0!!5 20H ~ A11 Addre. , Bu:.

fi ropror;e soi Aio
0 Ay
A 0 A11
A E l::.nable 'J G

07 AD1
0
0
~H::? Q ,, 0 A1
L-.il. A,,
AD,,
AD, 0 - ,_Q A~
0 0 A~
051l = ~
AD.i
!AD.1
AD 1
0
1
74 1.S37J -
1- L
0

A-.
A,
Low-Orde,
Addrc~~ B 11~

AD 1
0 ___JL A,
Du AD(1 I
oc .---l A11
I
~
0
D7
I D6
0 Ds
/ l _ _ •ll· H 0 04
I Dau Ru~
D1
I Dl
I o,
l l)"

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

Tlte need for demul1iplcxing lllf' bu: D 7- become, e.isi ·r lo understand after mu
ining Pi ure . J-.1. hi-. figur shm s that the mlclrcss nn the high-order I.Ju..; (20Tl) r~mains
on the hus for th ree clock periods. Howcv~r. lhe low-order addre. s (05 ) ls Jost after the

first clock period. hi. add1· s ne d · 1 he latched and u ·ed for identifying the memory
addre . lf lhe bus D.,-A O is used to identify the memory location (2OO5H), the ad-
dress will change t 204FH aft r the first Clo k peri d.
Figure 4.4 show, a schemt ti · t af u. es u latch amJ the LE signal to demultiplex
lhe bus. The bus AD7- AD0 is connected a · th ·· inpuL to U1e lat ·h 74 S373. 111e ALE sig-
nal is con11ected to th Enable (G) pin of the latch, and the Output control (OC) . ignal of
lhe latch i:- rrounded.
Figure 4.. shows lh aL the ALE go l1i.:,h during T 1• Wh •u the ALE is high, t •
la tch is transparent; th i' n nns that l he output chan 0 s according to input data. During T 1,
the oulpttl of the latch is O5H. Whe the ALE goes low, the da ta byte 05H i latch d un-
ti l the next ALE, arid 111 outpu t of the Ja tcl represen ts lhe low-order address bus r 11
flcr the latching operation.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

Generating Control Signals

8085
74LS32
101M i.----------,1'"--~

iffi t>----+-_,
WR

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 ◄igure 4.3 shows t~ RD (Read) as a conlr I . ignal. BecaL1. · thi " signal is used hoth for
readin memory and for readi11 .- 11 inpuL de ice, 't b nt!c~ssary lo genernte two diff rent
Read -ignals: one for memory und anolh r ro, in put. Similar! , two s~par, t Wrile ignals
must be generated.
Fi u c 4 . 5 shows that fou ,· lifr renl control si nals are generate hy ·ombin in g
the si rials RD, WR, and fO/M . 'fhe ·i n I J /M •oes low for the mc111 r I operation.
his signal is ANDed with RD and WR 1;ignals by usin g th 74LS32 quadrupl lwo-
mput OR ates, m; ·hown in Pigu1 .. 4.5. T he OR atcs ·tre functionally connectt::d as
negative NAN gate.. Wh n bolh input signnl. 0 low, the 01,1tputs o the gates o
1

low anti generat MEMR (M mory Read) nnd M ~MW (Memor Wnle) ontrol sig
mlls. When Llle TO/M si •nal goes hi 0 h, it indicates th pcriph ·ml 1/0 opel'ation. igure
. 5 shew that ti~ .sign I__!_'.!_ complemented usin° _ili_e Hex inverter 74LS0 and
AND ·d with the RD and WR signals to gen rate lOR (TIO Read) and lOW l/O
Write) control sigllrll&.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 Au t A1.s
Aa Aa
AL . } Add~•
Bus
AD, EN
ADo alch

+D1 Dall\ Bus

808S Do

10/M
M MR

RD
MEMW
WR
Control
Signals
IOR

iow

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

Memory Read Machine Cycle

M 1 (Opcode Fetch! M2 (Memory Read)

T,

32H Data

Memory Addrc~,

o,s I , S., 0

fW

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

1, h first machine cycle M 1 ( Opco.lc ·ld1) is identical in bus. timi11 . with th ma-
ch ine cycle il lu. tra ted in E ·ample 4.1, except for the lrns. cm t nts ,

2. n'r complc tiof lh

11 pcode F Leh y
I . the 8085 pla s the cldr . 00 I H on th'
a dres bu and increment. the p1ogram c; untcr t th next mkh ~. s 2002 H. he : c-
ond machi ne cytle M1 is idenlill I .is Iii· M ·mory R ad cycle (10/M = 0, S 1 = I. and
• 0 - 0):mdth~ ··as· rtd. l'f,. 1 RD.i nalbe me. tive.ndenallc. th
111 m I chip.

3. At the ri ing edge of 2 tie 8085 activates th da t.1 bus as an input bus, memory
place, the d la byt • 32H on l lP data bu s and the 8085 reads and . _re, the I yre in ti
a cumulator during TJ.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 10

 lnstm tion cy le · defint:tl as tli e tim · 1· :quit ti to complete the xcc 1tion of a n in-
strnctjon. The 8085 ins lruction cycle con is(s of 0111e to six machine cycles or one Lo ;sjx
opefllti ons.

Machine c •cle is u fi n ti a · lb time rcquir {! 10 o mplete on opcrali m of ace ss-

ing m mor , 1/0, or· ack.J10 ledgin an c t~mal r qu . t. Thi s c h: may con,;ist o ti r ·
l i · -. talc . In icrur 4.3, the in slruclio n cycl and th machin cycle a, th ' sam

T-st 1/e i •
fined as 11 1.; ubdivision f the op ration performed in 011 -lock p riod.
Thcs su div i ioni; are int rnal slat . ynchr ni zed ~,j1h th' sy. t ·m ·I ck, a nd each
·Late i preci. el ·quaJ t one I ck p<:riod. The term . Stale anti c lock period nr · flen
used . yn n mou ·I 1•

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 11

Th e "cutio11 1i111 s of th M mol"y Reau mach in cycle and the instrnctio n cyc l are cal-
'ulmed as fo l low :

rr
D Clo ·k ·qu nc:y f = 2 MHz
D T-state = clock period J/f} = 0.5
D Execution ti me for Ope.: cl Fet ' : (4 • ) x 05 = ~ls
D x ution time !'or Memory Read: 3 T) x . = 1.5 µ~
'xecutio n Lime for lnstrnction: (7 T x 0.5 = 3.5

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 12

THE 8086 INTERRUPT

Step 1: The inle1rn pl pro ·es · should b enab l d by \ rili ng th inslru tion El in th
main pro ram. Th is is imilar to keepin the phon re eiver on th hook. The
illSll1J lion El ~ ,. lh l nterrnpl ".nahl ' tlip-flop. h in. lntcti ,, DI re.<, 1-. the
flip-0 p an<l di:rnbl •s th · i11 l rrnp l procc s.
Stt:p 2: When th· ruicroproc ·s or b ·xccuting a pro •ram, ii cb ·ck~ lh · INTR tin· <lur-
ing the execution of each instrucli n.
Step 3: If th line I TR i hig h and lhe inte1r upt 1s enabled. the micr pr ce,,s I om-
pl ·t th url'cnt in. truction, di. hies the lntcrrurt •11abl' flip-nop, nd . end a
. ignnl call cl [NT - Int rmpt A ·knnwl ·dg (net iv - l w). The pro ,;or annot
accept any interru t requests until the interrupt fl ip-flop is enabled again.
Step 4: TIP signal INTA i. 11. ed to in. rl a re. tart (RST) in tructicm (or a Call i11st rll -
ti n thr ugh e.rtenwl l,ard11·arc. I h · RST instrn ·Lion is a 1-byl ' ·all instt u ·-
tion explained below that tran sfers the pro ram control le .i specific memory
locnt ion on p:.i e OOTI and rcstaI1. th c, cc11tion ::it 1ha1 memory locntiot aftc
xe ·u1ing St 'P 5.
Step 5: When Lhe microprocessor receives an RST in truct ion (or o 'al l instruction , iL
sa\' . the memory ac1 It ~ss or the n xi instru tion on the st, k. Thi is , imil, r to
inserting a bookmark. h program is trnnsfi 11 •d lo Lh · 'A L location.
Step 6: Assuming that the Lask lo b performed i \\,.nllen as a sub1oulme at the speci-
fied lm:atmn , the p10 essor perform tht: task. Tlm, snhrnut tll.: is kn< wn · s a
serv ice routin•.
Step 7: 1 he service routine hould include the insu·ucllon l:.L to em.hie the intemtpl
Huain. This is • i Ill i la, ro pulltn • the I ccc1' 'I' h::ick on t Ii IH )I .
Step 8: t tlic end of th· subtul1ti11 '. the ~ mslntctio11 1 ·hi ·v · th • m ·mor, m.ldr · ·
\ 'here the program Will> mletTupletl and continues the execution. Thi. is smtilar

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

RST (Restart), Instructions

'h 8085 in ·truclion sel include. eight RST (Restart) insLruction. Ii . led in SecLion 9.3.
Th are I-byte all instruction:-. that tran . fel' the prng1..11ll e ecu1 io11 to a ,pecifk loca-
tion o n page OOH, a li t cl in T,,bJ · 1-. 1. '1' RST in trn lions are executed in a similar
wa l that o all in ·truct1 11 ·• The addre:s in the prog·am unler (meaning the addre. s
or th ne t ins tru ction to an R T instrncLion) i. . 10.-ed on the tac k before the pro1?rnm
execution i. 1ra11sfcrred to the RST all locat ion. WI, n 1h • proc s: r nc 1111lcrs a R turn
instl'tl ·tion in t he ~ubrou1ine associated with the R T instruction , the program returns to
th address that was stored on the stack. l n ca. of. hardware in terrupt, w wi ll u. c an
RST in tru lion 10 rc1;,1nrt the progrnm c u1i 11 .

Resta1 t lnst1 uctions

Rimll"y ode
h1c111onk.11 07 n6 D-: , D.i 03 02 01 Do
R~TO ()
-0- 0 7
RST I 0 Cl·
RST :! ( 0 D7 001()
RS'l 3 () I DF 0018
RS I 4 0 0 E7 002
R.S ') 0 I El· 0028
RS t I (1 F7 001()
RSJ 7 I FF 00~8

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

 17 i1t1pl m 'nl l p 4 in th i ntenup l process. in · rt one of these instru tions in the
mkroprocessor by u. ing exLerw1l hardware and Lh . io nal TNTA (lntermpt clmowl-
ed-e), as shew n in Fi 0111-c 12. 1.
l n Fig Ir J . I, th in:t:ruction R T 5 h bui It 1si ng resistors and a lri-state buffer.
Hgure 12.2 shows 1e timing of the 808'.1 Inter upL Acknmvledo-c mnchinc cycle. To re•
spon. e to 1he rNTR (lntern1p1 Re 1 . I hi0 h signal. th . 808~ mh th INTA (Int •ffupt
Ack110 I dge) I \ ·ignaJ, whi ·h is u-;ec.l lo enable the buffer, and the RST inslru tion i.
placed o n the data bus duri ng M 1. During M 1, the progr.. m 011nter hol L Ih memory d·
dress or the next instruclion, which ._1,ould Ii st1 red 011 th '{ lack so that the progrnJLL can
conlinu aflcr the : ·rvicc rou tine. uri ng M , the address of th stack poin ter minus one
(SP - 1) location is placed 011 the addres. bu. , an the igh-order addrcs. f the pro Pram
counter i. :tored on the . tack . uring M:1, ti J« w-or<lcr ttd<ln.:ss of the pr gram counter
i. . tored in tl1c 11 'Xt lo ation (SP - _) ol 1h sla k.
The machine ycle M I f the Interrupt Ack no ledg is identica l will the Opcode
Fetch ycle with tw , cept ions he IN A signal i s ul l1I in l ·ad f th' signal,

and tJ1e status lin s (] O/M , S0 and S 1) m·c J I in l .id of 0 I l ( c Fi ur L.2 . Duri n°
1• the RST 5 is decoded, a ]-byte all instruction to location 0028 . TlP rnachin ·y-
dcs M1 and M 1 arc Memory Wri1c ycle. lhtll store the onte nts of the program counter
on the stad·, un<l the n a n ~w i nstrnction ·y l ·gins.
ln this nex Lin. lruction ycl e, the program is lrnnsferr d to locaLion 0028H. h s ·r-
vicc routi ne i. written . m whcr ls in memo ·y, and the Jump instruction is written al
00 H to specif'y the adtlr ss of 11i ~ ser i '" rou1i n . All th o;;e tep:; llf ll lu. !rated in rhe
foll w ing xample.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

 +5 V

ID k Ji.Stat
Bu et
Pl,
Dt11

0
EFH ⇒ o..us,
Dl1
.. 01 1
Dlo

L - - - - - - : ; :..-~~.::::_- rffl rro,nMicro1i1ocessor

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

8085 VECTORED INTERRUPTS

The 8085 has fi in Ie1rnpt inputs (Figure 12.5). One i1 callc I INTR (discussed i11 rh pre-
vi us section) thr ar called RST 5. , 6.5, and 7.5. r p ·liv ly, and the fi rth i · called
TRAP, a nonmn. kubl' inten upl. These last tour (RST. and TRAP) ar f\ Ll lomatically vec.:
tored (transferred) to specific locations 011 memory p.. 111 c 001-1 wi thoul an I xt rnal hard-
war . 11,ey do not requi 1c the TNTA signal I an inpul port; the nece.ssary han1war' is al-
ready implc111c11ted im,ide lht.: 8085. These intern1pt<; and their call lo ·atinns are as fo lio
lnterru1>ts Call Localiuns
I . TRAP -4 11
2. RST 7. 00 'H
3. RS'l 6. 0034H
4. ST .5 002 I I

The TRAP hm: the highest p1ioriIy. ~ II wed by R T 7.5, 6.5. 5 5. and INTR , in that
ordc1; however, th ~ TRAP has a low r prioriL · than lh Ho ld si nal used for DMA

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

TRAP

Priority lnpul Pm Ma&k Vector

I Location
2
n RST
1.5
D

CLR
Q

oo Cu;
Reset
RS 7 .5 lntem1pt Recognized
003816

J~_n_ RS1'
6.5 003416

00 o,,,
4-_n_ RST
5.5 002c, 6

0028 ,,,
1---4-fi 002416
002016
Dl
El s Q
0018 16
Reset R
Any Interrupt R ognized Interrupt 00101<,

5--~_n_ INTR
Enable
frorn E 1emul
llardwarc
00081<,
0000,(,

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

TRAP

TRAP, a nonmaskablc i11lermpt known ns NMl, is analogous to 1he smoke u,etecror de-
sc:ribtld i..:arlier. ]t has lh · highe1 t priority among the inre1n1pl signals. it need not be ~n-

ab led, 011d it ca nn t b~ di. nblecJ. 11 is le'tc l and edgc-sen\iliv , meaning thot lhc mput
hould go high and ':i la high to be a k1101vledged. It c:.inuot be acknowlerlp. ·d :~ ,ain unti l
it makes a tinnsi tion from high to low lo high.
Figure 12.5 shows that when thi5 i11l·rrupt i.'i triggered, the program c ntrol is
trnnsfcn- cJ to location 0024H vithou1 .iny external h rtlwar ~ ur 1he in1en up1 enable m-
slmction I. TRAP is g ncrally us ·cJ for such ~rit ical ·vents as pow l fa ilur~ and emer-
gency shu1 off

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

RST 7.6, 6.5, and 6.5

Th -·se maskable inrcrrup ls (sl,own in f igure 12.5) are c11, blt!c.l under progl'am con trol wi th
two in structio ns: El (Enable ln1 c rru pl) de cribed 1.:arlier, 111d SIM (Set Inte1rnpt l\•fa. k)
described belu v:

5 4 3 2 0

: ~ :~
M7.S M6.S M5.5

l { Mask Se l Enable
~~~~
RST5 .5 MASK

{
{ O
I

If 0, bits 0-2 ignored

tr I k t
= avai lable
= masked

, rna~ 1
RESET RSTI .5: If I, RST7 .5 flip-nop j5 re\et Off
Ignored
ff I, bil 7 i ou tpul to Seria l Ou1pu1 Data Laich
Serial Output Da111: ignored if b11 6 =0

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

lnsh·uction SIM: et Intcrmpl Mask. his is a 1-byt · i m,m1ct ion anJ t·m1 b used for
three <liff r -·ni func tions (Fig ire I __ 6 .

D On fun ·ti<11 is Lo set mask f r RST 7.5, 6.~, and 5 .5 i11l ~rrupl ,. This i nstru ·1ion reads
th cont nl uf tl1c. u cumulalor and enables r ch · ble. the int rmpls accordi ng Lo 1l1c
con tent of the accum ul m r. Bil D3 is a o ntrnl bit and should= I ror bits D0, D1. and
2 tu b, ffeel ive. Logi · 0 on 0 0, D 1, and 1 \ iII enabJ th~
correspondi ng interrupts,
and logi · l wi II disable th inl 'trupts.
These ond fu11c11on is I re:el RS 7. fli -flop (Figure 12.6). Bil D i~ addit.ionul
control fo1 RST 7.5. l f D..i = l. RST 7.5 is r~set. This h, us to overric.J · (or ign e)
RST 7. without ~ervi ing it.
D ' he thi rd function is co implem ·nl serial 1/( (di'Scuss cl in Chapter 16 . Bit. D7 and D6
of the accum u1. tor ar u ed for setial I/O and do nut :1lfoct the i ntenupts. Bi l D6 = l
enable.\. lhc crial 1/0 m1d it . 7 is used L trn11~1ni t (output) hit~.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

TRIGGERING LEVELS
These inlen-u1Hs nre ·ensit ive 10 differ Ill type of trig ering as lisle<l below:
D RST 7.5 Thi. is pus11ive-ed e 1,cn ilive and can b triggered w it h a sho11 pu lse. T h '
,eque l is stored i1lli.:rnally by the D llip-Hop (Figure 12.5) until the micru-
proces. or 1(!sponds to 1he reque ·1or until it i.- l .,tred by Reset or by bit D 1
i11 lhe SLM mstructton.
D RS '6.5 and RST 5.5 Thl!s' intem1pt. arc I vt>l-sensitive, 11m111 i11g that lhe lrigg r-
ing I vel sl1oukl be on until lh · microproce. sor l'nmpletes the e ·cution ot
the cun·ent instructio n. lf 1he micrnproccs.sor is unable to respond to tli esc
ret111 • ·ts irnme<l iately, lhey should be stored or hd,I l>y e:ternal hardware.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 ENDING !NTERRUP
Becaus her are everal i11lerru pt lines, when one inle rn1 p1 r qu st is b in served, o tl1er
interrupt requ, 1s may occur .md remain pending. The 808 has im additio nul in. true lion
call ~(I RIM (Reau IntcJ'J'u pt Mask) to . ense the pending inlerru1 ts.

In truction RIM: Read lnl rrupt Mask. Thi i. • I-byte instruction Lhat ·.mbe u. d for
the followin ftmc tion .

o r ad inlerr pt m. sk~. This instruction loads the acc umulal r with 8 bits imlica tin
Lhe cun nt status of lh · interrupt mask (Figure l .7 .
D To idenlif>, p nding interrupt . its 0 , s, and 0 6 (Figure 12.7) id nt1f lhe pending
i11t1,;,1 rupt. .
D lb r ·eive . erial data. Bit 0 7 (Figure l .7 is useu lo r~ eive serial d l .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 'n1e insrm ·tion RIM ch cks for a pen ling intenupt. Instruction ANI 20H masks all
the bits c pl D5 to c heck p nding RST 6.5 . 1f 0 5 = 0, the progr m 'Ontrol is tra nsfe1rd
to the 1£Lain program. D~ = I ind i l s thaLRST 6.5 is pending. lnscru ·tion ANl ODH sets
D 1 = 0 (RST 6.5 bit for SJM), in ·trnctio n ORI ets D3 = I thi is necessary for SIM to be
effe tive), and instruction SJM ~nables RST 6.5 with ut affecting any olher in terrupts. Th
J in tru · ion Iran. f ,,· · lhe progra to the servicer uline (S RV) wriHen for RST 6.5.

The RfM instruc1io11 loads 1lte a~umulator with the following inform· ion;
7 6 I 5 4 3 2 l 0
SJD I f6 ..5 !5.5 lb M7.S M6 ..5
11 ..s M5.5
Ly-)l~ -~y---" -y-Jl~- -y

l
J

L L JntemJp1 Mi. ks; I

lntemtpr nablc Flag: I = enabled
Pending InterruplS: 1 = pending
masked

S ria l Input Data Bit, if any

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

8085 Machine Language
Th 8085 i '. · mi ·ropro ~ ·sor with 8-bit word length: its instruction set (or language) is
de igned by using variou co1nbinations of Lh se eighl bits. Tl e 8085 ·s an i1nproved ver-
sio1 of the ear ier processor 8O80A.
An instruction · a binary pa' te ·n entered lhrough an input device in 1ne nary to
conunand t 1e n icroproce or to perform thot specific function.
For example:

OOJ ] 1100 is m1 inst ·ucf on that incre nent the number in the register caHed the
accumu~ator by one.
JOOO 0000 is an instruction that add the 1u nber in Ll e regi ter call d B to lhe
nun ber in the ccu11nu[alor, and kc ps the sum in the accum dato ·.
i:

The 8085 n1kroproces or has 246 such b1l palterns, amuunLing tn 7 different i1 -
:t ·uctio 11s for perfon ling vario 1 operaf ons. These 7 different inslructions are caHed its
instructio 1 set Th. s binary Jan 0 uage ,vith a predeterm.ined insln ction set is called the
808 5 n1achine Ian uage.

Be au it i l diou and err r-indu i c f r p opl to r co 0 ni ze and rit instruc-

tion in binary la1 i:,ua , th e instru tion s ar , for con ~nicn · , \ rilt n in hex ad cimal
code and nt red in a . ino-J -hoard rnicr co1np 1ter by 1, in He k y . r x, rnpl , th
binary instruction 0011 1100 (m ntion d previ u l y j quiv I nt t 3 in h , a I 11 al.
This instruction can be nt red in a . ingle-board micr c01nputer. y. t m with a H x y-
board by pressin two ys: ~ and . 1 h monitor program f the y tem tran. lat the
keys inlo th ir quiva l nt binary patt rn.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

BOSS Assembly Language
ven though th in truction an be writt n in h x im l c de, il i till diffi ult lo un-
der tand a program writt n in h ade imal nunb r . a h manufa tur r of a
mi ropro sor ha d i d a symbolic cod" or a ·h instruction, cal I d a mnemonic.
(Th word 11111e111011ic i · bas d on th Gr ck word m anin minc(fi,I; that is a men1ory
aid. Th 1ru1 m nic for a parli ·ular inslru ·tion consists of I tlers that su 1 0-est th opera-
tion to be perform d by that instru ·tion.
For , , mpl , th binary code 0011 1100 (3C 16 or 3CH* in h xadecimal) of th
8085 mi ropr e r i r r s nt cJ b th mn rnoni · JNR A:

INRA INR ·Land f r incr n nl. and A r pr ·nts th accumulator. This symbol
ug 0 t · th op r, lion of incr n1 nting th , c umulator ont nls by on

Similarly. the binary ·od 1000 0000 (80 16 or 80H is r pr s nted as

ADDB ADD and f r additi n. an<l B r pr nls th

cont nts in register B. This
symb 1 ug t th addition f th c nlent in register B and lh cont nts
in lh a u1 ul, t r.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

 An instrudion is a comma nd to th, rnic1op1 es ·or lo perform a given tn k on specili ,d dat.a.
Each im..iru tion has Lwo parts: one is th· la. k to b per~ rm d, called Lh 01>cration code (up-
end ). and lh' , econd is the data Lo be op ral cl on, called th operand. Th operand (or dala)
cu n he speci l1e<l i n v rious way ·. It may mcl ud' 8 bil (or 16-bit) daia, an internal r· i~Ler, a
m~11101y location or an 8-bit ( r I -bit) address. Jn ·o < in. 11 ucti ns, lhe operandi implic.:11.

Instructi,on Word Size

The 8085 in:-trnclion sec i. cla. sified into th followi ng lhr'c 1 roups accordi 11 to word
si1.e or byt siL .
In the 808 . "byt " and "word'' ar . ynonymo us h aus it b an 8 bit micropr ·cs
sor. However, instru Li ns me ommonly rd rred to in term. of bytes rather than \¥Ord ·.

l. I -byte ins1n.1·1i ns
2. hyt " i nslrncti ns
3. 3-byL in. 11uctions

1. On · byte instruction-A mnemonic.: fullm cJ by a letter (or two letter~) , pr s nting

the register. (such as A, B, , D, E. H, L, M, and . P) i. a \ nc byte i1nruction.
In struc ti on in which r gisters are impli ii are al-;o on ·-bye· im,lructions.
E ampl s: (a) MOVA, B: (b) X SP· c) RC
2. 'J\vo-byte instruction -A mncm ni1: followed b , 8-hil (byte) is a two-byre iustruclion.
Example. : (a MVJ , 8-bit; (b) DJ 8-biL
3. Thr YI· instru ·ti n-A mnemoi1ic follow ·d by 16-biL (also terms such as adr or
d I ) is a Lhree-by te i n. truction.
Examples: {a) LXT R, 16 bil (dble); (b) JNZ 16-bit (ndr); (·)CA L 1 -bit (adr}

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

 Machi n lanuuag and assemb ly lan°uag are 1 icroproc sor-spe ific and ar botl
nsiderccJ lo v-le el la guages. Th ma hin · language is in binary, and the ass mh ly
langua e i. in En IL h-1·k , rd ; l w r, tl mi r I roe r 111cl r ·tan · oly tl bi-
nary. How, then ar the assen1bJy I nguage mnemm i s wri lten and lran.Ja d int m'- -
hine tan 1ag or bit ,r, o I '.} Th m1 m li . ai -..vritt n b I and 1

n t b ok ·md translated n1anually in hexadeci na code caUe ha d asse11b)y, as ,_

plain d in S ction 1.25 . Similarly the mne1nonics can he written lectronically on a om-
put r u ing a program alled an Editor in the SCII ode ( xplain d in th n xt s ·lion)
an I tran lat d into bin ary cod by u ing th program called an assembler.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

High-Level Languag,e s

Progra1nmin 0 Ian uage that are intended to be machine-ind pen lent are call d high-level
languages. Th e includ su h lan mwes as BAST PAS AL C C++, and Ja a 11 of
which hav certain t of rules and draw on symhoJ and convention fro1 Engli h.
In tru ti n written in th languag s ar known as statements rath r than mn monic . A
pr gram writt n in BASIC for a n1i rocompul r with th 8085 n1icr pro e. or c, n °en r-
ally b run on another microc n11 uter with a diff rent mi ropr ce sor.

Compil r
Object
Sourc Code ~

or
ode
Inlerpreter

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

 Operating Systems

he interaction betw en the hardware and the softwar is managed by a e of programs

alled an operating system of a computer; it over ee all the operation of the computer.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

PERSONAL COMPUTERS (PC)

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 WORKSTATIONS

Th ' are high-p format c u ins of th p r onal computers. h y ar used in enoi-

n rin and scientjfic apr li ation u h a compu r-aid d si 0 11 AD) comput r-aided
A ), and omputer-aided manufacturin ( A ). h y gen rally includ
and to a e (ha.r di I mory 1n igabyt · and a hi h-r . olution

Th work ati 1 ar des·gned around RISC (r due d ins ruction s computin )

pro L ors d scribed in hapter 18). Th RISC proc ssors t nc.1 to b fast r and more f-
ficient tt an th r c s rs us d in personal compu er . S 1 f I e work tati n he
b te · erf n an e than that of th I w- nd lar~ con puter .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

 SINGLE-BOARD MICROCOMPUTERS

h se microco1nputers as shown in igure J .7) are prirnarily u ed in ollege labora-

torie and indu tri for instructional purpo e r to va luat the p rfon 1anc of a

Monitor pmgrum-a progrnm thaL inte1-prels the input from a keyboa rd and con-
vert. the inpuL into its binal'y equivalent.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

 8085 Ins tru ctio n Set

Th following abbr iations ar u d in th description f th instructi n l.

Flags
g. = 80 OA/8085 Regi t r S = Sign
M 111. = Me1nory Location =Zero
R = Re j t r
0 A = uxili· ry Carry
R· = Regj ter Source P = Parity
d = Regi t r D ·[ination Y = Carry
M emory
= ontent of
XX = Randon, nformation

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

ACI: Add Immediate to Accum lator with Carry

Opcode Operand Bytes M-Cyd es -States Hex Code

ACI 8-bit da ta 2 2 7 E
OC'srription The 8-bit da ta (opernn ) and the CiuTy nag are added to tht.! cont nts of the
accum ulmor. and the re~ uIt is stor d in the accumLJlator.

Flags All n..i g~ nre modi tied to r 'n •ct th re. uh of the add ition.

Example A':,, 1Jmi ng the accumnl.ilnr ·ontains 26H ancJ Lhe pn.:vio11s opnation has ~er
the Ca, r fl ag. a<lcJ b 1 te 57H to th accumulator.

ln lrucli< 11 : 157H lie ('d : E 57

Addition:

(A): -6 H =0 0 I O 0 I 0
(Data): 57H =0 J O l O I I
I I
7EH =0 I I l I 1 0
Flags: S O Z=0 - 0
P = I CY = 0

C'omtut'nts:

t. h •r addition lhe previous 'any fog i~ ·I •are<l.

2. l hi, ms truct inn 1s commonly used iii 16-bit add11 ion. This ins1rnc:tio11 should not he
used w accou nl for a c: rry gene.rat d by 8-t it nu mber:-..

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

ADC: Add Registe to Accumu ator with Carry

Opcode OJ) rar1d Bytes M-C •) s T-States lie · Codes

AD Reg. Reg. Hx
Mem. 7 B 88
89
D 8A
E 88
H 8C
L 8D
M 8~
A 8~

Description The contents of the op nwcl (re,aisrer or m mury) ri nd the Carr' flag · r ·
add d Lu the contents of tl accumulator and the re. ult i. placed in Lh acc utnulat r. Th
ontent of the operand ar not alter d; however, th pr ions Carry llag i · re ·t:t

Flags Al l Hags are m difletl to reflect the restill f the audition.

Example Assume rc 0 i. t r pair B contai, ,s 24981 1 and reg 1st ·r pail' DE contain,
54A IH. Add these 16-bil numb 1s ancl save Lhe result in B registers.
The sc ps in ridding J6-bil nu mb.,rs are as follows:

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

ADD: Add Regis er to Accumu l tor

Op ode Operand Byte M-Cycles T-Statcs Hex Codes

ADD Re . 1 1 4 Reg. He'
Mem. 2 7 B 80
C 81
D 82
8.
H 84
L 85
M 86
A 87
De -cription he conte nt. f the operand (1· isl r or memory are added Lo the ·onlents
of the a c umulator and th ~ result is .sto d in the accum ula tor. f the ope nd is a memory
loc lion, that i. indic.:aled by the 16-bil mklr ss in th - registel'.

Flags All nags are modi fied lo reflect the r suit of the addition.

Examp Register B has S IH nd tb accum ulato1· hes 47H. Add Ill c.:ont nls of re 1s-
tcr B to the cont nts of the ac 11rnulator.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

AD : Add Immed iate to Accumula or
Op~ode Operand B tes M-Cycles Hex Codes
ADJ 8-biL 2 2 C6
da ta

De cription he 8-bit daLa (operand are added t the onl ·nls of th ac mnu lator. and
th r · ult is plac d in I he accumula 1or.

Flags All ftag. are mod ified to refiecl lh result of th addition.

Example The accumulatot ontains 4AH. Add the dat, byte 59IJ to the contents of lb
t1ccurnulator.

lnstrnction: ADJ 59H H x Cod : 6 59

Addition:

(A) : 4Afl=0 0 0 0 I 0
+
(Daw) 59H O I O l OO I
A3H =1 0 10 0 O J J

Fla •s: S = l, Z - ,A =I
P = I. Y=O

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

ANA; Logical AND with Accum ulator
Opcode Op rand Bytes M-CycJes 'J'-Stat He Codes
A Reg. 4 Reg. Ie
m. 2 7 B AO
Al
A2
E A3
11 A4
L AS
,t_ A6
A A7
Descrip iot h contents of the accum ulator are logically ANDecJ with the ontents of
the operand regi. t r or memory) , :md the result is pla cd in the accum ulator. If th
o crand is a incmory locatio11, its address is sp citied by rh con LenL of HL regi st r .

Flags S, Z, P at c modi ed to reflect the res uTr of Lhe operation. CY is 1 & t. l n 8085 A
is set, and in 8080A AC is th resull of ORing bits D3 o the op!ntnd ·.

Example Th co ntents of the accumulator n d the register D are 54H and 82H. 1 sp c-
t ively. Lo
ically AND the contents of 1 gister D with th content of Lhe accumulator.
Show th tlags ,md the ontenls of each register aft r A Din .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 ANI: AND Immedia te with Accumu lator
Opcode Operand Bytes M-Cyclcs T-Srates Hex Code
AN T 8-hir 2 2 7 E6
dala

Description Th contents of the accumulator Hr logically AN eel wi1h the 8-bil daLa
op rand) and the r sulls ate placed in the accumuJa t r.

FJag.s S, 'l, J> are modifi d to reflect the result of the operation. CY i re. et. In 8085,
AC i · sec.

Example AND data byte 97H with the con tent · of lhe accum ulator, which ontain
A3H.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

CA.LL: Uncond' tional Subrouti ne Call
OJ>code Operand Bytes M-Cy,des T-States Hex Code
CALL 16-bit 5 18 CD
address

Description The program sequ nee is tnmsfer d to the addr ss speci fied by t
ope and . Before lh t1 nster the addr ss of Urn next instrm.:tion to CALL (th contents of
the prngr m counter is pu ·1ed 011 the slack. TI e sequence of events is de cribed i11 th
example b l w.

Flags N Ha s are affected.

Exampl Write CALL in truct~on at mcmoty location 2010H to caH a ·ulbroutine lo,..
cated at 2050H. Explain lhtl sequence of eve t when the st.lck po"nter is at location
099H.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

CMA: Compl ement Accum ulator
Opcode Operand Bytes M-Cycles T-States Hex Code
CMA None 1 1 4 2F
Description The contemi- of lhe accuinula lor are co 1r1plemen ted .

Flags No fl ags are affected.

Example Compl e11enl the accumula tor, which has data bylc.: 89H.

CMC: Compl ement Carry

Opcode Opera 1d Bytes M-Cycles T-States He. Code

MC None 4 3F

D Tiption T he Carty flag i. co mplement ed .

Flags The arry nag is modified, no olh r Ila •s ai e affe t d.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

CMP: Comp re with Accu ulator
Opcode Opcnind Bytes M-Cydc~ T-States Hex Cod
CMP Re . I I 4 Reg. Hex
Mm. 2 7 B B
C .89
r) BA
B
H H
L BD
M BE
A B
D scriptinn The co111enls of the operand (regisl ~r or 1uernory) are compar ·cl \ ith the
coment · uf lh ac umulator. Both c.:unt1,;n1s ar preserved untl the con1parison is shown by
setting Lhe flags as follow :

D If (A}< R •g/M ·n, : at ·y flag is set and Zun tlag is set

D Jf (A)= Reg/ m); Zero nag is set and Carry tlag is 1eset.
If (A)> (Re /Mem): Can-y and z~ro flaes are reset.

Th c.:mpari:on of two byt --s i performed by subt1, cl ing Lhe contents of th -- operand
from l.h · contents of the a ·cumuli t 1·; h wever, neither c:ontcnl · , re modihecl.

Flags S, , AC are also modifi :din. ddition Lo Z amJ Y to ren ct the results of the op-
eration

E a npl R ister B contain: d:lla by1e 62f I and 1he a ·cunllllator contains datu b e
5711. omp, P th ' con tent s or register B with tl1ose of th a::: u1 ululor.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 10

CPI: Compar mmedi te with Accum lator
Opcode Op~rnnd n tes M-Cycles T-Statc-s llex Code
Pl R-hi t 2 2 7 FE

De.Ii r'1>Ho11 These o ncl byt (8-bit dat. i. compared with 1he contents of the ·cu mu-
lat r. The value. h ing ·umpared remain unchanged and rh · resu lts of the comparison are
incli "tell by s ·Hing the Ha s ti. foll )WS .

Jf (A) < Data; arry Ila i, set ancl Zero fl g is l'e · ·t.
If (A) = Data: Zero tla is -. l and Carry ft g i · reseL
D Ir (A)> Data: Carry nnd Zero tlag. ar' 1 : t.

The comrnrison of two hytcs is p rformed by s~1btrncting the JaH, byl' from th onte111
or ltl' ac ·umulator; how· ·r, neither c ntcnt · ,tre modifi I.
lt'lags . P, A are al modified i n '1ddition lo Z nncl CY tu refl ·•cl Lhe re. ult
of th operation.

Rxan>J)le ~sume the n ·c11111ulator contain data byt C-H, ompare 98H wi th th . a·-
cumulalor contents.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 11

DAA: Decim I-Adjust Accumu ator
0JJ ode Operand B tes M-Cycks T-States Hex Code

DAA one 27
Description The coritents of the a umu lat r a, chan ed from a bi nary v, lue to two
-bit binary-cod <l decimu l B DJ dioit. . This is the uni>' i11 ·t1u ·tio n that use · the auxil-
iary tfo, (i11 temally to perform th inary-to-BCD conversion; the con 1cr. ion procedure
is de ·<.·lib d b low.

Flags S, Z. A . P, Y flu12s are altered to reflec t th r ·sult. of the operation. In ·tr wti n
D A converts the bi nary cont nls of the accumulator as f lk)W,:

1. If the value of lhe I w- rder fo ur bits (D:,D0 ) in th c1 • ll t1 ut::uor is gr ater than 9 0 1

11· A tlag is el the in~lru lion adds 6 06 to the low-order fo ur bits.
2. U the vulu · of the high-order four bit ' 7 -1 in the a umu lalor is gre. tcr than 9 nr
if the Carry fla i~ s ~, , I he instrnc tion adtls 6 (60 tu 1h hi h- rder four bits.

E, am le Add de imul 12RcD to lhe accumu lalor, which c n1am. 398 0.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 12

DAD: Add Register Pair to H a d L Registers
Opcode Operand Bytes -C des 'J'-States He · Codes
DAD Reg. pair 3 10 Reg.
Pair Hex
B 09
D 19
H 29
SP 39

Dt:!SC ·ipUon 111e J6-bit t:onlcnt · of the spe ified re ister p;iir are m.lded lo the conten1.
of the HL reglster · nd th· um is saved in the I IL r gist r. he conlen s of' the so111· r g-
bter pair ai n ( ah red.

Flags Tf th· r • ·ult is larger than 16 bits the CY flag L set. oth~r flags are affected.

Example A"-. um r gis ter pair IJL cont:1in 0242ll Multiply the onL ' 11(1) by .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 13

DCR: Decrement Source by 1
Opcode Op •rand By es M-C cles T-Slates Hex Codes
OCR Reo. I 4 Reg. Hex
Mcm. 1 3 10 B 0
C OD
T) I-
E ID
H 2~
2D
M 35
A 3D

Descriptio 1 h • ·onl ' Ills of th e desig nated regist r/memory is tJ , Tt!111 ··11tcd by l und
the 1· suit. ar stored in the sam place. ff 1he perand L a memory location, it i: pec1-
fi d by th cont nt~ or the 1lL register pair.

Fags S, Z, P, A(' are modified to reUecl tlP r suit or th· operali 11. Y is not modified .

.l!:xamp e D ·crement regi. ter B, which 1s lear d. and s pcci ry ii!-. co nten ts after the
decrement.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 14

DCX: Decrement Reg· ster Pair by l
Opcode Operand Byte.,;; M-Cycles T-State.s Hex Codes
DCX R.eg. pair [ 1 6 Reg.
Pair Hex
B OB
D lB
H 2B
SP 3B
D s ription The con ents of the specified "C ister pai.- are decremented by 1. his in-
stru ction views the contents of th wo register as a 16-bit number.

Flags No t'la 0 s a1· af[, ·c ted.

Example Register pai DE contains 'O0OH . S1)ecify the con tents of the entire r gist ·r if
il is de,cremented y 1.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 15

DI: Disable Interrupts
Opcode Operand Bytes M-Cycles T-States H Code
DI None 4 F3

D Cl'iptio The 1ntcrrupt Enable flip-flop 1s rese t and all the interrupts except lh
TRAP (808S) arc disabled.

Flags No ags ar · affec teu.

Comment: Thi. insl.J uction is ommonly used when the execution of a ad s ·qu ·nc'
·annal b interrupted. ◄or example. in c rit ical time delays, this instruction is used at th
beginning of th code and the int 1nipts ar nahl cl nt th end of the code. The 8085
TRAP cannot be disabled.

EI: E a le Interrupts
Opcode Operand Bytes M-Cydes T-State H x Code
I N n 4 FB
Oesc iption The Interrupt Enable flip-flop is set anc.l all interrupts are enabled,

lt'lags No flags ar affected.

Comments: After a syst •m reset or the ad· 10wl dgn,ent or an rnterrupt the Interrupt
Enable flip-flop is reset, thus disabling th int •n·upls. his instru 1io11 i. necessary to
1· ennhle the intel'rupts (except TRAP).

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 16

HLT: Hat and Enterwa·t Sate
Opcode Operand Bytes M-Cyde -States ex od
Ht: Non 2 rn mur · 5 l I' 1110f'C 76

Descriptio l The MP fJ11i . hes executin the cu1Tent ins ·uction and halt~ any fu1tl1cr
xecuLion. The MP t.ml ·rs the Halt A ·k.nowl ·dgc 11H.1cll ir1e c clc an<l Wail stales a1e in-
serted in eve1y dock peri . he address ,rnc.l th· data bus ,u pla · cl in th higl imped-

anc · :-.tat . Th · contents of U1 r gisters ar unaffected durin the HLT state. 11 in terru[Jl
or reset is neces ary to exit from the lla lt stare.

Flags flag~ ar" afl' cted.

IN: Input Data to Accumulator f om ort with 8- ·t Address

01, ·ode Op~nu1d Bytes M-Cycles 'f-States He, Code
IN 8-bit port address 2 3 lO OB

Deseription T l. e content. of tl input port designa ted in the operand are read and
loatlcc.l into th· accumL1 lator.

Flags No flags are afl'ec red.

ormn nts: Th OJ ra nd is an ~-bit addr ss; th re1'0 1·e po1 I , ddr , . n ra n from
OOH to FFH. While executin g the im,t1·uctio11, il p rt ad 1r ss 1~ tlupli ·,Hcd 0 11 low-order
(A 7 - Ao anti hi,eh -orde1 ( 1~ A8 ) uddres · buses. Any one of the se ts ol' address Jines can
I t= 1,h.:od ·d lo ·1nbl · th' inpul port.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 17

INR: Increment Contents of Register/Memory by 1
Opcode Opera ul Byte M-Cycles T-States Hex Codes
R l{eg. l 4 Reg. Ile
Mem. lO
B 04
0
D 14
E IC
H 24
L C
M 34
3C

Descriptio11 h · ·onl ·nts of the designated regL Ler/memo1 y il'e mcrernented

b I and the re ·ulls arc stored in the c;ame pla e. ff th· op ·nmu is a mcmor , lo-
cation. ic il. specified by the cont nt s of H register pair.

Flags S, Z, P, A nr m uified to ref! ct the re. ull of che operation. CY i. uot mod1ikd.

Ex,1mplc Regi sl r D contain~ FF. Spe ·if the l:0111 'nls ui' the register after th incre-
ment.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 18

INX: nci::ement Register Pa ·r by I

Opcode Operand Dyl-es M-Cych:s T-States Ht:X Code

TNX Re . pair 6 Reg.

Pa"r Hex
B 03
Di J3
H 23
SP 33
DescriJ)tion T l1e crn11en t~ of tl, e i,peci nee! register pair are incremented by I. T he i. □ -
slrnc tio11 vjews 1th• ·ont nls of ct1 two rcgisccrs as a 16 bic number.

Flags No fl ags ::ire aft'cc ed.

Example Register pa ir HL comai ns IJFFFH. Specify !he co nten ts of the entire register
if il is inct menl d by 1.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 19

JMP: J mp Unconditionally
Opcode Operand B t s M-Cydes -States l:lcx Code
J p 16-bil 3 3 10 3

Description The program sequen e i. transferred 10 Lhe mem ry location p ' ·ifi d by
Lhe 16-bi Laddress. Thi ~ is a }-byte i I srructio11 ; the ·ccom.1 byl spe · ifies Lhe low-order
byte a nd the third hy tc specif· the high- rd er byte.

Example Writ the instruction al loc.tion 2000H to lram,fer the program equence l
memory lo at ion 050H.

J mp Condition ly
Op rand: 16-bit address

Op rlag Hex
Code Description Stah1 Cude . )'des/T-States
JC J l1ll1p 011 HJTY CY= I DA 2M/7T (if condit ion
J Jum p on No Carry Y=O D2 is not lru )
JP Jump nn po. itive F2 M/IOT {if condition
M Jump on min u · S=I FA is 1nie)
Jp 7 Jump on Parily ven P= I EA
JPO Jump on Pd'ity OJ<l P- 0 E2
JZ Jump 011 Z ·m Z= I CA
JNZ Jump on No Zero Z=O C

Flags N flngs ar affected.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 20

LDA: Load Accum lat or D ·rec
Opcode Operand Bytes M-Cycles T-State.'- He, Cod
LDA 16-bil 3 4 13 3A
address

Desc iptio l h conlenls of a memory location. specifi ed by a 16-bil address in the

operand, ar copied lo th accumulator. Th content of th . ou ,·ce are not allc1-ed. his i
a 3-byte inst mction: the c ond bye ~cific lb· low-o:d r adJ ress an<l th th ird byt
sp itics thi. high-or I r acJ fr 'S'-.

Flags N flu s ,.11' nffcclcd.

Example As..<; ume memory localion 050H ' n1a i11 s by1' 8H. ,Id 1h ac ·umtdator
with th '01H •111-, f lo alion 050H .

LDAX: Load Accumulator Indirect

Description The content. or 1he <lesig11aLed rcoistc1 air point lo ,J m 'mrny lo ·at ion.
his in~1rnctio11 copie~ th· ·unt ·111. ul' that rn ·mory lo ·ation into !he acc um ula tor. fhe
·uni ·nts or ilh r lhe regis ter pair or the me m ry location are not a1£ereJ.

Flags o !fags ,1rc aff ct d.

Example s umc th c nt nl ol 1 • •i ·1T 8 - - UH, C - 50H, an<l mcm r ' loca tion
OSOH - 9FH. Tranc..fi r tl1e cc ntent~ r,f the rn m r I cation _QSOJ I to the accumu-
lator.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 21

 LHLD: Load and L Registers ire ct
O pcode Opernnd Byte M-Cycle.s T-States He · Code
LHLD 16-bil 5 16 2A
nddress

Description Th insLrucLion opi s th' con tents uf the memory lo ·atiun pointed out by
the 16-hil nclclre.,;;.s in register L :incl c pies l h con tent. of the nexl memory location in
11 gist r H. Th · ·n111 nt, of '-O ll i'· ,n mury lu ati 111-i are not ,dt I cl.

Flags N flaas nre affe ted.

l!:xamplc Ass ume memory location 050H contains <JOH and 2051 H contai ns OI H.
Tr:crnsfer mem ry contents to register:-. IIL.

LXI: Load Register Pair Immediate

Opcode Operand Bytes M-Cydes T-Shdcs Hex Code

LXT Rco. pair, 3 3 10 Reg.
I6-bit fair Hex
data B 01
D 11
H 21
SP 31

DescrjpOon 1l1e instn1 tion loads 16-bit data in lhe register pair designated in th·
operand. This is a 3-byte instruction; the second byte specities tthe low-order byte and tbe
rh ird hy1c specifics I he hioh-orcb hyre.

FJag.1; No ft ao. ::ire affected .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 22

MOV: Move-Copy from So rce to Destination
Opcude Operand Bytes M•Cydes T..States Hex Corle
MOV Rd.Rs 4 See table below

MOY M,R · 2 7
MOY Rd,M

Description This instruction copi "S th · conten ts of the source reg ister into the c.le$tina
tion register; the conten of the sour · regi ter :u· nol alte1 d. If one of the operands i ·
a m mar lo alion, it is pccified hy the con tents of HL registers.

Flags No fic.1gs ar · affcclc<l.

Hex Code

Sour'e ca1ion
B C D E H L M A
B 40 41 42 43 44 45 6 7
48 4A 4B 4
9 4D 4 4F
D 50 ~ J 52 53 54 55 56 57
De. tina tion E 58 59 SA 5 5 5D SE SF
Locati 11 JI60 61 62 3 64 65 66 67
68 69 6A 6B 6 ' 6D 6 6
M 70 71 7 73 74
A 78 79 7A 7B 7

Ex.a nple /\SSlllOC registe, 8 co ntains 72H and regist r <.unt;;i i11 · 9Hl. Transfer the
con te nts of register C to regi1-tcr B.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 23

MVI: Move Immediate 8-B't

Op ode Operand Bytes M-Cy I T-States Hex Code

MVI Reg. Data 2 2 7 Reg. Hex
Mm., nara 2 3 10 B 06
C OE
16

H 26
L E
M 6
A 3E

Descript·on The 8-bi l data are stored in the de.,;tina1ion r i te or m rnory. If the
operand is a memory location, it is speci(i d hy th ' nt nls of HL registers.

Flags No Ha s are atleclcd.

Example ud 92H in Pgister B.

NOP: No Operation
OJ)code Operand Bytes M-Cycl s T-State.-. Hex Code
NOP None 1 1 4 00

Description No opera tion is perform ti. he in ·trucli n is fotch ·ti and <l ·i;;odc;d; ho -
ever, no operation is executed.

Flags No flags ar affected .

Comment : The ins11 1clio11 i u. d 10 19 11 in tirn <l lay. OI' to dcl re and in. e c i11srruc1ion.
whi le troubleshooting.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 24

ORA: Logically O with Ace mulator

Opcode Operand Bytes M-Cydc.-; T-Stat Hex Code

0 Reg. I 4 Re-g. Hex
Mm. 2 7 B BO
C Bl
82
R3
H B4
L B5
M B6
A B7
DescriJ>tion Th ~ ·ontenl · of th ac;cum ulator ar logi ally ORed with th ·ont nts of
the opernnd (r gister or memory) and the results are placed in the accumulator. If th
pcrand is ;1 memory toe rion its address is specified hy the contents of HL re ister..

Flags Z, S, P are modified t reliecl the results of the operati n. AC and Y are reset.

ExampJe Assume the accumulator has data byte 03H and regisler C holds byte 81H.
Combin the bit. of register with th accurnul t r hits.

0 : Logically OR Immediate
Op ode Operand By~ M-Cycles T-Statcs Hex Code
ORI 8-hit 2 2 ? F6
data

Description The content of the accumulator ar logically OR d with the 8-bit data in
th op rand and th· r ·sults ,u placed in th accumulator.

Flags S, Z, Par modified t 1 fl t the r suits of Lhe operation. Y and A are re1-et.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 25

OUT: Outp t Data from Accumulator to a Port with 8-B ·t Address
Opcode Operand Bytes M-Cycles T-States Hex Code
u 8-bil porl 2 3 10 03
address

D ·cription The conlents of 1e a umulaL01 are c pi u inlo the OUIJJU l porl spec ified
by the operand.

[t'Ja , · N flags ar ., affecled.

PCIIl.i: Load Program Counter with HL Contents

0Jlcode Operand Bytes M-Cyclc-S T-States Hex Code
PCHL None l 6 E9
Descripti4m The contents of registers H .ind L n.! o,;:upietl. into Lhe program counter. The
co nten Ls of H ar pla.ceu us a 1 igh-ortler byte and of L a.<; a low-order byte.

lt'fags No ffa os re affected,

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 26

POP: Pop off Stack to Reg· ster Pair

Opcode Opernnd Bytes M-Cy l T-States Hex Cude

OP Reg. pui1 3 10 Reg. Ilex
B Cl
D Dl
H El
PS l

Description The conl nts of th · m mory location poin ted out by the stack. point r r •g-
ister a .e copied to the low-order regi ler (sll ·h :-t'i , , L, ::ind fla s) o l' the operand. The
:ta ·le poi nter i:- i11cr inented JY I and the conten s of that m mory Jo atio11 arc copi d 10
th high-on.l r regisl •r (B, , H, A) of th operand. T he sta k point r register ii-. ag< iu in
cremented by I.

Flags No fta s are modified.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 27

PUSH: Push Registe Pair onto Stack

011code Operund Bytes M-Cy les T-State.s Hex Code

PUSII Reg. pair 1 12 Reg. Hex
B C5
D D5
H
PS FS
Description The contents of th rcgisl r pair de ·ignated in the ope.- nd arc copied inlo
the . tack in rhe fol io\ ing s qu nee. The stacl· pointel' re ist ·r i · d ·1 me nted and th
wntl!nls of th , high -order register B, D. H, A are copi d into that lo ation. The stack
puinler reg ister is decl' mented a oin .ind th' con Lents of the low-ord ,· re i. t r (C, E, ,
flag.) al'e copjed to th t I cntion .

Flags No Jlags nre modified.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 28

 RAL: Rot te Accum lat,or Let hrough Carry
Opcode Operand Bytes M-C. des T-Statcs Hex Code
RAL None 4 l7

Desc ription Each binary bit o ' lhe accumulator is rotated l ·ft by one positim1 thrnugh
the nrry flag. Bit D 7 i , placed in the l it i11 the Carry flag and the Cany flag is placed i 11
the least significan L position Dtl·

Flags Y is modified according to hit D, , S, Z. AC. P are not affected.

Example Rotate Lh content~ or th a unrnla to1 lhm u 0 h Carry. a4-sumin(T Lh accumu-

la101· ha 7JT and the ' arry fl a is r s l.

In!.l ruction: RAL H od ·: 17

'Y
IQ]
·umulator con t nl
before instruction

ccumulator con tents '--"-Io_._;.....-L-.I-"-

o __.__I---"-0_.__-'---'--___1I oJ
an r in ·1ruc1io11

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 29

RAR: Rotate Accu ulator Right through Carry
Opcode Operand Bytes M-Cycle T-States Hex Code
RAR ne 4

Description Each binary bit of th" ai:.:cumula[ r is r rar d righ t b one position through
h Cimy flag. Bi1 Du i::- placed in the Carl'y flag and the bit in th' Carry flag j ~ pla ed in
the most sig11ilkanl po ition, D,.

Flag,s C i dificd accorclin to hir 0 0 . S, Z P, AC are not affecLed.

RLC: Rotate Accum lator Left

Opcode Operand Bytes M- 'yclcs T-Stat He, Code
RL Non 4 07
De. criptiou E.1c.:h binary bit of the accumulator is rolal d l ft by one position. Bit D7 is
plac.: d in the position of O ~ well as in Lh arry ag.

Flags i modified according Lo hit D7. , Z, P, l · fected.

Example Rot, tc th 'Ont nl f the a cumul dor lefL, a. . urning it conlains 7H and the
Carry fl, g i r s t to 0.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 30

RRC:Ro Accum lator Right
Opl'Odc Operand n. tes 'f'.Statcs He, orl
RRC Non 4 OF
Description Each hinary bit f the accunTJlator is ,or. red ri hi b, m · p sit ion. Bil D0
i. 1 la· ·d iu lhe p sition or D7 a!. ,vei l a in thr Carr Oag

Flag CY 1s 1110<.l ifi ·c..l according I bit D0. S, 7, P, AC ar ' n l affccte<l .

RET: Return f om Subr,o utine Un.conditionally

Opcode Operand Bytes I-Cycles l'-Statcs H ex Cudt:
RET N ,ne 3 w C9

Descri1>Uon he prog a m sequence is transferred from ilh ·ubrmHin to th calling

program. Th tw by tes from lhc lop of I he srrck are copied i1~to the prngnm1 co unt .- • nd
the program execu tion begins at the 1e \ ad ,· s.:: . 1h~ insrrnctiofl is. equivale nt to POP
Pro:.ram Coutu r.

Flag N - flags 111 • m~ctcd .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 31

 Return Conditional y

Op Flag He
Code Description Status Code M~Cycles/T~States
RC R turn on a1 -y y =I 08
R Return with No Carry CY =0 DO 1/6 (if condition is not true)
RP Return on po. itive S=O FO 3/12 (if condit ion is true
RM Return on mi nu S=I F8 Nott': If c 11 dition i, not true, il continue
RP ·tum on Parity Even P= I E8 the sequence and thus requires
RPO Return on Parity Odd P=O EO fewer T-states.
RZ Return 011 Zer Z- 1 C8 If c ndition is true, it r turn lo Lhe
RNZ cturn on No Zero z = () () calling program and thus requires
more T-states.

Flags No fla . ar aft· ' l ·c.J.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 32

RIM: a Inter upt Mask
Opcode Operand Byte M-Cycl T-Slatcs Hex Code
RTM one 4 20

Description This is a multipurpose instrnction used to read the . tarn. of inl rru1 ts 7.5,
6.5 , 5. ~ and lo read seria l datu inpuL bit. Th in t1 t<.:tio11 loads •ighl bit · in th accumula-
tor wi th the followin i111erp erntion.:

17 16 15 IE 5.5

.Se ial input ll1terrupt

data bit ma l·cd if
bit = l
Int rr1pts lnt rrupt Enable
pentling if flir-flop is set
bit= I ,r bit - I

Flags o llags arc aHecled.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 33

RST: Restart
Bytes M-Cycl s '1'-Stat~s
1 3 12

Restart
0 code/Operand Binary Code Hex Code Address (H)
RST0 000 I I I 7 0000
RST I l 001 I I 1 CF 0008
RST2 I l 010 I 1I D7 0010
RST I I 0 I I Jl 1 .;
00]8
RST4 I I 100 I 11 E7 0020
RST II I O1 J I I EF 0028
RS1 6 I I JI 0 J 1I F7 0030
RST 7 I I I I I I I I F 0038

DcscripOou he RST in. truct ions are equhalenl to l -bytc call instruc Lions lo one of h ·
ight memory locations on 11~ 0 0 . The instrncLions are • n rnlly used in conj unction
wit lt int rrupt. and inserted using ext ·rnal ha1clware. However. th se can be 1sed as soft-
ware in ·tructions in a pm mm Lo transfer progrnr11execution to one of the eight locations .

Flags No fl g. are affe ted.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 34

S : Subtract Source and Borrow from Accumulat or
Op ode Oper·and D le.s M-Cycl T-S(atcs Hex Code
SBB Reg. 4 R~g. Hex
Mm. 2 7 B 98
99
D 9A
E 9B
H 9
L 9D
M 9E
A 9F
Description _h · nt nts of Lil oper, nd (register 0 1 memory) and the Borrow lfo ;ir
suht1·, Cl (! from the contents of the a ·cumulator and lb r su its or placed in th a ·cu-
mula1or. The cont nt. of th· operand are 1101 alli;r ·<l; however 11 previous Borrow lfa
is reset.

Fla • · All fl ags , r~ ahu ·d to 1-eftect the re ult of lh sublracti 11.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 35

 SBI: Subtrac mmediate with Borrow
Opcode Operand Bytes M-Cydes T-States Hex Code
sm 8-bit 2 2 7 DE
data

D cription The 8-bil data (operand) < nd the boITov ar . 11b1racted from Lh ontents
of the .i ·cumulalor, and lhe resul ts are pla · d in lh accumu lator.

Flags All flags ar air ed to reflet:l lh r . ulLof th opernti n,

SHLD: Store Ha Registers Direct

Opcode Operand Byt s M-Cyl'les T-States He · Code

HLD l -bit J 5 16 22
addres

Descdpti n The conlenls f e i. Ler L are l red in the memory lo ation spe ·ineu by
the 16-bil ad Ir ss in the operand. aud the cont nts of H register ar stored in the n xl
m m ry I cation by incrementing th operand. The cont ms f regi ters H nr not al-
tere<l. his i a 3-byl instruction; the econd byt . pecifies the low order address am.l th
I hi rd byte speci fie. lhe high-or r ddress.

Flags N rlag~ are aff ct ·d.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 36

SIM: Set Inten pt . ask
OJ>rndc Opct·and R. tes T-Slates Hex Code
SlM None 4 30
De cri1>tion This i a mullipurpo. in ·truct ion and u d lo impl m nl the 80~5 int r-
rnpt1. (RST 7.5, 6. - , and 5.5) and ·erial darn output.
The instrnclion int"rpr 1· the a um ul.1 r ontent.s as follows:

O,; o, ~ 02 D, Do
jsoo I snE 'XX R7. MSE M7. I
J
M6.5 5.51

J l
I

S ·,i,tl Ou1puI dalu

l
Reset RST 7.5 MasK!) lnrerru prs
flip-Hop if D-1 = J if bit~ = I
S 'rial data nabl Mask Set
L = Erwb l · Enable if
0 - Di able I: j

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 37

 SPHL: Copy Hand L Registers to the Stack Po'nter
Opcode 01>e and Bytes M-Cycles T-States He. Code
PHL one 6 (8085 F9
5 (8080)

Desc iption Th im,truc;tioo loads the content. of tile H and l, registers into the s t. ck
poinLer regist r; the contents or
lite H register provide the high-order add t-ess, an<l the
con tents of lhe L regi~tet" provide the lo\ -ord r addr 'S'-, T he contents of th H and L reg-
isl ,,·s al' , 1101 alter d.

Flags o flags ,m: affected.

STA: Store Accumulat or Direct

Opcode Operand Rytes M-C Jes T-States flex Code

STA 16 it 3 4 13 32

Description The contents ol' th n umulat r ar' copied Lo a 111 mory I ation sp cified
by the operand. ' 'hi is a 3-byl in.·truc1i on ; th secoud l}yte srecifie: th· l W·l rder ad-
un.:ss and Ihe thlrd byl · ·1,xifies the high order address.
Flags N flags arr affi cted.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 38

ST.AX: Store Ace mulator I direct
OflCOdc Operand Bytes M-Cyde-S T-States Hex Code
STAX B/D L"eg. 1 2 7 Reg. Hex
pair B 02
D l2

ST : Set Carry
01>code Operaud Bytes 1- yclcs T-Stalt:s Hex Code
ST None 4 37

o~ -cription any Hag i. . '! to I.

Flags No oth I Hag ar affected.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 39

SUB: Subtrac t Registe r or Memor y from Ace mulato r
Op ode B t s M-C cles T-States He · Cod•

SUB R g. 4 ex
Mem. 2 7 90
91
D 92
E 93
H 94
L 95
M 96
A 97

Description The content,; of th I ister r the memory loc.:ation ·p ified by th

ope,and ar btrnct d fro m the cont nls f the accumula tor, and the result ar pla ed in
the ltccumulator. The cont nts of th sourc re not altered.

Flags All fla )S are aff t cl lo retlect Lhe resu lt of the ubtraction

SU: Subtrac t Imme · e from Ace ulator

0 1> ode Operand B tes M- yclcs T-Statc · Hex Code

SUI 8-b1t 2 7 6
da ta

Dcscd1,tion 1 8 hil data (th ' op ra nd) are wt 1racted from lhe content, or lhc accu -
111u lator, and the resu lt ' arc placed in th acc umulator.

Flags All flags are modified to reflect the rc:,; ult.'i of rhe subtrac1ri, ,n.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 40

XCHG: Exch ang Hand Lwit hD ndE
Opcode Operan d llyt -Cydes T-States He Code
X IIG N n I 4 EB
Dcscripfou 111 cont nts o· register H .u- e:xcl anged with the co1w•nt of regi
lcr D,
and tb · contents of re i. I r L arc e hanged wilh the c ntents of , gister E.

Flags No flags ur affected.

XRA: Exclu sive OR with Accu mulat or

Opcode Operand B ies M-Cycles '!'-States Hex Code
XRA Reg. I l 4 Reg. Hex
Mein. l 2 7 B A8
C A9
D AA
E AB
H AC
L AD
M AE
A AF
Descrip tion T he conlent~ of lhe opei-a 111J (register or memol'y) are Ex ltl"ive ORed with
the co11lenls of the accumlllulor, a nd the resul ts .-u-e p laced in the accumulator.
Th con-
te1Hs of lhe op~rnnd a, nol E1ILe1 cl .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 41

XRI: Exe usive OR Immediate with Accumulat o ·
Opcod Operand Bytes M-Cycl~s T-States Hex Code
XRI 8-bit 2 2 7 EE
data

Description 'C he 8-bit data operand) , re Exclu~ive ORed with the contents of th · · c.; -
cumulat r, and the re ult · arc pJ ced in the accumulator.

Flags Z, S, Par ult 1' .d to reftec L th res ult of 1he operation. Y and AC are reset.

XTHL: xc ange H and with Top of Stack

Op ode Openmd B tes M-Cydes T-Statcs Hex Code
XTHL None 5 16 E3

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 42

80 S utslru<mon ummary by Pundional Oro p··

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Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 43

L e.d in & gist r
i\tJn ,e11u111ics Opcode Co.11111i.ents
tl fil 0 Load FF in & gis r 1mm diat ~1

Load F r gist r r air b · th · d· .t a ' l ,..OI .

11111.e,11.o nic~· Opc0,de Coninwnts
L .. I H ' 1 OH '1 ,..0 1 Load HL r gist ·r pair ith I "" OH

L ad th ont n of m mor location ' 1OOI in h · a· "umul·1tor.

M11 ,e11.1,011,i,cs Opcode Co 111111.en t~·
II 1OOH 1 00 ' l ad m mor l . ".t ion addr ·ss 1OOH in H
regist ·r pair
MO M op 'Ont "nt of m "mor loc·1tion in th
a , 'Unlulat r

Transfi r d·ita s o,r d in m mocy lo ·a ion 99,..0 to th a· ·umula or.

l\111 .e1110,nics Opcode Con1ni.ent~i.
LO 9·9' OI . '"O 99, M data to a umulator from m m ,cy
lo · .t ion 99· 01

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

Load 4 data in t h m m r lo ·ation 00 . In ·r m nt th · cont nt of
n.
M 11.e11,i.011i,cs Opco,de Co11u1.ients
00F . 1, 00, ,.. Lo· d m ·mor · I ·ation ·]ddr ss · ,.. 00 in EL
. .
r r pau
MVI M,4 F is stor "'d in · 00F lo · hon
RM ont nt of m m ry lo ·ation in T m nt db on

r"nsfi r th con nts of IOU and ' l0OH to r gist -r s F and L r sp ·ti
. h n stor · th · HL nt nt 1 , m mor l ·. ·ation 9·,..0 l 1 and 9'300H r sp cti
M 11.eni.011ics Opco,de Co11.u1.i.e11ts
L D 100 H 00 l Lo· .d .. and L ..r rn m m r lo .,. ti n ' 10 lI . and
l00H
LD 9·300I 00, 9·3 .r .rn Hand L m m r l 'ati n 9 OlI
·md 9· 00 I r sp · ti "'1 .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

 Add1t1on oif Two 8-bit Numbers with S.-b1t Sum

START

Algorithm In itialize th e memory location of first data

1 . illnifr liz" th m · mor l ·at ion of th· first numb r in

H1 L r gist r p· i r. Load first data in accumulator

Mo first numb r/data in o th · a · 'umula.tor.

illn -r m ·nt th c n nt of h r gist r pair t · l nitiali. e th e memory location of second data
initializ · th m mor lo ·ati nd d· .ta.
4. nd data \ . ith th · ... Add th e cont.ent. of memory locat.ion , i. e.,
second data with accumulator
' to r h · r suit in th m. mor l "lti n 00

Store th e result, i.e., the content of

accumulator in memory loca ti on

End

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

 ltemmy Jll/,cwhi'n ,e
,u l,d1~es:\· Cmles L ubeb,, Op.enm ,ds C,m., ments
0 dd r . f fi r. t numb .r in HL r ] t .r I ai r
Tran:fi r fo :t numb r in ace umufat r
1. lncr m nt c · nt nt f HL r i:t r pair
6f DD M dd h r. t numb r and nd numb r
3_ ( 3 0 T ( 1( 3H ( 03 H
6 HLT HaH

·---------------------------------------------~---------------------------------------·
: Data : Re. ·ult :
t---------------------------------------------,---------------------------------------1
1 Me m rv 1€ c ati n : Data -I• M m ry ] c ati. n. : Data 1

•-tt>c------------------t-------26tt- ------------ •------(>(>3-- ---- ---- ---- --:---- - ~ -11------.

I . . ·J . I

l----------------------~----------------------~------------------------~--------------J
I
I I
( ( _H
I
I (
I
I
I
I
I
I

·----------------------~----------------------~------------------------~--------------·

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 Addition of two 8-bit Nu1
mbers with '16-lbit Su1
m
STA RT

l nlt.ia lize the memcry location o f first d ata

Sto re f irst d ata in the memory loca tio n

tnitia lize t he memory loca tio n of second d ata

Algor.i thm Siore second d ata in t he memory loca tio n

I. In ii i.aDiize the memory loc.a:i ion of the firs t number in

the .L ie •i~·ter pair. Initia lize the re{liste r C to
st o re MSBs o f Sum (C = OOH)
2. Mm,e fi l1it m.onber/dat.i in to 'lhe a.oou.mt.illator.
3. ln.erement the oont1ent of 'lhe HL re ,-i_~ler pair to
in iti-a.Dize the memory location of !il:lDOnd da.t.i. Move seco nd da ta in accumulato r
Add the sroand dam ·witb the a.e,.,"tJmulalor.
5. Sliore the re>-qu[t in ,the memor , I a titln 8003H . Add first data w ith seoo nd
data , Le., t he oo ntent of
w ith accumulator

Incre ment C by 1
C =01 H

Sto re LSBs of sum, i.e ., Co ntent

o f Accumulato r in memory

Sto re MSBs 0 1f sum, i. e., Content

of Registe r C in memory

E nd

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

, 1emor_ i J1a hill.e
mldr.e!!o": C,Jdes lahds
'()()()1 2 1. 0 l. LX l 01H ddrL'.SS >f 1s t trnm oc r in HL rgisl.n pair
,00 36,F2 MI. M, F2 H SI.m e 1st 111m1i11 bc r in mcmrnr lo ';;iii m Ill:])'
Fe. ·IJllc..xl b HL n~gi.'> ·r pan
, 00 lJ X H lncn:mclJlt ~Jilli ·1111 >f HL r :gisl ·r pair
, 0()6 6,2F Ml M, 2FH Ston:- 2nd IJlwn b ·r in lfn ·m ry I J 'c;:ltio111
Fcplll:s ·1111 ~ by HL T -gist ·T paiF
(l()i 2nd n 111:m b ·r in a ·11111 111.la l n
, ()(),9 Ml 1 ' , OOH ln ilializc Rcgis t ·F ' with OOH lo store
1

MSBs of s111.m
,OOH 2B 0 'X H ddrcss >f l st Til!ll.m oc r, 0 1 i111 HL pair
'(l () ' 66 DD M ddi ion of 1sl mi:mbt.·T and 200 m1m bcr
,00D D2, 11 , 8 j LE :;-L l I f carry ,cio c-'> n >I gclJl ·ml. \ j111.mp t L - -L l
,(HO 0 l[ R \.VbclJl 'c;:IH)' is ~ocralcd, i111 :Tl"IJll ·111tR ·gis t ·r 1

,0 11 "'2,0 5 L - EL 1 S 503H S~otc LSR\l of sLlm in 1Jl1c11mry I ';ii[i JIJl

8 0 H
MO Mov · MSBs >f slim in a ·1.1.mulal n
32, ( 5 SA 851() H Slotc MS Bs f S L.IIJl] i111 TI1 ·moFy lo ';;iii( l'l
, 504H
6 HLT Halt

·---------------------------------------------,---------------------------------------~
1 Data : R.e.m/J 1

•~---------------------------------------------,-----------------------,---------------i
M ·mury loc-aLion : a ta M ·mnry loc-ati rn Ia ta • I
I I I I I
,----------------------T----------------------1-----------------------~---------------1
1 850 1 f2H 1 1 8 ff' • 2H LSBs ol' s111.m 1
~----------------------~----------------------J-----------------------~---------------~
l 02 : 2FH l 80 : Ol H ·1SBs ifsL.1.111 l
~----------------------~----------------------~-----------------------J---------------~

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

Addition of N 8-bit Numbers

START

Loa.d coun'l in reg ister G

Inc rement HL reg ister pai r

to loa d next number
Algor ithm
I, Load the number of bytes to be added iTI l:be Fl R memo !o<-.i:t ion.
2. Initialize aroumulator. a:.G LSB:s oHhe re_',U[I will be s-tured in aooumullator.
S um = S um ;- Next Nu m ber
3. Re11·i:.Gter B i.GalGo in itiia.lirzed to ,· tore MSB:s of,•um
Let l:be memory point l:h.e n'iln:lber ofl.he bytes to be added and:stured in R.eg-i:.~ter C.
5. "M:o¥e ne:.-rt memory foeat ion for data and data m lh aooumulatur.
6. If ca.ny i:s ,ener.ded., Re rister B ·witUI be incremented , one.
7. Decrement the counter havin • number of byt:e.i;.
8. Check if zero-no :repeti tion from paint 5.
9'. Store I.he ~m[t at F200R and F20 I H 'kic.a:tion'.G.
MSl3 or Sum = Prev lous
Va lue+ 1

[Je,aremenl coo n,ter

N,o

Slore LS B o·r S um
Store MSl3 of Sum

c End )
Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7
,11em fJJ"J,1 ua ./l i m!
mldress Cod e~; Opem11d~;

F( 0 () 21. 00. F l LX!l H.Fl<l()H ddrcss >f n111.mb ·r of byl ·sill HL n.:gist ·r paiw-
Ft 03 E Tra11sfi:rr1111.1111be..-ofbyLcs from mcllmry lo ·.ati n
lo Rcgi-.1 ·r. '
FOO .F XRA , ' I ~r a 'LU!lllllal.o r n:gi'>t ·w-
F( O 06,(H> M 1.nilializc R ·gist ·w- B willn OOH U> sl. )TI: 1SR'>
of s 1m1.
F( O I. X H ddrcss of l sl llL.111i11 ber in HL pair.
F( 08 66 DD M dd IIIL"m ny I. ) a ·u:m 11lal.or
F( () D2. OD. F() J LE :;-L l Lf carry drn:s TI >I gcm:rat · • j L.l.lllp lo L - -L 1
FOO ( I. R B If carr is g ·m:ralcd. i n.:111cll R ·gisl.c r. B
F( OD OD L - EL 1 0 'R De :t1:mcnl. 'OLl:llt by 011 •
F( UE , ·2.0. F0 1 J z L f ,p T ·st t > ·ln1.sck v lrictlncr additioll of a ll nwnbl."rs
an.'. dom:
FO l l "'2. 00. f2 STA F200 S~u~ L Bs of s111.m i11 · 1crn1 ry I J .. llio11 F20UH
Fl 1 .B ' opy J ill ·11 l 1f B i11 a '. llllill ulaI Jr
FO l , 2.0 l. F2 ST F20 1 Slon.: M SBs 1f s111m in m ·mory lo ~ Lion F201H.
F0 18 6 HLT S~up

1 Dllla --- --- - --- - --- ---- ---- ---- ---- ----T-- Rl!!IIIII -- - --- ---- ---- ---- ---- ---- ---- --- - ---1
t-----------------T---------------------t--------------------------,-----------------1
I M~mol)' loc ion I llit:a : M~mol}' loc ion I 03.t:a. I
•-----------------T---------------------1 __________________________ _,_ _________________ ~
1F l OO , 0 H : F200 , OHi LSRsofsum I
L-----------------•---------------------r--------------------------...1...-----------------J
: FlOl i ffl H : Fllll I OOH MSRs ofSlDll :
I~-----------------t---------------------r--------------------------J------------------
1
Fl02 I 02H I I I
~-----------------r---------------------~--------------------------~------------------t
i Fl 03 , OJH I I i
t-----------------t---------------------l---------------------------<-------------------1
1 F l 04 1 04H I :
1-----------------T---------------------t--------------------------.------------------1
: Fl05 I o -H :
L-----------------i _____________________ i __________________________
I : _l_ _________________ J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

A.drUti nn nf Twn 1,f \. Rit N 11mhP,r ~ with 16,- bi't Sum
START
Argorithm
I. Store fb:s t 16-lbil ntonber in HL paiT.
Sto re t he fi rst 1'6- blt num be r In I-IL reg iste r pa ir 2. Exc:b.a.n ·, e 1tbe c,on•Leat.~ of DE pair and HL paiT to !'.-tore the 6in;t n·umber in DE ·, i.~ter pai-r.

3. ore seoond 16-.bit nu.mber in. HL reni~ter pair.

Mov,e the fi rst nu mber In DE reg iste r pa ir
Addition of firli t and ~eooad mm ber.s.
5. ore resu.11 iTI 8505H and 85 H l.oc.at i.un~~ .
Load secmc:1 16,.,lb lt nu mber in I-I L register pai r

Add the co nte nt of I-I L reg iste r pa ir r-.o;.:i---------------------- -------------r-----R;;;-11------------------- ------1

wit h co nte nt o DE reg iste r pa ir ~-----------------r---------------------•------------------------r--------------------~
I Memo!}' Joe ion I ta I Mano:ry locat ion I Data I
~-----------------L---------------------+------------------------L--------------------~
Sto re the res ult in memcry locat io n ~-~ J-------------+---~=~-1:.~~~~~-~---+-----~~----------------+-~~-~~~!~------1
I &502 I OIH MSBs ofdala- 1 I 8506 I OOH MSB:s: ofSIDD I
[ &503 ____________ ~-- 02H L SB:s: of data-2 _
&504 , OJH MSBs ofdala-2 ,
--i ________________________ [___________________ _]
IL-----------------L---------------------~------------------------L--------------------~
I I
End

,U i!llUJr 1 ,1fa lii11e

labels , 111~TllfJTU' .\: (Jperaud!'!i:
5 LHLD ' Ol H Load tine 0 1H Ii Ml iu . •isl ·r L allild
R ·gisln H is I adoc1 wil'.ln Lh'I ul. ·TI I of 02H I J ~liollil
, 00 -s X ' HG '
1 Tin· ml. ·Tit."s of HL FCgisl. ·r pair arn·x i'langl'-<1. willn D ~
t1.:gi st ·r pair S( I.hat firs! dala is sloTI:d in OE Tl'.gi" ·r
pair
80() 2A . O LHLD 03H Loads :,c,•ollild 16-bil mullb ·r dala-2 iTI HL p.air
, 00 19 DD D Tin '. c Jllill ·TI ls of DE pair Ml'. addL-d v,ri l!h lh!: Jllill. ·Tit.'l of
HL pair and 11:s111.ll i-; sun :d iTI HL pair
00 22.05.,5 HLD 0 H S~or · LS Bs of s Wl1 in 505 H and M SB s f stm1 S06 H
800B 6 HLT HaH

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

Decimal Addition of Two 8•Bit Numbers with 1 ,6 ■ bit Sum

START

lnltiall e t he memory location

o,Hirst deoima l number

Load fi rst deoi ma I

nt.1mber in acc umulato r Algor ithm
I. Lood add:ress of i.he fi.'rst number in L re •iGter pair.
lnlt1ia li e the register Lood the first m.anber in il.C(IUmullator and ":tore H in Re · .•' I.er B .
B witih OOIHI 3. Increment ihe ronieni of JlL re · -:rer pair lo initi.11/ize the memor I t ion of :!leCO!ld data.
Addition of the content of ' toond memor kicat i:on ·with fin:t data .
Initialize the memory location .'i. Decimal adj LL\>'tmeni of re.'ill.lt.
of seco nd deolma I nu mber 6. If earr , ·s , •enerared Re ,i ~'ller B ics incremented by one .
7. re the re.G u tt in F052 and FO.'i3H I •· tionG .

Addition o:r-flrst and

seco nd decima l nu mber

[Je olma l a~jt.1stment

aft.e r Add ition

Increment B by 1
B= 01 IHI

Stor,e the result. In memory locations

End

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 10

,Jlemor .i ,J1a •lii11e
addre~;_,; ( ftdes ("omments
FlO( 2 1. 50. FO LXI H.FO 0 ddr ·ss of lirsl nu.mbl."r in HL ,cgis er p,a ir
Fl O., E MO .M Mo c fir.il 1111111bn i11 ac 'Ltmulalor
FlO 06.00 M l B.<mH Load OOH in ·gis t ·r B
Fl05 2 [ X H l.n ·rcllil1cnl. H L r ·giskrpair lo I J "cal.· . x.~md 1111m bi:r.
Fl06 6 DD M ddilion of l st a11d 211d m11n1bi:r
FlO 2 D IJ :,cimal adj uLsl
FlO, D2.0D. F l J LE EL_ l If -arr d 1 ·sno gi.:-ocrnkd.j1.1mp t 1'LE ◄ L_ l

Fl OB ( BR B lm.Tclillcnl. R ·gisl.c r B

FlO ' ,2. 2. FO L ◄ VEL_l ST FO 2H St nc LS IJ s f R."S Lill in FO 2 H lo "cali >n

FlOF A.B Ml"-' · M · Os fium B ~oA
Fl 10 2. . FO ST FO 3 St nc 1SOs ol ·su.dl mFO H 11 "calion
Fl03 HLT Hall

•---------------------------------------T---------------------------------------------•
: D "1tJ R l!'IM II :
t-----------------T _____________________ LI ____ -------------------r--------------------1
, Memo!)' loc ion I Data I Memo!)' location , Data ,
I~-----------------f---------------------+------------------------t--------------------J
F050 , 52H I FO 2 1 89 H I.SD!i of sum I
~-----------------+---------------------i------------------------i--------------------1
IL-----------------~---------------------i
1-"0 " l : 85H : Fll "J I Il l H MSDs of sum
________________________ L ____________________
I J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 11

Subtraction of Two 8-bit INuimbers
Algorithm
START I. Load a:tld.re.s:s of fu-.!lt number LTI HL re •i~tei: plir.
2. Mo\•e fi~t data into a )'iJmulliitor.
Initia lize the memory locatio n o f fi rst data 3. lm.•--rement the content ofHL regi,;tei: pair.
ublr.ib1 the second data from a umul\a:to.r.
Load first data in accumulato r 3. to.re ihe n:,_~1.LII in memory l\x,a:tion 8002H .

Ini tia lize the memory loca tio n o f seoond data

Subtract the con ten t o f memory locat ion ,

i.e., second data f rom accumulato r

Sto re the res ult, i.e., the con ten t o f

accumulato r in memory location

End

,li/em <JrJ,i ,Wa ,Jiln e

address C.f!des ,t111e11umi ,s Op·e1·ands
2 1. 00. 80 LXI H. ()( 0 dd11:ss ,cf hrsl namb L"r in HL n.::gis ·r pan-
M ·' .M Tr.mslh· ln~l nwnli:11:r in arc wmda or
I X H l.11 TCllillcnl. sun l ·TII. of HL ptlir
s B M S111bL-ra '. l ~oond rmmber f m first TIWitlb L"r
I X H l.11 Tcn1c l c nl ·nl of HL pu.ir
M ' M. S LJl"l: rcs111U
850, HLT Hall

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 12

Subtraction of Two 16,-bit Numbeffs

Load f irst 16-ibit lilLHlibe r irn D register pair

from memory locatiorns 00001-1 aoo 800 11-1

Load secolild 16-ib~ rl l.lmber irn BC reg ister

pa ir from memory locatiorlS 80021-1 and 80031-1
Algor.ithm
I. Lwd fin,! number in DE re,gii.'le:r pair loom r=mory ~ ti.um 8000 and 800 IH .
Lwd seOlllld nwnber in B _ re •-i:.~te:r [liiir from memory lacati n.~ .S002H an.d 8003H.
3. Co.mpare L B.~ of two number~ E an.d C. Tf E ~ . fmd D-IJ and F. . When E < C, find D-/J-·1 and
E+ - + I.
Then , ·ore :re.Gull~ i-a me:rnor ' luca:tions 9 OH and 90O 11-I .

Stoi:e t he resL1lt irn memory locations

5111d

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 13

Memory JU, di Jne
'ililres.~ ,Q i d, LJbel .
8500 2 1, 00, &0 DJ H,&000 l.oad address of fi rst number in HI.. rcgisrer pair
8503 "E MOV E, l'Y.f l.oad fi:rst wm bytl! numbcra i.n UE n:gi:ster pa"ir
L:sBs in RqisrerE and MSBs i.n Rcgisrer U
8504 INX H Iocmncnt oo11tmt ofH·Lpa.irforaddn: of. ond
350 - M O\' D, M number
8506 INX H
&50' 4E M O\' C,M Load ond t wo byte: monb cr ·in BC rcy;i:ster pair.;
850& ? INX H LSBs in Rl:gi er C and MS& in R£gistcr B
&509 M O\' B,M
&50A MOV A,E T1111nsfcrl.SB:soffi:rst number i.n a.a :umulator.
850B CMP C C-0mp1m : bcm"c:c:n l.SB:s of ond numbcr
d I..SBs of fast nmnbcr
&SOC DA, 00, - JC LEVEL l if cany is gmcm:tal, j wn,p to LEVEL_ l
8501/1 ' B M O\' A,E Tmmferl.SB offi:rstnumber ·ina.a:umul tor
91 C FindE-C
3· 00, 90 TA 9000 1Dn: lSB:s, crorult of(E- , in OOOOH'loc ion
'7A M O\' A,U M SBsofll)Ccond number in .a :wnulator
9& SUB B FindD--B
3· 0 1, 90 STA 9001 S1Dn: M S Bs, D-B in 900 l loc lion
0,2B, J MP B Jump to 2B
79 l.EVEL l M OV A,C Transfer l.SBs of fi:rst number in aa:umula.tor.
21/1 CMA C',ct t:hc c:mr~pkmcnt ofC =l'
&J A DD E
O'i, 01 A Ui OIH Determine E l' I p.1 iT
3· 00, 90 TA 9000 1Dn: lSB:s the n:sult of E :i; l in
9000H loc t io11
A M OV A,U Tmnsfcr MS'Bsoffim:11umbcr · a:umul tor
00 SUB B Subtra.c t B from c:umul or
Dll, 01 s OIH Subtm.c t orn fimn rumul r . F ind -~ B,-- 1.
3· 01, 90 TA 9001 1Dn: MSB:s, 1lhc remit ofUBl in 9001H loc ion
76 H LT

[ D llla i Re.w t 1
It------------------r-------------------------,---------------------,-----------------i
Mc:mo:ry location I Data. I Memory locat ion I Data I
t--- . --------------r------------------- . -----~----------------------.-------------------1
1 &00 1 1 RlHLSB:sofdata- 1 1 &005 1 FFHLSB:sofsum 1
f------------------~-------------------------~----------------------+------------------i
I 8002 : RlH MSBs:of data- I : &006 : OF'H LS Bs of sum I
1------------------~-------------------------~---------------------+-----------------l
1 &003 , OFH LSB:sofdata-2 1 &007 , OlH MSB:s of sum 1
t------------------r-------------------------,---------------------...,..-----------------1
iL------------------L
8004 I _________________________
l F'H MSBs:of data-2 : i i
J _____________________ ...J.... _________________ J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 14

One's Com p~em en1t of an 8-bit Number

STA'RT

load data ifl acaJmulator

from ory lom11lon 8i()S(}H Algo.r.ithm
I. Lood memo , location of data SOSOH in HL re ·,i'iler pair.
Comple;rnem Ille oootem
of aooumulaDr 2. M011•e data into aroumul:a:lor.
3. Complement arou.mt.illiitar.
tore the R!'-~utt in 1ibe mem.ory l!aca:ti.on 80.5 1

End

Memory M diine
adJres., ,C oda Lzbeh J\'fnemonks ~rand!i -C ommmt.,
8000 2 l, 50, &O I..XI H,l!OSOH I.. d ddre.s:!l of nwnbcr in HI.. registc- pair
8003 E MOV A,M M O'i/C the number into rumul.ator
8004 3F CMA c~mplancnt ccwnul tor
&Oil - 32, -1, &O STA &05l H Ston the resu'lt in &05 lH
&Oil 6 HL'f top

~ Dllla __________ r ___________________ ----L Re.Wilt ___________________ _[_ _____________ ---l

! Mcmmy location i D.1ta I Memory loc ion I D.1\1 !
[ go o _________ _I _______ FOH ____________ !_ go - 1 _____________________ Lorn ____________ J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 15

Two's Complemen1
t of an 8-bit Humber

STA.fU Atgorithm
I. Tran'.~fe:r the content of the me:m.or , !oc:.a:t iun 8.'lOOH to
Load dala in accumu'la10r aroumubtor.
from me.noory locaU@n 8500H
2. Complleinen'I the roa'lent of the acoumufator.
3. AddO IHw ilh aroumt.illatorto ~-a1 t""o ':s oamplemen'l o f a n'umber.
Comp'lement lhe mment Store the re.~ult irn the memory Il · a:tion 8501H .
of u1ator

Boo

L1hel. Mnemonics <Opt!Nlndi ,C ommmu

LUA 8500H l.oadthc oo:nlent ofmcmory locat ion
&SOOH in ccmnulator
-13 2F C MA Complement ~rumulator
-14 C6, 0 l ADI om AddlllHw-it!h ccumul .t or to find tvm's
oomp lcmcnt of the number
-16 32, Ill, & • STA 8501H rrc result in 850 1H I t ion
. 0 19 6 HLT [P

f---------------------------------------r---------------------------r-----------------l
D/IJa , R'511ll
---------------T-----------------------~---------------------------~-----------------
1

i M~mol)' Joe I I i
r&500 __________ t_________FOH __________ !_ &SOl ______________________t___ lOH __________ j
ion : l!l:lm M~mol)' location llita,

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 16

Slh ift an 8-bit Humber Left by One Bit

Sl'AIU
AlgorJthm
I. Load memo. , location o f dati 80 ·H in. HL re •i'ilerpaix.
2. Move data frum memo1y to a m ator.
3. Content of a )'Umulator rotate l!eft by om:bit.
lo.re the Je_~utt in 1ihe memory l!aca:tion 800 I

End

Memary i'dacliine
'ildres. Otdi!. UJbel., Mnemonic., Opi!roNI. ,C ommml.
80111 21,00, 30 DJ H,&000 Load mcmmy addr of d!l.t a &OOOH ill HL pair
80lJ E MO\' A, M MO'i/C data. in acrumu lator
8014 07 RLC C~ntmt of ccwnul tor rot:ak kft by ooo bit
801 - 23 INX H lncmncnt H t n?gistcr pa ir
8016 MO\' M, A Smn? 1ihc IT&U lt inmcmmy loc ,l ion l!OOlH
801' 6 HLT Ha.It

r DoJo 1 ROMII r l
[Mcmol)' loc ion:=[:==::==::= lllti =::=::==t==::= Memo])' loc :ion :==::==t:=
: !!;050 : 04H : 80 l i
CAltl ::==::==:] 08H :
~---------------~-----------------------~---------------------------~-----------------~

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 17

SIMft a 16- b'Srt Humb er Left by One Bit

Algorithm
from I. Load 16-bii or 2-lbyte data [rum memo. loc.a:tion m lil. ie •-ic~ter pl! ir.
2. Content~of HL re •·ii! ter pl! ir are added to itself on and the result , tared in HL pair for :sh ift l'e · by
onebii
3. Store the result in OO.'i3H and 8053 location_~ .

Stote ~ result, i.e., i e com.em

of I-IL in me ry
IDca, 8054H

End

i'demary i\fa.:lun e
adJN!!I.¥ ,Code.¥ Label. J\1nemank:. ,Opi!rands 0:mmi enl!I
811111 2A, 50., 80 LHILI) 8050H l ood data.from mcmmy Joe Ii.o n 8050H d 80 · 1
to Ht ngista-pair
&UH 29 DAD H Shift 16-b it numb a- by OO£ b it
8104 "J, 80 SHLD go · H ton: re-suit in 80 "JH nd 80 " H memory
Joe ions
810 76 HlT

rDoJa - --- ---- --r- ---- ---- ---- ---- --- - --l-----Re.WIii - ---- ---- ---- ---- --- - --- - --- ---- __]
I Memory location I Data : Mcmmy Joe ion i D I
Ll!O O ________ __ [_ ___ 52H _____________ _ _l _____ 80 J _________________ [ _ A4H LSBs ofn:-sult _j
IL---------------L-----------------------~---------------------------L
00 · 1 I "H I so· 4 I _________________
OAH MSBs ofn:-sult I
J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 18

 IF'ind o·ut t he Largest of Tw,o Numbers

Dlllri)er ill acrumUlatoJ

AlgorJthm
I. Llad Ole fi~t n\.lrnbe:r in aet.'l\J.mullator frurn the mem.or loc,a:tioa 8050H.
Compare ~eoond n'umber with fin.1 number.
3. If ~ nd number i-.~ "rea:lie:r than firs t number, OOifl: · Second number in the arou.mul:a:tor from memo
Store Ole re,i;ull in 80.52 . l.ocatiun.
I!)

Seoooo numb is large:51

and inlo!i) acrumula!.oJ

l'J em·ory J\1 adline Store the largest ilJfflt.eI

'Jfdres.~ ,C odes lJnffllonk-.~ ,O perand.,
81011 2 l, 511, &II LX I H,311511 !" fumi memory
End

8 1113 7E MOV A,M

8104 23 INX H Addn?ss of 2nd nwnbcr in HL pair
3 111 - BE C MP M C-0~n? bctwem 2nd nwnba- nd l number
8106 ID2, CIA, l JNC LEV-EL lfboirow ( CSlll)' i.snotgencmtoo, jump LEVEL
8 1119 7E MOV A,M Mow 2nd number in c:umul r
&LOA 32 LEVE L STA J00.52 Smn? 'laJQ!4? nwnb a- i.n &a1,""2H
&l llB 76 HLT Ha.lt

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 19

Find out the Large.s t Number fr.om an Arrary of Numbers

START"

Al90rithm
I. Load oounl var-u.e of numbe:r.s 05H in Re ,i:_~tc:r immedi.atei '·
2. Load the fi rst number in aroumul:atar from the memor lllGil:tioa 9 I H.
3. Move the fir.st number in the · oum.ul:a:ior.
Decrement the oounl ·,'il.h.ie by one.
5. 'Move to ithe ne::d memo · kK.-;a:tiun far next da:t:a.
6. Compare the content ofmemory w itb oontent of a ,wnulliitor.
7. 1f c.a.rr ' i · .,en.er.ired, ooP'. uontent ofm.em.or ' in a ~umulla:tor.
8. Deaem.ent the oount · 'il.loe I> , one.
9. If oount \'alue doe.~ not equal to zero, repeat •.tep, 5 to 8.
I 0. :o re the re.s1Jlt in !XI06H lllGil:tion .

En:!

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 20

Jtfl!mary M, dil!t l!
ai/Jr, . , Lab«.f Mnffll•onJc.~ •O}lt!Nllllfs ·Comml!nt.
MV I c, o- Load cout va:Juc in Rcgi e r e
91112 2 1, Ill, 911 U::I H, 9001 Load ddress: of fim dlil in Hl ~ u pa.ir
9111 E MOV A, M Co,py 1 dl:lil in a.e cumul .t or
9106 (Iii) OCR C Decrement Reg i r e
91117 23 LOOP INX H Increment HI.. n:gi.sta' for .ddress: of ocict dan
9108 HE CMP M Comp ooc:tdlta,\\tjt!h c content of accwnul or
9109 02.,110,91 INC lEVEl If carry oot gc:ocnttcd, j wnp to l. £VE l
9lOC E MOV A, M Co,py 'laJge number in cumul if fimmmcmmy
9 1111) 01) lEVEL OCR C Decrement Reg i re
9lOE C-2, 0' , 9 1 JNZ lOOP Jump not zero to LOOP
9 111 J 116,911 STA 9006 toIT 'l number in 911116H 'location
9 11 4 6 Hl.T

I Dllla , Rl!.'11111 :
~ Mcmmy
1
-------------,------------------------t-----------------------~---------------------i
loc ioo , llita I Memory location I llita. 1
I I I I I
['l.liDlll __________ J_-:DH" ___________________ J_ gllOi) _________________ ~ ______ Fm ____________ ]

l 9002 l FFH : i l
1
9003 --- ---- __J_ 4 7H --- ---- ---- ----
t 9004 , ~2H
----l---------_---_--- ----_I__-------------------
, I
li 1

[900 -_________ j_ IOH ___________________ i_______________________L_____________________ ]

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 21

IFi1nd out the Smalll est of Two Humbers

Algorithm
I. Addre.~s of the fiI's-t n1.1.mber i.Gin HL ~ ,j-st~ pil'ii:.
2. Mcwe lin:t number into a · · umulator.
3. lnerement HL re •·i!.te:r pair for addr.sl-.inr• !leCOnd number.
Compare ~roond number with first number.
5. \Vhen the fir.st m.mber i.GI .Gs l:han seoond n'umbei: the oontent of ' :OL,1.LmuJ1.itor i.Gthe smaDle.,;t n'LDILber.
1f seoond n'LDILber i.G ~,GR iha.n fi n;t n'LDILber, OOiJ.l: , seoo.nd number in a umu.l.ia:lor from memory.
6. lore the ~~utl in 9052H location ..

IEnd

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 22

 J\' f~mary J'dadlJne
lufilll!I. O Mfe.f uibel. i'd lll!manics ,O pl!ran~
9100 21, .50, 90 I..Ji.1 H,9050H annulator frnm

9103 7E M OV A,M
9104 INX H Addr o:f2!oo 11wnbc.r in HI.. pa:ir
910 - BE G l"P M c~p 2nd 11wnbcr d l nwnber
9106 IDA-- JC l.EVEI.. lfbmr • ( C3IIJ)' is gmcmtal,j um,p LEVEi..
9109 7E M OV A,M Mll.'C 2nd number in .c aunul to r
910A 32, - ,90 l.E\'"EI.. S'fA 9052'.H S to~ smsllc nwnbcr in 9052'.H
9101D 6 HI..T Halt

ID4"1-----------------------------------i-Ri.wii______ ---------------,
~---------------------------------------+-----------------------~---------------------~
: Mcmmy loc ion : IDat:a : Mcroo:ry loc ion : ID3ta :
too-o----------~--1sH-------------------t--oos1------------------i--flfH----------------1
t 90 _l ____ ---- ---t- - FFH --- ---- ---- ---- ---f--- ---- ---- - --- - --- - ---f---- ---- ---- ---- ---- --~
t ______________ J________________________ l _______________________ ~ _____________________ J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 23

Fi1nd O'Ut the SmaUest Humber from an Array of Numbers

START

Algor.ithm
I. n re oou.nt ofnumben. OS i:n Re -·:.-ter immedi..ire~ .
2. Load the fin.t num.be:r in aocu.muliator from memor ' I " tion 8001H.
3. Decrement the oou.nt '\'il.lue b • one.
Move to next memor ' l'o<:ation for next da:ta.
5. Compare the oontent ofmemor •w ith oontent of ' :,e;umuJ1.itor.
6. Tf carry i:s not generated, oop: , the oonten.t of memor · in arou.mulator.
7. Decrement the oou.nt '\'il.lue b • one.
8. Tf oount value doei, not ~ ua.l to zero, re,pt".tl step, 4 to 8.
9•. n re rei.u lt in 8006 location.

End

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 24

Me111,qry M diine
;uf,i,es_f ,Co d, LaM. AJnemonJ.:-. Opl!Nnd!I ,Commenl.~
lllOO OE,05 MVI c,o- l!...oad rou t value in Rcgi rC
8102 2 1, Ill, 811 DJ H,8001 l!...oad addin?ss: o iTir number in HI.. ngister pair
&10 - 7E MOV A,M Co,py tim: nwnl!u in .c rumul .t or
8106 OD DC R C Dlmunmt Register C
8!0 23 LOOP INX H tn mm1mt HI.. n:g i r fur address ofooXil number
!!IOI! HE CMP M Compare ooXil nwnbcr with the contmt of crumul tor
1!!09 DA, IID ,11 1 JC t:EVEI.. If c In}' 'is gmcmtcd, jump 'D ·1..1:VE I..
l!IOC E MOV A,M Copy l c lllllll'bcr ·in acrumul tor from IDlllDOJY
l!IOD OD LEVEL OCR C Dccmnmt Register C
l!IOE C-2, IJ , I JNZ LOO P Jump oot 21:ro to LOO P
111 l l J 2, 116, 811 :STA l!Oll6 S tore small1!51 number in 9000H loc ion
IU 0 4 l'l Hl.'f

lDo/a - --- ----

: Mu n my loc ion I llita.
----r ---- ---- ---- ---- ____ [ __ - -- Re.'1111 ---- ---- ---- --t-- - - - - - - - - - - - - - - - - - - - - -·
I Mcmo:ry location I IData
t----------------r--------------------L-----------------------~-----------------------
1 l!OO l I OlH : l!OOO I OlH
•----------------~--------------------r-----------------------~-----------------------·
: 8002 : FA-1 : I
~---------------.l...--------------------+-----------------------f-----------------------
1l!OOJ : 27H 1 1
t---------------;---------------------+-----------------------~-----------------------·
, &004 1 44H I i
~-----------------+---------------------L-----------------------~----------------------- ·
l l!OO I 65H I I
~-------------------------------------------------------------J----------------------- ·

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 25

Arrange a. se,ries of Nu mlbe1rs in Descending 0rder
1

START

E n:!

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 26

Algorithm
I. re 05H number of data to be arr.in ,ed in Re •i&ter from memory and :store n'wnber of oompari-
oom in Re •·ister D .
2. lnil ialliize the memory l'oc,atill[l 9 offtrst data .
3. Load the fi rst data in a · · umt.ilator from memor '·
Increment HI... re •i~-ter p,air fur add~Gs-in • next da1:iil.
5. Load the ne.~ data in Re · -:ter B from rreroo1y.
6. Compare next data 'wi th a-oou.mula:tor. tore th.e smafle,,i;,t number in a - umLillator and lla:i!J:est number
i11 memor ·•.
1. Then next n'umber is compared with a · um ator an.d i.t ore the ~e.Gt number in memor · an.d ~H-
ei,-; number in a :,umLilla:tor.

8. This procoe:ss will con'tinue n1 oompi,ri!:iOn of an ntm1bers ha,.,e been oumpk:ted After completion of
oo:i:ipariisll[l of aH n:wnbeis 1lh.e :sma]la'lt nwnber in a-oou.mula:lor and store ii in memol}'- In thi.~ 'way
th.e fl-rst l_ll"(!Ce.•,s will be oompl1eted.
9 At the :sti.rtin •· of second !Pruoe.~s- Reg.ii,t er i.Gdecremented and store ntJmber of oompari:.~n'.~ in
1•

Re ,·ic!iter D Then repeal i.1:e,p; 2 to 8. A 'er completion ofth i:.G proce.Gs the :smallest n'wnber i:.G in 9005H
and the second !.'IIIAilfe.s l ntJmber i.~ in 9 H.
I 0. Re •i~ter icS decremented and Hie ne.'d prore!L~!.tiilrts if 'Lh.e content of Re •ic!iter i.~ not zero .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 27

J'lfl!ll1MJI J\f. '£1IJIII!
a,idr ~ 01,ie.~ Label.~ M11mto nic .~ ,0 'paands •O1/tJ'lllt!III.
9!00 0£, 05 'MVI C, 05H Load cOU11t vallll! ofmunber of dala. in Rc-gi rC
9 10 2 16, o- START MVI Load collllt fur number of romp oons in
il£g is:oor D
9Ul4 21, 0 1, 90 1-XI H, 9001H l.oadmcmory loc ion ofl number
9107 7E MOV A, M I munb cr in cumul II"

9 101! INX H rncremmt Ht register pair fur addn!~in

natnumbcr
9109 46 MOV B, M C'ol')'nat munbcr in R£giffr 'B from mcmmy
910A Bl! CMP B Compan: nat numb a- w i1lh .c cumul br
910 8 IDA, 17, 91 JC 'tEVEt l lfllhc contm t of .c cwnul tor > ooxtnwnoo:,
jump to LIE\'El l
9UIE B DCX H rncremmt Ht register pair to locate 1lhc a ~ing
ring larg4: number
9lO F ' 7 MOV M, A ore ·1 g,£&t ofllhc nm numbcn: in manoiy
9 110 '8 MO\' A;B Move smallestoftht two munbc:r.;: in .c cumulator
fmmRcgistu'B
91 l l c.l, 19, 9 1 J MP lEVEt Jum,pto LIEVEt_2
911 4 2B DCX H
911 - MOV M,A Place smaller of c tll!.'O munbe.lll in crumul tor
911 6 C.J JMP Jum,p to U:VEt_2
911 2B llEVH l DCX H Store ·1 g,£&t ofllhc tll!.'O numb cr:s in mcmoiy
911 8 70 MOV M, B
911 9 2J UVH2 INX H
911 A 1- OCR Decrement Register D to oount for munber of
mmpari:sons
9 11 B , 01!, 91 JNZ tOOP Jmnpzcm to
911 IE ' 7 MOV M,A Pl cc sm:a.llat number in mcmnry
911 F OD OCR C Dccrcmcnt cOU11t valoo
912 0 C2, 02, 91 JNZ START Jump not :urn 1D START
912 3 76 HlT Halt

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 28

Find out Sq1,u1;r,e Root of 0, 1, 4, 9, ·t 6; 25,, .36, 491 64• and 81 1u:inrg
a Loo:k-Up Table

Algorithm
I. ·ore the number in the a -umu.tator from the memor , location
9000H.
2. Mo,.,e ihe c ontent of a umu.tator in Re • isier L and ..tore 85R in
Re •i:.~terH .
3. \\/hen ihe number i.~ 16, the content ofH and L re• ·ster.s are 85H
and 16H re.~pecfoe ly. Then the HL re •i:.~ter · ir rtpre,,;ent~ ihe
85 16H memory ! · tion .
Cop the .square root of the mon.ber in the a mutator from the
memory location which i.~ represented b JU. re .i,t er pair.
5. ore the resu.tt in I .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 29

M em·o ry l't1 'i:hlll .t!'
'J/dr; -~ ,Code.~ Lilbeh i\lMmoniCl ,O peraNI..~ ,C ommenl!l
911111 3A, OO,OO "I..DA 9000H l..oad the nwn bes- in
Joe i.o:n9000H
91113 6F MOV 1.., A Copy the content of Acrumu] rr ·in Rcy;istcr ·1..
91114 26, l!" MVI H, -· l..oad >H in Rt:gistcr H
9 lll-G ' E MOV A M MoYC sq11Sn: l"OOt ofdecimal nwnber in .c cmnul tor
from manoiy
9111 32, Il l , 911 S'fA 9001H Sto:re sqttarc m Jue in900lH
9111A 76 H"I..T

r ADDRESS i SQl.iARE ROUT ]

~------------------,---------------------l
I &S-011 I oo I
rL-------------------t----------------------'
&S-0 1 T 01 1
I &5-04 : 02 I
~--- ---- &5-09 --- - __
I -[6
J-------- OJ - - ---- ___ )
I (14 I
L------------------~---------------------J

~--- ---- _ -2 _ ---- ----~--- _ --- _ 0 -- ---- ---- ~

I -36 : oo I
r-- ----- 11549 --- - ----r-------- 01 - ---- ----l
~-------------------~--------------------~
I 8564 I os I
r-------------------r--------------------,
1 l!58 l , 09 1
L------------------~--------------------J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 30

Mu ltiplication of Two 8-bit Numbers

AIJor.ithm for Repetitive Addition

I. tore mult ipli:cand in Re ri:.\'ler Band multiplier in rister E.
2. Clear Re ,·i.<:ter D and cle-.ar KL re · -:ter pai-r.
3. Content of DE re ,i<:ters will be added w ith content ofHL regic!iter.s.
Decrement Re •·ie!iller B .
.5. If content of Re ·!.'!er B i ' not c;qua] to zero repe.at ·,tep.~3 to .5 .
6. \Vhen Regi:si.er Il i.- c,q u.al to zero the c ontent of HL will Ix: 1iored in memory location1i 90 H and
900 1H.

M enu1ry Ma dilne
ail.tr ,Code., u beh i'dnemanic:., ,Operand ,<J>mmm l.
9100 21, 00,M LX I H,&OOOH Address ofmult i;pl.icr in HIL pa.ir
9103 4E MO\' C,M Sto:rc mu]t i;pl icr in Rcgi u C from mcioory

9 10 4 24 IN:X H Address ofmult i limnd 'in HIL pair

910 ·- ·-E MOV E,M M ult\pl ic-and in Register E
9106 16 , 00 MV I IJl,OOH 11..oadOOH in Ri?gi rD
9108 21, 00, 00 l..XI H, OOIIO Init ial vallll? of pmdoot =OOH in Hl. pair
9108 19 l-OOP DAD I) Add content oflJE w ithconrent ofHl
9lOC OD OCR C l)cc:rnmcnt Reg ister C
910D C-2, OB, 9 1 JNZ !LOOP lifoot 21em, j wnpto l OOP
911 0 EB XC HG Tibc co:ntcnt oflJE n?gi c.rp ·rand Hl reg istcr
pair exchanged; n:sult in DE n:gi er
91 l l 21, 00, 911 l..XI H, 9000H ILoadOOOOH in HL pa.ir
911 4 J MOV M;E Sten content of Register E in OOOOH loo ion
911 - 2J IN:X H Address ofncxtmcmory 1 i.o n in Hl. pa.ir
911 6 72 MO \' M,D Sto:rc contcnt of Register E in 9001H loo ion
9 ll 6 HILT Stop

r------------T---------------r---------------.--------------,
J AdJu.u I Data I AdJu.u I Re.w:11 J
t------------1---------------r---------------r-------------1
1 8000 H , 45H Multiplicand 1 9000 H 1 05H 1
~------------~---------------L---------------~-------------~
J 800 I H : UH Mu ltiplier I 9001 H : FFH J
L------------~---------------L------------ ----1--------------J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 31

Binary Multiplication

START

Algorithm
I. Lood the multipllicand and mulliplliser.
2. lnili.afue produ 'v a"lue = 0 .
3. Loo:d ni.Jmber of b it.~ of multiplier in Re• · ster C.
Sh if-I multiplier r i , hi by one b it.
.5. If t."'.illl" Illa ,. i.~set mu[tipllicand add.~ 1,.,-ilh irutial \•alue O H + mull ( i:c-,and Th.en p:odoot is e ua.l
to O H+ mU:ltipfa:i md. Thi!!i re1,1.1.[t i!!i also called as parti,al product. Then partia.l podl..ll>i i..~ "rafted
l!efit , on e b it.
6. OCR counts v.ilue,
1. If lhe oontenl of Re ·st-er i,· not zeru modifred multiplier a n·· in sh ifted me b it rhghi . Product =
Prodoo:+ M ,ilicafld
8. If can- Illa , i,s s . sh ifted rnultipl icand add~ w ilh pa.rtia I product. Th.en oaoe a , ·· in s hi, s 1he modi li'ed
mutt iplicand le .
9'. Rt,pe.at step.~6 1 a.nd 8 till the ooatent of Re •i~ter beoome.s zero.. IDeaement
IO. Store l:be result iTI 9000H and 9001H.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 32

J\'femury
'IIJr, iUnellfflnic., ,Opera11d . ,G u tJ'M ffl l .
9LOO 21 00,.IIO lX I H,l!OOOH Address ofmult ipl io.md in H l pair
9LOJ )IE MOV E,M Store multiplicand in Rcgi r E from memory
9104 INX H Address of mult iplicand in Hl pair
910 - 56 MOV ll,M Multipl ic nd in Rcgistcr D
9106 OE ,08 MV I C,Ol!H l .oadO& H in Rcg:i re
9108 JA, 02, &O lDA 8001H l..oadmultip liu · .c cmnul tor
9108 21,00,00 lXI H,OOOOH l'nit ial value ofpmduct =00 in HI.. pair
9lOE 011 lOO P RRC 'Rlln tc .c cmnul .lion left
9lOF U2, l l, 9 1 JNC l..:E\'El Wt!htn? i.s oo carry, j mnp to level
911 2 19 DAD I) Add 0011tmt ofDE w ithcontcnt ofHl
911 ] EB llEV El X CHG The content of DE ngistcrpair nd H l n:g istcr
pair exchanged, rarult 'in DE rreg:i r
911 4 19 DAD H Multipl ic nd . II iftoo one b it right
911 - EB XCHG loo content of DE ngistcrp ·r and Hl n:g istcr
pair exchanged, mrult in DE rreg:i r
911 6 J STC O the carry flag using set c-arry d
en oomplcmcnt 1!ht carry tm
911 JF D iC
911 & OD OCR C Dccrnmcnt 'R.cg:i er C
911 9 C2, OE, 91 JNZ lOOP W con'lmt of Register C 'i.s oot zero, j mnp to
1..-0 0P
9 ll C 00,90 HlD 9000H Store 1!ht content of Hl n:g ister pa.ir in 9000H
soo 900 l mcmol)' Joe ion
9 ll F 76 HlT Stop

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 33

IDiv"sion of Two 8-bit Number.;
Repet;tive Subtractions

Algo.rithm
I. ore ilie dir,•i:dend in ilie memory l'oc:at iun 80 and ilie
diii•i:sor in the memory ki<-.a:ti.on 8001H .
2. Clear Re Ti:.'iler i.-t orin ,. · H w ilh in it
3. Mt·we d i1tidend in a tJmulialor and oop it in Re ·,i~te:r D.
Su.bt.ract diivi.Gor from d i\•itlend.
S. If carry iG not LJenerated i:no:ement Regi:.te:r C. Re,peat
,1iiep.~3 to S.
6. \Vhen l.l.rr)' i.~ .,ener.i.ted, quotient, content of Regi.~ter
and rem.fl inder oontent of Re ,-ii_~er D are stored in mem.-
or location.
7. If zero a -, i: set. Re ·, i.~ter i:.~ incremented by one. Then
quotien oontent of Register and rem.ai:nder, oontent of
Reni:.~ter D are :StiOred in memo. location.

End

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 34

J\femmy J\1adi l11e
adJlres. ,C od Lobel. ,Comm·ent.
9100 21, 00, 00 tXI H,OOOOH A ddrcss of d ividend in HL pi.ir.
9103 36, 22 M VI M, "Div idend ton: d iv idmd in memory locat ion
(l) ividcnd)
910 - 2J INX H A ddress of d iv iSIOO" in Hl.. pair
9106 l6, 21 M VI M, Div isor S tore: div · r in mcmmy loc ion
(l) ivi if

9108 OE,00 M VI C,OOH L oad OOH in R.C?gistcr C for in it ial Jue

ofqoot icnt
9 10 A ucx H Do::n:mcnt Ht n:gistcr pa.ir
9 10 B MOV A,M L oad dividend in cumul o:r frommcmmy
9 10C MOV l),A C~ dividend in Reg i.ter D
9 10 1) INX H lna:cmcnt Ht n:gister p air
9 10 E 9/l SUB M Subtra:t d iYiSIOO" from d iv idend
9 10F DA, l B, 9 1 JC tEV Et_ lhhcn : isc ny j ump to LEVEl.._ l
9 112 CA,20, 91 JZ lEV Et_2 lhhcre iszcro, j ump to LEV£t_2
9 1l C 2B UCX H Dccn:mcnt Ht n :gistcr pa.ir
9 11 6 7 MOV M:,A S tore moditii:d d iv idend in memory
loc ion from cumu'I if
911 7 oc INR C lncn?mcnt 'l ttgista" C
911 8 CJ, IIB, 9 1 JMJ> t .OO P
9ll B 37 tEVEL l STC Cl£ar1ht c,my flag using S£t CSIIT)' s 13Jtl.l!l
and then co:mplcmmt 1ht CSIIT)'
9ll C JF CMC
9l lD CJ, _ l , 9 1 Jlyfp LEVEt_J Jump to tEV Et_J
91211 oc t EVEt_ INR C
912 1 l , 00, 90 lEVEt_J tXI H, 91100H
9124 ,l MOV M,C :Store qooticnt in 9000H imm ·RJ i rC
912 - 2J INX H Increment Ht n:gister p air
912 6 '2 MOV M,U :Store remainder in 9000H 1mm Ri:gistcr C
912' '6 Hl.'f :Stop

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 35

 fl:fnory Division Bi:n.arydi,•r.~iaa r.5 al<,0 perb.r rned b , i:ria] subtra io m. The di,<i:sor i:.~ s ubtracted
from the B rm.Gt s ignificant 1:iit:s of the d ividend. When there i:.~ no bornw.· the bit ofthe quotient i: :set to
I· otberwire 0. Then the dividend and uotient are sh ifited [left by o re bit be bre the next subtraction . The
di,•itlend and q L10I ient can lL~ a, 16-lbit re · sler. A,; di,<idend is shi ed, aae bit of the re · .iter Ellis vacant in
ea-i.:h i;tep a nd ,the 1IDtient i:.5 •.tored in unocoupied b it pa; ition'.~.
The di,•i:dend i.5 a, 16-hil number and di\ . sor iln ,8-lbit number. \Vhen the di,<idend i:.5 iln 8-lb it ntonber,
place OOH in MSBs po.5itiom . Th.e di,'1rlen.d ES stored i:n.the memory foca:t iom B H and 8 I H. Th.e di'l'i~or

i.5 placed in the memory l!ocati:on 8002H. The resutt5 will I be stored i:n the m ernor loca:tion.5 800'.m and
SO H.

PROGR. M 4.27
M emary M adlilll!
'ifdr Coh.~ Labl!l!; i\fnt!ltlonic.'I ,(J:perand>i •C ommenlS
9 100 2A, OO, &O LHLD &OOOH Store d ividcnd ·in HI.. pa iT
9 103 3A, 02,&0 IL.DA 8002H tore d ivisorin .a :umul .b rr from mcmmy
h,c ion 3002 H
9 106 47 MOV H,A C-0,py 1!hc mn11?nt of .a :umulator in l«gis tuB
9 10 OE, 01! M \11 C, 08 l..oad O!!H in l«gi i?rC
9 109 2!I LO) P DAD H Shift dividend nd qootim t right by ont b it
9 10A 7C MOV A,H Mow MSBs of dividend in .a :umulabrr
9 10B 90 SUB B ubtract d ivi:mr from dj,,, idmd
9 10C
9 10F
DA, ll, 9 1 JC
MOV
LEVEi..
- If ml is cany, jwnp to LEVEL_ l
Afrersubtra.c tion ore dj,,,idcnd in ·R£gista-H
67 H,A
fimn cumul or
9 11 0 2C liNR L lncnmcnt L n?gistcr
9 11 l OD LEVEi.._ l OCR C Da:remmt C rrcgi c:r
9 11 2 CT, 12, 9 1 mz LOOP If ml is oo zero, jump to I..OOP
9 ll - 2, OJ, 80 SHLD &OOJH Store usul In 8003 d 8004 H
9 11 & 'G HLT Stop
.,..... ...... ... ......... ... ....... ........

.......................... ... .
r-----------r-----------------------------T----------------------T--------------------,
I Addus. : DaJa : Addus.~ I Resull I
1
t-----------~-----------------------------+----------------------+--------------------i
l!OOO H ' 9A H LS Bs of di,·idmd ' 9003 H ' F2 Quotient 1
t-----------~-----------------------------1----------------------t--------------------1
I 800 I H I 48 H MS Bs ofdr.·idcnd I 9004 H I 00 Remainder I
l 8002 H _____ [ ___ IA H D r.·isor _______________ J_ _____________________ l_ ___________________ ]

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 36

Convert an 8-bi .. Hexadecimal! Number to, Binary Number

lni1iia1iz.e lilTJe addfe9s OOOOH o f J-r.u:m v ry Jn ·1 .11a11.ne

He:xadedmal nmrile in IH4. R ~ adilll!I.~ ,Code.~ Label.~ J\f1U!tllOJ1 k:. ,O'JN!!l 'iHld!I ,Commeru.,
and a:mre numbe1 in memo
8HIO 21, 00, 80 l XI H~ H lnit i.sl iu 1!hc me:mol)' loc ion llOOIII H 1lhrough
HL n:gisoor pair
8 11H 3'i, DATA M, UATA l!..ood UATA "in 1!hc mc:mol)'
s 10 ·· _l , . ., 80 LXI H,30S&H lnit i.sl iu 1!hc me:mol)' l..omt ion30 " H to n:
binary
8108 JA, 00, l!O LDA 8000H l!..ood d .-in accumul r from the mc:mol)'
location 8000H
8HI B OIE,Ol! ?,,f\'I C, Ol!H Store Ol!H in Register C
HI D IF I..OO P RAR R c 1lhc content of ccumula,t or rright >A'i1h
ClllIT)'

810E ..F M O\' E,A Copy c cnn,mt of cumul or in ·Register E

810F JE,00 M \'I A,OOH Store OOH in accumu] r
81 l l &F AIDC A Add 1lhc contents of .ccumul .tor dc Ill)'

811 2 7 M O\' M, A Move the content of ccumul.a:tor in memory

8113 7B M O\' A IE Tmnm:r c content of accumul r in R£ g isoor E
811 4 El-7 ORA A C k:ucmy
811 ·· 2B ocx H l)ccran1:nt H I.. n:gistcr pair
811 6 OID OCR C IJlccrantnt R£gisoorC
811 C2, OD, 81 JNZ I..OOP lfcontcnt ofC i.soot 71:!ro, Jwn,p to l..OO P
811 A 76 Hl.T Halt

Ir---------T---------------------------------------------------------------------------,
& Bit DATA I Binary 111111tlur in Me1t1ory LoalllOII I
r---------1 ,01,n _r_ , 011n r , 011n -r s o54n-T , 011n T , 016H-r 805 H-r 8058H --------1
!End ~---------f-------+---------~--------~--------+-------+-------~-------f---------------~
12 10 I o 1 1 10 10 1 1 1 1 1 1 :
1 1l t O i ________
•---------~-------~---------J
9F O tl i l il t l i l 1
L _______ ..J... ______ ..J... _______ L _______ ~---------------~

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 37

'Transfer a Bl oclk of Data frnm o ii'le•Section of Memory to the Otlhe r
Sectiiorn1of .Mem,ory

Initialize 1lhe address o f 1lhe

n umber o f dala in Hl-l ~ ister pair

lloao number of data in R~ister 1B

lnitliaftze 1lhe sla g add ass o f

destina1ion in DE r~ister pair

lnitliaftze 1lhe slalliing add ass o f

SO\JIDB in HI. register·pair

load d ata into acownulab- from

SOIJKll rnemo,y

store dala from aooumulalor - o

des1irlation memory

lna ement H L by 1
Increment DE 1

Doorement 1B r~ister·by

No

Em

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 38

 Memory J\ladline
ilifiJN!!I.~ ,Co.le. Libel. i'dnema11Jc-.~ ,O pera~ ,Cammenl.
8000 21,50,00 I.XI H,005n Storct!hc _d dra;:s ofmnnbcr of data, 9050H
in Ht n:g iSl!!r pair
8003 4li MOV B,M load oomba- of d in Rcgista- B from memory
8004 21, 00, 9 1 I.XI D,9 100 St~t!hcdc instion ddre in DE rc:g ister .ir
800 INX H locmnmt HL r~stu pair
800& E toOP MOV A,M Mow data.from sourec to aunu'lator
8009 EB XCHG Exchang,c the contmt of Ht aoo DE
SOOA MOV M,A ore 1lhE content of .c cwnulamr, data in
destinat ion addn:ss
SOOB EB XCHG Exchange the contmt ofH l 8lld DE
800C 2J INX H locremmt soura: address
SOOD lJ INX D locremmt dc instion address
SOOE 115 DCR B l)ca-an£nt R£gista- B .
800!1 C-2, 0&,80 JNZ UlOP lfB . oot 211:ro, Jump to LOOP
8012 76 HlT

............. ...........................
[ ________________ lnplll ________________ [ ______________ Re!mll ________________________ ___ ]
I
j_ _______ 115 H _______ [ ______ 9 100 ____ __1______ 115 H __________________ J
I ADDRE•.._.. ' DATA ADDRESS ' DATA I
[_ ______ 005n _____
1 90 I : 48 H i 9LO I ' 4g H
•-----------------,-------------------~----------------....1...-----------------------------~
I
1 90"2
1----------,
1 IA H ' 9llt2 I LAH
------~-------------------~-----------------,...-----------------------------~
1

1 9053 i F2 H 1 9103 , F2H 1

1-----------------,-------------------~----------------.. . . -----------------------------i
1 9054 1 116 H 1 9 104 1 OOH 1

I~-----------------~-------------------~----------------+-----------------------------~
90 - 1 33H , 9LO 1 33H I
L-----------------~-------------------L-----------------'------------------------------J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 39

TME DELAY
Th proc dur u ·e<l lo d sign a specifi delay is similar lo that u d t et up a cou 1t r.
A r ·ster i loaded with a number dep ndin on the time d lay required, and th 1 th
regi ter i dee ·etn nted until it reach s zero by s t ing up a loop with a condi ional Jutnp
in tructio1 . Th loop caus th d lay dep nding upon th cloc period of the syst 111 a
illustrated · n th next secti ns.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

Time Delay Using One 'egister

h fl w hart in Fi ure 8.2 how a tim -de]" y loop. A count is loaded in a register, and
th lo p i xecuted until the ount r ach zero. The s t of in tructions n c ssary to set
u the loop is also shown in i ur 8. 2.

Load
Delay
Register Label Opcode Operand Comments T•states
MV C,FFH ;Load register C 7

Decrement
Register
LOOP: DCR C ;Decrement C 4

No JNZ LOOP ;Jump back to 10/7

I decrement C

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

 l ck freq 1en y o th ystem f = 2 MHz
l c p riod =
l/f = 1/2 x 10- 6 0.5 =
ime toe e ute MVl = 7 T- tat x 0.5
= .5 µ

In Figur 8.2 register C is loaded with the count FFH (255 10) by the ins ·uct' on
MVI, which is executed once and takes seven T-states. The next two instructions. DCR
and JNZ, fonn a loop w Hh a total of 14 (4 + 10) T-states . The loop is repeated 255 tirnes
mtH register C = 0.
The Lime delay in the loop TL with 2 MHz clock frequency is calcufated as

TL = (T x - oop T-states x N 10)

where L = Thne delay in the loop

T = System clock period
N 10 = E . uiva ent decimal nmnber of the hexadecimal count loaded in the delay
register
TL= (0.5 X 10- 6 X lli4 X 255)
= 1785 µs
~ 1.8 ms
1

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

Time Delay Using a Register Pair
he tin1e delay can be consid rab]y increased by setting a loop and usin a re ister pair
with a 16-bit number (maximum H). he 16-bit number is deer ment d by using the
instruction D X. However th in ·lrucli n D X does not et th Zero flag and without
th test flags, Ju1np in tructions cannot chec desired data conditions. Additional tech-
niques therefore must b us d to s t the Zero fla_g.

Label Opcode Operand Comments T-states

LXI B,2384H ·Load B with 16-bit count 10
LOOP: DCX B ·D cren1ent (B by one 6
ov A,C ·Place contents of in A 4
ORA B ;OR (B) with ( ) to set Zer flag 4
TN OP ;If result -:t:. 0 , jump back to LOOP 10/7

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

TME DELAY
The tim d lay in th lo p i. calculated as · n the previous exampl . The loop includes
four in tructions: DCX, MOV ORA, and Z, and a e 24 cloc period for execution.
The loop is rep at d 2384H times, which is conve ted to decitnal as

2 8 H = 2 X (l 6) 1 + 3 X ( 6 2+8 X (16 I + 4(16

= 9092 10

If he clock p riod o the sy m = 0.5 s h delay in he loop L 1

T = (0.5 X 24 X 9092io
= 109 ms (without adju m for he last cycle)
Tota Delay T 0 = 109 m + T 0
= 109 ms (The instru tion LXI adds only 5 µ s.)

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

Time Delay Using a Loop within a Loop Technique

A time d lay imilar to that of a register pair can al o be achieved by u ing two loops·
one loop in id the oth r loop as shown in igure 8. (a . or exan1ple regi ter i u ed
in th inner loop LOOPI) and r ist r B is us d for the outer l op 00P2). he fo] -
lowin in tructions can b u. d lo implement the flowchart hown in igur 8.3 a).

MVI ,- 8H 7T
L00P2: MVl •➔ H 7
00 1: DR 4
NZ 00 1 10/7T
DR B
JNZ L00P2 10/7T

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 MVJ 'FF

. L,
lay in
OOPl

DR

JNZ OP2

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 LAY CALCULATIONS
The delay in LOOP 1 is T 1 = 1783.5 ~ls. Th se calculat ions are how :i in ecti n 8.1. l.
We can replace OOPl by T 1.. 1, as hown in Fi 0 ure 8.3(b). Now we can al ulal th d -
lay in LOOP2 as if 't i one loop· ti i loop i executed 56 time b cause f th connl
(38f in register :

T L2 = 56( 1 + 2 l -state x 0.5

= 56 1783.5 s + I0.5 µs
= 100.46 ms

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

ADDRESSING MODES

'Ille m•cH{8t ~ U3ol to copy or traDtfer data fa:m a WJl'ec nro a ddmattcn., nc ~ 11118)" be a re,-
ktert •nci~ aa input~ or an. I-bit ■1•1lbcr ~R to W~ In. tile ..-c ftYt die dd:inatiotl nAtY Ibo be
• rea;ili« ~ or aa ourp, port 'Ille ~ Ill(( dd:lnatloal r1 data are lmowa. • ~ Tbcre are
varicNs foarietsto ,pocify o,ci:eads f o r ~ ' I l l e ~ ~oflpcdfyia& dltaare callcd tile
~ modes. ~ die folbrri• lddrculaa moda • U3ol :in die 808.5 ~ :
l Imm.edWe addrc:N,:ia.g
1Rcpter~
l. Directadtklll•
4. lm.4lrcet .......

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

In. th i.',.; · Mn:: ·~m
n, mode 11:b , · rldre. :s ofth ~artd •'Il ., s i.!its ·itbirU:h ·Eni:itrut:rt' n Thi,:, mode can. be
.d l'o r .' d · taJ fr
Ill:!" o utput de ·, _'i art.d ··tore it i.rtth.·. • umu1Latoror . T i re th. . - ·t'eatof 1the · :;umu-
la1tor tu 1th out ut de._,it-.,e,·. 'E.x.aimpl _'i of dil.'eCI: · Mn:: · m "' .are ·Eltusifr· l:ed in.T.· 'b'E

Ir--------------1----------------------------------------------------------------------,
J,rslrMd-. I Tavl I
I INO I lmnl'u- OO H I
f--------------~----------------------------------------------------------------------,1
I UUTO lH I . nli!! 111 Port Ol H
1 11
t--------------,----------------------------------------------------------------------•,
I L D .I! Ii : Lmtl. th! cmlli!!n \ t1f 191<!! ay I( i m .I! H iin 19ie mu bta- I
,--------------;----------------------------------------------------------------------,,
l---~~~-------J------~~-~!~-~~!~~~~~--~i~~~~-~~--~~--------------------------~
In. Ith.· iti"Stroot i:ort 1N O liI Ith.. addr ~·s of .ii.ti. I . port is O Ii ./here tl-ie da1ta is ar ,aillabL F rom 11:hi.,;
-• hen data fr to be read a:nd :stored irt the • - -urru.ill • r. ·. ia:tillarly tlie m nie:nt of the · :umullal'or can. · ·
·eat 1tu the out · ut · rt ·rldre..,;s OlliI u.~iti ·,·O . T OlliI mc,;trU(,-hua .
liI i i; fue memor --· tion. from 'here datii! ·i:s to be oo -- d. Th.e refoie
fu - insrtruc1ti:on it•,d f · - · fteS 1:he :so ure - of da:ta . After r ' din 1 diiitai from SO Ii it . -m'lfll Ile · ;t .oo in 1th
a ,umul<ittu r.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

Retlster Addresstna

Ia Ile reptor addrcMlag ~ oac ti lie rea1-.A. ~ ~ D1 ~ D at L can be uad • scurcc of opci:-
...., C081equea.dy1 dara it proride(l duw&h lie ~ la dlJt ~ Ile l!l)(!Wnlllafor it iaq,Hed U a
~ operand, Pot" e'1'8'9\; Ile :laO.lctlca. ADD C a,- diet die conten• ~ lie Creal_. will be added
will. Ile ccatcat, of the eccumqiatOt". Moltofllc ~ - . q_,--addrctq mode haw:: 8-bitdatet
•ou•t 10me ~ deal 'tridl 16--blt reptor P11•1 for exempk; PCIIL ~ Hxampes ofrep-
terl!d.dtclda& are~ ill Tattc 3.2.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

In th · re:r ind' . ' mod rthe rortt t~ of rto l pec.irf · th. · dtlT _ of 1th o .and
Ther in re "°id . indii.. h,t rtrUDt·iJ rt.i; 11:h 1tlcl.r _ 11· n.o't iit i fi, tl For iex.artq, i1'L itruc:f ITT.
MOV •: , M me:..art.'i th , t lJ'l.0/!,/ . th 00t1tent:s of th.. ronrertt of th. . , loc;ah:oa. . m.'i , itw.td 11n.
H and L . · ·.· ir in il:h., , roum . in~i,1ructiior'I. L · i.'i · ·l'fio · .er ltiiimp,·11e.. m .il:hii.,; i:r'l'.Srtruc-
muJ:.at'Or . ci.th 't · &la! il:rat i'i ·spec· 1:hr. ·in. fbe B .and rer · · iT.
Th. ·m~'irtruo ion ADD M i:.'i · l1.,;o .an. · of r - .st'er in.dir · - ' ddre!iS·m "' · . sh. trie et.a.n:i; · l1e.'i of
r 11ii,ier indireot · ddr ~·s · · .

~---------~---------------------------------------------------------------------------,
: ~~ : ~ :
: LDAX B I L<Dli ll1'! ac,rurmd 'rromad.d.n!I:! i,, ~;i,.,,.panr B-C :
~---------~-------------------------------------- ----------------- .------------------lI
I MOV A,M , l,l'ic,....,lh.,a1JJ1m.<1 fll., men:aylocst,m whu,.,ad.m.s,"' gwenm Ii '""'1 L ~""""" ete~UDU btc"
~---------~--------------------- ·-----------------------------------------------------1
~ MOV 1,_11,B -~- l,f,o....,lheaml<!III o f lhe kCUIDUI _ ,111 d>e1D<!IDlt1J)' k..,..,;.m mi _ adili= ,, ~""'1111 Ii "'1d L ~_,...,. ______ )
I A DD M I A ddll11111 oflh.,cvnl_enl <1flhe memmy I, llH1 whu ad.on,.., u !!,'M!ll '11 Ii '""'1 L reg,.i.,,, an d U... aa,lm o l'd><! i
I I ~..... I
L---------~---------------------------------------------------------------------------J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

Imime d1a1te Addiresstng

In. il:h ~. imm.edii · . · dd _. ·in ~-mode. the t:ip,erand or tla: · ll'!i pre:· nt _ri.thit1. the iru·tr --· n . Lo.ad th ~.·imrru:.•d:i.c-
il:h ~'it'in · ti:ott . ·h · ·h ii; , · ' et!. i n. th it1_,;rtrl.Jl."o't ·i:on. E.xamp,'11e..:; of direct · dch- -!i. -il'I "' · ,re ~ -re,d il'I.

---------------r-------------------------------------------------------------------·
lnxlr ,m I Tad,

H 1 li fo ~i:1 D
---------------r-------------------------------------------------------------------·
L X r Ii, 5 L
I
Ii d L regi:oq1:m wiltJI050 Ii
1
---------------~-------------------------------------------------------------------
0[ H El witJi rti
1 ~I cu11U!lll l ! J i e ~ .(•
---------------r-------------------------------------------------------------------·
er r B
I
I C e lie oonlll!!rl f"llni!! rul Willi lie oml!!!!II. ( Reg:,
(I B
---------------~ ~-- ------------ ~-- --------

Th imm.ed·i.ate im lb:w im'S U'ie 'th • -:umullii.tm •sS an ·im: ·]ied operand. The f.M (m.o , ·i.mm.edi.iire ·
it1~'ittwho rt Cii.tl. mm it:s imrri.edii •·re da:tii! to an.· ofrthe ,.1 ,10.mm -,.
re •i'iter~'i. For exampl!e 'th itl'stru - .- n MVI D
Fm I1iM s 1:he h •d -ima] dii.tii! FFH to 1th D re ri:!irer. 0

Th.- LXJ ·in~fb:·uction. Oood re •i'i krr p.ai.r imm.ed.i.iite ll..~ _'i 16-bit imm.edi.iit - dii.tii!. Thi.'i i:rt.,t ru.rti:on. i.s.'i ,,enc-
1

t'rr:" Em ru.'lBd to l'o.ad • ddte,·s - in.to ii! r ri:...-ter -·· ir. T:n. LXJ H 8030H ·n · d H and L re · !.!:er pa.i.r ._ith. I -it
immedi.iit dii.tii! S030H .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

lmpHcit Addrasslnl

'111.e ~ modeof ccrf8ia. i81t1Uctioat can. be -.w

by die ~ ' I tuactioa. Aceuaily. dlae

R,campb of-.li ~-.arc~

~ work Cll tile ecd~ of die aoeua,uWor aad dlere is a.o aced r1 tile ~ of di(. opct8tlii
bcbr:

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

Simplified Memory Model

WR
RD
cs
cs ms WR

11 R3

A1 10 R2
Address
Lines
Ao 01 R1

00 Ro

It in lud nl four r gist ·., and ach r ister can t re 8 bil . This hip can b r f rr d to
as a 4-b l r 32 (4 X 8 bit m 111ory chip. Tt ha tw ad Ir s lines, 0 an I 1, t identi fy
f ur r gi t r ·, 8 data lin . t . t r 8 bits, and thr timing or control signal.: R ad (RD).
Writ W , n I hiJ S lect - . )· all conlr 1 i(Tnals ,u- design d to b acti lo , indi at d
by bars over th mb I . Th· proc . . r an · l t this ch ip and identif it ~register, and st r
(Writ ) r ac . (R a I 8 bits at a time. Figur 2.2 ~ho\ sonly f ur r i l r~ lo simplify th

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

R/VV Memory Model

------A,,

Address
R/WM
Line

------tAo

Data
(a) Lines

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

ROM Model

----,A,,

Addre
Lines ROM

- - - - , Ao

Data
( ) in s

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

S ste , Memory M p

0000

ROM

Of ~
1000
Re rv d
F r
Expansi'->11
1 ~rr
2000 R/W

27 F
800
Jdtack
21- i: M roory
JOOO

FF

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 d ess ecod'ng

Ad ess Decoding Using NAND

A1:'i - - - - - t
A1~ _ __.---...
D---
A1~--L-- MSB
A,:!:----1

3-to-8
Decoder

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

 A,, ~ --· I

"" ----r--.....,
11,,
A 11 I>--- - -- I
A11
Ar~ -'I>-- , -
",--,.., I
¼~-- I

11,.-----· I

---,J l.16 11 i ,.

A, - - - -- I
1
. - . . - - - -- - - I

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 "•
5 iiiEiiw
J iimwl

... ,
....
"·
.... I ,_,~ paid.A

"' 1
.
... ,
...,
....

A1~ A,~ A13 A,i A11 A,ti A~ As

l O O O U O O O - SOH

The m1mmry adllr~s 1,rnge in R'gurc 3- IOt.h) will be 800CIH Lo 80fFH.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 A,,
A,.
Au
A,,
A11 __,......._ . - - -

1\ 1•• -et>-

A a - - -- - - cs RD WR
A, - - - - ----1
A r - - - -- -1
A•
A,
1
~
C
1 \ , - - --
A, - - - - -_J
A, _ _ _ ___ 1
A
A,,-- - - - - l -...J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

3-to-8 Decod er (

5V
10/M
A,
RD

MSB A 11
A 14 3-to-8
Decoder 2732
A:J PROM
74LS138
A12 4096 X 8
Oo A1 ~ A1 1 A-i ~ A12 A11 A1t1 A"~ A1 A;, A~ A~ A~Ai A, A,1
I.I O l 0 0 0 0 0 0 0 0 0 0 0 0 0 = OOOOH
.J, !
Ao 0 I I I I I I I I I I I
0 0 0 I - 0 , -l-I
Oo I
.J..

7
Output
Lines
Doata___
Bus ___ ____,

𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

 A14 Ai,
RD
IOJM WR

I\ f;~ 'E1 •'1~

CTof.w•
An 3-40-8
o,
1\4~ 6 116
Ot!rncfer
A,1 RI\V M~lllOf)'
74tSI 18 MSEL1
o, 1\11 2048 >< I!
0,,

°"'"
Lhc,
l} u,.

𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0

1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 10

The process of addres decoding should r sult in identifyin a regi t r for a giv n add ·ess.
We should be able to general a unique pulse for a given addr ss. For exa1npl in · igure
4. 1 l(b), 12 address lines A 11 - 0) re onnec ed to tie me1nory hip and the · 1naining
four addr Lines (A 15- A, 2 of the 8085 microprocessor 1nust b oded. Figure 4.14
shows two methods of d coding these lines: one by using a NAND gate and the other by
using a 3-to-8 decoder. I e output of the NAND goes active and selects the chip only
when all addres. lines A 15 -A 12 are at logic I. We can ob tain the sam r sull by usin 0 7
of the -to-8 d cod r, which i. capable of d oding eigh difi r nt input ac..klr sscs. In th
decoder circuit, thr e input lines can hav ight different logic combinations fron1 000 to
l 11; each input combination can be identi fie<l by the corrc. ponding output line if Enable

line are active. In thi circuit the Enable lines E I and E2 ar enabled by grounding, and
A 15 must be at lo ic l to enabl _. Wi will use this address decoding scheme to inter-
face a K EPROM and a 2K R/W 1ne1nory as illustrat d in th next two examples.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 11

 0
- + V

Au

() MSB
A14O 3-10-8
Au O Decoder
A11
On
Memory
Address

I · oFF H
A11
I
Au1 ~
I
~
As
1 It'
Cl./
A, I I 4096
I
I I 8-Bit
A6
A~
I ...u Memo y
I -,::,
Registers
A4 0
V
J
Ai
I Q
----r- 2732
Az
A1
Ao
I
caC:
...
4)

.§
EPROM
j
O(KK11-1
10/M
output Buffer
RD
Oulput
AD1 Lines
01
t Data Bus Oo
ADu

𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 12

 A1-t A15
RD
10/M
l lj
E, E1 E1 Aio
!
CE OF. WE
l
WR

MSB
J-Lo•8
Decoder 6116
R/W Memory
74J.Sl38 MSEl.1
o, Ao 2048 X S

I Data
I .i11es

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 13

INPUT AND OU -pur (1/0) DEVICES

input/ utput d i ar th mean througl which the MP communicate with 'th out-
.de world.' Th MP ace pts bi nary data a input from d vices ucl a 1eyb t rd and
AID conv rt r and n<l: data to 1tp 1t devi u h as L D. or printer . Th r ar Lwo
differ nt m th d b hich I/0 d j e. can b id ntifi d: on uses an 8-bit addre and th
other us s a l 6-bit addr ·. hes m lhods ar des ribed bri fly in th followin ection .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

I/Os with 8- it Addresses ( eripheral-Mapp ed 1/0)

In thi. Lype f 1/0 tl MPU uses i ht addre lines t id ntify an inr 1t or an output de-
ic · thi. i kn n p riph ral-mapped J/O ( ls lmo, n as I/0-1napped 1/0). Thi is an
8-bit nun1bering y t m for I/Os used in c nj rnction \J ith Input and Ou put in ru ti n .
hi. is al o kn wn a I/O spac . s parate fr n mem ry space which j a 16-bil nu,nb r-
ing sy t 111. The i ht address lin can have 256 (2 8 ombination addresses; thu the
P can i l ntify 256 i1 put devices and 256 output d vie s with addre e ranging fro1n
OOH t FFH. The input and output d i · s are differentiated by the ·ontrol si nal · he
MP u es th /0 Rea I onlr 1 ignal for input device nd tl I/O Writ control ign 1
f r output d vi s. h ntir ran f I/O addre es from 00 l FF is nown as an 1/0
n ap and inc.Ji i<lual addr . ·e are r f rr 'd to as /0 d vie addr s es or I/O port num er .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

]/Os with 16-Bit Addre,s ses (Memory-Mapped I/0)

In this typ of 1/0. he MP use 6 add· lines to identify an T/O d vi ; an I/O i on-
n ct d a if it is a me1n ry regi ter. " hi i known as m mory-mapp d 1/0. The MP
th am control i nal (Metnory Read or Memory Writ and instruction c lho
m m ry. In me m1croproce or uch a the Motorola 6800, all 1/0 hav 16-bit ad-

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

-rl--t--i-+-+--1--Wl-

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 1

t
o.
Bu
ta I ~l ·h
to .•

tc:h E11 ab l
0

L
1 1M iow
nal lJ e ·ic S le l uJs

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

Absolute vs. Partial Decoding

In Figure 5.4, all eight address line,; are decoded to ~n'rnt · >11 • uniqu out ul pu lse ; th
device will be se le ted only wi1h ch• addr's ·. 0 I H. hi is t:alled absolute decoding and
j:,, ,1 oml d ·sign p1m.: tic •. Hm ·rr. to minimize Lhe co. t. 1he output I II c.1 11 b sclcl'l ·d
by <l • · ding some uJ the a<ldtess ti n s. as shown in ri )u ,c 1.5: tlii . 1s ulllc<l partial de-
coding. A. a re!iult, the de i1.:e IHI'. 111ulli t I· address ·s ( ·imtlar to fo ldba1.:k memory ml-
d11.!s:,,cs).

//
Q7 1<1.../\/v\r
--
IJ7 lJ7

Data Lmch t-5 \I

Bm
/J'
0 Do On

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 Fi •ure .5 is similal' lo rig ur · 5.~x.ccpl Ll wt 1c atldres · lines AI and O are nol
connected, and lh y are replaced by 10/M and WR. signa ls. Because the address lines A 1
and ~ are al <lon't care I gic level they can he a. sumed lo be O or I. Tli s lhi out-
put p or·L ( latch) can ht: ac ·-cssec.J by I l1e He .iddrcs ·c · 00. 01. 02, an<l 03. 'l'he partial
d ·coding is a commonly used technique in small systems. Such mul tiple addresse. will
not cause any problem . provided Lhe. e addresses al'e not as. i~11ed to .111y ot her out -
put ports.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

I put Interfacing

D1

DIP Tri-St I D I Bu~

A1 Buffer
Swi lche!>
A,,
A
A~
A, En ble

A2
I
A11
lJ IOSEL
Devi e Selecl rul~e
IOR

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

lnterfaci ,g I/Os Using Dec,oders

sv

~
A1
Dali.I T ._ tote
Bu~ Bulfc1
IOR
E1 E2 E,
EN
B J-10-8
A, - -
-=-
A; FJ\11

Ao F8H
//
l<l-¥1\r
D111n L:uch I.ED~
Bus + V
//

IOSEL
10\

A-, A" As A.:1 A3 A2 A1 Au

I 1 l 1 1 0 0 0 = F8H
I I
l
Decoder Enable Input

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

Mulf ple Port Addresses

15 V

s,
A1 D7 7-4LS244
A6
Oclal s6
As Bulfi:r Ss

°E 1 li2
s..
Data
MSB I S1
A2 A2 Bu.s
IOADR 0 S2
A,

Ao
A,
Ao
-10--8
oder
o,.
u Do
OE
0
0
s,
s

74LSI B

10/M
RD--Q._____J !OR

In Figure 5. 11 . t l1 l! ad<lrcss lin~s A~ anti A are 1101 us ·<l by lhe <lec.;ouing circuit: th lugk
levels on the e lin scan be O or I. Therefor . Lhi,; input port an a ce. sed by four dif-
ferent addresses, as shown he lm: .

A1 A6 5 A-1 A- A2 A, Ao
I 0 0 0 0 0 0 = 8411
l 8 H
0 =94H
= 9 II

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 10

 THE 8255A PROGRAMMABLE PERIPHERAL
INTERFACE

ontr I Word

Po11 A
BSR Mode l/O Mode
( Bil SeUR sci)
!1255A
Cu
CL
Por1
For Pon +
Mode 0
i
Model
l
Mod 2

No ·ffcc:1 on Simple 110 Hrnhhake 110 Bidircd1onal

I/ M ~ r port ~ for rt A at bu~ for
Port B
A, 13, nd an or B port A

Port C bt1s Pon B: ither

are u~ed for in Mooe o or I
h;u11hh11l.e
Port bi t are
u.!>ed for
(b) himd~hakc

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

 THE 8256A PROGRAMIVIABLE PERIPHERAL
INTERFACE

111 8 55A is a wide ly u · ·d. programmabl •. parallel 1/0 devi "'. 1L can be pr ,·, mm d to
tn. nsrer data und r va riou-. condi rions, from sim ple 1/0 to interrupt 1/0. It ic: n xi bl , ver-
sat ile. and ·onomical (v hen mll ltiple 1/0 ports m • ·4uired), hut . om what complex. Tt i,
an imponanl ge neral-rmrp sc l/ d vi chat an b used with almost any mi r pro· ·ssor.
The 8255A has 4 l/O pi n. that an be grouped primari ly in two 8-bit pm11U J po11 :
A a nd R, wi 1h th r mainin ·i ht bits as port . h e1gbt bi ts of p rt ·an u. eel as
individua l bit or t re 11 p <l in two ~-bit ports: C, IPPER u and CLOWER ( 1_), a · in
·igure 15.1 a . Th fu nction. ol the. r rl ar de fin ed by wri ting a control wo rd in th
conLrol n:gi$l •r,
· igur 15. 1(h) sh0\:.., a ll the funct io n:,; of lh 8255A, l, - ified a 01d ing tu two
mod s: the Bi t S •t/R 'set BSR m d rm I th 1/0 111 c. h • BSR m de is u ·d t ·et r
reset the bi ts ill purl . Th 1/0 mo e is fo rt h r divid d into three m d • ' : Mod 0, I
I anti .t,. ode ... In Mod 0. all ports functio,, as simple 1/0 p rt . Mode I i. a ha ud hak
mode hereby put ls A un<l/or B us bit from port C a ha nd ·hake sign I. . In the ha nd-
hake m tk, lwo types f 1/ data tra nsfer con I i1upl 'm nt d: statu heck and in ter-
rnp l. l1 Mode 2, 011 A can be sel up r I hiclil" ·1ional data tran . f r u-.ing hand. hake 1g-
11al-. from p It C a11d port B can I ' ~ct up eit her in orl 0 r d I.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

Pin Cor.fiiura:10n

PA.. l'o.,er { - .. sv
1,0
PA, s~ppltts - GND PA,-J>
PA. 1w
PA1 Wi!
Wft
RESET
Pon
Du A
D, 1,0
OJ E1'
D PC PC.
D,
o. >.,..Do
o,
o.
D, Bas
LO
1~
~
u~
. Purt
-c
.PC,-PCo
Vee Ill E1'
pa.,
PB 1m
iro
P81 WR-
WR
P8 4
A, A
PB l•'O A, C
An PBrPB 0
~a A., 8

Pi11N~
... 00
A 01

V,-0,, o~~ &s (Bidi=~l

RESET Rts.et lnpgt
cs Cti,p_~l,~1
I RD Rt:sd lnpu,
WR Wm, lcoat
An, A, Pon Addrel>
PA..-,A,, PM A{Bil)
PB..-PS.. Pon B (Biel
PC.-PC., """1C(Bnl
VCT - j Vol!s
C1'1) 0 V__()lt>

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

 CONTROL 1.0GIC
lltc c llltul ctlion has ~ix ltr1,~,. 111eir l'unctmn~ .in I c nueetil>t arc n~ h>llo\\,

D RD /RcJtri): this ,·011trol signal e11:1hle, l!Je Ri:.it.l uperntmn, When tht:l ~iJ!nitl i~ low,
the_ MP re,1ds <l.it1l fro111 a ,dec1cd 1/0 p1 rt of the 8255A.
□ ,\'R t WrltcJ; 1lus control !'-ignal cm1blc,- the Wri1 0JJ1:fi1Uou. When th· signnl g1~~
lmv, lhc Ml'l r wl'ite~ into u 'iCIC'C'lNI 1/tl pt1r1 or the control , gh,1<-t

RF.SET Reset) : Thi s b un n'liv high si •nal; ii ch::ai-i. tlie cu11L1 o l 1e-gi&1c1 :mcl ,ec~ nll
~1~ i11the inpul mork,
D CS, Ao, and A 1: Thc1,e arc device !.elt!Cl i,ig11a l.s. CS i, cnn m,ic- 1.-1110 n decoded addres-..
and Ao ond A 1 :m: •enerally c~noecied lo Ml>U nddress Imel> A<J aml A,, rt:..,pec1ively

'Tbc CS :.i~1K1l is 1J1e rna:.ter ·11111 S .lccl, 1111d A0 ,rnd A I spi:cify one of th UO pom
or the cm1tml r1:g1ste1 a., g1vrn hclow:

C'S A, Al} Sel c1c<1

0 0 ll l'oi1 A
0 0 Purl D
0 1 P ,tr
0 J Cnn1rol R<--gt)>tcr
X 82S51\ ,~ nul ~lt!cte<l,

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 ti X
A, s:m cs Alldre'ls l'ull
A. rs
A, A7 A. A~ A, A, Ai A 1 A,.
A, I 0 0 0 I) 0 II 0 - lliOIJ I\
•
A, Au Au 0 I • 8 1 1◄ B
A, 1U1f RU I 0 =- R2tt
TOW WR' lleset I I - 1!\ 11 C-oolrol
l(cgh

(<ll (I>)

com 0LWORD
Figu re 15.2(b) llowi.. rrgi .. rrr called the coutml rc1-: ste1~ Tle c nlent;s ol this register,
call d the contn1I word, specify ll11 1/0 fom;1iou fOJ · ch p;xt Thi ~ reg,. lc:r can be m:-
ccs.<.erl lo writ e a cu111rul wo,\J wh II Au ancl A 1 arc 11 logic I, as mcnticmeu pn:viou~Jy.
The regi.-;lcr is 11ol aci.:ci-<.tblc I r il en I opcratmn.
Bit D 1 1 f th · ntrol rcgi .. tcr "pecifics eithe, thc l/0 rmctmn or lhe lllt Set/Rc:-;cl
funclion. :is. l:is.">tfied in Fi pun: 15. 1(bl. [f l>it D,. = I l>it D,,-0 11 cktcrminc 1/0 fll11c1i,J11s
in \'llnOU!i moues. as i.hu11,,u in figu, 15.. rr bi l IJ 7 - . port C opcr.ites in ,he Bil
Sc:1/Rei;et {BSR) utu<le Th BSR con lm l word oe!I. not affc:I lit • fm1c1i ri-. of por1~ A
,,nu B tJ1e BSR mode wi ll be described luter).
·1o com municate w1lh penpherah th1ougJ1 ti ~ S- 55A, 11·1= slc-ps are ncce,;sary:
1. Del ,mine 1hc .iciclrc.~~ of p,>rt" A, B. 1111tl llBU of lh n n1 ml rcg1sIer ncC(lrdm!l, to
the Chip Select lo•ic 1111d oodres:,. line:,. 1\4, and A 1•
2. Wri te a cont,•ol wmd in th cotttrol reg 1<:1cr.
J. W, ite 1/0 inslnt ·tion, o com11111nrc □te with pcriµ ht!rnls 1J11uugll µ , ts A. R. :ind .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

Mode 0: Simple Input or Output

In llJL mode. p<Jrts. A llnd B 1trc used a,; two irnple 1:1 bit 1/0 ports 11nd port f' us lwu 4-
bil [)111"I. . Elllch port (or lta lf-pu11, in C:il:le or ) c:m be programmed lo fu11c tio11 rn, :..imply
an input port or an o ulput po11. The input/output fealure~ 111 Mud!! 0 .J.1'e il~ fo llows:

• 0 1:1 1puls ::iri= lim:h.ei..l.

2. lnpuls ate not lulched.
3. Po1ts do not have h:111<lshnke or interru1>1 1.:.ip~1biliiy.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 anln,I W

[!, I n. n, I D, I Di ] D, I 0 , ! 0o I
'-
/ Gn,,1p til
'\
I l'ort <: (Lot,-.,r

O
t ~ I l
= Outpu,
PC",l'C(>J

PPJ1 13
I - lf1pm
0 - Uui,>llt
Mooe Seleclion
0 - Mu<le 0
I = Modt I

/ Clrour A
\
,~,
l'l'lrt C' Wrp«-f'Cr J'C◄ l
I
D = O\Jtput
rnstA
I - l11pul
Cl - Oldpuc
"1~Seltt1W11
00 • Mod<: 0
01 - Mode I
IX - Mrnle l

I :: IIO ode
0 - SSR Moote

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

BSR (Bit Set/Reset) Mode

The BSR 111odc i:,; c:c,nc:csncd o nly with lhc ei3h1 hi!~ of port C. whid, c.ambe ~cl or re.sel
by writ ing ,m apprnpnale c:rnHm l wot'd in Iht: rnnlml rcgi1>1er. A conL1'0J wurcl with Ml D 7
= 0 is rccog11 izetl as a BSR ct1n11ro l word, and it does .nol altc.- any pr viously i.1•a n~milt~cl
rn11 lrnl word wuh bit D 1 = I; thus 1he J/0 c,pcrnHons o r port~ A :;incl 11 81-C not atl'ectetl l.ty
a BSR l"01LL1\J I wcml. Tn lhe BSR mode. i11di 11idL111l bils ot' po11 C o;; ,111 b~ used fo r ~Pl)lica-
1irn,s :1,1.1.ch as a n unlufl' ~w i1ch.

BSR CONTROL WORID

This. conll'OI wort!, whe n wn1tc11 in die coot!'Ol re·gi~lcr, ~ct.; or re~t~ w1e hit ,11 111 i111c, :\S
s.rec ificcl i11 Figure l5.6.

o, o. [l, o. u, o, o, 0.,
0 .x )i X llit Srlr

llSR Mndc
Nni I l<cd ,
C.cnrmll)' r l = 0

000 - lli1 n
001 - llil I
1110 011 2
llll - !Iii I
100 = Di,
IOI = 811 ~
I 111 !111 6
111 - 11,11

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

Mode 2: Bidiroctiom d Data Transfer

This mod i~ u~rf primari ly iu ap1>lica1ion~ ~uch as data trnn~f'c r hccwcen 1\\10 co111pul 'r.,;
m nOJ)l>Y rli<;k controller inuufacc . In ch,~ mode:, J)Olt A an be conligureu a 1hr. birfircc-
tiorml ()Or1 111i<l p n B eilh r in ode Om Mocf I . Port A U!,CS live ign.11~ from port C
,~ hantbhak~ sign.iii- rQf' dat 1 tram.rei. Th rcmmnmg thrc . ignnl~ from port C con be
w,ed either n,; implc 1/0 0 1 haod~hakc lcr port B FiguJ'c I 'i. 14 shows tw conti g11ro-
lion~ of Morlc 2. Titil> mode is illustrnted III Section I 'i .3

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

 THE 8269iA PROGRAMMABL
INTERRUPT CONTRO-.......

Th 8259 i a pro rammabl interrupt c ntroller de i n d o w rl with Intel micr -

proc or 8085, 8086 and 8088. h 82 9A inlenupt c ntr Iler can

1. nrnnage i l int rrupt rding L the instructions writt n into its con trol re i ter .
hi j equivalent to providin i ht int rrupt pin on the processor in pla of ne
INTR (8085 pin.
2. ve t ran int rrupt reque t anywh r in th mem ry map. IIowev r all eight int rrupt
arc spaced al the int rval of ith r four or ei ht location . t j eliminat ll nrnjor
dr, wbac of th 8085 int rrupt in which all interrupt r v ctored l m 1n ry lo a-
ti ns on pa c OOH.
3. r ol eight I ,Js of int rru t prioriti in a vari ty f n de u h s fully n t d
1 o , aut mati · rotation mod . and pecific rota ion 1110d (to e xpl ir d lat r .
4. 1 a ·k ·ach int rrupt rcqu st individually.
5. r ad th tatu · of pcn<lin interrupts in- en i interrupt an I ma eel int rntpt .
6. b set up t ace pl ith r th I vel- rig re I r th edge-trigg red it t n'ltpl r ue t.
7. b expand <l lo 6 priority levels by ca cadin ad itional 8259A .
8. be et u1 work with either ti 8085 1 icr pr 'cs · r mod or h 8086/8088 micro-
proce ·m d .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

Block Diagram of the 82S9A

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

READ/WRITE LOGIC
T his is a typical Read/WriLe control logic. When the address line A0 is at logic 0. lhe con-
troller i.. elecLed t write a command or read a statu .. The hip Select logic and A0 de-
t rmin th port aullr . s of the contr lier.

CONTROL LOGIC
This bl · has two pins: INT Tnl rrupl) nn outpllt, and TNT A (In t rnipl Acknowlcd :.c
.i:
as an input. The INT is onnected to lhe interru t pin of the MP . Whenever a valid in-
terrupt i. sse,·1ed, this si 11 1 ooes hi h. The 1NT A is the Tnte1n1pt Acknowledge signal
fr )111 th MPU.

INTERRUPT REGISTERS AND PRIORITY RFSOLVER

' I he interrupt Reques t Register JRR) has eight input line · ( R 0- 1R7 ) fur int rrupls.
When these lines o high, the re u sts ar .<;tored in the re isr r. The in-Service
Rl!gittler I R) stor · all lh I v I~ thal an: currc1Hly bcin serviced. a1 d the Interrupt
ask R ·gi l r (IM R) stores l he musk ing bits of th in l •1-rupt l in ·s lo be maskctl. The
PrioriLy Reso l\'er (PR) exnmines th se three registers and determines whether lNT
should be:,; nl 10 ch ~ P .

CASCADE BUFFER/COMPARATOR
·1his blo ·k is used Lo expand the m11n r uf interrupt level · by t;a~ ·ading l w or m01
8_59A1,. To .simp lify the discuss ion, thi s block will not be me ntioned again.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

Interrupt Opera ion
o implement inlerrnpts, the Interrupt Enable nip-flop in the microprocessor should be
e11~1bkd by w1 it111g 1111: ·l in'itruetion, ,ind th, 8259A shoul I ht! initi.dilecl hy writin con-
lrol word · in th, control regi ter. 'l be 8 59/\ r quir !) two l p of control word ·:
Initialization ' mmand Word. ( I W. ) and Operalional mmand Words (OCWs). The
1 s a.-c u ed to . et up the pn per condi ti ons and specify RST vector addresses. T he
OC. W · ar • u · ·c..l lo pcrr rm lunclion · su ·h a ma king inlcrrupl ·• sctlrn up ·r, ht read
operati n,, etc. After the 8259A ts initinlized , Lh following sequ nee of events occurs
when one 0 1 m 1 rnte , rnpt request lines go hi h:

1. T he lRR store · Lh requests .

2. T he priority r s Iver ch ks thr " 1 ist rs: th I R for inlerrupt r qu st~ . th IMR for
maski11 bits, and th, ISR ~ r th • in ttmupt req u ·t being served. It r solv~ the prior-
jty anc..l ~e ls lhe lN ' high when appropriate.
3. The MPU acknm: ledges the interrupt hy . end in r TA.
4. After the INTA i recci ed, lh appropriate priority biL in the lSR i · sel to indicate
which interrupt le cl is being ·ervecJ, and the corre. ponding bit in lh IRR i. re. et to
indicat thal the request is acceple<l. Then the 01 code for th LL in tru tio11 i
placed on lhe data bus.
5. When the MP d od th CAL instruc tion, it places two more lNTA signals on
lh data bus.
6. When th 8259A receives the second I TA. it places rhe I w-ord r byt f th CALL
addres. on the data btK Al the third !NIA. il places the high-order byle on th data
hu . . T he AL aci Ir . i<; th v c l r mern ry location for the interrupt; this address is
placed in the contro l reg i ter during the initialization.
7. During the third INTA pulse, the JSR bit is re I ither aut matically (Automatic-End-
of-lnt rrupt AEOT or by a om mand word that must be issu d at the end of the ser-
vic.: rouline ( nd -of-lnt rrnpt-E l). 1 his opticn is determined hy the initiali7aLion
command word ()CW).
M. T h pro _n1m :-etiueni.: b trans[ ·nt·d to 1h memor locati n speciHetl by th CA
instn,cti 11.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 Priority Modes and Other Features

Ma11 1 lYJ s of pri rily mod s a1• a 1aila le uncJ r so ftwtu- control in the 8259A. and 1hey
can ·hang ti tlynamically during the progra 1 hy writin appmprial c mmnnd word ..
Commonly used priority mode ore dis u., cd bel w.

1. FuJJ. Nested Mod 1l1is i. a general-purpos · morJ · in which all lRs lnl rrupl Re-
ue. I a, a1 n°ed fr m hi 0 h · ·L to lowest, with ll~ as the highest and 1R 7 as lhe low-
t.
In addition. any JR an be as. i nec:1 1he hi ,..h t priorit in Lhi mod ; th priorily
<;equence ill the, h ,in al that TR Ju th · c-xampl hel w, IR 4 ha 1he hi h . ·t priority, and
TR I ha · th low 'SI prio1i Ly:

TRo TR, TR!. IR, -I 1R5 l IR7

4 5 7 0 l 2 3

+
Low •sL Jigh st
pnorily priori Ly

2. uto1 at'c Rot:ltio l Mo e ln thi s mode. a devi e, al ter bei ng servi ed, receives lh
lm: e Lprioril ,. suming that the IR::i has just hee11 scr ic.:ed, it wil l r ·cciv1,; th
pn rit '. as shown low:

IRu IR 1 I lR lR,, 1
I 6 0 I 1 4

3. Spedfic Rotation Mode Thi 11ode · imilar to the autornahc rotation mode, except
that the ruser can seJect any IR for lhc [ west priority, thu xi 1g aU othe r p1fo1·ities.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

 P ogramming the 8269A

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 Schematic of an Interrupt System Using tbe 8359A

Ay.--------
A.-----
At-----
B, lia B,
A, MIB !-to-I
A.1 - - Dlaader
A, ·o.-------.....el.
74LSIJI ---At

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 OG

The 8254 progra1n1nable jnt rval timer/counter is functionally similar to the software-
design d counters and tim rs described in Chapt 8. It generates accurate time delays
and can be used for applications u h as a ·eal-time clock ar even coun er a digital ne-
shot a squa · -wave generator, and a complex waveform enerator.
Th 8254 in ludes tlu- id ntical 16-bit counte ·s that can ope ·ate independently in
any one of the ix 111odes to be described later). It is packaged in a 24-pin DIP and re-
quires a single +5 V power supply. To operate a counter, a 16-bit count is loaded in its
regi t r and, on o n and, begin to de rement the count until it reaches 0. At the end of
the count it generates a puls that can b used to intenupt th MPU. The counter can
cou1 t eitl r in binary o · BCD. In addition, a count can be read by the MPU while the
ounl r i. · d crementing.
Th 8 54 is an up raded version of the 8253 , and they are pin-compatib e. The fea-
tures of thes two d vi are aln1osl identical excep ha

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

62 54 Block Dia.gram

Pin Configuration Block D1 gram

D1
Oa111 -----CLK 0
Dt1 oun1er ____ GATE 0
Ds Bus
Buffer
=O
04 --► OUT 0
D,
D2
D,
Do iffi
CLK 0 Readf
LK I
OUT0
WR Counter
Writ GATE I
GATE0 = I
~ Logic
GND OUT I
A,
Pin Names

D,Dn Dala Bus (8 Bit)

s
CLK N Counter Clock Inputs
Control CLK 2
GATEN Counter Gate Inputs Counter
Word GATP. 2
OUTN Counter Outputs =2
Regisier
RO Read Counltr 0 T2
WR Write Command or Data
cs Chip Selec1
~, A, Counter Select
Vee +5 Volts
GND Ground Int mat Bus/

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

Fi tu l 5. 3 is the block di agram or the 8254; it includes three co unt er ' (0, 1, an 2), a
data bus buffer. Read/Wri 1c contrnl logic, a nd a co ntro l register. Eac h counter has two in-
pu t signals-Clock (CLK an<l GATE-and one output signal-OUT.

DATA BUS BUFFER

This lri-state 8-bil, bidirectlonal buffor 1s connected to the data bu of th MPU.

CONTROL LOG C
The control. ect1011 hn. fiv signals: till (Read), WR (Write) CS (Chip Select), and the acl-
d re s li n ·s Ao, ud A 1• In th periphel'al TIO mod , the RD and WR signa ls are conn ctcd
to IOR and 10 . re. pectively. rn m moiy-mapped 1/0, these ar connecl cl to ME R
(Me mory Read and M MW Memory Write). Address lin 'S A11 and A 1 of the MPV are
usually co,mected lo lines A0 and A 1 of the 8254, and S is Lied to a decoded addre .
he c;ontrol word registe, a,1d counters are selected according to lh ,.. signal on lines
A 11 and A 1, as sho\ 11 be l w:

A1 ~I Selection
0 0 Cou 11 tcr 0
0 l ountcr 1
I 0 Co unter 2
I Control Re isle

CONTROL WORD REG STER

T his reg ister is acce s d when li nes A and A 1 ar al logic I. Il is us ·d t write a com-
mand word which specifics th counte r to be used, its mode, and either a Re<1u or f\ Wri lc
op 'ration. The co ntrol word forn1al i. shown in Fig11rc 15.24.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

MOD
T he 8254 can op rnl' in si different modes. and the gate of a collnl -r i used eithe1 Lo
tlisal le or e n ble counting, as shown in igurc 15.25. llowever, to maintain clarit y, only
one mode (Mode 0) i.s illustrated first, and de tail of th rcmai ,,in mode. are di cus d
in Section 15.4.4.
In Mode 0, after the counl is written and if the gale i high, lh ·ount is le rc-
mented v ry clock cycle. When the count re;;1ches L.Cro, the output goes high and remains
blgh until a new count or n )<le word i loatle .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 D,
SC I SCO RW l RWO M2 Ml MO BCD

SC-Select ounter: M-MOD

SCI SO) Ml Ml MO
0 0 Select Counter 0 0 0 0 Mode 0
() I Sele ·t Count r I 0 0 I Mode 1
I 0 Select Counter 2 X 1 0 Mode 2
Read-Back ommand X I I Mod 3
I I
(Se Read Opera.ti ns)
I 0 0 Mod 4
I 0 I Mode 5
RW-Read/Writc:
RWI RWO
unler Latch Command (see Read B D:
0 (}
Operations)
0 R ad/Wril lea. t significant byte only. 0 Bina y Counter 16-bits
0 Read/Write most significant hyte only. Binary Coded ecimal (BCD) Counter
(4 ecade)
Read/Write leasl significant byte first,
then most ignifi an l byte .

Note: Don'1 re Bia (X) Shou ld I3e Oto Ensu Compatability with uture Intel Products.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

Modes
As men 1io.11e{l ,·arli r, the 8254 can opernre in six differe nt modes; we al1Feady illustrated
Mode O in Sec lion J 5.2.3. ow we will clcscrio briefly various mode of d e 8254 in-
cl uding Mode 0.

MODE 0: INTERRUPT O TERMINAL COUNT

ln his mode, ini liaUy the OUT is low. Om:·· · count i · rn•d ·d i11 lh re. iste , Lhe counter
is decren ented every cycle, and when Lhe cour.t reaches zero, tl e OUT go s high. his

ca n be u. ed as ar1 int n 1pt. h O U f remains hi h until a new coun1 0 1 a com mand, 'Ord
i · load d. igur 15.27 al h ws thaLthe c un li1 (1 1 =. ) is temporarily stoppe when
Lh a te is disa I d (G = 0 , and con tnnt d • fiai when the Oat is at logic I.

MODE 1: HARDWARE-RETRlG
In Lhi. mode. th • OUT is in itially hi 1:ll i tri g r , th goe · low,
and at the e nd of the count, the OU , · high a •ain, th us •enerating a on -shot pul.
(Figure I - .27, M cl~ I).

MODE 2: RATE GENERATOR

Thi1- 111ode i u ·eel Lo gen rate a pulse equal 10 th cl l p rio I flt n giv n int rval. Wh n
a count i · loaded, the OUT stay. hi h unti l th c unt r ach •~ I , an then th OUT goe.

[ow fol' one clock period. The count is r ]oadcd au tom lica]Jy. aind the lu l~e .is genernted
,co t.ir1u ously. Tihe cou nt = I. is i!. legal in this mode.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 Mode 0: lnterupt on Termina l Count Mode I: Programm11bJ One-Shoe

C luckI !
WR n ~ WltJl-i___.r-

OuIpu1 Clnterrupc) L.._L__ frigger

(n = 4) ,.....---.- n--+-t ~1 0
~~ Outpuc (n~ ~---
WR m
ate~
T n g g e r ~10
Output Clntcrrupt) ~ 011 tput --, ...
, ---
(m = 5) - ~
A 8
A t B m

Mode 2: R tc Gcncnttor lock ode 3 S4u,1.1e Wave Generator

lock Clock
Wttn Output n - 4}
Output
Output 11 = 5) --
Ou1p11t (n 3)
RESET - i..._ __,

Mode 4: Sortware iggc:red Strobe Mode 5: H1udwF1re Trigg red Strobe

Clock
n =4
WR:~ ate
Out1ut~ 0\llput (n 4)

Load 11 n = 4 _r-u
~ Gate:
G,11e Output (11 = 4) 4 3 4 3 2
Output 2 I 0

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 MODE 3: SQUARE-WAVE GENERATOR
In this mode, when a c unt · · load d, th OUT is hi h. The coun t is decremented by
two at every clock cycle, and when it reache zero, th O T g es low, and the ount is
reloaded again. his is t pc ti.;d ·ominuously; 1hu a continu us qua.re wave witb pe-
riod equal to the period of th count i g ·n rat d. In rher words, the frequency of Lhe
quat wa is equal Lo the frequency of the ·loc <livided by th ·ount. I th count N)
is odd, lhe pulse stays I i h fOI' -1 I )/2 clo k ycles and stays low for (N - 1)/2 d c
cycles.

MO E 4: SOITWARE-TRIGGERED STROB
In lhis mode. the OUT is initially high· it lo\! for ne c.:Jock period at the end of the
unl. The count musl e rel adc<l for sub~ quent out:>uts.

MODE 6: HARDWARE-TRIGGERED STROBE

This m de is similar to Mod 4, cxc pt that it is lJ·igger d by the risi ng pulse at the gate.
Tnj1 ially, the OUT is low, an<l when the Gate pulse is triggered from low to hi h, the coun t
b gi11s. I Lhe end o the count, th OUT s low for one cloc p riod.

READ-BACK COMMAND
The Read-Back Command in rhe 8 4 llow · th user tor ad the count and the status of
the cou nt ; thi corrunand is not available in the 8253. he fol'mat f the corn, 1 nd i,
shown in igure 15.28(a).
The comm and is wrinen in th control I' gist r, and th count of the specifi d
ounter s) an h latched if COUNT (bit D5) is 0. A counter or a combination of ounters
i p cified by k eping the respective CNT bit'> (0 1 D 2 , and D3) I i b. or amp! , lhc
control word 1 l O I 0 1 I O D6H wdtten in the c ntrol r ·gist r will latch the cou nts of
Coun tel' 0 and Count r l, and th · counts ·an be obtained by reading respective counter

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

Simplified Memory Model

WR
RD
cs
cs ms WR

11 R3

A1 10 R2
Address
Lines
Ao 01 R1

00 Ro

It in lud nl four r gist ·., and ach r ister can t re 8 bil . This hip can b r f rr d to
as a 4-b l r 32 (4 X 8 bit m 111ory chip. Tt ha tw ad Ir s lines, 0 an I 1, t identi fy
f ur r gi t r ·, 8 data lin . t . t r 8 bits, and thr timing or control signal.: R ad (RD).
Writ W , n I hiJ S lect - . )· all conlr 1 i(Tnals ,u- design d to b acti lo , indi at d
by bars over th mb I . Th· proc . . r an · l t this ch ip and identif it ~register, and st r
(Writ ) r ac . (R a I 8 bits at a time. Figur 2.2 ~ho\ sonly f ur r i l r~ lo simplify th

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

R/VV Memory Model

------A,,

Address
R/WM
Line

------tAo

Data
(a) Lines

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

ROM Model

----,A,,

Addre
Lines ROM

- - - - , Ao

Data
( ) in s

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

S ste , Memory M p

0000

ROM

Of ~
1000
Re rv d
F r
Expansi'->11
1 ~rr
2000 R/W

27 F
800
Jdtack
21- i: M roory
JOOO

FF

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 d ess ecod'ng

Ad ess Decoding Using NAND

A1:'i - - - - - t
A1~ _ __.---...
D---
A1~--L-- MSB
A,:!:----1

3-to-8
Decoder

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

 A,, ~ --· I

"" ----r--.....,
11,,
A 11 I>--- - -- I
A11
Ar~ -'I>-- , -
",--,.., I
¼~-- I

11,.-----· I

---,J l.16 11 i ,.

A, - - - -- I
1
. - . . - - - -- - - I

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 "•
5 iiiEiiw
J iimwl

... ,
....
"·
.... I ,_,~ paid.A

"' 1
.
... ,
...,
....

A1~ A,~ A13 A,i A11 A,ti A~ As

l O O O U O O O - SOH

The m1mmry adllr~s 1,rnge in R'gurc 3- IOt.h) will be 800CIH Lo 80fFH.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 A,,
A,.
Au
A,,
A11 __,......._ . - - -

1\ 1•• -et>-

A a - - -- - - cs RD WR
A, - - - - ----1
A r - - - -- -1
A•
A,
1
~
C
1 \ , - - --
A, - - - - -_J
A, _ _ _ ___ 1
A
A,,-- - - - - l -...J

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

3-to-8 Decod er (

5V
10/M
A,
RD

MSB A 11
A 14 3-to-8
Decoder 2732
A:J PROM
74LS138
A12 4096 X 8
Oo A1 ~ A1 1 A-i ~ A12 A11 A1t1 A"~ A1 A;, A~ A~ A~Ai A, A,1
I.I O l 0 0 0 0 0 0 0 0 0 0 0 0 0 = OOOOH
.J, !
Ao 0 I I I I I I I I I I I
0 0 0 I - 0 , -l-I
Oo I
.J..

7
Output
Lines
Doata___
Bus ___ ____,

𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

 A14 Ai,
RD
IOJM WR

I\ f;~ 'E1 •'1~

CTof.w•
An 3-40-8
o,
1\4~ 6 116
Ot!rncfer
A,1 RI\V M~lllOf)'
74tSI 18 MSEL1
o, 1\11 2048 >< I!
0,,

°"'"
Lhc,
l} u,.

𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0

1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 10

The process of addres decoding should r sult in identifyin a regi t r for a giv n add ·ess.
We should be able to general a unique pulse for a given addr ss. For exa1npl in · igure
4. 1 l(b), 12 address lines A 11 - 0) re onnec ed to tie me1nory hip and the · 1naining
four addr Lines (A 15- A, 2 of the 8085 microprocessor 1nust b oded. Figure 4.14
shows two methods of d coding these lines: one by using a NAND gate and the other by
using a 3-to-8 decoder. I e output of the NAND goes active and selects the chip only
when all addres. lines A 15 -A 12 are at logic I. We can ob tain the sam r sull by usin 0 7
of the -to-8 d cod r, which i. capable of d oding eigh difi r nt input ac..klr sscs. In th
decoder circuit, thr e input lines can hav ight different logic combinations fron1 000 to
l 11; each input combination can be identi fie<l by the corrc. ponding output line if Enable

line are active. In thi circuit the Enable lines E I and E2 ar enabled by grounding, and
A 15 must be at lo ic l to enabl _. Wi will use this address decoding scheme to inter-
face a K EPROM and a 2K R/W 1ne1nory as illustrat d in th next two examples.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 11

 0
- + V

Au

() MSB
A14O 3-10-8
Au O Decoder
A11
On
Memory
Address

I · oFF H
A11
I
Au1 ~
I
~
As
1 It'
Cl./
A, I I 4096
I
I I 8-Bit
A6
A~
I ...u Memo y
I -,::,
Registers
A4 0
V
J
Ai
I Q
----r- 2732
Az
A1
Ao
I
caC:
...
4)

.§
EPROM
j
O(KK11-1
10/M
output Buffer
RD
Oulput
AD1 Lines
01
t Data Bus Oo
ADu

𝐴15 𝐴14 𝐴13 𝐴12 𝐴11 𝐴10 𝐴9 𝐴8 𝐴7 𝐴6 𝐴5 𝐴4 𝐴3 𝐴2 𝐴1 𝐴0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 12

 A1-t A15
RD
10/M
l lj
E, E1 E1 Aio
!
CE OF. WE
l
WR

MSB
J-Lo•8
Decoder 6116
R/W Memory
74J.Sl38 MSEl.1
o, Ao 2048 X S

I Data
I .i11es

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 13

INPUT AND OU -pur (1/0) DEVICES

input/ utput d i ar th mean througl which the MP communicate with 'th out-
.de world.' Th MP ace pts bi nary data a input from d vices ucl a 1eyb t rd and
AID conv rt r and n<l: data to 1tp 1t devi u h as L D. or printer . Th r ar Lwo
differ nt m th d b hich I/0 d j e. can b id ntifi d: on uses an 8-bit addre and th
other us s a l 6-bit addr ·. hes m lhods ar des ribed bri fly in th followin ection .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

I/Os with 8- it Addresses ( eripheral-Mapp ed 1/0)

In thi. Lype f 1/0 tl MPU uses i ht addre lines t id ntify an inr 1t or an output de-
ic · thi. i kn n p riph ral-mapped J/O ( ls lmo, n as I/0-1napped 1/0). Thi is an
8-bit nun1bering y t m for I/Os used in c nj rnction \J ith Input and Ou put in ru ti n .
hi. is al o kn wn a I/O spac . s parate fr n mem ry space which j a 16-bil nu,nb r-
ing sy t 111. The i ht address lin can have 256 (2 8 ombination addresses; thu the
P can i l ntify 256 i1 put devices and 256 output d vie s with addre e ranging fro1n
OOH t FFH. The input and output d i · s are differentiated by the ·ontrol si nal · he
MP u es th /0 Rea I onlr 1 ignal for input device nd tl I/O Writ control ign 1
f r output d vi s. h ntir ran f I/O addre es from 00 l FF is nown as an 1/0
n ap and inc.Ji i<lual addr . ·e are r f rr 'd to as /0 d vie addr s es or I/O port num er .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

]/Os with 16-Bit Addre,s ses (Memory-Mapped I/0)

In this typ of 1/0. he MP use 6 add· lines to identify an T/O d vi ; an I/O i on-
n ct d a if it is a me1n ry regi ter. " hi i known as m mory-mapp d 1/0. The MP
th am control i nal (Metnory Read or Memory Writ and instruction c lho
m m ry. In me m1croproce or uch a the Motorola 6800, all 1/0 hav 16-bit ad-

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

-rl--t--i-+-+--1--Wl-

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 1

t
o.
Bu
ta I ~l ·h
to .•

tc:h E11 ab l
0

L
1 1M iow
nal lJ e ·ic S le l uJs

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

Absolute vs. Partial Decoding

In Figure 5.4, all eight address line,; are decoded to ~n'rnt · >11 • uniqu out ul pu lse ; th
device will be se le ted only wi1h ch• addr's ·. 0 I H. hi is t:alled absolute decoding and
j:,, ,1 oml d ·sign p1m.: tic •. Hm ·rr. to minimize Lhe co. t. 1he output I II c.1 11 b sclcl'l ·d
by <l • · ding some uJ the a<ldtess ti n s. as shown in ri )u ,c 1.5: tlii . 1s ulllc<l partial de-
coding. A. a re!iult, the de i1.:e IHI'. 111ulli t I· address ·s ( ·imtlar to fo ldba1.:k memory ml-
d11.!s:,,cs).

//
Q7 1<1.../\/v\r
--
IJ7 lJ7

Data Lmch t-5 \I

Bm
/J'
0 Do On

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 Fi •ure .5 is similal' lo rig ur · 5.~x.ccpl Ll wt 1c atldres · lines AI and O are nol
connected, and lh y are replaced by 10/M and WR. signa ls. Because the address lines A 1
and ~ are al <lon't care I gic level they can he a. sumed lo be O or I. Tli s lhi out-
put p or·L ( latch) can ht: ac ·-cssec.J by I l1e He .iddrcs ·c · 00. 01. 02, an<l 03. 'l'he partial
d ·coding is a commonly used technique in small systems. Such mul tiple addresse. will
not cause any problem . provided Lhe. e addresses al'e not as. i~11ed to .111y ot her out -
put ports.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

I put Interfacing

D1

DIP Tri-St I D I Bu~

A1 Buffer
Swi lche!>
A,,
A
A~
A, En ble

A2
I
A11
lJ IOSEL
Devi e Selecl rul~e
IOR

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

lnterfaci ,g I/Os Using Dec,oders

sv

~
A1
Dali.I T ._ tote
Bu~ Bulfc1
IOR
E1 E2 E,
EN
B J-10-8
A, - -
-=-
A; FJ\11

Ao F8H
//
l<l-¥1\r
D111n L:uch I.ED~
Bus + V
//

IOSEL
10\

A-, A" As A.:1 A3 A2 A1 Au

I 1 l 1 1 0 0 0 = F8H
I I
l
Decoder Enable Input

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 9

Mulf ple Port Addresses

15 V

s,
A1 D7 7-4LS244
A6
Oclal s6
As Bulfi:r Ss

°E 1 li2
s..
Data
MSB I S1
A2 A2 Bu.s
IOADR 0 S2
A,

Ao
A,
Ao
-10--8
oder
o,.
u Do
OE
0
0
s,
s

74LSI B

10/M
RD--Q._____J !OR

In Figure 5. 11 . t l1 l! ad<lrcss lin~s A~ anti A are 1101 us ·<l by lhe <lec.;ouing circuit: th lugk
levels on the e lin scan be O or I. Therefor . Lhi,; input port an a ce. sed by four dif-
ferent addresses, as shown he lm: .

A1 A6 5 A-1 A- A2 A, Ao
I 0 0 0 0 0 0 = 8411
l 8 H
0 =94H
= 9 II

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 10

 THE 8269iA PROGRAMMABL
INTERRUPT CONTRO-.......

Th 8259 i a pro rammabl interrupt c ntroller de i n d o w rl with Intel micr -

proc or 8085, 8086 and 8088. h 82 9A inlenupt c ntr Iler can

1. nrnnage i l int rrupt rding L the instructions writt n into its con trol re i ter .
hi j equivalent to providin i ht int rrupt pin on the processor in pla of ne
INTR (8085 pin.
2. ve t ran int rrupt reque t anywh r in th mem ry map. IIowev r all eight int rrupt
arc spaced al the int rval of ith r four or ei ht location . t j eliminat ll nrnjor
dr, wbac of th 8085 int rrupt in which all interrupt r v ctored l m 1n ry lo a-
ti ns on pa c OOH.
3. r ol eight I ,Js of int rru t prioriti in a vari ty f n de u h s fully n t d
1 o , aut mati · rotation mod . and pecific rota ion 1110d (to e xpl ir d lat r .
4. 1 a ·k ·ach int rrupt rcqu st individually.
5. r ad th tatu · of pcn<lin interrupts in- en i interrupt an I ma eel int rntpt .
6. b set up t ace pl ith r th I vel- rig re I r th edge-trigg red it t n'ltpl r ue t.
7. b expand <l lo 6 priority levels by ca cadin ad itional 8259A .
8. be et u1 work with either ti 8085 1 icr pr 'cs · r mod or h 8086/8088 micro-
proce ·m d .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

Block Diagram of the 82S9A

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

READ/WRITE LOGIC
T his is a typical Read/WriLe control logic. When the address line A0 is at logic 0. lhe con-
troller i.. elecLed t write a command or read a statu .. The hip Select logic and A0 de-
t rmin th port aullr . s of the contr lier.

CONTROL LOGIC
This bl · has two pins: INT Tnl rrupl) nn outpllt, and TNT A (In t rnipl Acknowlcd :.c
.i:
as an input. The INT is onnected to lhe interru t pin of the MP . Whenever a valid in-
terrupt i. sse,·1ed, this si 11 1 ooes hi h. The 1NT A is the Tnte1n1pt Acknowledge signal
fr )111 th MPU.

INTERRUPT REGISTERS AND PRIORITY RFSOLVER

' I he interrupt Reques t Register JRR) has eight input line · ( R 0- 1R7 ) fur int rrupls.
When these lines o high, the re u sts ar .<;tored in the re isr r. The in-Service
Rl!gittler I R) stor · all lh I v I~ thal an: currc1Hly bcin serviced. a1 d the Interrupt
ask R ·gi l r (IM R) stores l he musk ing bits of th in l •1-rupt l in ·s lo be maskctl. The
PrioriLy Reso l\'er (PR) exnmines th se three registers and determines whether lNT
should be:,; nl 10 ch ~ P .

CASCADE BUFFER/COMPARATOR
·1his blo ·k is used Lo expand the m11n r uf interrupt level · by t;a~ ·ading l w or m01
8_59A1,. To .simp lify the discuss ion, thi s block will not be me ntioned again.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

Interrupt Opera ion
o implement inlerrnpts, the Interrupt Enable nip-flop in the microprocessor should be
e11~1bkd by w1 it111g 1111: ·l in'itruetion, ,ind th, 8259A shoul I ht! initi.dilecl hy writin con-
lrol word · in th, control regi ter. 'l be 8 59/\ r quir !) two l p of control word ·:
Initialization ' mmand Word. ( I W. ) and Operalional mmand Words (OCWs). The
1 s a.-c u ed to . et up the pn per condi ti ons and specify RST vector addresses. T he
OC. W · ar • u · ·c..l lo pcrr rm lunclion · su ·h a ma king inlcrrupl ·• sctlrn up ·r, ht read
operati n,, etc. After the 8259A ts initinlized , Lh following sequ nee of events occurs
when one 0 1 m 1 rnte , rnpt request lines go hi h:

1. T he lRR store · Lh requests .

2. T he priority r s Iver ch ks thr " 1 ist rs: th I R for inlerrupt r qu st~ . th IMR for
maski11 bits, and th, ISR ~ r th • in ttmupt req u ·t being served. It r solv~ the prior-
jty anc..l ~e ls lhe lN ' high when appropriate.
3. The MPU acknm: ledges the interrupt hy . end in r TA.
4. After the INTA i recci ed, lh appropriate priority biL in the lSR i · sel to indicate
which interrupt le cl is being ·ervecJ, and the corre. ponding bit in lh IRR i. re. et to
indicat thal the request is acceple<l. Then the 01 code for th LL in tru tio11 i
placed on lhe data bus.
5. When the MP d od th CAL instruc tion, it places two more lNTA signals on
lh data bus.
6. When th 8259A receives the second I TA. it places rhe I w-ord r byt f th CALL
addres. on the data btK Al the third !NIA. il places the high-order byle on th data
hu . . T he AL aci Ir . i<; th v c l r mern ry location for the interrupt; this address is
placed in the contro l reg i ter during the initialization.
7. During the third INTA pulse, the JSR bit is re I ither aut matically (Automatic-End-
of-lnt rrupt AEOT or by a om mand word that must be issu d at the end of the ser-
vic.: rouline ( nd -of-lnt rrnpt-E l). 1 his opticn is determined hy the initiali7aLion
command word ()CW).
M. T h pro _n1m :-etiueni.: b trans[ ·nt·d to 1h memor locati n speciHetl by th CA
instn,cti 11.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 Priority Modes and Other Features

Ma11 1 lYJ s of pri rily mod s a1• a 1aila le uncJ r so ftwtu- control in the 8259A. and 1hey
can ·hang ti tlynamically during the progra 1 hy writin appmprial c mmnnd word ..
Commonly used priority mode ore dis u., cd bel w.

1. FuJJ. Nested Mod 1l1is i. a general-purpos · morJ · in which all lRs lnl rrupl Re-
ue. I a, a1 n°ed fr m hi 0 h · ·L to lowest, with ll~ as the highest and 1R 7 as lhe low-
t.
In addition. any JR an be as. i nec:1 1he hi ,..h t priorit in Lhi mod ; th priorily
<;equence ill the, h ,in al that TR Ju th · c-xampl hel w, IR 4 ha 1he hi h . ·t priority, and
TR I ha · th low 'SI prio1i Ly:

TRo TR, TR!. IR, -I 1R5 l IR7

4 5 7 0 l 2 3

+
Low •sL Jigh st
pnorily priori Ly

2. uto1 at'c Rot:ltio l Mo e ln thi s mode. a devi e, al ter bei ng servi ed, receives lh
lm: e Lprioril ,. suming that the IR::i has just hee11 scr ic.:ed, it wil l r ·cciv1,; th
pn rit '. as shown low:

IRu IR 1 I lR lR,, 1
I 6 0 I 1 4

3. Spedfic Rotation Mode Thi 11ode · imilar to the autornahc rotation mode, except
that the ruser can seJect any IR for lhc [ west priority, thu xi 1g aU othe r p1fo1·ities.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

 P ogramming the 8269A

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 Schematic of an Interrupt System Using tbe 8359A

Ay.--------
A.-----
At-----
B, lia B,
A, MIB !-to-I
A.1 - - Dlaader
A, ·o.-------.....el.
74LSIJI ---At

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 OG

The 8254 progra1n1nable jnt rval timer/counter is functionally similar to the software-
design d counters and tim rs described in Chapt 8. It generates accurate time delays
and can be used for applications u h as a ·eal-time clock ar even coun er a digital ne-
shot a squa · -wave generator, and a complex waveform enerator.
Th 8254 in ludes tlu- id ntical 16-bit counte ·s that can ope ·ate independently in
any one of the ix 111odes to be described later). It is packaged in a 24-pin DIP and re-
quires a single +5 V power supply. To operate a counter, a 16-bit count is loaded in its
regi t r and, on o n and, begin to de rement the count until it reaches 0. At the end of
the count it generates a puls that can b used to intenupt th MPU. The counter can
cou1 t eitl r in binary o · BCD. In addition, a count can be read by the MPU while the
ounl r i. · d crementing.
Th 8 54 is an up raded version of the 8253 , and they are pin-compatib e. The fea-
tures of thes two d vi are aln1osl identical excep ha

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

62 54 Block Dia.gram

Pin Configuration Block D1 gram

D1
Oa111 -----CLK 0
Dt1 oun1er ____ GATE 0
Ds Bus
Buffer
=O
04 --► OUT 0
D,
D2
D,
Do iffi
CLK 0 Readf
LK I
OUT0
WR Counter
Writ GATE I
GATE0 = I
~ Logic
GND OUT I
A,
Pin Names

D,Dn Dala Bus (8 Bit)

s
CLK N Counter Clock Inputs
Control CLK 2
GATEN Counter Gate Inputs Counter
Word GATP. 2
OUTN Counter Outputs =2
Regisier
RO Read Counltr 0 T2
WR Write Command or Data
cs Chip Selec1
~, A, Counter Select
Vee +5 Volts
GND Ground Int mat Bus/

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

Fi tu l 5. 3 is the block di agram or the 8254; it includes three co unt er ' (0, 1, an 2), a
data bus buffer. Read/Wri 1c contrnl logic, a nd a co ntro l register. Eac h counter has two in-
pu t signals-Clock (CLK an<l GATE-and one output signal-OUT.

DATA BUS BUFFER

This lri-state 8-bil, bidirectlonal buffor 1s connected to the data bu of th MPU.

CONTROL LOG C
The control. ect1011 hn. fiv signals: till (Read), WR (Write) CS (Chip Select), and the acl-
d re s li n ·s Ao, ud A 1• In th periphel'al TIO mod , the RD and WR signa ls are conn ctcd
to IOR and 10 . re. pectively. rn m moiy-mapped 1/0, these ar connecl cl to ME R
(Me mory Read and M MW Memory Write). Address lin 'S A11 and A 1 of the MPV are
usually co,mected lo lines A0 and A 1 of the 8254, and S is Lied to a decoded addre .
he c;ontrol word registe, a,1d counters are selected according to lh ,.. signal on lines
A 11 and A 1, as sho\ 11 be l w:

A1 ~I Selection
0 0 Cou 11 tcr 0
0 l ountcr 1
I 0 Co unter 2
I Control Re isle

CONTROL WORD REG STER

T his reg ister is acce s d when li nes A and A 1 ar al logic I. Il is us ·d t write a com-
mand word which specifics th counte r to be used, its mode, and either a Re<1u or f\ Wri lc
op 'ration. The co ntrol word forn1al i. shown in Fig11rc 15.24.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

MOD
T he 8254 can op rnl' in si different modes. and the gate of a collnl -r i used eithe1 Lo
tlisal le or e n ble counting, as shown in igurc 15.25. llowever, to maintain clarit y, only
one mode (Mode 0) i.s illustrated first, and de tail of th rcmai ,,in mode. are di cus d
in Section 15.4.4.
In Mode 0, after the counl is written and if the gale i high, lh ·ount is le rc-
mented v ry clock cycle. When the count re;;1ches L.Cro, the output goes high and remains
blgh until a new count or n )<le word i loatle .

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 D,
SC I SCO RW l RWO M2 Ml MO BCD

SC-Select ounter: M-MOD

SCI SO) Ml Ml MO
0 0 Select Counter 0 0 0 0 Mode 0
() I Sele ·t Count r I 0 0 I Mode 1
I 0 Select Counter 2 X 1 0 Mode 2
Read-Back ommand X I I Mod 3
I I
(Se Read Opera.ti ns)
I 0 0 Mod 4
I 0 I Mode 5
RW-Read/Writc:
RWI RWO
unler Latch Command (see Read B D:
0 (}
Operations)
0 R ad/Wril lea. t significant byte only. 0 Bina y Counter 16-bits
0 Read/Write most significant hyte only. Binary Coded ecimal (BCD) Counter
(4 ecade)
Read/Write leasl significant byte first,
then most ignifi an l byte .

Note: Don'1 re Bia (X) Shou ld I3e Oto Ensu Compatability with uture Intel Products.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

Modes
As men 1io.11e{l ,·arli r, the 8254 can opernre in six differe nt modes; we al1Feady illustrated
Mode O in Sec lion J 5.2.3. ow we will clcscrio briefly various mode of d e 8254 in-
cl uding Mode 0.

MODE 0: INTERRUPT O TERMINAL COUNT

ln his mode, ini liaUy the OUT is low. Om:·· · count i · rn•d ·d i11 lh re. iste , Lhe counter
is decren ented every cycle, and when Lhe cour.t reaches zero, tl e OUT go s high. his

ca n be u. ed as ar1 int n 1pt. h O U f remains hi h until a new coun1 0 1 a com mand, 'Ord
i · load d. igur 15.27 al h ws thaLthe c un li1 (1 1 =. ) is temporarily stoppe when
Lh a te is disa I d (G = 0 , and con tnnt d • fiai when the Oat is at logic I.

MODE 1: HARDWARE-RETRlG
In Lhi. mode. th • OUT is in itially hi 1:ll i tri g r , th goe · low,
and at the e nd of the count, the OU , · high a •ain, th us •enerating a on -shot pul.
(Figure I - .27, M cl~ I).

MODE 2: RATE GENERATOR

Thi1- 111ode i u ·eel Lo gen rate a pulse equal 10 th cl l p rio I flt n giv n int rval. Wh n
a count i · loaded, the OUT stay. hi h unti l th c unt r ach •~ I , an then th OUT goe.

[ow fol' one clock period. The count is r ]oadcd au tom lica]Jy. aind the lu l~e .is genernted
,co t.ir1u ously. Tihe cou nt = I. is i!. legal in this mode.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6

 Mode 0: lnterupt on Termina l Count Mode I: Programm11bJ One-Shoe

C luckI !
WR n ~ WltJl-i___.r-

OuIpu1 Clnterrupc) L.._L__ frigger

(n = 4) ,.....---.- n--+-t ~1 0
~~ Outpuc (n~ ~---
WR m
ate~
T n g g e r ~10
Output Clntcrrupt) ~ 011 tput --, ...
, ---
(m = 5) - ~
A 8
A t B m

Mode 2: R tc Gcncnttor lock ode 3 S4u,1.1e Wave Generator

lock Clock
Wttn Output n - 4}
Output
Output 11 = 5) --
Ou1p11t (n 3)
RESET - i..._ __,

Mode 4: Sortware iggc:red Strobe Mode 5: H1udwF1re Trigg red Strobe

Clock
n =4
WR:~ ate
Out1ut~ 0\llput (n 4)

Load 11 n = 4 _r-u
~ Gate:
G,11e Output (11 = 4) 4 3 4 3 2
Output 2 I 0

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 7

 MODE 3: SQUARE-WAVE GENERATOR
In this mode, when a c unt · · load d, th OUT is hi h. The coun t is decremented by
two at every clock cycle, and when it reache zero, th O T g es low, and the ount is
reloaded again. his is t pc ti.;d ·ominuously; 1hu a continu us qua.re wave witb pe-
riod equal to the period of th count i g ·n rat d. In rher words, the frequency of Lhe
quat wa is equal Lo the frequency of the ·loc <livided by th ·ount. I th count N)
is odd, lhe pulse stays I i h fOI' -1 I )/2 clo k ycles and stays low for (N - 1)/2 d c
cycles.

MO E 4: SOITWARE-TRIGGERED STROB
In lhis mode. the OUT is initially high· it lo\! for ne c.:Jock period at the end of the
unl. The count musl e rel adc<l for sub~ quent out:>uts.

MODE 6: HARDWARE-TRIGGERED STROBE

This m de is similar to Mod 4, cxc pt that it is lJ·igger d by the risi ng pulse at the gate.
Tnj1 ially, the OUT is low, an<l when the Gate pulse is triggered from low to hi h, the coun t
b gi11s. I Lhe end o the count, th OUT s low for one cloc p riod.

READ-BACK COMMAND
The Read-Back Command in rhe 8 4 llow · th user tor ad the count and the status of
the cou nt ; thi corrunand is not available in the 8253. he fol'mat f the corn, 1 nd i,
shown in igure 15.28(a).
The comm and is wrinen in th control I' gist r, and th count of the specifi d
ounter s) an h latched if COUNT (bit D5) is 0. A counter or a combination of ounters
i p cified by k eping the respective CNT bit'> (0 1 D 2 , and D3) I i b. or amp! , lhc
control word 1 l O I 0 1 I O D6H wdtten in the c ntrol r ·gist r will latch the cou nts of
Coun tel' 0 and Count r l, and th · counts ·an be obtained by reading respective counter

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 8

 8086 Microprocessors
1

•
I
I, I, ■ ■ .... .I lo
lliill'!li.iil!'w.
I, ■ ■ .I .I .. I,
I N
I, ■ ■ ■ .I .I I

The Intel 8086 is a high-performance 16-bit, N-channel, HMOS ‘High-Speed MOS’.

microprocessor which is available in three clock rates: 5, 8, and 10 MHz. The 8086 is
Intel’s first 16-bit microprocessor. This processor was introduced in 1978, due to the
demand for more powerful and high-speed
computers. This processor has a more powerful instruction set and more programming
flexibility, and its speed is more than the 8085 microprocessor. The CPU of the 8086
processor is implemented in N-channel, depletion load, and silicon-gate technology. This
processor has the following features:
The CPU has a direct addressing capability of 1 MB memory.
Bit, byte, word and block operations are available.
8-bit and 16-bit signed and unsigned arithmetic in binary and decimal operations are
performed.
It is available in 40-pin lead CERDIP and plastic DIP package (Dual In-Line Package).
It has architectures designed for assembly language as well as high-level language.
It contains an electronic circuitry of 29000 transistors. The 8086 has 20 address
lines and 16 data lines. This CPU can directly address up to 220 = 1 Mbytes of memory.
The 16-bit data word can be divided into a low-order byte and a high-order byte. The 20-
bit address lines are time multiplexed to select lines of low-order byte and high-order byte
data separately.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

The 8086 architecture has been implemented using two-stage pipelining in instruction
execution. The processor logic unit has been divided into Bus Interface Unit (BIU) and
Execution Unit (EU). These units are always operating asynchronously. The Bus
Interface Unit (BIU) provides interface with external memory and I/O device addresses
and data bus, and executes all bus operations. The BIU has a 6-byte instruction queue.
On the other hand, the Execution Unit takes the instruction from the 6-byte instruction
queue of BIU and executes it. Thus, the instruction fetch time has been drastically
reduced.
The 8086 is a 16-bit microprocessor and it has a 20-bit address bus and a 16-bit data
bus. Therefore, this processor can directly access 220 = 1,048,567 (1 MB) memory
locations. It can read/write 8-bit data or 16-bit data from/to memory or Input/Output
(I/O) devices. The 8086 has time-multiplexed address and data buses.
Hence, the number of pins can be reduced, but it slows down the data-transfer rate. The
block diagram of the
internal architecture of the 8086 processor is shown in Fig. 5.1. It is divided into two
separate functional units such as Bus Interface Unit (BIU) and Execution Unit (EU).
These two separate units are worked simultaneously for instruction execution based on
two-stage instruction pipeline principles.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

ARCH ITECTURE OF 8086

l tq

~ ~'=

I
L ___________ JI

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

Bus Interface Unit (BIU)

The Bus Interface Unit (BIU) consists of bus interface logic, general-purpose registers, segment
registers, stack pointer, base pointer and index registers, memory addressing logic and a 6-byte
instruction queue. The BIU carries out all bus operations for the Execution Unit, and it is
responsible for executing all external bus cycles.
The BIU performs data and addresses transfer between the processor and memory or I/O devices.
This section computes and sends addresses, fetches instruction codes, stores fetched instruction
codes in a First- In-First-Out (FIFO) register which is called a queue. The BIU is also used to read
data from memory and I/O devices, and write data to memory and I/O devices. While the EU is
busy in instruction execution, the BIU continues to fetch instructions from memory and stores
them in the instruction queue. This unit relocates addresses of operands while it gets unrelocated
operand addresses from EU. The execution unit tells BIU from where to fetch instructions as well
as from where to read data.When the EU executes an instruction the BIU resets the queue, fetches
the next instruction from the new memory location, and passes the instructions to the EU. In this
way, the 8086 BIU fills the queue when the queue becomes empty spaces of two bytes. This
process is known as pipeline flush.

Dr. Anwar Sadat, Electronics Engineering

4
Department, A M U Aligarh.
 Execution Unit (EU)

The Execution Unit (EU) consists of Arithmetic Logic Unit (ALU), general-purpose registers, flag
register (FLAGS), instruction decoder, pointers and index registers, and the control unit which are
required to execute an instruction. The EU gets the opcode of an instruction from the instruction
queue. Then the EU decodes and executes it. The BIU and EU operate independently. When the
EU is decoding or executing an instruction, the BIU fetches instruction codes from the memory
and stores them in the queue. This type of overlapped operation of the BIU and EU functional
units of a microprocessor is called pipelining. This process becomes faster except for Jump and
Call instructions as the queue must be dumped and then reloaded from a new address. Hence,
the function of the EU is to execute all instructions, provide address to the BIU for fetching
opcodes and operands and perform ALU operations after using various registers as well as the flag
register.

Dr. Anwar Sadat, Electronics Engineering

5
Department, A M U Aligarh.
 Fetch and Execute

During fetch and execute of instructions in the 8085 microprocessor, the nonpipeline concept
follows so that instructions are fetched and execute sequentially as shown in Fig. 5.2(a). In the
8086 processor, the BIU and EU perform the fetch and execute operations with overlap.

Dr. Anwar Sadat, Electronics Engineering

6
Department, A M U Aligarh.
 REGISTERS

The 8086 CPU has fourteen 16-bit registers as depicted in Fig. 5.4. All these registers are
subdivided into different groups, namely, Data Register Group (four registers), Segment Register
Group (four registers), Pointer and Index Register Group (four registers), Instruction Register
(Program Counter) and Flag Register. In this section all registers are discussed.

Dr. Anwar Sadat, Electronics Engineering

1
Department, A M U Aligarh.
 D,ata Re,gisters

h · 0 6 has four 16-bit g n rd -purpos r gist rs ( B , and D ). h ·s r gist rs can b us d in

arithm tic, logical op -rations and t mporar storag . of th s 16-bit r -gist rs is furth r subdi id d into
h o -bit r gist rs (upp -r ,nd low r b s) as shown in -.b,I . ..)"' .

Table 5. 3 General-purpose data registers

·-----------------------------~--------------------------,----------------------------·
: 16-Bit : 8-Bit Iii h-{Jrt/er 8-BifL{Jw-onler
1 1:
: Re 1 i.,·ters • Re 1 ister.,· : Re 1 isters :
·-----------------------------~--------------------------~----------------------------·
~------------~---------------~-----------~'!------------!------------1:~--------------~
I BX BH
I BL I I

~------------cx---------------t-----------C-H------------1------------CL--------------~
~-----------------------------►--------------------------T----------------------------~
I DX DH
I DL I I

·-----------------------------~--------------------------·----------------------------·
Th fimctions of ·ach data r ·gist ·r ar · discuss d as foJlm s:

AX Registe·r Th·
gist 'lf s r s as an a· ·umula or. H p rforms irrpu output p n: .t i ns i: nd
lf

pro ~ ss s d,ita through r · H or L. During x "cution of a 16-bit multipl and di id" ins1tn1 ·hon,
·ontains h on -\ ord p rand and th r suit is s or d in th · a· ·umula .,r. In , '-bit multipl "nd di id
instru ·tions is us d o hold h lo\ r -ord .•r \ ord op ·rand. filnstru ·tions in ol ing or · H or L ·an
l ad dah imm ·di~d 1 and h n · " data usuall r quir I ss pr gmrn m nmry.

Dr. Anwar Sadat, Electronics Engineering

2
Department, A M U Aligarh.
 BX Register B can b us d s an ind . regist r fi ,r MO I ,p, ration and b· s r gist r hil
·omputing th data m mory addr "ss.

CX Reg1ster r gist ·r ·an b · us d as c: . ount f gist ~r for string op ·rati ns and holds ;; · unt
alu " during hug · numb r it rations. n LOO . instru ·tions holds th· d "sir d numb r of r p itions
rnd is • u -mati ·all d "cr "n nt ·d b on " a tt "r ·rch it ·ration. Whil" b ·om "s z ro th· " · ·ution of
instru ·tions sh uld b t rmimt d. fu th · sam ay th -bit L r gist ·r is us d as t ·ount r gist r in bi -
shifting and ro a · instn1 ·ti - ns.
15 0
15 87 0 SP Stack Po inter
AX AH AL Aocumu ator BP Base Po"nter
BX BH BL Base SI Sou roe Index
ex CH CL Gaunter DI Desf nation I ndlex
DX DH DL Data IP Instruction Pointer

(a) (b)
15 0
ES Extra Segment
-----1

cs Code Segment
-----;

OS Data Se,g ment 15 87 0

-----1

ss Stack Se,g ment I F lags I F lag sL I Flag Re,gister

(c) (d)

Dr. Anwar Sadat, Electronics Engineering

3
Department, A M U Aligarh.
 DX Register D ·an b ~ us ·d as a port
addr ss fi ,r r and OU insh11 ·tions . . h · D
mt . b · us ·d in 1/0 ins rue i ns, multipl · and
di id instru ·ti ,ns. n -bi multiply · nd di id
instru ·ti ns D . is us d to hold h · high-ord <·:r
\. ord op ~rand.

Dr. Anwar Sadat, Electronics Engineering

4
Department, A M U Aligarh.
Segment re·gisters and segm·ent memory

Segment Memory
Segme,nt Register
BIFIFFFIH
64 KB 8000H
80000H Code Segment

6F FFFIH

64 KB 6000H
60000H Data Segment

3F IFFFIH

64 KB 3000H
30000H Stack Segment

1IFIFIFFIH

64 KB 1000H
10000H L---___..L..__-------l- Extra Segment

00000H ·1 j
Dr. Anwar Sadat, Electronics Engineering
5
Department, A M U Aligarh.
Seg1
ment IRe·gist ers

Th· on· -pt of m .•m r s -gm nta ion\ as intro-

due d in th ' O' 6 pro · ssor. n m mor s g-
m -nt··tion, th· · mpl ·t · llB m -mory ·an b ·
di id d into 16 parts whi ·h ar · ·all d s gm nts.
'"' a ·h s ·gm nt thus ·ontains 4 E B of m mor .
In · ·r ar tr s "gm ·nt r ·gis su ·h
· .s . m·nt ) R gist r, Data ·m nt
(D ) R gist r, l ' gm nt .. ,ist r and
xtr'l ·gm nt ) R gist ·r. 6 mi ·ro-
proc ssor- · m m mory is di id ·d into
· if nts, n · , d gn ·t
( D 1 1 nt (D' ) k )
· nd rn nt ·· . . gm - has ·
of 64 , • s d pi ·t d i ig. ,.. . ,.. ,
I

"nd "ach s gm. nt can b addr ss d b 16-bit

s gm nt r gist rs.

Dr. Anwar Sadat, Electronics Engineering

6
Department, A M U Aligarh.
 Code Segment (CS) h · cod s gm nt r gist ·r is u: d for addr ·ssing L m ·mor lo ·ati n in th ·
·od s gm nt of th· m mor in , hi h th program is s or d for x ·ution.

Data Segment (D.S) Th data s gm nt r gis r points to th data s gm nt of h m mory \.Vh r

data is s or "d.

Extra Segment (ES) h tr s gm n 1s a s gm nt , hi ·h n b · us d as an .th r dtt· s gm nt

of h " m ,•mor . h "r for

Stack Segment ,(SS) 1

h . sta ·ks gm n r gis r is U.' d fi r addr ssing sta. ·ks gm nt f m m r

in , hich s ·1 ·k data is s or d. h · U us s th stack for t mpornril st ring da a, i. , th · cont nt of all
g n r l purpos " r gist rs whi ·h v ill b us d I· r.

Dr. Anwar Sadat, Electronics Engineering

7
Department, A M U Aligarh.
P'o,inter and Index Regist,e1
rs

h ,·p int ,r and ind , r , gist rs f O' 6, · r · as fi Ho, s:

♦ ta ·k Point r ( P)
♦ Bas P -,int ·r (BP)
♦ . urc Ind · ' ( I)
♦ D ·s in-- tion Ind "X (DI)
♦ lnstnt ·hon Point ·r (IP)

Dr. Anwar Sadat, Electronics Engineering

8
Department, A M U Aligarh.
 Stack Pointer (SP) The tack pointer i. used t I .ate the . tack-t p addre . s_ ]t c ntain . an
, .. et addre. s.. ]n P 1,U], p, ,p ( .' LL and RE~f instructi ns, the . tack addres. i. detem1ineda er addin the
c ntents I the stack .e ment re ·ster, after 4 -bit ldt-shift and the c, ntent P.

Base Point,er (BP', 1

Tl
. re base mer
· t re. 1· ter can proVJ,
· c1e
·. • d.irec t acces. ·t
111 - ta. ·111
da a .st ac -k"_Tt-
. 1e BP
,
may al be used . r eneral -purp e data st ra e_

Sour,ce Index (St) and Destination Index (DI} These re · ters are u...ed in mem ry , r
tack-addre . c, mputation r eneral data . t rage_ The main purpo . ,e the ere i ter i t t re .. ,et r
di.placement ]n mem ry addres. computation, tire o ntent o. data se. ment and index re L ter dependin
up n addres. in mode . _
1
metime is used a . . urce index and rn ru destinati , n index_ ] tire o ntent
1
] i added with the
1

c ntent , D t, detem1ine tire phy . ical addre .. , it will be used as .· urce addres. data_ Whi l,e the c, ntent
f D] i added with the c ntent t . md tire destinati n add:re s . the data, these reg isters can a l e
u, eda. eneral purp . ere i. ter _

Instruction Pointer (IP) Oerrerally, the instruction p inter re. Lter i. ruedm a pmgram counter_
mem ry add11 . ses , instructi, 11. ,vhkh wi II be execute,d_ Thi. re ister
st res the .. set ., r the imtructi n_ Thee ntent , IP i aut matically incremented while the executi n . an
in. truction i. oin n_ The addre. s , the next in . tructi n i. computed a . er addi n. ]P ntent t the code
. •e ment re ·ster o ntents a. ,er 4-bit left-. hift_

Dr. Anwar Sadat, Electronics Engineering

9
Department, A M U Aligarh.
PIN DESCRIPTION OF 8086

G ND vcc
A D,4 2 A D,5
A D,a 3 A ,i Sa
A D 12 4 A.,.,JS4
A D,, 5 A.,J Ss
A D,0 i6 A ,J S6
A Dg 7 34 BHEJ~
A D8 8 33 M /MX
A D1 9 32 RD

A D0 10 31 RQ/GT O HOlD
8'08'6
A D5 11 30 RQ/GT 1 H l DA

A D4 1.2 29 l ook WR

A D3 13 28 &i MAO
Minimum
A D2 14 27 s, Max imum
moo,e DTIR mode
A D,
15 26 so DEN
A DO
rn 25 QSO
AL E
NMI
17 24 Qs,
18 23 INTA
INTR TEST

Cl K 19 22 READY

G ND 20 21 RESET

Dr. Anwar Sadat, Electronics Engineering

1
Department, A M U Aligarh.
 AD, 5- AD,0 (Bi-dire,c tional) Address/Dat,a Bus ~ hese Iines con. titute the time-multiplexed
addre.. data bus. "fllese lines are low 11der addre .. bru. They act m an addres. us durin the . u. t d ck
cycle multiplexed. \Vhen D lin . are u ,e d t tran. mit mem ry/]0 addre.. the symb I I used , AD. , r
example, represent. 1-- 0 . \ hen data are tran. mitted du u h D line. the sym I Di used in place ,
D. r example represent D 7JD0 , D1rD 8 , r D 1rD0 .

A19- A16 (Output) These are hi h~ rder addre line and they are time-multiplexed line .. During
T1, these Iines can be ru ,ed a. hi. her rder bit. ·. memory addres. . But in 1/0 perati n, these line. are I, ,v.
Durin T2, T3 , and T4 , they carry ..tatus .. i nals.

A,JS3, A,.,,ts,, (Output) . 16 and naretime multiple. ed with se ment identi. 1er si nal J and L

' 4.Dorin . T1 dock cycle, 16 and n are used a . addres. bit . ~n T2 t T4 clock cycles, these Ii nes carry . tatus
. ignaL. Ta l,e -_ · h ~ mem ry se0 ment identi11cati, 11.

-
r---------,-----------r--------------------------------~
~

1 L\'4 1 S3
~---- 0 ---1----() -----r---- .
1 F1m tim,
·xt.ra sq~ncnt mc mO!)' a 'l't.'SS - - - - -i
~---------,-----------r--------------------------------~
1

1 0 1 l I St.a ·k scgmc1111 uncmoTy a ·css 1

~---------J-----------L--------------------------------~
~---- ]----~---- 0 -----~---- CCldc SC},'lTICn l mc mos y a n...-ss -----~
1 l 1 1 1 a ta sc•rmcTI t m ·111011• a 'C ·s s 1
~---------J-----------L----------~ --------------------~

Dr. Anwar Sadat, Electronics Engineering

2
Department, A M U Aligarh.
 A1sfS5 (Output) ui is time multiplexed with interrupt . tatus -. Dunn. r. c , ck cycle,
. 18 i.
tra.n. mitted t the address bus. Dorin other dock cycles Ti, T3 and T4), the ..tatus i nal 5 i.. tra.n. mitted
thr u h this line. 5 i. an interrupt-enable . talus signal. t the e. innin. , each dock cycle, the tatru the
interrupt enable fla . 5 i. updated_

A1/S6 (Output) 19 i. multiplexed ,vith the . tatus . i nal ' 6 _ Dunno T 1 cl ck cycle . 9 i.
tran.mitted t an addre . . bu... Ourin T, t T4 the talus si nal 6 is availabl ,e n this line. :It i. lmv durin
L

f2 t 14-

BHEIS7 (Output:) Bus High Enoble/St,atus Dorin T• the bus hi,gh enable . i naJ BHE can
be used t enable data nt the mo ..t . i ni11ca.11t ha.I the data bu.. D 1r '8 . n , -bit de,~c.e c nnected t

the upper hal the data bus u. es a BHE . ignal t conditi n chip .ele<:t functi ns. BHE L I w durin T1 r
re.ad write and interrupt ackn wle,d e cycle. when a byte i. t tran . erred , n the hi h p rtion I the bus_
Thi . pin i. muhip le . ed with the . tatus . i nal 7 . The 7 status . i nal is avai la.bl e durin f 2 t T4 . The . i nal
L

i. active I w, and fl aL t 3- tate OFF in h l,d U i. I w during T1 . r the first interrupt ackn wled e cycle_
Table .6 . h w. the function BHE and 0

l•--
__
IJ.HE
--r----------,----------------------------------•
l A'-1 : Frm lim1 l
~---- 0 ----+-___ 0 __ --~---- \Vhol · word __________________ --~
•---------·----------,----------------------------------~
1 0 • l l Uppi:r byt · from/ Lo odd adc.lri:ss 1
•---------~----------,----------------------------------~
~---- l ----t-___ 0 __ --~---- Lo\\' ·r byt · fmm /to :'\'en address ___ --~
I l I l 1 011 • I
~---------L----------J----------------------------------~

Dr. Anwar Sadat, Electronics Engineering

3
Department, A M U Aligarh.
 RD (Output) (Read} Thi. control si. nal i. used r re.ad peration. lit i. an output ·gnal :11 is
active when LO\ _The Read signal indicates that the prooes. r is per. m1in a mem ry r 1/0 read cycle
dependin n the tate o the ' 2 pin. Thi si nal i lL'>ed t re.ad device which r . ide n the O· 6 bus. lW i
active I w durin T2 , T3 and rw , any re.ad cycle and i. guaranteed t remain hi h in T2 until the 8086 I cal
lL'> 1. ated. Thi. j nal fl at to 3~. tate O in h Id acknowled e.

READ Y (Input)
1

The addressed J/O r memory devic.e . send acknowledgment thmugh thi. pin and
it indicate that the data trans. er is o mpleted. The RE D . i nal r m mem ry r 1/ 0 i. synchr niz.ed by
the 284 d ck . enerat rt pr vide R D input t ~O 6. Thi ignal i acti,re HmGH. The 086 - D
input isn t synchr ni .zed. Correct operati, n i. not guaranteed i the set -up and h Id time. are n t met \l\1hen
R D i. · I G H , it indicates that the peripheral i. ready to trans. er data.

INTR (Interrupt Request) h L a level-tri ered input which is sampled durin the lmt d ck
c de each in tructi n t determine i1 the proce s, r sh uld enter int an interrupt vect r-1 k up table
located in the . ystem mem ry. ]t can be internally masked by s, ftware resettin. the interrupt enable bit.
I TR i.. inte mal ly . ynchroni .:red. " hi.. .. i nal i. active H JGH.

Dr. Anwar Sadat, Electronics Engineering

4
Department, A M U Aligarh.
 TEST (Input) Thi. i. rued in conjunction with the\ JT in..tructi n. 11 the TE. 'T input i. 0 \ ,
executi no ntinues. Otherwi.e the pr c.e • r wait in an idle . late . Thi. input L . ynchr ni.red intemall~ir
durin .each cl, .k cycle , n the leadin ed. e , f CLK. \Viren it i I w the rnicr pr ce :r c ntinue . executi, n
, therwi.se it wait• .

HMI (Input) Honmask,ab-le Interrupt ThL Lan ed e-tri."' ered input which causes a type 2
interrupt. ub:r, utine L vec:t red 1 ,faan interrupt vect :r I k-up table I ated in. ystem mem ry. i.
not ma. kahle i ntemall by software. trans1t1 n m LO\ T , HJOH initiates the interrupt at the end o the
current in. tmcti n. This input i. internally sync hr, nized

MN/MX i(lnput) The minimum/ma: immn . i nal indicate. tire , peratin m de , , . When it is
hi h the O 6 pr ce sor , perate . in minimum m de. I this pin i . 1 w, the proces .. r perates in ma. imum
m de.
~

in max imum m de dependin . up n the tatu. f the pin

~

/JWX. When
. .· 8086 w rk in
minimum mode which mean . that operate. in a .in le proces.- r em~ronment. I
I IMX = 0 D, it
w :rks in maximum m de and the pr ces .. r can be per.ated in multip:roces.- :r envir nment. T di .. e:rentiate

RESET (Input) The re.et signal i active 'U,GH. The pr, c.e •. . r immediately tern1inate. it pre. ent
activity and . y. tem i. re. et. The .i nal mmt e active rUGfJJ rat le.a. t . urdock cycle . . lit re. tart executi, n,
a described in the instmcti n set when · T return I w. T is. internall y ynchr nis.ed.

CLK (Input) The , ' L . ignal pr vide. the ha ic ti min . , r the pr, ce . .· r and bu . c ntr, lier. ]t i.
asymmetric with a 33% duty cycle to pr vide , ptimi.red internal timin . It i. an nma. kable interrupt request.

Power supply, de

GND O:round

Dr. Anwar Sadat, Electronics Engineering

5
Department, A M U Aligarh.
 ha.. a. 16-bit a re i ter. Thi. re. i. ter i also called Pro. ram ' ta.tu. \ rd P \"/). h ha. nine fla .
ich six are ..tatus flags and three are he status · · , '• ·· •. Parity fla
uxiliar , 'any fla ·· er, fla, F and Over. 0 Fla. . are
.ted after thee. ecuti n hmeti lo . 1• . The co o ·e ]ntermpt
la I F. and Directi n Fla . Fi. u .6 · 1e 1 . -bit . a. re i. ter the . •

15 Flags11 8 7 F lags._ 0

X X X X I OF I DF I IF I TF I SF I ZF I X I AF I X I PF I X I CF I
CF - Carry flag SF - Sign f lag
P F - Pa ri1
t y flag TF - Trap f lag
A F - Auxil ary cary flag IF - Interrupt flag
Z F - Zero f lag DF - Dire,c tio11a l f lag
X - U11de rfi11ed OF - Overflow flag

Dr. Anwar Sadat, Electronics Engineering

1
Department, A M U Aligarh.
 Carry .Flag (CF) The carry ·a is sett l i a er arithmetic peration a carry is enerated r a
b rr, w i. . enerated in subtracfi n. \ hen there i. no carry ut the carry tla . i. reset r zer _~ his fla can
al. o be used in s me . hi . and r tate instruction.

Parity Flag (PF} l the re ult • -hit • perati n r I wer te thew rd • perati no ntain an
even number L parity fla i. .•et.

Dr. Anwar Sadat, Electronics Engineering

2
Department, A M U Aligarh.
 AuxUio·.ry Corry flag (AF) Thi:.~ a • i:s :seuo I ifthere i · a airr , wt of I.he , ·e:r rubbl'e: to the
h ighe:rnibhl'e: ofan 8-bit operation. It i.: ~ for BCD ope:ratiorr.~.

Z,e ro flag (ZF) The zero · a ,. i,s ~ to I if I.he re,<:Utt of an , arilbrtlrlic or log.ii - 1operation i:.~ zero.
\Vhife the re.'itlfl i..~ zero ii i:s re.'d: .

Sig,n1IFlag (SF) The . · gn n:a ,. i. :set to I 1fthe M B ofthe re:sutt i.· I after the arilbmet' or lot•i
operation-~. Thi'ii n:a • rq>n.-Jient~ a :sign number. 1..og-· 0 irrlicate_~ a po.~iti, , n.1.1.ntber and b .•-ic I ·i:.~ u~ed to
repre.~t ne ,, fo · ntl.rrlber.

Ov;erf,fow Flog ,(OF} Thi:.~ ' ' r, i..~ set i.O I if the i.i.gned re,i,u !I c annot be expre.,;.~ed w-ithin. the
n:umber of b it~ in. the de-,~ ina tion operand. Th.i. G · ·, · s 1u~ed to &c,tec,t magn.itude O\'e:r o,,,,, in.s i,\p]ed arith.metiJ
oper··'Irons. Du.rin" addition operation. th.e a ,. i · set ·1,,:ben th.ere i:.~ a carry into 1the MSB and the ··. ,. ·ias reset
if there i:.~ no carry out of the MSB . For subtraction operation. the rra • i:.~ :set wn.en.the MSB de.~ire.~ a borrow
and the an ·i. G re,..et if l:here i.Gno b>rra....· from M SB .

.Oirect.ion Flag ,(O.F) Th.e d iTeL,"tl'On fla ·• i. G u.~ed in. strin r• operatian.G. \Vhen ii i..G set i.l'.) I sitrinr,
by-tees am be acre_,;.,;ed from a memory addre, " in dec...Tem.ent order i.e. h i •h memory add.re~. to] · memor
add.re_,;.~ . Tf il i..~ zero i.'lrin r, b)sle!a-;;Jn beaooe:!iliCd from memor , a-dd.re.,;.~ in in.crea.~in • onler i.e. lo,,,,, memo..··
· ddre_,;.~ to hi ••hmemo.· , a-dd.re_~.s. Fore.-.:.ampl'e: in. Mov · imtructi:on ifDF i..~ :set1to I l:h.e oontent~of the index
ren-i:.~1~ I and D I are auJ:a:n.aticaMDy@remented lo acoe:ss the ~trin lT b Ii-Ji. TfDF = 0 ·inrex re ,·i.'iirer& SJ and
D I are automatiw"t.11' •incremented to ' _., l:h.e strin ,
1 • te-~.

ln•terru,pt Enable F,log (IF) Tb i:.~ 1.- , . c.an be u~ed as an interrupt enabl'e or dis.~bl'e , , . \Vhea
1h i..~ a ·, i:s set. l:h.e ma:.~k;J.bl'e interrupt i..~ enabl'ed and 8086 reco. irze_~ l:h.e ate:rn.al interrupt reg_ uest:s and
the CPU tran.!.l'e:r control to an inter:rupl ,,ecto.r specified kication. When IF i:.G (l .aUI ma:.Gkablle in·terrupts are
diisa ed and there wll be no effect on. nonma:.~kable interrupts iii.~ ·weJI ili.'i in.ternallly generated interrupt~. If
8086 i. G n.-,Gel. IF is automaf caUly ere.ired.

Tr,a p Flag (TFJ TF is a :sin •le-!.'lep, Ila , When TF i:s set to I ai s-inr•l'e .ilep, interrupt OOl.-'1.1.r.!i after
the Ill'.',.: d inGtru(-1ton t:'XCoui:e,Gand the pro, am c-.a n be e.-.:ttiuted in. s in.r•l'e-ste,p mode. The TF ·wiiU be cleared
b the s in , Ee~i.'lep interrµpt.

Dr. Anwar Sadat, Electronics Engineering

3
Department, A M U Aligarh.
LOGICALAND PHYSICALADDRESS

The n the addre. s bust dete,ct a memory locati n or mem ry read r write
p erat i, 11. . ddresse. with in the se ment can be varied fr m O· .I t ·➔ .I 4 . :r. detect a mem ry

I ati, n the .egment regj . ter . upplies the hi her- rder 1 bits o the 2 -bit memory addres . . The I wer-order
1

1the 2! -bit mem ry addres. are .. t red in any the p inters and inde. regj. ter. , r BX re. i. ter.
There re, mem ry addr-es e o. the 86 are c mputed by smnmin the c ntent. the segment re. i. ter
which L shifted le ft by 4 bit and the o ntent o I set addre.. s. The 2! -bit addre . s . ,ent by the ,

i called the phy. ical addre . . as depicted in i .

The phy. ical addre . s i. calculated from the .e ment addre .. and .et address. The .e ment
re ister contains the hi her-order l • bit. the startin addre . a mem ry se. ment. The CP hifts the
c, ntent , the . egment regi . ter left by , ur bit r insert. ur zer r the I we . t ur bit o. the 2 -bit
mem ry addre . s. r example i. the content I the o de .e. ment re i. ter is ' [i, the .tart in addres.
the code se ment will e ]_ knee the 4 mem ry se ment may be anywhere within the c mplete
I MB mem ry ba....ed n the c ntent , f the de _egment re i. ter and the ..tarti n .addre s h ul d be divi . ibl e
y 16.

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

 The et addres i. used t detennine the mem IY I, ati n di . tance fo m the startin addre. within
the mem ry . e. ment _ n set can be
Effectiv,e Add ress I
detern1ined dependin up n the addre sin o r Offs,et
rn de _ The , set addre. s wi II e d i . erent '--------------'
in di .. erent addressin mode. _ To I cate a
4 Biits
mem IY I cation within a mem ry . e ment, Segment Addr,ess
the 8 1
' pr, .e . .. r enerates a 2, -bit 16 Bits
physical addre. s_
~i-: detern1 ine the 2, -bit ical addres.
with a . egment re · and et, the c, n-
tent the se me, ter i shi. ted by
4 bit. and then a · ded it_ F r
example, i the c ntent o , · ' i. 40 H and
P hysica l Add ress .2 0 Bits.
an . . et i. 20 H the computati no . 20 -bit
physical addre s i 4 2 OH_ Then 2! Ftg. 5. 7 Construction of physical addr,ess
represents the starting addre s the . e ment
in mem ry_ igure _ . how. the ,c, mputa-
ti n . phy. ical addre . .. _

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

 Detennine the phy. kal addres when C = 3, I and P = 1 20 ]. \ rite the
Example 5.1 sta.rtin and endin addre .. s fthe c de se ment.

The ntent . the de ,e ment i. le shi1ted by 4 bit and the base address bee, mes 3 t ~ detem1ine
the physical address, the c ntent 1 wil I be added with bac;,e addre . Bence phy ical addre = I
= 32
1 H.
The startin de ,.egment mem ry = 320 H.
s - ment mem ry K mem ry lo cati m , the end addres will be c, mputed after
additi n ith the . tartin . ,- 1ent mem ry.
= 631 F t

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

 , etem1ine the phy ical addre . . when - , i and , . !'>et addr 4 H
............................................
S,oliuti on 1

The content . the segment regi . ter I i. 6 - nL \ hen it is le. t . hi . ed h~ir 4 hits , r multiplied y 1 D , r
IO H, the base addre .. s i equal t , H x 10 i:-i = 6 H.
Phy . ical addres. = 1
' ntent . segment re. i. ter x I Oi . et addre ss
= ..·x 1 H 1 4 6 H =
1 :1= 69 -

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

~ · ............... .u ............................................................. , _

Examp,le 5.3 hat is the c, ntent data . ,egment t locate the physical add:re . . 436 - T.
•s•••••••• .. •••••••••• .. •••••••••• .. ••••••••• ·
s wne the c ntent IP = U · ~I.

Solutiion
The phy. ical addres i. 436 - 'I when the c ntent IP i. 2 1 - H
Phy. icaJ addres.. = C ntent o. data se ment re ·. ter x I H t ] P addres
There. re,
43 H = , 'ontent o data . e ment rec,ister x I
Then the ntent . data . eg,nent re 43 · =4 160 M
The c ntent data . egment re i. te _

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

 ADDRESSING MO DES 1

••••••••••••••••••••••••••••

lmmediat,e Addressing.

Wn thi. m de o addre . in , the 8- bit r I -bit perand i. a part o the instruction. For example, OV .X
4, H. ]n thi . instructi n, the data 4 I can be I, aded t the .X re ister immediately: "ome , there. am-
ple .. are iven el, w:
0 · BX, 0 :1; load I H in BX re. i.ter
O · CX 4 , :i:-:1 ; t re 4 -0 H in , 'X fi . i. ter

Register Addr,essing

]n the 86 mic:r pr ces . r, me instruction. are perated n the eneral-purpose re · sters. ~ he data is in
the regj , ter ped fi ed ythe in. tructi n . The ., m1at r regj ter addressin. . 1s
urc:e
In thi . instructi n, the data I mm the sour-c:e re. i. ter can be ,c pied int thede. tination regj , ter. The 8-bit
re Lter. , H, , :1, ' ' L, C :1 DL, ,f and l -bit re isters X, BX, , 'X, ·.X )may be
used ., r thi. instructi n. ~ he nly re tricti n i. that both perand.J must be . the same len .th. r examp le,
0 L , BL; ' pie the value , BL int, AL
OV .X, BX; C pie. the content. BX int X

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

M.e,mory Addressing

.em ry addre in re.quire detem1inati, n , physical addre. s. The phy ical addre can he mputed fr, m
the c ntent o. se ment addres. and an e e.ctive addre. s. The . egment addre . • identi. 1,es the start in I cation
o the . ,egment in the mem ry ande ective addres. re'presents the , . ,et , . the , perand from the be ·,min
I 1

, · this e ment , mem ry. The 2 -bite .. ective addres can be made up
1
base, index and di placement.
The hru ic . , mmla or the 16..:bit effective addre. - ) and the 2 -bit ph sical addr s P ) i. iven bel ~v:
1 • -bit = Bas,e :Index
t t , isplac.ement
2:0-bit IP = Segment :x 10 I Base I !Index I Dii. placement

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

Branch Addr,essing

The ha. ic types branch addre in a.re . h wn in Fi. _ .8. The imra. e'i!lnem mode i. used t trans.er the
o ntr I t a de. tinati n that lies in the rune segment where the c ntr I tran. er instructi n itsel1 re ide. _ ]n
the inte1. egmel1t m de, addres i .. used t tram er the c ntr I t a dest inat i, n that Iie s in a di e rent ..e ment.
I , r the ranch-co ntr I tran er in ..tructi ns the add.res. in mode. depend upon whether the de tinati n
location i. within the same . e_ ment, r in a different ne. U depenru up n the method o . pm . i no the destina-
ti n addre st the proce .. - r. ·n1ere are tw type. , branch control instructi, ns: inters,egment and intra.se -
ment addres in mode. _
Durin_.executi n pro ram in. truction, when the I cation t which the contr It be tran . erred Iie. in a
di .. erent ..,e ment ther than the current ne, them de is called inter. egment mode. ] the destinati n I cati n
lie in the rune se ment the mode i called i11tra. egment mode .

Ca ntiro l Transfer lnstmctlo ns

l ntiraseg· ent lnterseg ent

Co ntro l Trans er Inst ructions Co ntro l Transfer nst ru,ctlons

lnuaseg ment Inte rsegment

rnre ct. Ind irect

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

 Example

Load 16-bit data '04,.. . . in th .. r gist ·r and anoth r 16 -bit drt':I 6,.. 4 1n
th · B . r gist r.

: \>D BUG
10.00
l 7D : l 000 tIO , '04,....; L ,a d 16-bit data '04,...H in th r gist r
l D : l 00"" MOV B ,6 4 ; Load 16-bit data 6 4 in B . r g1s ·r
17D . : l 006 LT
17D : 1007

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 1

 Example

P'r,ogr,a1
m1for Addition o,f 'Two 8-Bit, Numbe1rs with a 16-Bi't Sum

Alg,orithm
START
1. tor · first dat· in RJ gist r L.
tore s " ·ond dat· in R "gis r BL.
dd th ·ont nts of · L and BL. Load first 8-bit data
in Reg ister AL
4. -" flrg \ _ill b s t, if r suit is mor than ' bits

Load seoon d 8-b it

in Reg ister BL
- 1000
1· D : 1OHO 110V L .; oad _ ___in AL r gist r
Add the content of
17D : 100 -11ov BL ' '.; Loc:d ' I In Lr gist r AL and BL
17D : 1004 DD L, BL; dd 'On _ nt fBL to L
Th e resu lt is present in AL
: 100 If the resu It is ,greater than
_- 1000 1006 8-bits, CY flag will be set
17D : 1000 BO F _ MO ,F .
17D : 100 B, _ ' ' 10~ BL, ' ' End
17D : 1004 00 ADD L,BL
17D : 1006 4 I=lL

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 2

 Pr,ogr,am1for Subtraction ,of Two 16-Bit
Nu1 mbers

Alg,orithm
1 . L ad first num b r in R gist r START

Load s ·ond numb r in R gist r B

ubtr .·t B . fr m Load fi rst 16-bit data
in Reg ister A)(

- l 000
17D : l OOOMO .. FF · 16 bit data in Load seoond 16-bit
in Regist er BX
17D 66 6 · 16 bit d· ta in B
'
170 : 1006 B .,B . .; ont nts of B i: subtr.-, ·t d fr m Subt ract BX fro m A)(
170 : 100'
170 : 1009 T he result is present in AX
-U 1000 100'
170 : 1000 B'
End
170 : 1003 BB6666
170 : 1006 '9 '
170 : 100 4 I_

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 3

 P'r,ogram for 2's Comp,lement of a 1,6-Bit Number

Algorithm
1. ,t or th ~ 16-bit numb r in R gist r
START
' D ·t rmin ·
,...
, tor h o's ·ompl m n of in B
Load first 16-bit data
in Register AX
- 1000
17D : l000MO .. ' 44 .; 16-bi data in Find 2's complement of AX
17D : 100,... G .; · 's · .mp,l ·m nt of 16-bit data sing NEG AX instruction
17D : 100'" MOV B .; R sult is st r- d in B
11

17D : 1007 HL Store th e result in BX

17D : 100
_- 1000 1007
End
17D : 1000B' 44 '2 MOV
1 : 1003 G
:100 ' 9,
4

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 4

 m to, Multiply Two 16-Bit INlumbers
Pr,ogr,a1

Algorithm START
1 . Load first numb r in R .,;ist r
· s · nd data in R gist r B
Load multiplicand, i .e., first 16-bit
·ont nts o · b B . number in Regist er AX

- 1000 Load multiplier, i. e., second 16-bit

number in Register BX
l" D : l 000 - tlO 1111 .; 16-bit mul ipli 'tnd in
17D : 100"' MO B . ' ' ' .; 16-bi mul ipli ·and in
Multiply th e content of AX by BX
l" D : l 006 filL B . · iiultipl ont nts of .. b B using M UL instru ction
1 D : 100 HL
17D : 1009 The result is s.t,o red in DX and AX
registers
-U 1000 100
l"D 1000 B' 1 1 1 1 .. ,1111
End
17D 100"' BB MO '
,.,
17D 1006 7 .) MUL B
1 D :100' 14 HL

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 5

 P'r ,ogra1
m1to, Divide, Two 1,6,-Bit Numbers

Algorithm
1 . Load first numb,•r in R gist r START
' t . r · th s · nd data in R ·gist r
3 . Di id ·ont ·nt of b and r suit in R ·gist rs andD . Load dividend, i.e., first 16~bit.
number in Register AX

Load divisor i.e., secolild 16-bit

- 1000 number in Register BX
170 : lOOOMO .; 16-bit di id nd in
17D : 100~ MOV .; 16-bit di isor in Divid e the content. of AX by BX
using DIV instructi olil
170 : 100 ·' DI ' 1 .; Di id , · nt nts f
17D : 100' HLI
Th e result is stored ilil DX and AX
17D : 1009 reg isters, Quotient in AX and
-U 1000 100 Remainder in DX
170 :1000 B MO !
17D :100 B9 ' MO ! End
l D : 1006 " 1 D filV
l D :100 HL

Dr. Anwar Sadat, Electronics Engineering Department, A M U Aligarh. 6