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Final Exam - VLSI - Spring - 2021

This document contains the instructions for a final exam for a course on VLSI Design. It includes 4 questions to answer. Question 1 has multiple choice questions about VLSI topics. Question 2 involves designing digital logic blocks including an FPGA-based frequency divider and a digital block with reset and clock signals. Question 3 involves creating a hierarchical block diagram connecting the designs from Question 2. Question 4 covers CMOS gates, transistor-level schematics, and manufacturing process layers. The exam is 3 hours long and covers VLSI design topics through practical circuit design exercises and theoretical questions.

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omar mostafa
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
52 views

Final Exam - VLSI - Spring - 2021

This document contains the instructions for a final exam for a course on VLSI Design. It includes 4 questions to answer. Question 1 has multiple choice questions about VLSI topics. Question 2 involves designing digital logic blocks including an FPGA-based frequency divider and a digital block with reset and clock signals. Question 3 involves creating a hierarchical block diagram connecting the designs from Question 2. Question 4 covers CMOS gates, transistor-level schematics, and manufacturing process layers. The exam is 3 hours long and covers VLSI design topics through practical circuit design exercises and theoretical questions.

Uploaded by

omar mostafa
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

October University for Modern Sciences and Arts (MSA)

October University for Modern Sciences & Arts

Final Exam

Faculty Engineering
Department Electrical Communication and Electronics
Module Code ECE 445/ ECE 561
Module Title VLSI Design
Semester Spring 2021
Time Allowed 3 hours
Total Mark 60
No. of Pages Four (including the cover page)
Material provided None
Equipment permitted Non Programmable Calculator
Additional Instructions All Answers must be in English otherwise it will not be
considered.

No books, paper or electronic devices are permitted to be brought into the


examination room other than those specified above.

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October University for Modern Sciences and Arts (MSA)

Faculty of Engineering
Module Code: ECE 445/ ECE 561
Module Title: VLSI Design
Semester: Spring 2021
Answer the following questions (Four Questions):
Question 1: (13 Marks)
A Choose the Correct Answer
1. ____________ of CMOS transistors allows for their very high integration
1 pts
density in VLSI circuits.
(a) Low power (b) Small Size (c) High Performance (d) All of them
2. The number of gates in a MSI integration level are _______
(a) 100 (b) 1000 (c) >10,000 (d) None of them
1 pts
3. Scaling down of the transistor dimensions in VLSI circuits _________
(a) Increases the packaging density (b) Decreases the switching speed
(c) Increases the power consumption (d) All of them 1 pts
4. Assume that a and y are 8-bit signals with the std_logic_vector (7 downto
0) data type. If the signals are interpreted as signed numbers, the following
assignment statement performs a / 8, ________ 1 pts
(a) y <= “000” & a(7 downto 3); (b) y <= a7&a7&a7&a(7 downto 3);
(c) y <= a(4 downto 0) & “000”; (d) y <= a7&a7&a(7 downto 2);
5. To design high-volume products such as memory chips, and high-
performance microprocessors, the preferred design style is ______ 1 pts
(a) ASIC (b) FPGA (c) PAL (d) CPLD
6. To add two 3-bits values from ports A and B and send to the result to
external 5-bits port ALU_Out, which VHDL statement is true:______
(b) ALU_Out <= '0' & (A + B); (b) ALU_Out <= A + B; 1 pts
(c) ALU_Out <= ('00'&A) + B; (d) ALU_Out <= ('0'&A) + B;
7. One of the simple programmable logic devices that has a fixed AND plane
and a programmable OR plane is ______
(d) PLA (b) ROM (c) PAL (d) RAM 1 pts
B Design an FPGA-Based low power frequency divider shown in Fig. 1. The value
of the output frequency “CDIV” depends on the selection signal “SEL” as 6 pts
described in Table 1. If we simulate and test the VHDL code of your design Draw
the graphs to show the output DIV with all combination of SEL. Hint. Use
variable declarations.

Table 1
SEL CDIV
1 CLK/3
0 CLK/4 Fig. 1

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October University for Modern Sciences and Arts (MSA)

Question 2: (21 Marks)


A Design a positive edge triggered digital block with an active low asynchronous 9 pts
reset signal, as depicted in Fig. 2. The digital block satisfies the truth table listed in
the Table 2. The width of A and B is 5 bits. The resolution of the fractional
numbers is 3 bits. Inputs and outputs can represent +ve and –ve values (signed
system).
Table 2
RST CLK Op Operation
0 X XX Clear Y Output
1 ↑ 00 5B
1 ↑ 01 0.25A
1 ↑ 10 MIN(A,B)
1 ↑ 11 A+3B Fig. 2
1 ↑ Others Unknown

B Design a simple positive edge triggered FIFO with synchronous active high reset, 6 pts
which consists of 4×N-bit registers. Initialize N by 8.

Fig. 3

C Design an FPGA based asynchronous positive edge triggered 4-tab FIR filter, 6 pts
shown in Figure 4. The relation between the filter input “D” and the filter output
“F”, in Z domain, is given by the following function:
0.25 0.25
The fractional part of the filter output is represented with 7 bits.
Fig. 4

Question 3: (11 Marks)


Design the hierarchical block diagram shown in Fig. 5 that is a part of an FPGA based VLSI
system. The hierarchy consists of the Digital block, and the FIFO memory of Problems 2.A,
and 2.B, respectively. The digital block output is connected to the FIFO input. The TOP level
output Top_Result is 10-bits with the F presenting the rightmost 8-bits. The master clock
frequency at which the FPGAs chip works is 120 MHz and it is connected to the input
“MCLK”. Use the frequency divider of Problem 1.B to generate the required clocks of the
Digital block and the FIFO memory.

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October University for Modern Sciences and Arts (MSA)

Question 4: (15 Marks)


A Consider the design of a CMOS compound gate computing
.
Fig. 5
i Sketch a transistor-level schematic. 4 pts
ii Sketch a colored stick diagram. 4 pts
iii How many transistors are required? Is it odd or even number and Why? 2 pts
B Draw a cross section view indicating different layers of an inverter in the 3 pts
manufacturing process.
C What is the logic function equivalent to the stick diagram shown in Figure? 2 pts

The End, best wishes, Dr. Hatem Zakaria

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