Review of M0SFET Operation and Fabri cation

2-42 ~

.....
.... .
• Digi tal VLSI (MU) Review of MOSFET Operation and Fa b

.......
Digital \Tl.SI (MU)

.
·
.. . . .~ ·
: Field oxide(S1O2)

Fteld oxide

n - type Si • substrate Si • substrate

(n • type)

(i)

...
S102
Field oxide

SI • substrate
(n -type)
Si • substrate
(n -type)

(ii)
Polysillcon Field oxide
,--..,....-,-...,.,..,....,,
. . ..... ... . . ..

Field oxide
Si • substrate
(n -type)

Si - substrate (vii)
(n. type)
Metal oontac:1

Field oxide
Field oxide

Si • substrate
(n -type)
Si • substrate
(n • type)

(viii)
Fig. 2_22_1 : pMOS transistor fabrication process
{iv)

_ td_.._·
.1_c_on
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _F_:ig:_._2_.2_2_ -----------------=
·!~.~
 _ Review ofMOSFET Operation and Fabr1cat1o~
2 44
2-45

[:::::.::::;;;;;:,:,;;;;;;;;;~~-r-- 3
Si N•
Review ofMOSFET Operation and Pabricati

Fleld
oxide Field
oxide
. fi Id oxide is grown selectively in
In LOCOS technique e : . Jete wafer bird'e
. beak
. eas instead of growing it over comp
certain ar h. th e selective area for active Si - substrate Si - substrate
Si - 9llbeln,te
and then selectively etc.. ;ggrowth is done by shielding

r:,-•eld
region. The seJecnve ox1 e . .
the active areas with silicon nitride (S13N4) during (x)
(ii) Active area Active area
oxidation, which essentially in hibits the oxide growth.
Photoresa,
1. This oxide layer is grown on the silicon wa fe r.
Si3N4 . . . . .. . ..
•
'
oxide

2. Si3N4 is deposited and patterned to defi ne the active

p•
areas. This Si02 under silicon nitride is used to
protect silicon surface from stress caused by nitride
Si - substrate Si - substrate
during the subsequent processing steps.
Si • substrate
3. The exposed areas of silicon surface will eventually (xi)
form the isolation region. These exposed regions are Fig. 2.23.1 : LOCOS technique

doped with a p-type impurity to create the channel (vii)

(iii) 2.24 Complementary MOS (CMOS)
stop implants that surround the transistors.

4. Thick field oxide is grown next in the areas that are l l l l l l l l l l l 1-uvugN
L._j_ _ _L,__ __._ _ _ __J-Malk - Complementa ry MOS technology utilizes both NMOS
not covered with Si 3N4• Field oxide extends in both and PMOS transistor in the construction of circuits.
the vertical direction since thermal oxidation process _____ _______,.,.,,,.....,.,r"" Photoresist
Although CMOS circuits are comparatively more
also consumes some of the silicon. Also, the field S'3N4 Si - substrate difficult to fabricate than NMOS transistor, the
oxide extends littl e in lateral direction under the complementa ry transistors makes it possible to offer
SIOi
nitri de layer resulting in what is called as birds beak. various powerful circuits design posslbllitles.
It is named so because of the shape of the oxide - Currently CMOS is the dominant integrated drcuit
extension under the gate oxide mask. The oxide (viii) technology. CMOS technology has almost su\)planted
extension results in reduction of th e active area. Si - substrate
bipolar technology. Fig. 2.24.1 shows a cross section

5. The silicon nitride and thin oxide layer are etched of a CMOS chip.

finally, resulting in active areas surrounded by - Since the substrate requirement for the
(iv)
partially recessed field oxi de . complementa ry transistors is different, well
160lallon regions
technology is adopted for the construction of CMOS
LOCOS process is a popular isolation technique.
based circuits. As shown in the Fig. 2.24.1 the NMOS
.
-- ..........................
SI0: : 1"~... ....,.............;...:.;_;,;.,;.;.;_:..;.;_;;;...:.;_:.:.:.,:~
transistor is implemented directly In the P-type
Si - substrate
substrate while the PMOS transistor Is fabricated in a
specially created n type region, known as an n-weil.
Si - substrate
The two transistors are isolated from each other by a
(ix)
thick oxide also known as field oxide. Silicon dioxide
Si • substrate Fig. 2.23.l Contd .. (Si0 2) is acting as an insulator isolating the two

(i) devices.

Fig. 2.23.lContd ...

(v)

____ ____ ____ ____!____ _~Fi!g.~2~.2 ~3-~lC~o~n t~d_:···~-~

 Review of MU~ ~to I up e 1dl1 u 11 d 11u rdoncation
2-46
_ Using an n-plus (n•) mask, n• regions for source and • Digital VLSI {'-1U2
11"18 o,ri<1o(SI02l 6 2-47
drain ofn MOSFET transistors are implanted Into the
substrate. The next step usually uses the complement n-weu
Si 3 N 4
of the n• mask, although an extra mask is normally
t UU~ not needed. The thin oxide areas where n• region Is
Si • substrate
not present indicates that its a p• diffusion or p.
(P·type)
~ EpllaXllllllly.r active. p-regions are defined in the n-well.
7. A )ayer of insulating silicon dioxide (SiOz) Is Si - substrate
p -_ ___... (Ill)
deposited over the entire wafer surface using CV!) (P·type)
The contacts are defined and etched away to expos~ S i02
F",g. 2.24.l : cross section of• CMOS integrated circuit. the silicon or polysilicon contact windows. ' n-well •
(viii)
s. Metallization is carried out to deposit metal over the
2.25 CMOS n-well Process
entire chip surface. Si. substrate
(P·type)
The cross section of the finished n-well process Is
1 1 i:h94?11N•M4➔h·I
Q. How the CMOS n-wen process is carried out? shown in Fig. 2.25.1. In an n-well process, the P·type
substrate is normally connected to the negative supply
IM 1 i•NL►iM@U Si:3N4
CVss)- This is called an Yss substrate contact On the other 5102
Si • substrate
1. The n-well CMOS process starts with a lightly doped hand, the well has to be connected to the positive supply (P- type)
p-type substrate. An oxide layer is grown over the (V ) through V00 substrate (well) contact Substrate
00
entire surface of the substrate. connections are formed by placing n• region in the n-wel) Si • substrate
2. n-well region is defined using photolithography (V00 contact) and p• in the p-type substrate CVss contacti (P·type) (ix)
process_Dopants are implanted through this window The V00 and V55 contacts are shown in the Fig. 2.25.1.
in the oxide creating an n-well. n-well can also be (v)
produced using diffusion or deposition. Diffusion .. ~ , : : . :.·:. ·:. :.·:. ·.·.·· ·. :-:-:-: -·-:-:-:-_».'18102 l l l l l l l l l l l l- UV light
process occurs both in lateral and longitudinal Mask
directions, the deeper the diffusion is the more it
spreads laterally_This lateral spread affects bow near ~Photoras"'t
Si• substrate
to other wells can be placed. Ion implantation doesn't (P·type)
r···..··.··."·•..··.· .·.··.·, . ·.. ... ... .£ ::·
P - substrate
spread laterally hence for dosely spaced structures newetl
ion implantation is used that produces shallow wells.
(x)
3. Once a-well is created, active areas of transistors are
SI • substrate Si02
defined and ion implantation is done to form p·type (I) (P•type)
or n-type diffusions for transistors source and drain
regions.
_____.,,.-n;::
.. . S~N 4
4. A thick field oxide is then grown in the areas where -~ .( -_,_-_,r -~ .]·.·:
the Si3N, layer is absent The oxide grows in both : n-weH ,2_
,, ..,-.~, ·;
directions vertically and laterally under the Si0 2 / Si • substrate
(P-type)
Si3N, layers resulting in birds beak.
P • aub91rate
5. Threshold-voltage adjustment of n-transistors and p·
transistors might be then performed using a p-type /

r (xi)
SI• substrate
n-type well photoresist mask. This is followed by the
L (ii) (P•type) Fig. 2.25.lContd ...
deposition of polysilicon layer using Chemical Vapor
Fig. 2.25.lContd ...
Deposition (CVD) and patterned by etching process. (vii)
.~ ·~~.~
 Pe l f - ~
---:1 10..----- ~~ u,-jd e)
~~

Si - ~
{P - t-. (P8)
(xvll

__c- MaSk
p otysitie:Ofl
Si02
Si - subs trate
( P-typ e)

(xvi)

Si - subStra1B
( P - type)

(xiii)

Si - subs trate
(P-ty pe)

(xviii)

Si - substrate Field oxide

(P-typ e)
Si02

(xiv)

SI - subs trate
(P-ty pe)

(xix)

Si - substrate Fig. 2.25. 1: Proc ess flow for

n-we ll CMOS
(P·lype)
Summary of masks used for n-we
ll proc ess: 4) Mask 4 : n• mask (n-plus)
(xv) 1) Mask 1 : Defines n-well area. - It defines area
be implanted n•.
Fig. 2.25. lCon td ... 2) Mask 2 : is called active
mask. It defines the active
area, that is, area for trans istor 5) Mask S : p• mask (p-plus)
- It defines area
.
be implanted p•.
3) Mask 3 : Pollysilicon mask 6) Mask 6 : Contact mask - It
- It defines the gates . defines the cont:
7) Mask 7 : Metal mask - It defin
es the inter rc
i
 Review of MOSFET Operation and Fabrication
2-50
The cross section of the finished n-well process is • Digital VLSI ( MU)
• Digita l VLSI (M U) 2-51
shown in Fig. 2.26.l. In a p-well process, the n•type Review of MOSFET Operation and Fabrication
2.26 CMOS p-well process substrate is normally connected to the positive supp]y
·th a lightly doped CVool • on the other hand, the well has to be connected to P-well
1. The p-well CMOS process starts W1 grown over the the negative supply (Vss) . The Yoo and Yss contacts are
n-type substrate. An o~ide layer JS

entire surface of the substrate. shown in the Fig. 2.26.1.

2 p-well region is defined using photolithography Si· substrate
(N•lype)
. process. Dopants are implanted through this window
in the oxide creating an p-well. p-well can also be
produced using diffusion or deposition. Diffusion (v) Si · substrate
(N-type)
process occurs both in lateral and longitudinal
directions, the deeper the diffusion is the more it
n - substrate
11111111111 1-UVlight (ix)
spreads laterally. Th is lateral spread affects how near -Maak
to other wells can be placed. Ion implantation doesn't
(i}
spread laterally hence for closely spaced structures
----♦--P · Wei
ion implantation is used that produces shallow wells. mask
3. Once p-well is created, active areas of transistors are
defined and ion implantation is done to form p-type p-weU
Si - substrate
or n-type diffusions for transistors source and drain (N • lype)
regions.
n - substrate Si - substrate
4. A thick field oxide is then grown in the areas where (x)
(N-type)
the Si3 N4 layer is absent The oxide grows in both
directions vertically and laterally under the Si02 / (vi)
Si 3 N4 layers resulting in birds beak (ii)

5. Threshold-voltage adjustment of n-transistors and p-

p-well
transistors might be then performed using a p-type /
n-type well photoresist mask. This is followed by the
SI · substrate
deposition of polysilicon layer using Chemical Vapor (N • type)
Si• substrate
Deposition (CVD) and patterned by etching process. (N-type)
6. Using an p-plu s (p') mask, p· regions for source and Si-substrate (xi}
(N-type)
drain of n MOSFET transistors are implanted into the
substrate. (iii)
(vii)
The next step usually uses the complement of the p+ Si02
mask, although an extra mask is normally not needed.
:"e thin oxide areas where p• region is not present p-well

md1cates that its an· diffusion or n- active. n-regions

are defined in the p-well. Si -substrate
Si· substrate (N. type)
7. A lay_e r of insulating Silicon Dioxide (Si02) is (N-lype)
deposited over the entire wafer surface using CVD. SI • substrate
The contacts are defined and etched away to expose (N-type) (xii)
(iv) Fig. 2.26.1
the s1hcon or polysilicon contact windows.
(viii}
8. Metallization is carried out to d . Fig. 3.26.lContd ...
entire chip surface. epos1t metal over the Fig. 2.26.1 contd ..
 ~
2-52

rM•sk . . Digital VLSI (MU)

The processes involved are as follows :

2-53 .
Review of MOSFET Operation and Fabrication
poly9ilic0n

SI02 1) Tub formation

2) Thin oxide construction
Si. subslra.te
3) Source drain implantation.
(N-type) 4) Contact cuts and metallization.

(xviii) Advantages :
51 . s,bstrate
(N - type)
1) Doping control is easier.
Aeldoxlde
(xiii) SI02 Z) Possible to preserve performance of n-transistor without compromising the p-transistors.
.-p• mask
G G
oxide
layer oxide
SI- substrate layer
(N -type)

(xix)
Si. substrate
Fig. 2 _26_1 : Process flow for p-well CMOS
(N-type) Epitaxial layer
p-well process are preferred in circumstances where
(xiv) the characteristics of the NMOS and PMOS transistors n - substrate
are required to be more balanced than that achievable in
an n-well process, because the p-well process has better Fig. 2.27.1: Cross section of CMOS fabricated using twin tub process
PMOS than an n-well process. CMOS using twin tub process :
7. A thin layer of SiO 2 is grown and patterned to locate
Summary of masks used for p-well process : This method avoids latch up for CMOS fabrication.
the gates for nMOs and pMOS. Also unwanted thick
1) Mask 1: Defines p-well area. Here the substrate over which CMOS is to be fabricated
silicon dioxide is removed. Refer Fig. 2.27.Z(g).
Si -substrate can be either of p-type or n-type silicon.
(N . type) 2) Mask 2 : Active mask - It defines the area for
1. Let us use n-type silicon substrate. The resistivity of 8. The polysilicon layer is deposited and patterns using
transistors. a mask. It is kept where over gate is required.. Refer
(xv) the material should be high. Higher the resistivity for
3) Mask 3 : Photoresist mask - It is used for threshold Fig. 2.27.Z(h).
the substrates, lesser is the current through the
Insulating
Si02 voltage adjusment substrate. Refer Fig. 2.27.2(a). 9. P-well is covered with a photoresist mask and P-type
4) Mask 4 : Polysilicon mask- It defines the gates. diffusion in done to n-well to form sources and drain
2. On this silicon substrate, n• layer Is grown epitaxially
of p-mos transistor. Refer Fig. 2.27 .2(i).
5) Mask 5: n+ mask(n-plus) - It defines areas that are to Refer Fig. 2.27.2(b).
be implanted n+. 10. n-well is covered with phororesist mask and n-type
Si-11Jb9lnlle
3. Silicon substrate is subjected to oxidation and SiO
2
(N - type)
diffusion is done to p-well to create source and drain
6) Mask 6 : p+ mask(p-plus) - It defines areas that are to layer is formed. Refer Fig. 2.27.2(c).
regions of nMOS transistor. Refer Fig. 2.27 .20).
be implanted p+. 4. SiO 2 layer is etched using mask and two windows are
(xvi) 11. The silicon wafer obtained in the previous step is
Insulating 7) Mask 7 : Contact mask - It defines the contact cut formed, one for n-well and another for p-well. Refer
again subjected to oxidation process and a thick layer
Si02 Fig. 2.27.2(d) .
of SiO 2 is formed for isolation. Also thin SiO 2 layer is
_2_.2_7_ T
_w
_ in_T
_u
_b_ P_ro_c_e_s_s _ _ ____. - 5. First window is covered using a photoresist mask and removed or etched out to expose source, drain etc.
p-type impurity is diffused to form a p-well. Refer Fig.

I
Refer Fig. 2.27.2(k).
This process starts with a substrate of high resiStlvitY 2.27.2(e).
. are then 12. The wafer is subjected to aluminium metal. The
Si - substrate n-type material. Both n and p type well regi~ns . hdY
(N-type) 6. Now the second window is covered with a metal layer is deposited all over the wafer surface
created. The substrate is then covered with a hg .
photoresist mask and n-type impurity is diffused to and removed using a mask from where there contact
doped (epitaxial) layer which has low resistivity aud th15
(xvii) give resi ton-well. Refer Fig. 2.27.2(f). cuts are not required. Refer Fig. 2.27.2(\).
reduces the latch-up problems considerably. ~

'I)!~~
 • Digital VLSI (MU) 2-55
Review of MOSFET Operation and Fabrication

n + d lffuelon

1111 .--
photoreelst mask

n - type SI · substrate

n • type smoon - substrate

(b) (f)

Thin oxide

-----:7r=~~-·
Thin oxide
(Si0 2 ) (Si02)

C
1- - - - St0 2

[ •·-·--- j (c)
Si0 2 Epitaxial layer

n - type Slltoon - substrate

Epitaxial layer

(g)

n - type Si - substrate

(d)
S10 2
p + d iffusion
photoresist mask
~
!! !1 Epitaxial layer

.....
.. SiO 2 1ayer

n - type Silicon - substrate

Epitaxial layer
(h)

Fig. 2.27.2 contd ..

n · type Sllloon - substrate

(e)
Fig. 2.27.2 contd ..
- - - - - - - - - - - -- -~
· ~~. ,,,,,,,
 Review of MOSFET Operation and Fabrication
2- 56

--
•
r- mask Digital VLSI (MU)

Summary of masks used for Twin Tub Process.

2-57
Review of MOSFET Operation and Fabrication

1) Mask 1: Mask to define well area. - The sequence of processing steps to achieve this is as
SI02
!allows. At first a very thin silicon oxide layer (thinox)
2) Mask 2 : To have p• diffusion, to have p-well. 1s grown on the surface of the wafer. Then a layer
3) Mask 3 : To have n• diffusion, to have n-well. of silicon nitride is deposited which act as an oxide
Epitaxial layer barrier.
4) Mask 4 : To have thinox in gate area.
- The wafer is subjected to photolithography process in
5) Mask 5 : To have polysilicon.
order to transfer the required pattern into the nitride
n _type Silicon _ substrate
6) Mask 6 : To have p• diffusion into n-well to form which defines the active areas for the oxidation process.'
source drain.
(i} - The thick oxide layer (field oxide) is now grown, the
n _type diffusion 7) Mask 7 : To have n• diffusion into p-well to form presence of nitride prevent oxidation of silicon in
mask

~ 1111 source and drain.

8) Mask 8 : To have Si0 2 layer and patterning it Remove
those areas. Since the oxide is grown on the selected
areas that are not blocked by nitride this process is
named as local oxidation. Finally the nitride layer is
it from the area where contact cut is required. etched away.
9) Mask 9 : To have contact cuts through metallizatio n.
- The advantages of LOCOS fabrication are the simple
Epttaxlal layer
Advantage : process flow and the high oxide quality, because the
whole LOCOS structure is thermally grown.
It avoids latch up, since parasitic transistor is not
likely to be formed. - The main drawback of this technique is the so-called
n _ type Sllloon - subStrate
bird's beak effect and the surface area which is lost
Disadvanta ges :
due to this encroachm ent
(j) 1) Two tubs are to be formed. Therefore the numbers of
Thin oxide
thick SI02 masks used are more. Thus the process is more
expensive.
2) An epitaxial layer is to be formed which is an
expensive process. SiHcon substrate

Epttaxlal layer 2.28 Device Isolation

Th8fflllll oxidation

n - type Slioon - substrate i

Q. What a~e t~e techniq~~s of device isolation?

(k)
(a) Silicon nitride patterned
,,,...1,1..■
.. -•--"'~i
V 10 metal
- There are several isolation techniques available for
electrical isolation of adjacent devices on the
integrated circuits. LOCOS, shallow trench and
metal junction isolation are discussed in this section.
LOCOS (LOCOS Isolation technique) : LOCOS is a
commonly used isolation technique in MOS !C's
Nitride removal
(explained in Section 2.25) . Here a thick field oxide is
Epitaxial layer i
grown between the adjacent devices that would offer
very high resistance between these devices th ereby (b) Thermal oxide growth
n - type Silioon - substrate
providing electrical isolation between them. Fig. 2.28.lcont ...
(l)
Fig. 2.27.2 : Twin tub process flow
 _ Review ofMOSFET Operation and Fabrication
2 58 • Digital VLSI (MU) 2 59 eVJew ofMOSFET Operation and Fabrication
- Junction Isolation : p•n junc~on i~ol~tion scheme is
Table 2.30.1 : (a) 1 to 6 Encoding for single metal 2.30.1 nMOS Circuit Stick Diagram
co mmonly used in bipolar IC~- T~ts _,s_based on the
nMOSprocess
fact that reversed biased jun_cno~ mh1_b1t current flow
Oxid• (b) 1 to 11 Encoding for double metal CMOS Normally drawing of stick diagram follows the
and thus will result in electrical isolation. For e.g. n-p.
P-well process following steps :
n transistor is surrounded by p-type material, the
1. Draw two parallel metal lines (blue in colour) for V 0 0
reversed biased p-n junction formed between n Layer Stick encoding Colour code and ground (GND) rails .The required circuit
regions and surrounding p region provides isolation. elements are placed in the space that is kept between
(c) Removal of silicon nitride
r----1 the rails for the implementation of circuit
F-.g. 2.28.1 : LOCOS process . 1. a-diffusion Green
Si02
. . n . The alternate isolanon 2. The thinox/diffusion (green) paths may be drawn
Shallow trench ,solano . . r----1 between the rails.
technique commonly used today m 2. p-diffusion Yellow
3. Polysilicon (red) crosses diffusion (green) wherever
. is trench isolation. This is the preferred transistors are required.
MOS _,cs . for the submicron technology, r----1
3. Polysilicon Red
isola□on technique . bird's beak shape 4. Width of the polysilicon defines the channel length L
because it completely avoids the and the width of the diffusion defines the width of the
characteristic.
r----1 Blue
P-typeSi 4. Metall MOSFET.
- In this technique a deep narrow trench is etched into 4. Use implant (yellow) for depletion mode transistors.
the silico n substrate and is filled with silicon dt0x1de.
Trenches are filled using CVD so it does not consume
s. Contact cut . Black 5. Write L : W ratio for each transistor (important for
nMOS circuits).
underlying silicon. Thus it allows the transistors _to be
packed more closely and increases the chip density.
Isolation p-n Junction

fig. 2.28.3 : Junction isolation

6. Burried . Brown Fig.3.18.1 shows the stick diagram of nMOS inverter,
contact 2-input nMOS NANO gate and two-input nMOS NOR gate
- The trench isolation process starts in the same way
getes.
as the LOCOS process. Unlike LOCOS a shallow trench 2.29 Layout Introduction
is etched into the silicon substrate (Fig. 2.28.2). The
................
7. Implant Yellow
2.30.2 CMOS Stick Diagram :
oxide layer is also underetched and a thermal oxide - We have learnt that MOS circuits are formed on four
in the trench is grown (called liner oxide) as shown in - CMOS circuits uses both pMOS and nMOS transistors.
basic layers : a-diffusion, p-diffusion, polysilicon and 8. V00 and Yss X Black
Fig. 2.28.2. They are separated in the stick diagram by the
metal; that are isolated from each other by contact demarcation lines.
- The thermal oxidation process is stopped after the silicondioxide layers. Whenever polysilicon crosses
formation of a thin oxide layer, and the rest of the - All the pMOS devices are placed above the demarcation
diffusion, a transistor is formed. line while the nMOS devices are placed below the
trench is filled with CVD (Fig. 2.28.2). Finally the 9. P-well Demarcation line Brown
- A nMOS transistor is formed if it in n-diffusion and demarcation line and are located in the P-well. Yellow
excessive (deposited) oxide is removed with
........................ colour in CMOS design is used for p-diffusion.
chem ical mechanical planarization and silicon nitride polysilicon layer crossing each other else a pMOS Is
is also removed. - The polysilicon line can cross the demarcation line
formed if p-diffusion crosses polysilicon layer. Layers
while the diffusion paths must not cross the
may be joined together forming contacts. P-well edge is demarcation line . The a-diffusion and p-diffusion
wires must not join. 'X' must be placed on V 00 and Yss
shown
2.30 Stick Diagram rails to represent the substrate and P-well connection
as a demarcation respectively.
p - wall
Shallow tmndl
- Stick diagrams convey both topology and layer line Stick diagram construction :
isolation information of a actual circuit through the use of
1. Draw V0 0 and Vss rails in parallel in metal (blue).
colour code. In nMOS design, usually green is used for 10. Via Black
N • substrate
Deep trench
a-diffusion, red for polysilicon ; blue for metal, yelloll' 2. Draw a demarcation line in between dividing the area
isolaUon
for pMOS and nMOS devices.
for implant, and black for contact. Dark blue or
11. Metal2 3. Place the nMOS transistors below this line and pMOS
Fig. 2.28.2 : Shallow trench isolation process - Table 2.30.l(a), (b) shown below, list of all the masl Purple transistors above this line.
required for nMOS and pMOS transistor fabrication-
 Review of MOSFET Operation and Fabricaua~

e~·+
2-60
VDo . . Digital VLSI (MU) 2-61
Voo
arcation Review ofMOSFET Operation and Fabtica
Digital VLSI (M U) v on
I silicon ca n cross th e dem Fi~. 2.30.1 ~hows circuit diagram and stick diagrams DO
4. Only metal and po y . here ever req uired by of a 4.1 nMOS inverter, 2-input nMOS NAND gate and 2-
F m the transistors w
line. . or diffusion an d polysilicon laye rs. I o input nMOS NOR gate.
crossing . . ~ rms a transistor. Yoo
Vo :
Polysilicon crossing d1ffus1on o I
s-cj
Finally make connecnons , I

{~v,
Vo
ther th e P-well nor the p mask I L A~

In sock diagra;r ;~en the snck diagram 15 translated i/p -:-w;;=+ A-j 1-s
appear They app F 2 30 2 shows th e sock diagram of Groulld
to a mask layout ig NANO aet and 2-mput CMOS NOR (b) 4:1 nMOS inverter
CMOSinverter, two input b (a) nMOS inverter circuit
(e) 2-input CMOS NOR gate circuit diagram
gate and the stick diagram of a complex gate. Yoo
nMOS stick diagram : ~--- __,

-=~_ . '.:~t.l .
(a) CMOS inverter circuit
VTC of depletion load inverter circuits like CMOS
~n
inverter VTC, vary with the driver to load ratio fip" .

µ.cox(n .

7
=
line ¥ Vo

·-·r-
~n
Where Vp Vo
1··--- ...
~P = o.en.
µ.C DemarcaUon line ' •••
_.,....__ ___,1_ _ Ground

Where, T is called aspect ratio of the transistor and Ground Ground (f) 2-input CMOS NOR gate
F"ig. 2.30.2 : Stick diagram
(c) 2 input NAND gate circuit (d) 2-input nMOS --!'1----M---G round
is defined as ratio of channel wi dth the channel length. Fig. 2.30.2 shows circuit diagram and stick diagrams
NANDgate (b) p-well CMOS inverter
We know that FIT resistance is inversely Fig. 2.30.1 of a CMOS inverter, 2-input NANO gate and a 2-input
proportional to ~ of the transistor. In other words NOR gate.
Voo Yoo
IV (i ).. 2.31 Design Rules
2i,u oc ( i )P ~ pull up
The design rules specify the minimum dimension that
Zpd oc (-'W=-) ~
n
pull down can be safely transferred to the semiconductor material.
In general, minimum device dimension is set by the
Z pu resolution of the patterning process. Design rules need
The ratio zpd is called inverter ratio R,,.,.
to be established when a new process is being created or
Fig. 2.30.l (a) shows circuit diagram and stick (c) 2-input CMOS NAND gate circuit diagram when a process is upgraded from one generation to the
diagram of nMOS inverter having inverter ratio of 4:1. (e) 2-input nMOS NOR gate circuit diagram next
Table 2.30.2
Design rules summary :
Manoclllome allck
encoding - Layout serves as an Interface between the circuit

Al_:::::::_~~:---'~~=00•
Oiftueion designer and process engineer. Layout must conform
the design rules.
ltne
Polysil100n

Metal
:---'---: B -- -1 - Design rules provide Guidelines for constructing
process masks
A: :B :-- ------- - Design Rules are constructed to ensure that design
Con1actCIJ1
TT
--!11-----i .--- Ground
Ground-!11------

(d) 2-lnput CMOS NAND gate

works even when small fabrication errors (within
some tolerance) occur.
Implant Fig. 2.30.2 contd ..
(f) 2-input nMOS NOR gate
... ,
•
Fig. 2.30.1 : Stick diagram
 Review ofMOSFET Operation and Fabrication
2-62
Intra layer design rule origins : • Digital VLSI (MU)
2-63
• Digital VLSI ~U) . ·mum dimensions (ex. widths) of objects on each Review of MOSFET Operation and Fabrication
Therefore, maximum misalignment of two features
Design 111les includes : Min 1 . . that object after fab . on different mask layer is 2t... The purpose of defining For a given process, A is set to a specific absolut al
)ayer to maintain.. -::=_~ - - - - - -- - and all design dimensions are conse uentl e v ue,
1) Dimensions oflayers en objects on the lambda properly is to make the design itself
Note : Minimum line width is set by the resolution the i~to absolute numbers. Typically, theqmini~u~slated
]ayer : relations betwe independent of both process and fabrication house
2) Intra - patterning process (photolithography) size of process is set to 2t... For example for a le~tu:
and to allow the design to be rescaled at a future
same layer relations between objects on process (that is process with minimum, dimens;o: of
Minimum spaces between objects (that ar~ not technology when the fabrication tolerances are
3) Inter - layer : shrunk. 1:2 µm pr?cess). A equals 0.6 µm (is minimum feature
related) on the same layer to ensure they Will not size on chip 1s always 2t..).
different layers be able to tolerate
are constr11cted to short after fab .
Design rules fab .cation errors such as 2.32 CMOS Design Rules

1) Maskmi~lj
some level of n

Table 2.32.1 : Encoding for double metal CMOS process

-0-n
Spacing between layer
IM•k layout enoodll'I
Monochrome Colorc:ode

Fig. 2.31.2 : Minimum spacing between two layers

n -diffusion
~
Inter layer design rule origins : p-<llffuslon
l<>>F><>>J .,
.....,_ _.,11
_ _·_i§. Yellow

2) Dust
rig. 1.31.l : Mask misalignment

3) Process parameters (e.g. Lateral diffusion)

4) Rough surfaces
Transistor rules - transistor formed by overlap of
active and poly layer
_ Contact and via rules
There are two kinds of design rules:
Metal1
-Elue
2.3l.1 Need of Design Rules r1.Micron rule 2. Lambda rule •
Polysllloon
~ - Aed

- Design rules are defined to yield workable and 2.31.1.1 Micron Rule
reliable !Cs. The rules are based on a particular
technology and detennine the minimum size and
spacing to all layers of the circuit geometry in an
Jn micron rule, the design rules like feature size and
minimum allowable feature separation are In term of
P·well
D .---,
t
I____ J
Bro'M'I
I (not shown In
Layout)

absolute dimensions in micrometers. Not shown In

attempt to maximize yield, perfonnance and P-e&leot
diagram
, Yellow
Scaling and porting designs between technologies
reliability. That is, when the design rules are followed
it helps in preventing unwanted short circuit among under these rules is more demanding and is relativefy
isolated features or avoids contacts from slipping easy using advanced CAD tools. Metal2 Oart<Blue
1111111111111111111 or Purple
outside the area to be contacted.
- For example, it is possible for thin line to break 2.31.1.2 Lambda Rule
during the fabrication process or afterwards
resulting in open circuit Also, if two lines are placed
Since the design rules tends to differ from compan!
Via
EE -
83 Black

to company or from process to process, therefori

too close to each other in the layout, they may form
porting of design is a challenging issue.
unwanted short circuit by merging during or after the Voo
One technique to address this issue is to use scala~
fabrication process. Aim of the design rule is to
achieve high overall yield and reliability of a circuit
-
design rules. This approach was made popular ~
0
Mead and Conway. It defines all rules as a functi ~
v00 orVss
contact ~(J
&k..
~ss

~
that is manufactured on the smallest possible silicon
area using a particular process. single parameter called lambda A and thus a~cal

~ ■
- The design rules are designed such that there is no linear and proportional scaling of all geom~ UJll Contact
Black
serious performance degradation under worst case constraints. Lambda specifies the maJCtl1I oP
misalignment and maximum edge movement of an alignment of a feature from its intended positi01I
y
- - - - - - - _ ! _________
feature. the wafer. _ ~
 Review ofMOSFET Operation and Fabrication

+=
Z-64
• Digital VLSI (MU)
• Digital VLSI (MU)
2-65
_ There are different layers available for implementation Review of MOSFET 0
f2 Minimum overla to peration and Fabri ca tion
of MOS transistor. Each of these layers are represented f3 M' . p any contact U
m1mum spacing 3.)..
uniquely eith er appl)~ng colour code or by using
G. Via 1
hatches for monochrome encoding.
- Table 2.3 2.1 shows representation of each layer in g1 Exact size 2.)..
monochrome and in colour coding. Polysilicon layer gz Minimum spacing 3.)..
transistor
is col oured in red in this book; while the diffusion and
g3 Minimum ov 1
metal layers are represented with green and blue M' . er ap by metall U
C. Poly g. M m1mum spac mg
· to contact
. 2.)..
colou r respectively. c Minimum width 2A
1 gs lmmum space t o poly or active
- A transisto r is fonned when polysilicon crosses edge 2A.
c Minimum spacing 2A
diffusion layer. Metal on the other hand can cross 2
polysilicon or diffusion layer without getting c Minimum gate extension 2A
3
connected. For achieving connection between metal c Minimum active extension to poly 3A.
and any other layer, speci al contacts are required 4
(Contact cut). CMOS design rules (n-well and p-well) Cs Minimum poly to active 1:>.. Meta

are listed below: D. Contact

A. n-weU, p-well d 1 Exact contact size z:>..
a, Minimum width 10), Ac1ive
d Minimum poly overlap
2 1.5:>..
a Minimum spacing (same potential) 6A
2 d 3 Minimum spacing z:>..
a, Minimum spacing (different potential) 9A..
d Minimum spacing to gate
4 z:>..

[}O {J Wells at Wells at

E. Contact
e, Exact contact size

e2 Minimum active overlap

z:>..
1.s:>..
same potential dlflerent potential
e3 Minimum spacing z:>..
B. Active
e4 Minimum spacing to gate z:>..
b, Minimum width 31, Poly

bi Minimum spacing 3i,

b3 Source / drain active to well edge SA

H. Metal 2

h1 Minimum width 3.)..

Minimum overlap of active 2).,
h2 Minimum spacing 4:>..
Minimum overlap of contact 1A
h3 Minimum overlap by vial !A.
Minimum overlap to channel 3.)..

Minimum size 7A

2.33
F. Metal 1

~ b2 _~ f, Minimum width 3:>.. - Let us first create individ .

~ active design rules Ii t d . . ual transistor using the
s e m Secnon 5.3.
 Review of MOSFET Operation and Fabricatio~
• Digital VLSI (MU)
66 2-67
2- much as possible, the ~ocal si&na! Review of MOSFET Operation and Fabrication
5 CMOS Inverter :
Therefore, a referably made by metal Imes. Finau
i, Digital VLSI (MU) . ize transistor. According :~ connect10ns are P made for the output node, V00 an~
2.34 CMOS NANO and NOR Gate Layout
·11 rorm minimum s ·dth of polys1hcon lay
We ,.,~ . I minin1um w1 . " metal connections are f metal lines in a mask layout a
o·mensions o
the design ru es •ffusion width is 3 . contacts. 1 b the minimum metal width and
te Two Inputs CMOS NANO gate consist of two nMOS
is 2Aand minimum d1 r polysilicon layer usually dictated y tion The metal connects are don
doffuO!on
transistors connected in series in the pull down
, have learnt that whene1;: in formatio n of a
~~:sses diffu sion layer it resu
o-ansistor. n- type diffusion it
using contact c_uts
the n-well reg10n m
a:~~
minimum metal serra g ~inimum size of 2A x 2A, Als e
be connected to VDD for prop;;
network and two transistors connected in parallel in
the pull up network. Using the layout rules discussed
When a polysilicon aosses ~-le when polysilicon biasing. in Section 2.32, the layout for 2-input NANO gate is
OS transistor, w 1 MOS 10}.
drawn (Fig. 2.34.2) p-select and n-well is not shown
forms a nM d•ffusion it forms a p
layer crosses p-type I n- wen
in the layout
lnpul
Oulpul
rransistor. of a transistor is determined fr~m - A 2-input CMOS-NOR gate contain two nMOS
The channel length . . ate and width of diffusion
the " ~dth of polys1hcon g ·dth Fig. 2.33.1 shows the transistors connected in parallel in the pull down
~:::,::::-;;~~',<,:?:i.\•:C11+---"'-'t- Diffusion
layer dictate the channel " ~ . nMOS transistor. 3;_ network and two series connected pMOS transistors
. ·mum size enhancement type
m101 Polysillioon in the pull up network. The layout of NOR gate (Fig.
2.34.1) is drawn by referring the layout rules given in
Section 2.321.

+
,'::.,I / "'"""' Fig. 2 _33 .2 : pMOS transistor

3i. Fig. 2 _33 _3 shows a typical CMOS i~v~rter_mark out of

. many possibilities for the layout of this c1rcwt. Fig. 2.33.4 : Alternate layout of CMOS inverter
Voo
CMOS 2-lnput NOR gate :
F"ig. 2_33 _1 : nMOS transistor layout

- Layout of a minimum size pMOS transistor in formed

in the similar way. For pMOS transistor, the diffusion
. .
m p rype sem1con ductor crossing the polysihcon MOS
layer. The overlap area is the gate of the p
rransistor.
- The pMOS transistor must be placed in a n-well
region and minimum size of the n-well is dictated by ln~IA
the pMOS active area and the minimum n-w_ell
overlap over p·. Fig. 2.3 3.2 shows the minimum size
enhancement rype nMOS transistor.
Input
- Let us now draw layout of an inverter circuit nMOS
and pMOS transistor are drawn in the way already
discussed
- The distance between the nMOS and pMOS transistor
is determined by the minim um separation between
the n· active area and the n-well. Si ngl e polysilicon
layer is used (Fig. 2.33.3) to make the gate
co nnection. Long polysilicon (in general layo ut) is in
fact avoided so as to reduce parasitic resistances and
parasitic capacitances resulting from the polysilicon
line, which otherwise would introduce significant RC Fig. 2.34.1 : 2-input CMOS NOR gate layout
delays. orour,d

•
F19. 2.33.3 : Mask layout of the CMOS •inverter clrCII~
 Review of MOSFET Operation and Fabricatio~
• Digital VLSI (MU)
2-69
Review of MOSFET Operation and Fabrication

Yoo

input A

Fig. 2.34.2 : 2-input CMOS NANO gate layout

Ex. 2_34 _1 : Draw layout diagram of the given functio n

f = A+ BC
Soln.:
Yoo

Ground

2.35 nMOS Design Rules

- Table 2.35.1 gives the encoding for simple single metal

nMOS process. Similar to CMOS process layout encoding,
polysilicon is coloured in red in nMOS process. Also
diffusion and metal layer are coloured in green and
blue
colour respective ly.

- A connectio n between metal and any other layer is achieved

using contact cut. In addition to contact cut, special
contacts called hurried contacts are required to form connectio
n between polysilicon and diffusion layer. Implant
region, coloured in yellow is to make depletion type nMOS.
 Review of MOSFET Operation and Fabnc:atio~
2-70
• Digital VLSI (MU) 2-71
. for single metal nMOS process Review of MOSFET Operatio n and Fabrica tion
Table 2.35.l : Encoding d 3 Poly extension in both sides beyond diffusion 2J..

-
coding eotour cod•
Mask layout en d 4 Diffusion extension in both sides beyond polysilicon 211.
Monochrome

Green ~ =1 : 1

n -diffusion

['--_]Red
p 0 tysilicon

-Blue
Metal 1
Enhancement mode nMOS transistor Depletion mode nMOS transistor

■
E. Burried contact

Contact cut
D Black
e 1 Overlap in diffusion direction 2A

e 2 Overlap in polysilicon direction 1A

Yellow
Implant e 3 Burried contact to active device 2A
\_______ ______ \
e 4 Burried contact to unrelated poly or diffusion spacing 2A

r-:::~::-1 r::~::-1 Brown

02 81

Burried contact
it:_:~~ t.,~:-=~,j

nMOS design rules :

A n• diffusion
a 1 Minimum diffusion width 2)..
a 2 Minimum spacing 3A

B. Poly mask
b 1 Minimum poly width 2A
F. Contact mask

f1 Contact size 2A x 211.

f2 Contact poly overlap 1A

----
b2 Minimum spacing 2J..
f3 Contact diffusion overlap l A
b3 Poly-diffusion spacing l A
f4 Contact to contact spacing 2A
b1 Poly gate extension beyond d iffusion 2A
fs Contact metal overlap 1A
b5 Diffusion to poly edge 2J..
C. Implant

c1 Implant gate overlap n

c2 Implant to enhancement gate spacing 2),
D. Minimum size transistor
d 1 Polysilicon with 2),

- d2-
Diffusion width

-------
2).

- - -- - ~
-II!~~
 2-72 i
Review of MOSFET Operation and Fabrj .
catio, • Digital VLSI (MU)
2-73
Review of MOSFET Operation and Fabrication
2.35.1.2 Burried Contact

v{ ~ 1 - In_this typ~ of_conta_ct the polysilicon comes in contact

with the d1f_fus1_o n with the help of an extra mask at the
w
~P = µ,, Cox

Where L is called aspect ratio of the transistor and

(Yi)
L p'

! ij"i 11 -
nme of fa bncatJon. Metal cap is not required.
The contact . cut _(broken line) indicates the area
whe re the thm oxide is to be removed to expose the
surface of the silicon water before polystlicon is
deposited, thus polysilicon is deposited directly on
is defined as ratio of channel Width the channel I gth
We know that, FET resistance is ~n .
proportional
L)
(
to ~ of th e transistor. In other
Wn
mverse~y
wor

I
R,, oc

cvo the underlying silicon substrate.

oxide._
- When diffusion takes place, impurities get diffused Z pu oc ( ~\ ➔ Pull up
Interlayer Contacts int~ the . p~lysilicon as well as into the diffusion
Each layer in th e integrated circuit is normally
reg10n w1thm the contact area. Zpd oc ( ~ ) . ➔ Pulldown

isolated by silicon dioxide insulator. In order to have - :hus a connection between polysilicon and diffusion . Zpu
1s ensured. Burried contacts can be smaller in area The ratio zpd is called inverter ratio Rnv-
interconnection between two layers it is necessary to
than this butting contact counter parts and since it
use mask for defining areas where the oxide is be T~e Fig. 3.24.1 shows layout of an nMOS depletion
Substrate does not use metal layer, they are subjected to tower
etched and metal is deposited to produce the desired design rule restrictions in a layout load inverter With inverter ratio of 4:1.
contact (for example metal to pry or metal to
diffusion contact). Aluminium is most widely used Fig. 2.35.1 : Butting contact, showing top vi- ProJICIIII Zpu _ ,i Zpu (~t
(.1..)
metal for contact cut for connecting two metal layers
cuts called vias are used.
The minimum size of contact cut and vias is 2A x 2A,
-
over the cross-sectional view

As shown in Fig. 2.35 .1, there is continuous met.1

present between the polysilicon and diffusion Le. 1
~.. == : zpd - 1 where, zpd =

Inverter ratio of u : 1 can be achieved with

W pd

-
etching much larger areas is not feasible. In order to
single metal cap is used. The two contact cuts are jlllt
adjacent to each other making a single buttq
Zpn (~ L =f and
increase conductivity or to make low resistance
contacts several standard size contacts are used
contact hole of size 2A. x 4A.. A border of width). b
added around all four sides to allow fir
zpd (~t =½
instead of making one large contact Also, multiple misregistration and to ensure proper contact, makq Note: Width otpolysilicon is channel length aoo'diffusion
contacts result in more uniform distribution of the metallization size to 4A. x 6A.. width is channel width. '
current - Otherwise, if continuous metal was not presen Ex. 2.36.1 : 4:1 : nMos depletion load inverter.
- In nMOS design sometimes interconnection between between polysilicon and diffusion, it would blw
Soln. : First method :
polysilicon and diffu sion is needed for example in required two separate contact cuts. Each contact cil Fig. 2.35.2 : Burried contact
would have been a square of 2A. with lA. extended I Zpu 4
nMOS techn ique where the gate of the load transistor - Basically polysilicon and diffusion layers are joined 1
each side making each of size 4A. x 4A.. Therefore, 1\11 zpd
is connected to its dra in terminal. There are two basic over a 2A. x 2A area with the hurried contact cut
contact cuts on combining would have been of sill
contacts used for achievi ng connection between
8A. x 4A., whereas for butting contact the size Is
extending by lA. in all direction around the contact We can take, (-wL )
pu
=i1 and (.1..)
W pd
=11
polysilicon and diffusion layers : area except that the contact cut extension is
6A.X 4A..
increased to 2A in diffusion. This is to avoid the (.w1. ) pu
.
ratio of
4
1 can be achieved by having
1. Butting contact formation of unwanted transistor.
Advantages of butting contact: polysilicon layer.
2. Burried contact
2.36 nMOS Depletion Load Inverter - Width (i.e. channel length) four times that of the
1. Contact cut is of smaller size.
width of the diffusion layer (i.e. channel width) .
2.35.1.1 Butting Contact 2· No extra masking step is required. VTC of depletion load inverter circuits like CMOS
- Since, we know that minimum diffusion width could
~
.
inverter VTC, vary with the driver to load ratio 'l3;:' . by 2 A.. Therefore, we will use polysilicon layer having
. In _a butting contact polysilicon is connected to the 3 - Simple to make.
width of2A. x 4 = 8 A.
diffus10n through the metal.
Disadvantage : Where - For pull down transistor we have (~ )Pd ratio of½ .
- - - -- - - - - - - - - - - - - i l. Requires metal cap.
 2-74
• Digital VLS I [MU) Alternate method : • Digital VLSI (MU)
.. d diffusion layers mu st be of
:. Th e polys1l1con an each Alternate form of 4 : 1 nMOS depletion load inverter 2-75
Review of Mos
same width. Let us ta ke it to be 2;,. . . . can also be achieved by taking different size of pun Up - Fi 2 ET Operation and Fabrication
• I d inverter schemati c is shown g. .37.2 shows the la out .
The nM OS dep let10 n oa and pull down transistors.
NANO gates for eac: _diagram of 2-input nMOS
in Fig. P. 2.36. l (a).
Voo Aswe know: length to Width . . dnver transistors channel
ratio is chosen to be½.
PU = 4/ 1 - Since polysilicon Width ( . .
NMos design rule is 21,. d minimum Width as per
Vo 211. Width of th d'ffu . ) efines channel length, it is
e I s1on defines the channel Width
V;n - - l ~ = 1/1 4
1 that must be 41,. to give length by Width ratio fl
o 2.

Fig. P. 2-36.l (a) : nMOS de~letion load inverter This can also be achieved, if we use channel length of
schematic pull up transistor to be twice as that of channel Width,
- In th e Fig. P. 2.36.l(b), the input Vn is applied to the And by using pull down transistor having channel
gate of pull down transistor. The gate and source of width twice of that of its length.
the pull up transistor is shorted and produces the
output V0 •

Yoo

For the pull up transistor, if the diffusion width is

chosen to be 2)... than the polysilicon layer
overlapping the diffusion layer must be of width 2 x 2 Fig. P. 2.36.l(d): nMOS depletion load inverter layout
1,.isH.
For pull down transistor if the polysilicon width is of 2.37 nMOS 2-input NANO Gate:
2A than the diffusion width must be 2 x 2A = 4 A.
VDD

Fig. 2.37.2 : nMOS 2-input NAND gate layout

2.38 Use of CAD Tools for Layout and

Ground
Simulation

Fig. P. (c) : Schematic diagram of nMOS depletion

2.36.1
load inverter
A---1 Z= 1/2 - Complexity of !C's is increasing exponentially over
the years (Moore's Law). Designing error free VLSI
th
- Fig. P. 2.36.1 (c) shows the schematic diagram of_ e circuits that consist of millions of transistors per chip
51 Ground
nMOS depletion load inverter with transistor z'.s is far beyond human ability and requires computer to
specified. The layout diagram for such an inverteris Fig. 2.37.1: nMOS 2-input NANO gates circuit diagram check layout, circuit performance, process design etc.
v.., drawn in Fig. P. 2.36.l(d). So, computers are used extensively to aid in the
design and optimization process.
Fig. P. 2-36.l(b) : nMOS depletion load inverter layout
 igital VLSI [MU)
. rs are norma Y
II given a set of -
• Digital VLSI (M U)

The advantages of GaAs are as follows :

rn
-
R"i= ,r MOS>ET Op,aOo, '""•bno,o, (

The tw~ n + semiconductor metal junctions (source

~
A
I circuit des1gne . ular technology and a 1) High electron mobility (about 5 to 10 tenies that
d on a part1c of silicon) and drain contacts) form ohmic contact whereas the
design rules base do their work
fil s in order to gate contact (semiconductor metal junction) is the
tech nology e i n and fabrication process. 2) High drift velocity schottky contact
Fig. 2.38.1 shows IC des g 3) Withstand high temperature.
- The flow of current through MESFET is controlled by
The design phase Involves : 4) High resistivity (It forms a better substrate) schottky contact

pattern generation Due to the above mentioned reasons. GaAs devices - Since the semiconductor-metal gate contact behaves
Design capture: f system may be
d / or structure o a are used in microwave applications (in gigahertz like a schottky diode, it forms a depletion region that
- The behaviour an description language range). extends in the n-semiconductor region.
expressed using a hardware 1c design process
- The structure of a MESFET is shown in Fig. S.3.1. Depending on the width of this depletion region With
such as VHDL, verilog etc. d through the
Unlike MOSFETs, that uses silicon dioxide layer, respect to the channel thickness, there are two types
- The design could also be entere
MESFET uses a schottky barrier junction to isolate ofMESFETs :
schema tic diagram. . the gate from the channel.
h sical layout may be generated either 1) Enhancement type MESFTs (normally OFF)
The P y lly from a high level description or may be - Like JFET it has two ohmic contacts (defining drain
2) Depletion type MESFET (normally ON)
automaoca a layout editor (MAGIC or and source contacts) with the difference having one
hand edited using schottky barrier (rectifying diode) instead of p-n 2.39.2 Modulation Doped Field Effect
MICROWIND). IC fabrication prooees junction. Transistor (MODFET)
Design verification : Fig. 2_38 _1 : IC design and fabrication process - The MESFETs can be fabricated either using
implantation or by using epitaxial techniques. - MODFETs offer even higher speed than MESFETs.
Verification happens at different abstra~tion levels.
Based on a typical VLSI design work flow, a good VLsi This is achieved as electrons attain very high
Various simulators may be used at the logic, circuit or - The structure of the MESFET based on implantation mobility.
CAD tool must support the following features : is shown in Fig. 2.39.1.
layout level (SPICE, IRSIM etc.). These simulators
Source Gate Drain - Thus MODFETs are also known as High Electron
perform functional, timing and other tests. l) Physical design layout editor, circuit schematics Mobility Transistor (HEMT).
Layout needs to run through get another type of design. - Fig. 2.39.2 shows the structure of a HEMT.
verification tool called Design Rule Checker (DRC)
2) Physical verification - Must contain DRC, circuit
which checks for design rule violations. S G D n• AIGaAs
extractor, capability to plot output and /or display for
- Design rules specify the optimum width and spacing Semi Insulating GaAs
visual checking. (SIGaAs) ~~'";,~(apaoerlayef)
between various layers.
Pattern generation : 3) Behavioural verification.
GaAs
Fig. 2.39.1 : MESFET structure
- It generates the database suitable for manufacturer.
2.39 GaAs Technology - The starting material for constructing MESFET is
Fig. 2.39.2 : MODFET structure
Translators are available to translate the design from
semi-insulating GaAs that have very high resistivity.
a standard layout format like Caltech Intermediate - The Starting material for constructing MODFET is
- High resistivity substrate material produces very low
Fonnat (CIF) to the pattern generation format 2.39.1 MESFET Device semi insulating GaAs.
parasitic capacitance that allows high speed
- That is, on completion of design and layout, the propagation of signals. - The layered structure as seen in Fig. 2.39.2 consists of
- MESFET stands for Metal Semiconductor Field undoped GaAs on top of SI GaAs.
system design is contained in system layout files in - This makes thin device substrate for microwave
5
intermediate form. These files are converted to Effect Transistor. Although it is possible to con tr1Jd
applications. On thin semi-insulating substrate, a thin - A layer of n-doped AIGaAs is present on top of thin
0ndu~
pattern generator files, to be sent to the mask making a MESFET device using silicon, but semlc layer of lightly doped n-active layer is formed by layer. The n doped AIGaAs layer serve as an electron
facility compound Gallium Arsenide (GaAs) is the commo implantation. source.

- The semi conductor device fabrication starts once the preferred material used for constructing MESFET, The heavily doped n + regions are formed by ion The electrons will flow to GaAs layer and thus it
masks are manufactured. The wafer undergoes implantation for source and drain contacts. results in difference in potential at the hetero
- The GaAs offers much superior properties a! junction.
several processing steps before it becomes a fully - The device has three metal semiconductor contacts.
physical IC component. compared to silicon.
 2-78 Review of MOSFET Operation and Fabricat;
01 . . Digital VLSI (MU)
. . Digital VLSI [ MU) - The mechanism of converting optical radiatio 2 9
The emitted photon energy is a r , ·7 Review of MOSFET
collected are confined in a very narrow electrical energy is called photovoltaic effect. n into Operat1on and Fabri catio
The electrons r:wo dimensio nal electron gas th at is equation gives the relationshi :p ox1mately equal to the band gap e
t d fro m doped. AIGaAs layer - Example : Solar cell and photodiodes are base hv = E p etween wavelength and energy band g:;r~ of th e semiconductor. Th e followi
area fo rming d on
photovoltaic effect g
spatially seelep:; : : fl ow through GaAs without
ensuri ng - Electrolumine scence is the phenomena of emissj
scatting. optical radiation by converting electrical energyon or
In order to fu rth er ensure no sca ttering a spacer layer light Into hc/E 8
is placed between n-doped, AIGaAs and GaAs layer as
Example : LED and Laser. Where,
shown in Fig. S.3.2.
_ The hetero junction not only benefits_ in increasing ➔ planks constant= 6.626 x 10- 34 m 2 kg/ s
2.39.3.1 Light Emitting Diode (LED)
electron concentration with out employm~ _dopmg but
also results in increase in th e mob1hty of the c ➔ speed of the light= 3 x 10a m/s
- A LED is essentially a p-n junction diode made Usi
electrons as electrons doesn't has to travel through a direct band gap semiconducto r material. ng
Eg ➔ energy band gap.
doped semico nductor in which case mobility would
- GaAs is a direct band gap material and is th
have decreased due to scattering caused by doped Thus, a semiconductor with band gap of 2 ev, emits light at about
preferred over the semiconducto rs like Si and ~s
atoms. which are indirect band gap material. e A= 6.626 x 10- 34 x 3 x 1oa
- Sca ttering limits the average velocity of electrons in 2 x 1.6 x 10- 19 = 620 nm
crystal and thus effects its electrical performance. - LED constructed by forming p -n junction using same
semiconducto r materials that are differently doped is Which is visible red colour of the spectrum. Fig. 2.39.4 shown below depicts the wavelength range for visible
- In MOD FET th e high electron concentration is created lights.
called homo junction LED.
in an undoped layer.
- LED's formed using different band gap materials are
Therefore it is possible to achieve very high electron
called hetero junction device. 10- • nm
mobility. -5
- Hetero junction LED's gives high radiance than a 10 nm
Th is high mobility electro n results in superior high
homo junction LED. 10· • nm
freq uency performance. 3
- Fig. 5.3.3 shows a simple forward biased homo 10· nm
2
2.39.3 Optoelectronic Devices junction energy band diagram. 10· nm
Vlsible lights
1
10- nm
- Devi ces that convert opti cal energy into electrical 1 nm
energy or vice versa are called optoelectronic V,olet
10 nm Blue
devices.
p-type 100 nm
n-type

_/? -- 10 nm= 1 µm
Green
Yellow

~ ·~] 1011m Orange

Red

:: ------ -- 1000m=1mm
10011m

10 mm=1 cm Microwaves
radiation

l
10cm

'• + ~ +++++++:· 10cm= 1 m

10m
100m
Fig. 2.39.3 : Energy band diagram of a forward biased homo junction Radio waves
1000 m=1 km
the electrons from the n-tYJII
- ~en_th e_p- n juncti on made up of a direct band gap material is forward biased 10km
j~r is mJecte_d mto : he p-type layer where they are the minority carriers. This i/followed
by the recombinadon
o e ectrons wi th maJonty hol es Simil ar! Y h OIes f ra m the p-type layer are injected into n-type layer where
combine wi th majority electrons:
th~ 100 km
I
. anl Fig. 2.39.4
- This recombinati on happens either radiatev 1 structllre
doping. Rad iative recombination g· e Y or non radiatevely depending mainly on the band
ives r 1se to e miss ion oflight, each photon releasing energy of hv.
 2-80 l'lcatioi
~ ~ ~ ~ ~ ~ = = = = . : ~ : : : : : ; : ~ ~ : ~==~R:e:vi:
ew~:o:fM:
OS:F:E~
i ;;;
O;:;;:pe""r-at_1o_n_a=n=a
d.;,;
Fa~b::;:· " ' Digital VLSI (MU)

t . . Digital vLSI (MU) . e ra nge

. lly visibl LED wasf
The first commerc1a . p alloy. All oys consisting o
2.40 Multigate Devices
•
2-81

-
Review of MOSFET Operation and Fabrication
Both th e gates are con
fa bricated using GaAs , - 'd ' ry corn pound s for ex.
th ree elemen ts are call e te;:aoperating wavelength
G As p etc. A spec1 .
11.:,111,--~
Q. What is the difference between the Silicon-on.
The electric field lines e:~ct~d fo r this configuration.
region underneath the . itting from source and drain
bottom gate electrode device terminates on th e
AIGaAs, a d for AIGaAS or caAs P etc. by varying Insulator (SOI) linFETs and Bulk l1nFETs? channel region. and thus cannot reach th e
can be selrte~;~s of th e co nstituen t atorns.
the propo e\ 10•MFl-i~ - Th e first double
LED tabriCSIJOn : DE plated L gate SOI MOSFET called DELTA (fully
fa bricatio n of LED diode is very sirnpl e. It sta rts Due to th e mini aturizatio n trend, the devices
1989. een-channel Transistor) was fabri cated in
:~~ a GaAs substra te (bulk). Th e bulk grown being scaled down continuously giving rise tO are
th
(a) Bulk MOSFET

materials such as GaAs usually do not have the nght short channel effects. As the channel length sh ortense
- The device was
energygap for the desired wavelength of the ern1tted (that is source and d_rains are corning cl~ser), the ga~ called 'f r' made is a ta 1I and narrow silicon iland
light Also there rnaterial has relanvely h1_gh defe ct voltage is not sumc1ent enough to_efficiently control s enge , or fi n. (Refer Fig. 2.40.3).
density. The light generati ng region (that is th e p-n the current fl ow m the channel reg10n. Gale
junction) on the other hand needs to be low dop ~d. Box
_ Essentially the problem is the presence of the leakag
Because of these reasons, practically all cornrnerc1al
current that exist in short c~annel device. In order to CU!e
LED strUctures consist of an epitaxially grown layer
off this leakage, we need to improve the gate control. This Si
on top of the bulk substra te material.
can be achieved by using two gates to control the ch3lllld
- The fabrication of LED sta rts wi th a heavily doped n- current (i.e a ~ouble gate device) ~r by using triple gate ~ . (b) Fully depleted SOI MOSFET
type GaAs substrate. A lightly doped n-type GaAs Fig. 2.40.1 : Electric field lines from source and drain on
a tri-gate deVJce or by surrounding the channel by ga~
layer is epitaXially grown on top of the substrate. the channel region
(Gate All Around (GAA)). ·
Then a p-type GaAs layer is grown on top using
- Such devices would result in improving the shon Double gate device :
epitaXial process. The thickness of the p-layer should
(a) 3D structure of DELTA device
be layer than the diffusion length of electrons so that channel effects. - Another way to address the problem of t
the electrons recombine radiatively in the epitaxially to control current flow is to go f
- Short channel effects are seen when the gate is M t or a gdaouble
e not able
gate
grown p-layer befo re reaching the surface. Finally the

_______
able to efficiently control the channel regions. Thi s ructure. The double gate transistor structure
front and back of the wafer are metallized. happens in short channel devices as in these device
.--__. - - - - - Aluminum contact the source and drain regions are in close proximi~
first proposed in 1984 by Sekigawa and Hayashi. was
- T_he~ claimed that the short channel effects ar e
and thus gives rise to electric field lines betwe11
~1gmficantly reduced by sandwitching a fully
p-GaAs drain and source that is, sufficiently stronger than th!
epleted SOI device between two gate electrod
n-GaAs electric field by the gate voltage.
~his device was called XMOS as its cross section loo::
The gate control in such a situation is limited to veij hke Greek letter= (Xi)-
n •GaAs subSlra te thin region beneath the gate surface. The current thal (b) Gate structure of DELTA MOSFET
is far from the surface cannot be controlled by th1 Fig. 2-40.3 : DELTA MOSFET
gate. Also the Drain Induced Barriers Lowerin! 0
Fig. 2.39.5 : Cross section of LED
Features of DELTA MOSFET :
(DIBL) results in increase in current.
Modem LED structures use Si-doped GaAs to increase
- Band to Band Tunnelling (BTBT) leakage, whid 1. Both the front and back gates are inherently self
th e efficie ncy Fig. 2.39.5 shows the same.
cannot be controlled and results in degradation ahgned.
p - GaAs : Si subth r eshold slope. This means that we can~
essenti ally turn off the device i.e. it starts to look Ii~ 2. The ~hannels are on the side wall s of the silicon body
n -GaAs ; Si
Fig. 2.40.2 : XMOS device 1.e. Fm.
a resisto r instead of transistor.
- One way to solve this problem is to essentially cut oii - Wi th th is configura tion (sh own in Fig. 2.40.2), the
FinFET device :
all th a t region below that gate was not able to con~ cha nnel de pletion region is better controlled than
This ca n be achieved by using SOI technology whI ~th regula r SOI MOSFET. Th e influ ence of electri c A double gate device flipp ed over is a FinFET device.
uses ultra thin silicon la yer (ranging few nanornete~ fi eld due to d ra in/source on th e channel is reduced
th at reSt on th e oxide la yer i.e. using fuilY deplel~ th e reby r educing the s hort channel effect.
SOI MOSFET.
Fig. 2.39.6 : Cross section of high efficient LED
 _ Review ofMOSFET Operation and Fabricati
2 82
· h' h h % ..., Digital VLSI (MU)
- GAA is a planar MOSFET m w tc _t e gate electro 2 93
is wrapped around the channel region. de Fig. 2.40.8 shows the gate structure 0 f · Review of MOSFET O .
and Q - gate FET. a n-gate PET
_ The MIGFET is a double gate device With tw
independent gate electrodes. These two gato
electrodes are not connected together so they can be
biased independently with different potentials. e
It is possible to modulate The threshold Volta
_
one of the gates by applying the bias to the of ~;h
gate. MIGFET can be used in signal moduJati:;
_(b) Cylindrical FET
applications.

□□□
The de,~ce is no more planar now and gives two (a) 7t gate FET
gates Gate 1 an d Gate 2 as shown in Fig. 2.40.5.

□□□
Oxide

_□ DJ DJ
Gate2
Gate 1

(c~ Multi-bridge/stacked na:wire FET

GAA
F In FET (bl n-gate FET Frg. 2.40.9 : Different gate structures
Fig. 2 ,40.8 : Gate structures
Fig. 2.40.6 : Gate structures of double gate devices
Fig. 2.40.5 : FinFET gate structure 2.41 Carbon Nano-Tube FET
Surrounding gate SOI MOSFETs :
Tripple gate SOI MOSFETs :
- The srructure of FinFET is almost same as DELTA
- Surroundi~g gate MOSFETs offers the best possible
with the difference of the presence of dielectric layer The FinFET device uses only the two side walls and
electrostatic control of the channel region. The first What are the advantages of CNTFET over
called the hard mask on top of the silicon Fin. This thus gives two gates. On a trigate device gate oxide in
su_rroundmg gate MOSFET such as CYNTHIA device traditional CMOS device? II!IIREI
hardmask prevents inversion channels to be formed uniform on both the two sides as well as on the top,
(circular section device) and the pillar surrounding
at the top corners of the device. thus giving three gate electrodes which further - It has seen that scaling of semiconductor devices
gate_ MOSFET (square-section device), were
improves the electrostatic control of channel. fabricated by wrapping gate electrode around MOSFETs and CMOS has limitations in fabrication
Bulk FinFET :
- It is also called as MUGFET (Multi Gate device). Fig. vertical silicon plate. Multiple surrounding gate and performance. Especially it has resulted in
So far we have seen FinFET devices fabricated on SOI 2.40.7 shows the gate structure of a trigate FET. channels can be stacked on top of one another with increased short-channel effects, reduced gate control,
waters. It is also possible to fabricate FinFET on bulk common gate, source and drain to yield increase in leakage currents, severe process variations.
silicon waters. Such kind of FinFETs are called body tied current drive per unit area. - To overcome these problems several alternative
FinFETs or bulk FinFETs. - Such devices are known as Multi-Bridge channel technologies to bulk silicon transistors are being
MOSFET (MBCFET), the twin silicon Nano-wi re explored. Ultrathin body devices such as FinFETs
Advantages of bulk Si over SOI substrate: have gained increased attention.
MOSFET (TSNWFET) or the Nano-beam stacked
1. Cost of water is less. channels. - It is essential to study new materials and devices to
replace silicon in nano scaled transistors. Carbon
2. Substrate heat transfer rate is better.
nano tube transistors seem to be the promising
Disadvantage of bulk Si over SOI substrate : device for nano technology.
Fig. 2.40.7: Gate structure of Trigate FET - A carbon nano-tube field effect transistor is a field
1. Additional isolation steps are required in fabrication
The electrostatic control of channel can further b! effect transistor whose channel is made up of a single
of bulk multigate MOSFET.
improved by extending the gate even deeper into t_hi nano-tube or an array of carbon nano-tubes instead
2. Large cycle time a nd cost of bulk silicon as in the traditional MOSFET structure.
oxide and silicon giving rise to Pi shape. This deVI''
Other double gate devices: - Carbon nano-tube FET (CNFETs) was first
in known as 7t - gate device.
(a) Quadruple gate FET demonstrated in 1998 that gave great impact on
There a re several other implem entation of vertica l The gate can be wrapped around further giving itan nano-technology.
channel, dou_b le gate SOI MOSFETs such as Gate All omega shape called Q - gate MOSFETs.
Around device (GAA), Silicon On Nothing (SON) Th e b eat electrostatic control can be achieved b1
MOSFET multiple mdependent Gate FET. -
having a gate all aro und device.
 ~ Re;;;v;,;.ie;a:;wa:aoa:afM
" 'O
" 'S"'F"'E"'T"'O._pe"'r"'ati=·o=-n~a~nd~Faatbr1.~ti
-

,-~~~~~===""".~~'.=:;.~::::'"i~
1) o· ital VLSI (MU)
,g . the CNiFEi structu res
carr}' h.,gh current
.
elecrro-migrat10n.
density and higher res·lstanc on
e to
1'
14.
Digital VLSI (MU)
Explain nMOS transistor fabrication .
2-85
Review of MOSFET Operation and Fabrication
There had been advance mrovi n th eir electrical
d processing for ,m p g
; : aracteristic Fig. _2 .1 show_s the structure O
6
f carbo n
The re are many types of CNTFET devices; a ge
survey of the most common geometries are . Bei.1
n 15. Which are the CMOS design rules?
21 0
.g:~: the 2 input nMOS circuit diagram using NANO
ated CNTFETs, Top-gated CNTFETs and ·,_,ac~.
g 16. Draw the CMOS inverter circuit. Explain the phases which . .
nano rub e- . . h carbon CNTFET ••ta 22.
fabrication process. are involved in IC design and
- A carbo n nano tube 1s a graphene sheet (wit d to around gate s. P·
17. Draw the circuit for two input NOR .
atoms appearing in a hexagonal pattern) roll~! ~Pup _ Back-gated CNTFETs : Two metal contacts are lo Hence draw its stick diagram and layogu~te using CMOS.
form a no\\ow cylinder also knovm as Ro e across both ends of the CNT to form the Sou cateq 23. What is mean by
advantages of GaAs. MESFET device? State the
c'n\.c\,en wire structure. tubular cylinders of Drain terminals of the FET. The CNT is place;ce anq 18. Enlist the nMOS design rules.
2 4. What are FinFETs?
Carbon nanotubes (CNTs) _a ,_·eordinary mechanical, of the oxide layer present above a doped o_n_top 19. Explain burried and butted contacts.
carbon atoms chat have extrahemica l properties. substrate, it forms the Gate terminal. Connecti sihcon
electrica l, th erma l, optical and c made to these three terminals to perfor~s are 20. ~~~;:~~~h between conventional and burried/butted
electrical measurements. This technique suft tbe
from several drawbacks. Firstly the metal co ereq
area to the CNT is small. Also, a Schottky bantact □□□
forms at the metal-semiconductor interface du;er
the semiconducting nature of the CNT, Whi:
increases the contact resistance.

-
- Secondly the thickness of back-gate device geomet
makes it difficult to switch on and off using lo:
1-2nm 2-2.5nm voltages, and the fabrication process led to poor
Fig. 2.41.1 : Carbon nanotubes contact between the gate dielectric and CNT.

CNTs typically have diameters ranging from -1 Review Questions

nanometer (nm) up to 50 nm.
- Power diss ipation is low because of the reduction of 1. Compare between full scaling and constant voltage
carrier scattering. scaling.
- Carbon nanotubes (CNT) have potential application
2. Explain hot carrier effect and its prevention.
in future nano electronic systems due to their
superior transport properties, low voltage bias and 3. What does the process lithography mean?
improved current density.
CNT 4. Explain the mask generation process.

5. Explain oxide patternization using photolithography ITT

case of silicon technology.

6. Explain pMOS transistor fabrication.

7- What is mean by LOCOS?

Si Bulk 8. Draw the Complementary MOS circuit.

9- Explain how the CMOS p-well process is carried out-

Fig. 2.41.2 : Carbon nano-tube FET structure

- ~he_structure and operation of CNFET is very much , a. Explain Twin tub process in detail.
similar to the conventional MOSFET with d·n 1 11 - Draw stick diagram for 3 input NOR gate using ct,lOS
in the chan I . erence
. ne material. The channel in CNFET . technology.
formed using CNT wire instead of the bulk silicon. is
12 · Draw sti ck diagram for CMOS inverter.
- CNTFETs have an extraordinary mechanical stre n th
low po wer consumption, better stabil"1ty , capablegto
13. Explain the need for layout rules.

- - - - -- ----2
. .,,,,,· .~~
 r7
• Digital VLSI (MU) 3-2
~,.,,,.1cMOSco;,c;=l<
- When Y0 0 voltage is applied at terminal v. = V00 this
is the drain terminal. roo-+IYTPI

combinational CMOS V, = V 00 , Vb= 0 V ... Initially

So, YGs = Yoo - 0 = Yoo, the MOSFET is ON.

Logic Circuit When voltage across the capacitor reaches Y00 - Yth, it
Fig. 3.1.5
Table 311 ..
makes YGs = Y,h which implies that voltage across
Voltage level Switch condition
capacitor cannot go beyond Y00 - Y,h because that would
mean that YGs < V,. STRONG '1' pMOS switch VG= 0, V5 = V 00
_ Let us apply y 00 voltage to the gate input of the Mos STRONG 'O' nMOS switch VG= V00 , Vs= 0
nMOS is ON till Yb is Y00 - Y,h.
MOSFET as a Switch transistor. The Table 3.1.1 shows the suitable transistor for
3.1 :. It can pass upto Y00 - Vth voltage.
_ The source and drain terminals are labelled in complete transmission of 'O' and '1' logic levels.
Thus, Y,n must be less than or equal to VG - Y,h for Therefore, generally pMOS transistors are used to
The MOSFET acts as a s11itch where ga te terminal accordance with the potential at these terminals, The
nMOSFET to be ON. Therefore, it can pass maximum produce logic '1' level at the output while logic 'O' level is
controls the current flow between the source and the one with the lower potential is referred as the source
upto VG - Y,h voltage. obtained at the output through the nMOS transistors.
drain terminals. terminal. Pass transistor
pMOS switch behaves in a complementary way. pMOS
For nM OS transistor when gate to source voltage is Case I : Passing 'O' voltage level
switch is 'closed' or 'ON' when there is a 'O' on the gate. It Let us consider two n-channel MOSFETs connected
less than the threshold 1·oltage of the device, the in series.
VGs Yoo-O=Voo is 'open' or 'OFF' when '1' is applied to the gate. pMOS
source and dra in are disconnected wi th infinite The gate voltages are being set to Y00 , giving
switch is almost perfect for passing '1' signals but is
resistance between them and no curre nt flows YGs > Yth, nMOS is ON. conduction between source and drain electrodes.
imperfect when passing 'O' signals.
between them. 1) When input voltage A= OV, X gets value of OV, since
It can pass the entire DV to point b. Voltage at b is Case I : Passing '1 ' voltage level
In this condition the nMOS transisto r is refe rred as nMOS switches are capable of passing strong 'O'
'open' switch or 'OFF'. When gate to so urce voltage is obtained by measuring voltage across the capacitor. Let us assume that output capacitor is initially voltage. Similarly this OY at point X gets completely
yb = 0 y uncharged. Sources are connected to Y00 and gate transferred to point B. Thus, B = OV. Thus, the OY
greater than the threshold voltage, th e transistor
terminal is grounded. applied at point A is therefore transferred completely
behaves as a finite resistance and sv.~tch is sa id to be
'closed' or 'ON '. iG = Voo(gate) YGs = 0-Voo=-Yoo
Thus the MOSFET is ON and is able to charge the
down the chain.
2) When input voltage A = Y0 0 , there is a threshold
voltage loss at X. Thus X = Y1n - Y1n. This make
VGS < Vu, a(sou~in) output capacitor full upto V00 . YGsz = Yoo - CVoo - Yrn ) = Yrn. Hence M2 is 'ON' and it
1 v.=ovl 1 can pass complete Y00 - Y1n voltage available to X to

a ___n__ b ⇒ ~---➔
'O FF'
. +
Fig. 3.1.2
point 8 . Thus at point B, voltage obtained is Y00 - Y1n .
We conclude that only one threshold voltage loss
occurs in a series connected chain of nMOS
Case II : Passing '1' voltage level transistors.
VGs > Vu,

l Assuming that the capacitor is initially not charged in

Ex. 3.1 .1 : Two nMOS transistors (M 1 and M2 ) connected
in series is shown in Fig. P . 3.1.1. Assuming power supply
aJ Lb ⇒ a Yb = OY V00 = 3.3 V and the nMOS threshold Vtn = 0.55 V. Find the
'O N' Fig. 3.1.4

Fig . 3.1.l : nMOSFET with its switch equivalent circuit IG = Voo(gate)

Case II : Passing 'O' voltage level
output voltage at node b.
(1)V8 =2.7V (2) V8 =3V
Yoo Yoo

l t
- nMOS transistor passes 'O' voltage perfectly but it is (drain) ~ o u r c e ) YGs = 0 - Yoo= - Yoo
an imperfect switch when passing a T vol tage level : . pMOS transistor becomes 'ON'. Transistor remains 1 1
Th at is, a 'O' voltage can be passed com pletely b .
nMOS transIStor wh ile ' J' voltage level when y
v,,v
00 'ON' until capacitor discharges to Yrr value thereafter +wL.-...TT-b
V•i M1 X M2
gets little reduced. passed It pMOS becomes OFF.
:. pMOS lowers the output no further than I YTP I- Fig. P. 3.1.1
Fig. 3.1.3
 combinational CMOS Logic Circuit i, Digital VLSI (MU) 3-4
3-3 Combinational CMOS Logic Circuit
V Digital VLSI (MU) MOS Inverters and Voltage Transfer VoL is the maximum output voltage when the output
3.2
Characteristics level is logic 0.
Increase in driver to load ratio
Soln. : . - V = 2.85 V. VoH is the minimum output voltage when the output
(1) Voltage at Xcan be maximum Yoo tn
_ There are several forms of MOS inverter that may be
(f) driver
Since V, = 2. 7 V, M, transistor can pass entire 2.7 V. level is logic 1.

V, = 2.7V
used as basis to build logic gates. In this section each (f) load j
of the inverter configurations is analysed.
can also pass voltage upto Voo '1' Voo
r,1
2
transistor Static CMOS inverter consists of complementary logic
VDD - Vtn = 2.85 V blocks, thereby requiring large number of transistors
V1H
vb = 2.1v to build the circuit. Also pMOS transistors are slow
Fig. 3.2.4
and occupy larger area on chip.
(2)V, = 3V - Most of the combinational circuits consist of two
Since, M, can pass maximum upto 2.85 V. There are several other techniques to improve the
blocks in general, a pull up block and a pull down
speed and density of static CMOS circuit We will start
V, = 2.85 V block. A pull up block is meant to pull the output of
study of inverters with the basic resistive load 'O'
Similarly M2 can pass upto 2.85 V. the circuit to the high voltage while the pull down
inverter analysis. drives the output to low voltage level.
Fig. 3.2.2 : Definition of the voltage noise margin
vb = 2.ss v - Figs. 3.2.1 (a) and (b) show ideal inverter symbol and
- Due to noise the signal value may differ at the two - We start with the most basic inverter circuit that
Ex. 3. 1.2 :The output of an nMOS (N 1 ) is used to drive the Voltage Transfer Curve (VTC) respectively.
ends of an interconnect line. Let us consider two consist of an nMOS pull down network realizing the
gate of another nMOS transistor (N2 ) as shown in Fig. P. 0
cascaded identical inverters to illustrate the effect of logic function (contains a single nMOS transistor for
3.1.2. Assume that V00 = 5V and V., = 0.2 V. Find the output V 1 L u
noise on the correct functioning of the circuit. inverter circuit) and a single resistive load in the pull
voltage at node b, when input voltages are at following up network block.
values.
V;n - { > o - - Voul
V;n v,n, ~ o Va1 = Vof V;n2,= V1L[::>o V~2 = VoH
The operation is as follows :
0
(1 ) V, = 0.5 V and V, = 3.0 V
{b) VTC curve of ideal inverter Case I
(2) V, = 2V and V, = 1.5 V
{a) Inverter symbol Interconnect
Fig. 3.2.1
Yoo
Fig. 3.2.3
- When a low input is applied, the nMOS transistor in

l - As seen in the VTC curve for low input, output

produced is high and vice versa. Ideal inverter
- The input to the 1st inverter is Vrn i.e. logic '1', so it
the pull down network is off creating an open path
(no connections) between ground and output. The

·f-7_ produces well defined logical output (0 or 1) even in

the presence of considerable noise in input voltage.
Produces a logic '0' output (V0d, Now this output is
given to the input of 2 nd inverter via interconnect.
output V0 is pulled high by the resistive load.
i.e. V;n = 0, M 1 is 'off'.
The signal while travelling through interconnect may
v,lX~ b
M2
Following section discuss Noise Margin concept. -
get perturbed due to noise. If the noise results in
:. Vo = Voo=VoH
Voo
3.2.1 Noise Margin changing the signal value smaller then Vou it would
Fig. P. 3.1.2 still be recognized correctly as logic 'O' by the second
v - Noise margin gives the measure of sensitivity of a inverter.
Soln.: (l) V, = 0.5 V and V, = 3.0
gate to noise. It essentially represents the level of
Transistor M2 can pass voltage of maxi mum V - V - But if the signal value happens to be larger than V,u it v,.-,~v,
noise th at can be accepted when gates are cascaded.
= 5 - 0.2 = 4.8 V. Since, V, = 0.5 V, it can pass
at node 2.
05~
·
enti:: - It is specified wi th two parameters Noise Margin Low
would not be recognized as logic 'O' by the second
inverter.
(NMd and Noise Margin High (NMH) -
V, = 0.5 V - Thus, v,L is the maximum input voltage that can be Fig. 3.2.5 : Inverter with resistive load

._. Output of 1'' transistor in d . . . NM L v,L-VoL interpreted as logic 'O'.

Case II
It can ass . nving transistor M2 .
. p maxim um voltage upto 0.5 - 0.2 = 0.3 V. and NMH = VoH - v,H 3.2.2 Resistive Load Inverter - When the input V;n is high, the pull down transistor
. . Voltage ab is Vb= 0.3 V Where,
becomes 'ON' thereby establishing a resistive path
(2)V, = 2V and V, = 2.5 V, V, = 2V v ,L is the maximum input voltage which can be llBlhA?iiN•tttMtifui between the ground and the output node.
M2ca n pass upto 2 - 0.2 = 1.8 V interpreted as logic 0. Q. Explain transfer characteristics for NMOS. Inverter - A resistor divider network is formed and the output
v,tt is the minimum showing different regions, What is the effect of V0 is determined by applying voltage divider rule to
vb = 1.s v • input voltage which can be
interpreted as logic 1. variation in W/L ratio? IMHM1'1@ifMlll1Mfflff the resistive network.
 Combin ational CMOS Logic Circuit

•
3- 5
1J Digital VLSI (MU)
Digital VLSI (MU)
... (3 .2.1) or Yoo -Vo
~2 RL(Y:L!.) ( Yin - V ~ tn )
2 Vo
3-6
Combinational CMOS Logic Circuit
-Voo
VoL = ~RL+RoN
...(3.2.2) ··-(3.2.8)
__lR_ • Voo
Differentiating Equation (3 .2.8) gives ,
1+~ /AL Increasing
RoN
2k~ L ) 2 ( Vin - v,n)
(W
dV0
... (3 .2.3) 0-~ RL
Also, v. = V00 -ILRL

'
········· VOL
Vpo - Vo ...(3 .2.4)
IL ... (3.2.9) VIL VIH V~
RL
k,f f l ( Vin - V,n) ... (3.2.lO) Fig. 3.2.7 : Transfer characteristic of resistive load
inverter
d V0
AtV1n VIL; ~ =-1 NM 0 = V1L- VoL, NM 1 = Yott - V1H (a) Deple:;:ctn load circuit (b) Depletion load inverter
5
ure circuit
Disadvantages
1
: . - ~(- 1) k~ (f) (VIL - V,n) ... (3.2.11)
1) Output voltage Y0 can never reach OV.
Fig. 3.2.8

- Both the driver transistor and the load transistor are

-1... 2) Large space is required to realize resistor RL. bmlt on th e same p-type substrate, which in
RL connected to ground.
GND
3) Ratioed circuit : Low output voltage depends on the
F",g. 3.2.6 : Resistive equivalent circuit k~ (f) = 13 ...(3.2.12) size of the transistor. Circuit dissipates power when
- Consequently, the load device is subjected to the
substrate-bias effect, so that its threshold voltage is a
From the above Equation (3 .2.2), it is clear that for input voltage is high since a path is established
1 function of its source to substrate voltage.
the inverter output to reach exactly DV, the load V1L-Vtn ... (3.2.13) between supply and ground for high input
fR: - The source of the load transistor is connected to the
,____.._ _ _ resistance needs to be infinity from Equation (3 .2.2). To 4) IL current depends on the output voltage V0 from
1 output of the inverter V, therefore, V58 , load = V.
keep the low no ise margin high, it is important to choose Y1L Vtn +fR: ...(3.2.14) . Yoo -Vo
equ at10n IL= --RL- . Hence threshold voltage of load (VT. J varies as a
Rl » RoN· function ofV0 •
At this input value, corresponding output voltage can
Wh en th e output is function of pull up by pull down The charging current drops rapidly once V0 starts to
be determined by substituting Equation (3.2.14) in VT.L = VTo.L + Y ( ~ - ~ ) ... (3.2 .21)
resistances (RJRoNin this case). rise. Therefore the charging time decreases.
Equation (3.2 .8). From the Fig. 3.2.8, it is seen that
This style of logic where the output is function of pull A better load would be a current source which has
~ (V1L -V,n/
V00 -V0 VGs. L = 0 V (gate to source voltage of load transistor)
up by pull down resistance (Rd RoN in this case) is called ... (3.2.15) the property that available current is independent of the

r
RL
ratioed logic. output voltage. It can be easily determined that for the Yos.L=Voo-Vo

From Equation (3 .2.2) , it is found that the low output l3RL ( 1 same initial current level the charging time for a (drain to source voltage of load transistor)
Yoo -Vo -2- v,h +13RL -Ym ... (3 .2.16)
voltage achieved ca n never be exact Oand would depend capacitor is reduced. VGs.o = V;n
on the size of the trans istor. That is, pull down transistor 1 (gate to source voltage of driver transistor)
Vo = Yoo -213 RL ...(3.2.17) 3.2.3 Depletion Load Inverter
needs to be scaled properly to obtain a workable gate. Yos.o = Yo
(HMOS - High Performance MOS)
(l)V1n is small bu t greater than Yrn: (2) Vin > Vo - YT M1 is in linear region : (drain to source voltage of driver transistor)

Yin ~ 1:1,;;:.;;1tN•ffi%itiffli
~ (2 CV1n - V, ) V
Vrn, Then M1 is in saturation Yoo -Vo Case I: When V1n < Vr, o
v! ] ... (3.2.18)
0 - a. Explain noise margin of an nMOS inverter using VTC,
z~ (w
RL
The driver transistor in this case is cut off and hence
1os = L)[VGs - Vrn ]2 ...(3 .2.5)
I
dVO
critical voltages and input-output window profile.
drain current is equal to 0.
and
~ - 1 .. Yin = VIH IMUM•NPIIIIMtMU
Where, ~ = l!n c0 x VoH = Yoo

~ In this type of inverter, the pull up networks consist

L ) ( Vin - v,n )
~ (W
-
Then VIH = V + _1_ Case II : V1n Is small value but greater than Vr, o
2
2
...(3 .2.6) tn
A

\J 3rw:;:- l3 RL .. .(3 .2.19)

of a depletion mode nMOS tra nsistor with its gate
connected to its source. In this case, the driver transistor operates in
Yoo -V0 (3) Vin = Yoo M1 is in linear region and V0 = VoL
-R-L~=l os - A depletion transistor is 'ON ' fo r VGs = DV. Therefore, saturation while the load transistor operates in the

VoL = Yoo -V, +'3RL -

1 1 )2 -13Ri.
~ the pull up transistor is always 'ON' and the load acts linear region.
~2 ('.!L_ ) ( Vin - V,n ) 2
...(3.2 .7)
( Voo -V,+13Ri.
... (3 .2.20)
as a current source as its current in saturation mode For drives transistor.
approximates.
 Combinational CMOS Logic Circuit
3-7 V Digital VLSI (MU)
3-8
Combinational CMOS Logic Circuit
lo,o _ p ° {2(VGs.o Vr,o) Vos.o -V\s.o}
Vos.o Voo
2 Th e actual load line deviates from the ideal current
so urce characteristics due to the body effect. The source
VG,.0-Vr.o = V1n-VT.D = P; 0 {2 CV1n - Vr, o) VO- v ! } of th e load transistor ls connected to the output of the
. VGs.o - Vr.o < Vos.o inverter V0 therefore V, varies as a function ofv •
0

driver transistor is in saturation. and 10,L = ~ [

2 - VT,L]2 Table 3.2.1 : Operation region for depletion
load inverter
The expression for drain current, therefore is Equating the current equation gives,
Driver Load
lo.o = ~ CV1n -Vr.0)2 ~n.o {2(V;n -Vr,o)V 0 -V! } = Pn,d-VT.L]2
VoH Cutoff Linear YsoP = Yoo- Y0
For load device Vos. L = Voo - V0 Differentiating both sides with respect to V1" and
VoL Linear Cutoff YSGP= Yoo
dV 0
VG,,L- VT,L = !VT.L I substituting V;n = VIH a nd dV;n = - l, Fig. 3.2.9 : Pseudo nMOS inverter circuit
VIH Saturation Linear
His in linear region, giving current of Let us assume that V0 L is small, so that M is non -
2
we get, VIL Linear Saturation saturated, then M I will be saturated. Since the current
\D.L = ~;" {Z (VG,.t - Vr.JV os.L-V\s. J dV 0 dV•} _ ~
Pn,O{ 2(V;n-Vr,o)dv;/2 v. -2v. dV1n -2Pn,L VT,L dVO Advantage over resisted load flowing in each transistors need to be equal (M and M
1 2
connected in series), equating the currents through th e
Equating the current equations and gives, Requires less area.
Pn L
~;° (V1. - Vr,o) 2 ~ZL{2(VGs,L-Vr,L)Vos.L
CV1H - Vr,o) (-1) + v . - Vo (-1) = Pn.o . CVr,J
dVr L
av:: Disadvantages
transistors give :

- V\s.L } .!hJ. ~ 1) Output VOcan never reach exact OV.

z~o { 2
2CVoo -Vtn )VaL -VoL } =
~p
2 (V 00 -IV,pl)
2
Pn,O (Vr,J dVo
2) Power dissipation when V1n high. ...(3.2.24)
%-1 {2 IVT.L l(Voo -Vo) ~ dVTL
V1H = Vr,o+2V. +Pn,o(-Vr,J ¥ , 3) Its a ratioed logic.
- (Voo -Vo)2}
case IV : To calculate V v we assume V 1n ls equal to 3.2.4 Pseudo - nMOS Logic
0
By definition, the slope of the VTC is equal to (- 1), i.e.
VoH=Voo :
dV 0 / dV 10 =- 1 when the input voltage is V;n =V1L· To - Pseudo nMOS inverter gives even better performance
satisfy the derivative condition at V11,, we differentiate In this case, the driver transistor operates in the than the other two that has been discussed so far. Solving the above quadratic Equation (3.2.26) gives :
both sides of equation with respect to Vin· linear region while the depletion type load is in pMOS transistor is used as a load and is biased to be
saturation. always 'ON'.
~.o (Vn - Vu) } ; t
Pno 2
{2CVott-Vro)·VoL -VoL} = ~ ( V J2 - The actual current through the inverter is controlled
2 2 - T,
{2IVr. ti (-d~~) 2(Voo - Vo)(- :: L) -2 (Yoo - V.) (-d~~•)}
+ The Yr Lin then above equation is function ofV •. This
by the nFET driver circuit. This configuration is called ... (3.2.27)

dV
Substituting V1n =V1t and dV;: =- 1, gives
second ;rder equation in VOL can be solved by
temporarily neglecting the dependence of Vr, Lon Yov as
-
pseudo nMOS since like the load of depletion - nMOS
inverter it is also always 'ON'.

Unlike depletion load inverter, pseudo-nMOS inverter

CVoo - v tn ) ± '
✓ CVoo - VuJ - To (Voo - I v,p IJ2
~p

follows : ... (3.2.28)

~
V1L - Yr.o = ~._o {I Yu I- 2Voo + V0 }
load does not experience anybody effect as its source
to bulk voltage is constant and is equal to 0. The load The valid solution for VoL is
(Yott - VrnJ2-ffij (I VrJ
V current in saturation region is given by
✓
~n L
IL = Yr,o + ~n.o (V. - Voo + I Yr,L I}
is function ofVoL· ) VoL = CVoo - Vm) - ( Voo -Vm) 2 -Tn(Voo
~p
-lV,p l) 2
... (3.Z,22 ... (3. 2.23)
Caselll : V1n >V 0 -V 1 , 0
... (3.2.29)
n be For Vin< V,n ,
Input voltage equal to V1H corres pon ds to the point in Th e actual value of the output low voltage ca )
Disadvantages
VTC where slope is - 1. found by solving the two Equations (3.2.21) and (3. 2·2\ M2 is OFF,:. V0 fl = V00
1) It is not possi ble to achieve VoL = OV since the square
Si nce the output voltage corresponding to thi s using num erical iterations. The iteration rne!b~n Since, pMOS provides a path from supply Yoo to Yo·
root term in Equation (3.2.29) can never be equal to
op.eratmg pomt is relatively small, the driver L trans istor converges rapi dly because the actual value of Voi Vin> V,n, M2 is ON . CVoo -V,n ).
ism the hnear region and the load is in satu ration . re latively small.
 Combinational CMos Lo&ic c·
3-9 ltC\in
.
f
• Digital VLSI [MU) _ Therefore , output correspo nding to high input . • Digital VLSI (MU) 3-10
is 10w.
. ce only one transisto r is 'ON' at a time, th eoui,,.
~p Sm .. Combinational CMOS Logic CirCUit
,
ds on - value,
~n ltage level is not depende nt on the ratio ·•111
of ho a. Explain CMOS inverter characteristic mentioning all Static Response
2) Value ofVoL depen .
vo . .
transistor size. Hence, 1t 1s called as ratio less logic.~ regions of operation. lffi1'M•M1¥iMdfid
- S~tic response analysis detennines output V for a
fro m Equation (3.2.29), Explain transfer characteristics for CMOS Inverter
a. given value of Vin• Input voltage Vin varies fro~ 0 to
Comparison betwee n Various fo,._
3.2.6 ""
15 Of showing different regions. What is the effect of Yoo vol~ a~d for each value of V,"' we assume that
Inverters variation in W/ L ratio? syst~~ IS m steady state, that is V• is allowed to
stab1hze before a measurement is made.
Table 3.2.2
The CMOS inverter circuit is shown in the Fig. - DC _anal~sis provides voltage transfer characteristics,
s large driver to load ratio. 3.3.l(a). The input voltage (V1J applied to the common
5 II value of Va.
mean Sr.No. Passive nMOS nMOS
CMOS which m tum tells us the noise margin (voltage
ma k FET more conductive to pull it closer load depletion enhancement Inverter gate terminals of the two MOSFETs M1 and M2, ranges that define logic 'O' and logic 'l ' values).
Wemustma en
to ground voltage. . Inverters type Inverter mode pull up determine their conduction states. - Inverter threshold is an Important parameter in
- 1 b th the transistors are conductin g Inverter Voo CMOS inverter design. This is defined as the point
where the Transfer Current (VTC) intersects the
.
3) When V;n - , 0 .

establishing a path from supply to ground resulting in Depletion type Enhancement pMOS
1. Resister is unity gain line that is defined by V = V1n = V!Nv• Static
0

used as a nMOS modenMOS transistor ~ I power dissipation in CMOS is ideally zero.

power dissipation . used
transistor is transistor is
pull up - From Fig. 3.3.l(a), we find that,
3.2.5 CMOS Inverter device. used as a pull as a pull up
up device. device. ""'••·1
up device,

nMOS Vr,,
Table 3.3.1
VGs.M VGSp (V)
1'1.11 ~Dl11ll•tmm~•~I
1

2. Power Dissipation is Dissipation is Power

a. Explain CMOS inverter characteristics mentioning its -5
dissipation high since rail high since rail to dissipaoon ~ VGsn=V,n
all regions of operation. What is the etfect of changing is high when to rail current rail current flows very less Fig. 3.3.l(a) : CMOS Inverter
-4
Yosn=V.
W/L ratio on it? Explain with example. Vin in high flows when when V;n is high (almost -3
VG,p v,.-Voo= - CVoo -Vi. ) ...(3.3.1)
l1~1•■•-~ll•l1~mn V., is high negligible). pMOS
-2
Vo,p Vo-Yoo= -(Voo-Vo) ...(3.3.2)
3, Full rail Full rail output Vout can never Full railsv.i~1 VGsp= Vin- Yoo -1
Fig. 3.2.10 shows a CMOS inverter circuit. It is built is never reach V00 if Vss is obtained al VG,n Yin
output is
using a nMOS and a pMOS transistor . achieved Vout = V00 which is output. Vo
Vosp=V0 -V 00
never Vo,n
- In steady state only one of the transistor is 'ON' other achieved can never normally the
Characteristic of a digital logic circuit involve both First of all we will draw output characteristics of
being 'OFF'. Therefore , there is no direct connection reach full Voe . case
static and transient response analysis. Static response driver (NMOS) transistor and then on the same graph,
between power supply and ground for steady state 4. Large space Space Space Space analysis is covered in this section followed by the will draw the output characteristic of PMOS. Only in this
input requirement. requirement in requirement is requirement fl dynamic response analysis. vd,p = v. - Yoo·
less. less. lesser than
- For low input voltage pMOS transistor is 'ON' while
resistance
nMOS is 'OFF', hence forming a connection between load inverts.
power supply and output node, bring output level
'high' (outp ut capacitor is changed). 5. Extra supply Extra supply Require an extra ExtrasuppY
Yoo rail is not raid is not supply rail VSS· Point of Intersection lvos,,= V1
of curv99 when Vos= 3V
required. required. and Vasp = -2V L-.U....~ -.....::..:: ._c--~t\- --1- curve labelled 4
lsfor
Vosn= 3V

'•{~,. DC Characteristics of the CMOS

3.3 Curve labelled d is for
Vosp= -2V
Inverter
I Voo

QJeil@MflHiiMiti I
Vosn_....
0. Draw voltage transfer characteristic l o ~
Fig. 3.2.10 : CMOS inverter circuit
and explain all regions. ■MIM1i . I Vd1p Is on ~ght hand side ol IOp axis
- For high input voltage nMOS transistor is 'ON ' while Q.
r w1tn
1~ as Vdlp = V0 - Voo

.,
Explain operating regions of CMOS
pMOS transistor is 'OFF', thereby providing path for equations ■Mi•M•&W" 1 • Fig. 3.3.l(b)
output capacitor to discharge,

~
...~ ~ \I 0111
 Combinational CMOS Logic Circuit
3-11 if Digital VLSI (MU)
-12
Then, ~gion of operation n-device Combinational CMOS Logic Circuit
~~~--==== =---Vrp=-lV, Voo =5V p-device
V = 1V, v: = f (Vin + £\ Vnoise)
1---
.. Yott = Yoo -
VGsp <V,p ... (3.3.3)
3V than Vcsp = V1- Voo 2) Region B . As in
Jf Vcsn = dV0 V
= f(V1nJ+v;;:-L \ noise Vin< V tp + Yoo . put voltage in increased beyond y
3 -5 Saturated
Vo,n > VGsn- Vin Vosp < Vc,p- v,p the nMOS transistor starts conducti . tn '

+ Higher order terms Neglected d ng in saturation

= - 2V
nds to curve marke
d as '4' and
. ~ ~>~-~ ~<~-~ mo e and the output voltage begins to d
[Vo > (V _ ecrease
....This correspo 'd' respectively. Higher order terms are neglected . Therefore, c, o In Y,h )] pMos transistor is still in non-
Fig. 3 .3.3 Shows the five regions named A, B,
0, Vou1 =Voo, lo =O
v: = Nominal output+ Gain x external noise and E. sa turation mode of operation. Note that the critical
For V,n = nMOS is off voltage V1t is located Within region 8. V1L voltage
i.e. Vcsn = OV, fV "fG • _ dVo < 1 (not amplified)
Hence, 1 am - dVin corresponds to the point in VTC where the slope has
_ 0 ...for every value o osn:
Ion - marked as '1 • a value of-1. That i s ~ - 1
this corresponds to curve Then, v ~ = y 0 + small quantity dYin -- .
. ·on of these two curves is at Yoo
h Since nMOS transistor is in saturation.
The point of mtersecn . tersection is marked which dV0
Otherwise, if dVin » 1 t en
on X-axis. Similarly each m . t voltage gives Voltage
when ploned with respect to mpu
v: = v 0 + large quantity
Ion = z (Vin - v,n l '
~n
... (3.3. 4)
Transfer Curve (VTC) of inverter. VTC .
Fig. 3.3.3 : Inverter VTC pMOS transistor is in non-saturation, therefore
The VTC curve obtained is shown in Fig. 3.3.2. IS
Hence, boundary is set in between two quantities current through it is
a plot of V0 as a function of Vin· 1) Region A: Region A corresponds to the region where
above as ,
nMOS is off and pMOS is in non-saturation. lop = ~p[ CVcsp - I vlp I) Vo5p-½vo!P] ...(3.3.5)
Vo dVo =-1 dV 0 = 1 (Unity gain)
dV;n dVin Vin < Yin
Voo = VDD Substituting Equations (3.3.1) and (3.3.2) in
The entire VTC curve shown in Fig. 3.3.2 can be Therefore, M 2 is 'off and M1 is 'ON'. Equation (3.3.5), we get
divided into five regions based on the conducting states Now, VGSP = - CVoo - v,n)
of the two MOSFETs. = ~p [CV1n-Voo-V1p)[Vo-Voo l-½(vo-Vool' l
Vosp = - (Yoo-Vo)
Table 3.3 2 . Region of operation of pMOS and nMOS ... (3.3.6)
Vosp > VGSP - v,p
Region pMOS nMOS
➔ : . M2 is in non-saturation .
A Linear Cutoff :. M2 is 'off, output voltage is equal to V0 0 .
B Linear Saturation equating Equations (3.3.4) and
Fig_3_3_2 : VTC plot of CMOS inverter Current through the MOSFETs are equal as they are connected in series. Therefore,
C Saturation Saturation (3.3.6) we get,
- The output voltage VO is high when input voltage V1n 1
D Saturation Linear Pn
is equal to or smaller than V1L where, V1L is the 2 (Vin - vtn )
2
: pp [CV1n - Yoo- v,p) CVo- Voo )-z(Vo- Yoo )2] ... (3.3.7)
maximum input voltage which can be considered as E Cut offLinear
logic 'O'. . . aions of T0 V dVO . 1
Table 3.3.3 given below outhnes various re,,. get 1u we find~ at Y1n = V1Land then equate 1t to - .
- At V12 the output starts fall ing towards low voltage
operation for the nMOS and pMOS transistors.
value. The slope at this point (corresponding to V1J
th
as shown in Fig. 3.3.2 is un ity. Table 3.3.3 : Relations between voltages for the ree
regions of operation of a CMOS inverter
- Similarly, the output is low for input equal to or layer 1

than Vitt; where, Vitt is the minimum input voltage Region of operation n-device p-devtce
y Gsn < Y,n YGsp > V,p
which can be considered as logic 'l'. Also, the slope is
unity at point corresponding to VlH· Cut off Yin< y tn Vin >V,p + Vvo Substituting Vin= vlL and ~~o = - 1, we obtain
in
_ _-+-Y-Gsp < V,p
- Since, output is functi on of the input voltage y1n, if the I r - - - -- - -1-_:::__..:::_
i_nput is di stu_rbed from nominal value due to external YGsn > Ytn VD Pn (VJL-V,n) f\ [(Vi t -Voo- V,p ) x -1+ CVo-Voo )-(Vo- Voo) x -1]

mII uences lk I e' noise output voltage Vo wi ll also Non- saturated Yin > Y,n V n<V1
1 Vp+ -D ' v~ Pn (Yit-V,n) PP [(V 1t-V 00 -Vtp) +2(Vo-Voo) ]
Yo,n<YG,n-Vtn Vo,p > GsP
change to sayVo. pp Yoo + v,p pp_ pp VI L+ 2 Vo pp - 2 Yoo pp + Pn vtn
V > Vin' V,p
Vo <V;n-Ytn ° ~
_-_-_-_-_-_-_-___...J...._-.:._=--_-_..::.:._-_-_-~~- ·~~.... /
 Combinational CMOS Logic Cir%
3-13 " ' Digital VLSI (MU)
3-14
Combinational CMOS l ogic Circwt-

1
+ZV f3 _zVoof3P+f3nV'" - Sup~ose the input to the inverter is a step input v,
tp Op
AV +2f3pV0 -2Voof3p (t) Fig. 3.4.Z(a), which is changing its level from OV t~n
tp + P'n Ul Yott Cut-off
Yoo· Therefore, it is going to change the operating of
f3n + [3p VoL Linear MOSFETs also accordingly.

zv.+(t) Vm ... (3.3.8)

V;H
VI L
Linear
Saturation
f3n/f3p) Noise margins are:
pMOS - saturation 1) NML = V1L-VoL =V1L-OV1L
3) Region C OS 2) NMtt = VoH - vlH
It e decreases further, the pM Equating ID,n = - ID,p
As the output vo _ag tion region of operation Pn
VDD+ v,p +T(2 v + v )
. enters into satura
~ [2 CV1n- Vm) Vo - =-+ [
f3 Fig. 3.4.1 : CMOS inverter showing capacitive load

✓-1;: · "
::;s~:~ndary of region C. Both the transistors are v! ] VG,p - v,p]2 ... (3.3.IS) = VDD- v,n(t)
in saturation region at this point Voo f------r- ~

Equating the current flowing through the two Putting VGsp = V1n - VDD , we get
The derivations shown above illustrate the
transistors gives, f3n 2 -~ importance of the MOSFET aspect ratio in the DC
[2(V n -V,n)V 0 -VJ- 2 CV1n -VD0-Vrp)2
f3n
7 ( V; - V,nJ2 = -
f3P y )2 ... (3.3 .9) 2 1
behaviour of the logic gate. We have seen that the ratio
0 2 (Vin-Voo - tp ... (3.3.16) f3n / f3P determine the inverter ratio (Equation (3.3.13)).
Inverter threshold V1Nv is defined by th e point where
This dependence is illustrated in the plot of Fig. 3.3.4.
the voltage transfer curve intersects th e unity gain Differentiating sides of Equation (3.3.16) with respect Vaa-V,h
Vo
line. It is very useful parameter that characterises the to V10 gives ;
Yoo \
entire VTC. It is located in region C where, Yin= Yout •
f3n [ dV 0 dV 0 (i) Step input (ii) Output waveform
Solving the above Equation (3 .3.9), we get -
2
2(V;n -V,n )dV+2V0 -2V0
In
dV tn
]

Fig. 3.4.2(a)
,/f.(V;n -Vml =-~(V;0 - V00 -V,p) Increasing
...(3.3.10)
P.,IPp Let us start with fall time calculation. The Fig. 3.4.2(b)
V; ( ~ + ~ ) = ~ (Voo +Vcp ) +-,ff. Vm ... (3.3.11) shows layer view of the output level transition from high
0

...(3.3.17) 0 e;.__----.-.L...::::,,. ;:;,~----,>--+ V1n to low value.

Divi ding Equation (3.3. 11) by ~ , we get,
Yoo
Fall time (tr) is defined as the time required for the
Y;n (1 + ✓f3 0 / f3P) = Yoo + Yep+~- Vm ...(3.3 .12) - -~
Substituting dV,n = -1 and V10 = V 1H, we get, Fig. 3.3.4 : VTC curve of inverter
output voltage to drop from the 80% to 10% of its steady
A symmetrical design with f3n = f3P gives V1NV = V00 /2
state value.
Voo +V,p+ ' M · Vm (Equation (3.3.14)). Increasing the ratio f3n / f3p results in
... (3.3.13) At the beginning of the discharge nMOS is saturated
V;n = V1NV = ---1-+-~- r=: - - reduction of VINv value. (From Equation (3.3.13)).
since Vos is greater than VGs - Vrn· Therefore,
- f3n V1H + f3n Vtn + 2 VO f3 0 = f3p V1H - [3p (V DD + Vtp ) 3.4 CMOS Inverter Switching
By setting f3n = f3Pand Vm = - Yep, we obtain
(f3p + f3J VIH = f3n (2Vo + Vm) + 13P CVoo + v ,p ) ... (3.3.18) Characteristics
... (3.3.14) Dividing Equation (3 .3 .18) with 13P gives,
Dll@#11M•MMN
4) RegionD

When the output voltage fa lls below CV1n - Vm ), the

VIH - _ _ __ ...... _c......,.____ . .
_ VDD +V,p+l3 0 /l3P (ZV 0 +V 01 )
(3.3.1 9)
Q. Write short notes on : Switching characteristics of
CMOS inverter. m•■•N€ii1,mn
nMOS transistor starts operating in the linear mode l+13n/13p - The Fig. 3.4.1 shows a CMOS inverter gate with a
while pMOS is m saturation. This corresponds re . capacitive load CL, which represents the load
5) RegionE
~VVIH is also located in this region at the point w~e:: capacitance. Fig. 3.4.2(b) : Expanded view of output waveform
With mput voltage y > (V + y ) the ptJOI
dV;" = -1 . - The switching speed of the CMOS gate is limited by
transistor Is m cut i~ff whffe nM~S , is in non·
the time taken to charge and discharge the load
nMOS - non saturation saturation region.
...(3.3,20) ~acitance CL.
YoL = OV

-----~
 3-15
" ' Digital VLSI (MU)
3-16
. . Digiral 1·LSI (MU) ·cor Equation as, . ..,(3,4_,)
Combinational CMOS Logic Circuit
Discharge is
. described by the capac1

I = - Caul
on
dV.
dt
...(3.4.1)

tput voltage Voo - Vin)

intervals :
1)
. .
h f II
From Fig. 3.4.2 it is clear t at a time consistoft:\v

- Time during which capac1t1ve voltage drops fr

O
Jt is . clear from the above expression that delay is
proport10nal to _the load capacitance. Also delay is
Inversely proportional to f3. (i.e. w. /
L.J of the driving
:tate rising input voltage and time for output voltage to
rop 50% of its steady state value.
(
. (corresponding to ou tn V to v O _ Vm. During this time nMos op 01li transi s tor. Thus as the width of the transistor is
At nme t, t d Therefore, 0.9 DD o . erates
nM 0S is nonsatura e p Vz in saturation region. increased the delay for that transistor decreases.
- ~ [2 (Voo - V°' ) Vo - o) . . . . Rise time (t,. ) - Rise time is defined as the time to
Ion - 2 _ V ) to 0.1 y 00 . Dunng this time nMOS 1s operatj .
·t r voltage drops from CVoo '" ng1n required for the output voltage to rise from 10% to 90 %
2) tr. . Time during which capac1 o of its steady state value.
n~nsaturation region. ...(3,4.3)
t,- = 1:n + ta t,.= Rp Cout ,1
0.9 Yoo d Vout
2(IV'PI-0.1Vo )+/n(20(V00 -1Vtell ) ]
Voo J- tn ~ + Caul ~ j ... (3.4,4) [ Yoo -1 V,p I V00 - 1
= Cout Ion (non-sat) Yoo - to
0.1 Yoo
... (3.4.8)
Let us represent 0.1 Voo with Vo and 0.9 Voo with V1, V1
Where,
f3p CVoo - I v,p I)
J ~
1100 RP =
~ Vo, ~ + Cout ... (3.4.S) ,1
t,- = Cou1 J 100 (non-sat) Yoo_ Vin 1on (sat) For equally sized n and p-transistors, where,~. = z~P
Vo then ~ ~~ i +-
v00 - V01 VJI d Yout
1PHL 1PLH
dVout C
f f3 / ...(3.4.6)
Cotrt Vo ~"/z
- - ~ ~ - - + out
[Z(Voo -Vrn )Vout -Vo~t] Voo-Vtn n z(Voo-VmJZ (a) Ideal step input waveform
Fig. 3.4.3
(bl Output waveform
Thus, the fall time is faster than the rise time for
equal size transistors, this is essentially due to different To simplify the analysis and the derivation of delay
carrier mobilities of p and n-devices (µ. = 2~ ). expression, the input voltage waveform is usually
Therefore, inverter with equal rise and fall time assumed to be an ideal step pulse with zero rise and fall
requires ti mes. Fig. 3.4.4 shows the propagation delay times with
a typical step input voltage.
V;n

This implies that the channel width for the p-device

Voo ····-· · - -- r - - - - - ,
must be increased to approximately two to three times
that of then-device. 50% ·-··-
Propagation Delay

The propagation delay time tP determines the

average time needed for the output to respond to a
change in the input logic state. voo,
tPHL + tPLH
tp = - - 2 - -

Where, tPHL and tPLH represents input to output

signal delay during high-to-low and low-to-high
tra nsition of the output respectively.
lo 11 12 13
Fig. 3.4.3 shows the input and output waveforms of a
(a) Typical input waveform (b) Inverters output
... (J,4,7) typi ca l inverter circuit. By definition, tpHL is th e
waveform
difference between time corresponding to 50% of st eady Fig. 3-4.4
 3-19 • Digital VLSI (MU) 3-20
Combinational CMOS Logic Circuit
1 is grouped, it This is because of the fact that when the two series Pull up and_ pull down networks are dual of each
-
connected MOSFETs are 'ON' it results in passion 'o' other. That Is a parallel co nnection of transistors in
an OR equation A+ ii . logic to the output and for remaining combination the pu~I up network corresponds to a series
d by connecting two p-MOSFETs are passing a logic '1' (Refer Fig. 3.S.3(b) connection of the corresponding devices in the pull
t ca n be implemente
truth table ofNAND) . down network and vice versa.
MOSFETs in parallel.
(c) K-map of NOR gate It implies that for a given inverting expression the Let us see how to design f = (A. B) + (C . D) .
(bl Truth table
Fig. 3.5.6 pull down network can be built by applying the logic
- The above expression Is in inverting form, therefore
that whenever there is an AND operation n-MOSFETs
For implementing the pull up network, the l 's in the PDN can be implemented by connecting nMOSFETs in
are connected in series and for OR operation they are
K-map are grouped together which forrn K-11tap series whenever expression contain AND terms and
connected in parallel. transistor r connected in parallel whenever th ere is
Fig. 3.5.4: K-map of NANO gate
(Fig. 3.5.6( c)) clearly yields an equation A- B. This _ Pull up network is an complementary network and OR term s.
Function (A+ ii ) produces logic 1 if either Aor B has yields an AND function. Therefore, two p-MOSF£'rs can be directly realized by just connecting p-
value equal to Oor if both A and B has value 0. We need to be connected in series. MOSFETs in series if n-MOSFETs were connected in
know that p-MOSFETs become ON and pass the logic parallel in pull down network and vice versa.
For pull down network, grouping the O's in the k-11tap
present at its one terminal to other wh~n OV is
gives the OR expression A + B. This can be
applied to its gate. Therefore, A + . Bcan be 3.5.4 Static CMOS Design
implemented by connecting two n-MOSFETs in
implemented by connecting 2 p-MOSFETs m parallel.
parallel. The circuit for 2-input NOR gate is shown in - The concepts that were discussed above can be
To obtain O volts at the output, the pull down Inputs{
Fig. 3.5.7. carried over to more complex logic gates
network has to form a path fro m ground to output by
Voo implemented using the same circuit topology.
switching ON appropriate transistors. Vss
From the truth table on grouping 0, we get - Static CMOS circuit implies that at every point in time
Fig. 3.5.8 : Structure of static CMOS circuit
expression A-B. This yields an AND operation. except during switching transients, each gate output
Therefore, two n-MOSFETs must be connected in is connected to either V00 or V55 via a low resistance - For the above expression, A • B and C • D can be
path. implemented by series connection of nMOS
series. Thus, 2-input NANO gate is implemented by
softwares. ORing of these two terms is accomplished
combining the two ci rcuits. - A static CMOS gates consist of two networks pull up by connecting the two structures in parallel.
Voo and pull down networks. Since nMOS transistors
- For PUN the series connection of transistor
produces strong zero, pull down network, and corresponds to parallel connection of corresponding
consists of solely nMOS transistor. device and vice ve rsa.
- The pull down network conditionally connects the Yoo
output to ground. Similarly, pMOS transistors passes
Fig. 3.5.7: Circuit diagram of 2-input NOR gate
strong l's, therefore pull up network contain only p-
3.5.3 Complex CMOS Logic circuits MOSFETs.
Rules for constructing pull up and pull down
- A compound gate is constructed by using a networks :
combination of series and parallel switches structure.
- Pull Down Network (PON) is constructed using nMOS
We have seen that implementation of 2-input NANO
devices only, while pMOS are used in Pull Up
Fig. 3.5.5 : Circuit diagram of 2-input NANO gate gate has an logical expression ~ . So it consists of Network (PUN).
3-5_2 NORGate 2-nMOSFETs connected in series in pull down - An nMOS switch closes when controlling signal is
network and a complementary circuit in the pull up high. pMOS switch on the other hand, closes when the
- A NOR gate _produces a high output if all its inputs are network. controlling signal (voltage applied at gate terminal) is
at low logic level. Fig. 3.5.6(a) shows the logical low.
symbol and truth table of two input NOR gate. - Al th0 ugh A· B indicate an AND operation and utilizes
two n-MOSFETs in series but the complete circuit - Series connection of switches corresponds to an AND
~==D-v 0 realized by combining pull up and pull down gives an operation and a parallel connection of switches is
equivalent to ORing the inputs.
Fig. 3.5.9
NAN Doperation.
(a) Symbol of 2 input NOR gate
 Combinational CMOS Logic Circuit
3-21
. . Digital VLSI (MU) . (Size all the transistors so_that rise and fall tirne of the
if Digital VLSI (MU)
. functions using static 3-22
Ex. 3.5.1 : Implement the following output of function is eqmvalent to s~ndard CMos Ex- 3.5.4 : Implement using CMOS inverters. Combinational CMOS Logic Circuit
CMOS technology. inverter with pMOS width ZW and nMOS width W). 3.6 FET Sizing
F=A-8 +C
Voo
(l) 11 = ~ and
DI!Mlii&Mi1~ml - It is common to design a gate to have the desired
(2) f2 = a+ (b + c) . d
Yoo B"4 Sofn.: A - B+C tranSient times, and then check the DC voltage
transfer curve to insure that it is acceptable. This
approach is based on the fact that the individual
(A · B) + C (A · B) ·C nMOS and pMOS transistors aspect ratio determine
the switching response.
(A · B) · C - Value of fln / flP gives Vrnv (midpoint voltage) of the
inverter, rise time and fall time also depends on fl.
and flP values.

- An approach to select aspect ratio of gate is to use the

inverter as a reference and then attempt to design
other gate that have almost the same switching times.
l-A Since inverter is the simplest circuit, it can be built
using relatively small number of transistors.
- Fig. 3.6.1 shows an inverter with device sizes
specified by flP and fl •. These set the rise and fall
Soln.: times for the circuit, which serves as the reference
switching times. Since both the transistors drive the
(1) f 1 = a+b -c (2) f 2 = a + (b + c) · d Fig. P. 3.5.2
Fig. P. 3.5.4 same capacitance, the difference is in the resistance
Voo values ;
Ex. 3.5.3 : Implement the following function using CMOS Ex. 3.5.5 : Implement following function using CMOS.

gate F = (A • B + C •D) E F=AB +AC +AB

IM 1M•Mli-ii1tttid
Soln. :
Soln.:

Voo
f = AB +AC+AB = AB +AC +AB
= AB . AC . AB =(A+ B)(A +C)(A + B) Fig. 3.6.1 : CMOS inverter
Voo
1

A symmetrical inverter has,

fln flp

Fig. P. 3.5.1
Fig. P. 3.5.l(a)
µ.c •• (-n ~c•• ff)p
Ex. 3.5.2 :
Soln. :
Design the function using CMOS logic. ff) p
t(·fl.
_ Mobility of nMOS transistor (µ,, ) is 2 to 3 times
greater than the mobility of pMOS transistor µP .
f = A + (B + C) . (D + E)

Fig. P. 3.5.5
- - Fig. P. 3.5.3 ~ ------------
- -------.--~~.~
 _ Combinational CMOS Logic CirC!iit
3 23
i, Digital VLSI (MU) 3-24
. . Digital VLS I (MU) - Th e drives circuit contains ~o n_Mos transistor .

(-n
Combinational CMOS Logic Circuit

ff)p
1 Consider t he driver ci rcuit first. Th e worst case
. Since the worst case situation is When n
i.e. z
3
discharge path is through two series connected nMOS
For t he series connected z nMOS transistors, the total
;:::~tor c;ntributes to the fall time. only l resistance would be
lues to find the device size f3 p and transistor on right side of the circuit. The sizes would
Let us use : ,:s~n;:t NAND gate with the philoso phy :. 13N : 13n RPI + Rp
be
~. for the hieve similar size and fall times. Th e series co nn ected pMOS resistances add to a total RP = RPI + Rp
that we wa nt to ac . . . ram of a two input 13N = 213n
Fig. 3.6.2 shows the nrcmt d1ag of2Rp. From Equation (3.6.1) we get,
_ The D input FET is alone so that we can select its size
NAND gate. .
. arallel pMOS transistors first. Smee the as being the same as for inverter.
Consider the P . . when only one transistor 13r (Voo - I vtp I) f3p CVoo - I v,p I)
13NI = 13n
worst case s1tuthao~~e i~me we may select the same Value of R
contnbutes to e ' For the load circuit, there are two paths for V0 0 to get
size as the inverter.
Where, connected to the output. One through two series
f3p : f3p 13N CVoo - vtn)
connected pMOS transistors on the left side of the ~Pl (Voo -1 V,p I) 3 f3P (Voo - lV,p I)
The actual rise time t,. " ~II be longer than that of Using the inverter as a reference, we set circuit and other through series connected nMOS
inverter circuit because output capacitance Cout IS
R Rn
transistors on the r ight side of the circuit ~p ½ ~ Pl
larger.
- The worst case situation for load circuit would be for
The series co nnected nMOS transistors chain has to 2 RN
the 3 pMOS in series, the total resistance woul d be
f3 p1 ½ ~p
be modelled as two series connected resistors 1
between the output and ground with a total. f3o (VDD - V,n) 13N CVoo - v,n) 3.7 Solved Problems
Yoo
i.e. f3 N 213n i.e. RP = 3 Rp ...(3.6.1) Ex. 3.7.1 :Find the ratio ~n I ~P needed to obtain an
Voo inverter voltage V 1Nv (mid point voltage) of 1.3 V with power
That is, the ser ies connected nMOS trans istors are
supply of 3V. Assuming V"' = 0 .6 V and V t? = - 0.82 V . What
twice as large as the inverter transistor.
would be the relative device sizes if t~ = 110 p.AJv2 and
llp= 3flp
mobility values one related by µ,, = 2.2 µP .
Sain. : VINV 1.3 V
vout ~ llp= 31lp
Voo 3V, vtn =0.6 V, v,p=- 0.82 V

f ~
N
V 00 - IV,pJ+ ~ -V"'

3.6.1
Fig. 3.6.2 : FET sizing relative to inverter

2-Input NOR Gate

VINV
l+ w,
-
p

w,
N

- Two input NOR ga te can be designed in the si milar

manner. Fig. 3.6.3 shows the circui t diagram of a two u(1+~) 3 - 0.82 + 0.6 ~

w,
input NOR gate.
Yoo
Fig. 3.6.4 o-t
The resulting fall time tr will be larger in the 2-input 0.7 ~ 0 .88
1--c
NAND gate becau se of the la rger output ca pacitance aod
FET-FET internal capacitan ce.

2f3p
w, p
0 .88
0.7

13n
1.56
(-¥) p
2(f) p
Fig. 3.6.5 13p

Th e two asp ect ratios are related by :

Com plex logic gates can be designed in the saJlle 13P (Voo - I v,pI) f3p(Voo- l V,pl)
manner. Consider the gate that h as an outpUI
express ion : f3p 3(3]1
Fig. 3.6.3 : FET sizing with inverter as reference

D +A · (B + C} .
~-- - ----.-=!•~.~~
 Combinational CMOS Logic Circuit • Digital VLSI (MU)
3-25
~ 3-26
• Digital VLSI (MU} Soln. : Combinational CMOS Logic Circuit
... given Ex, 3.7.4 : The pass transistors followed b .
2.2 µp ~
µ,, V00 + V,p + ~ (2 V + Vtti)
0 shown below, find the voltages at different . Y inverter is
ii points x, Y, and z (½t (~)
ID
(f )p
x 22 =1.56
.
1+~
~p (i) VA=5V, V8 =Vc=V 0 =3.5V
(½)
nlnv
~('!!._)
L
Iv

Plnv
= 2
1.8- 0.5 + (2V9 + 0.5) (ii) VA=V 8 =Vc=V0 =5V (f ) 2('!!._)
(n = 1.39 ( f ) n
= 2.1 mA//
2
1.8 + 2V 9 _
sv
nhlv
=
L
Voo
Plnv

. VIH = 2 -0.9+Vo B C D
Ex 3.7.2 : An inverter uses FETs W1th ~"
.
and ~P = 1. :v _·-
8 Atv2 The threshold voltages are given as
O 7 V respectively. The power supply
V1n = 0.6 V anf Vt!> -_ 5 ~ The parasitic capacitance at the
Substitute the above expression of VIH into KCL
A ~ V ,
_I'~(~).

~~H~t
. Equation (3.3.16) to obtain a second order polynomial in
has a value o oo - ·
output node is estimated to be CFET = 74 F. Calculate nse Vo.
and tall times at the output when CL = O ?
~
2 [2 CV1n - Voo- Vtp)]2 Fig. P. 3.7.4
Soln. : Rise time and fall time in approximated as Fig. P. 3.7.S(a)
CL Soln.:
ti = k x ~ n Voo z(V0 + 0.9 - 0.5) V0 - V~ CVo+ o.9 -1.8- o.5) 2 Using this as reference 2 i/p NANO gate is designed
as follows :
CL CVo - 1.4)2 ·: nMOS is poor passes of high logic there will be one Voo
t, = k x ~Px Voo
threshold voltage loss.
V~ - 2.8 V 0 + 1.96
Where, k = 3 to 4 for values ofV 0 0 = 3 to 5 V
Let us say M 1 can pass upto X1 voltage, it can be
andV.,;, = 0.StolV. 3.6V0 1.96
determined from the fact that for nMOS to be ON, VGS has
3 x 74x 10- 15
ti 2.1 x 10- 3 x s 0.54V to be minimum V, voltage
:. V GS = 3.5 - X1
-I (~~ = (~)~. 1/2
21.14 ps From this, we can calculate the critical voltage V1Has

t, = 3 x 74 x 10-1s =24,67ps V0 + 0.9 = 1.5 V Equating their to V,

l.8 x 10- 3 x s

Ex. 3.7 .3 : For the CMOS inverter, let the supply voltage
-V 00 + Vtp + 2V 0 + (t)vtn 3.5-X = 1.5
: . V, = 2V i.e. it can pass upto (VG- Vu,)
V 00 = 1.8 V, the threshold voltage for both nMOS and pMOS
1+ in Now for znd MOSFET, Fig. P. 3.7.S(b)
transistor Vth = 0.5 V. Both the transistor are matched ~p
Consider first p-MOSFETS. Since worst case situation
exactly such that ~" = ~p- Find the unity gain points (the
VGS = 3.5 - zv = 1.5 V
- l.8-0.5+2Vo+0.5 =Vo-0.9 is when only one transistor contributes to rise time, we
values of input voltage V1L, V1H and corresponding output : . It is ON and can pass entire 2V to point Y and
2 may select the same size as inventor.
VocJ of the inverter characteristics assuming that the inverter
is not loaded.
similarly to z. The series connected n-MOSFETS chain has to be
modelled as two series connected resistors between the
Substituting the above expression in Equation (3.3.7) v. ZV, Vy= ZV, V, = 2V
output and grant
(ii) v. v,. = 3.5 V
~ (Vin -Vu,)2
VG- R RN+RN
~p[ (V,. -Voo -Vq,)(Vo-Voo)-½(Vo-VooJ2]
V, Vy =V, = 3.S V R 2 RN
(Vo- 0.9- 0.5)2 2{(V 0 - 0.9- 1.8 + 0.5) (V 0 - 1.8)- (Vo- 1.8 )} R
Design a CMOS NAND gate (two Vp) which is RN 2
~ - 3.6~
Ex. 3.7.S:
V~ - Z.8V 0 + 1.96

V~ - 2.8Vo + 1.96
2 { (V 0 - 2.2)(V 0 - 1,8 ) _

ZV~ - 8Vo + 7.92 - V! + 3.6Vo- 3.24

9+ 3.24 }
equivalent to the CMOS inverter with KA= 2·

Soln. : For inverter :

Uv\ ½(~t
l.6V 0 = 2.72 2ffi
L Inv
ffiN
V0 1.7V

.', VIH = V0 -0.9: 0,8V

------- -----
 _- - - = = = = = =_;C:o~m~bi:n:at1:·o~n-al_c_M_o_s.;;;L~ ogi~·c c·lrC\lit
17 if Digital VLSI (MU)
Solving the above Equation gives,

0.66 V~ + 0.05 Vo - 6.65 = 0

=--;~~~~~A"~~;]u====
Cr)n
(w)
43·2r8==~~~~~==~~~~~
~
p
µ,, cox
NML
Combinational CMOS Logic Circuit
vlL -voL = 1.69- ov
Only one root in with Vo > 0 P ~co, p p
NML 1.69V
:. v =
r 0
3.14 V
Substituting the value of Vo in Equation (1) gives,
NMH
NMH
VoH - Vrn = 5 - 2.43
2.57 V
V1 L 0.57 x 3.14 - 0.77
Though V,n V,p, but Pn ,t. PP :. inverter is not Ex. 3.7.8: Design the circuit in Fig. P. 3.7.8 below to
1.01 V
symmetric obtain a current 1o of 0.4mA. Find the value required for R

-12/1
Pn
Voo +V,p+ f(2Vo+Vtn) -Yoo + V,p + 2V0 + (t)
p V
tn
a nd fi nd the de vottage Vo, Let the NMOS transistor have
2
Vr = 2V, µ,, Cox = 20 µ AN , L = 10 µm and
1+~
pp 1+ (t) w = 100 µm . Neglect the channel length modulation effect.
(i.e. assume,. = O).

:r~r
Fig. P. 3.7.S(c) 3.3 - 0.7 + 2.5 (2 V9 + O.~ 0.57V0 - l
1 + 2.5
Consider a CMOS inverter circui1 with the Substituting this in Equation (3.3.7) gives,
Ex. 3.7.6: VIH 1.43 V0 + 1.11 ...(2)
following parameters :
Substituting this Y;n = VIH in Equation (3.3.16) ~ CV1n-V..J 2
= ~
Voo = 3.3 V Vrn = 0.6 V,

VII> = -0.9V p
T[2(V n-Vtn)V
1 0 -V
z] = ~2
0
[Vin-Yoo-Vtp]
2
[ 2 CV1n - VDD - V1p) (Vo - Yoo) - (VO - v0 0/ ]
. • :i ~n
K,, = 20Dµw./, t<i, =80µA/V •°ii;=2.5V Yin = Y1L=0.57V0 -l

Calculate the noise margins of the circuit.

200/ A [ 2 (1.43 VO+ 1.1 7 - 0.6 ) Vo - V !] 2.5 (0.57 V0 - 1- 1)2
Soln.: 80 µA 2 Fig. P. 3.7.8
= (1.43 V0 + 1.171- 3.3 + 0.7] = [ 2 (0.57Vo- l-1-5 + 1) (V 0 -5)-(V 0 -5/]
OV 2
Vo1 Soln. : Because V0 e = 0, the MOSFET is operating in the
3.3 V Solving the above equation gives , Solving the above equation, we get saturation region. Thus
VoH

½µ,, Cox f
V0 4.72 V
V0 = 0.27 V 2

pp --
A. 2.SV ... given lo CVes - VT)
0.57 X 4.72 - 1
Substituting this V0 in Equation (2) gives,
VIH 1.43 x 0.27 + 1.11
1.69V 0.4 ½ 20
X X 10-
3
X \
0
°
0 (Yes - 2)2

V1H 1.49 Which yields two values for Yes, 4 and 0. The second
Yoo+Vtp+(tJ f2Vo ;Vin ) value obviously does not make physical sense since it is
NM L V1L- VoL = 1.01 - 0 = 1.01 V
Substituting the values VoH - VIH = 3.3 - 1.49 = 1,81 V
1+ tpp lower than VT. Thus Yes = 4 V, and the drain voltage will
NMH be
- 3.3 + (- 0.7) + 2 V0 + 2.5 (0.6) 5-1+2.5(2V0 +l) V0 = + 4 V

VIL 0.57 V0
1 + 2.5
0.77 ... (1)
Ex. 3.7.7 : For a CMOS inverter if { ~} n = ( t )P' 1 + 2.5
The required value for R can be found as
-
VIH 1.86 + 1.43V0
Substituting V;n V11 = 0.57 Vo - 0.77
' the value of
find i°"" ' margi~~ -
p and compute the noise
Substituting this in Equation (3.3.16) gives,
R
Yoo - lo 15 - 4
-1 o- =lJ.4
. P V - _ JV,
in Equation (3.3.7) Iollowing specification V00 = 5 V, V1n = 1V, 1p - R 27.5'2.
2 2
µn = 580 cm / Vs, l!p = 230 cm / Vs .
ti2 [2 (V In - VmJ VO - V O] =
2
zPr (V;n - V DD - Vtp) z
Ex. 3.7.9: Design the circuit with resistive load (given in
Soln.: 25 2
· [ (1.43V 0 +l .86-l)V0 -v !] Fig. P. 3.7.9), so that the transistor operates at 10 = 0.4 mA

200µA
[ 2cv., -voo - V1p) (Vo - vDD)-l(V
2 o -v DD )2]
Pn ~cox efl" :. Weget,
[1.43 Y0 + 1.86- 5 + 1) and V0 = + 1 V. The nMOS transistor has V, = 2V,
0
2
µ c 0 , = 20 µ AN , L = 10 µm and w = 400 µm . Neglect the
2 [0.57 V0 0.71- 0.6] = ~ 0.398
channel length modulation effect. (i.e. assume '),, = 0)
µr cox(1)r
-

Pr VIH 1.86 + 1.43 Y0 = 2.43 Y

[ 2 (0.57 Vo- 0.71- 3.3 + 0 7) (V
' o- 3.3)-(V0 -3JJ2]
 3 29 • Digital VLSI (MU) 3-30
~
CM
na""l""""""OS..;L~ogic c
=.; ~ :i;~ = = = = = =C=om=b:i:na~ti""o""
~ ~~~ ~~'v 7:~' F== === Combinational CMOS Logic Cireuit
T_

Soln. : VDD
Digital \/LSI (MU) Voo = 9V 1UJV1n=V1L
~• VIL = - 3.04 + 2 V I
pMOS transist or is in non-sat uration region. ~

r
to ! Ro

v,{ Vo
nMOS transist or is in saturati on mode.

lv)V1n ::V,H
pMOS is in saturati on mode.
nMOS is in linear mode.
= - l.l69 + 0.769 V

~
.•
Substituting this In Equation (3 •3-7) gives,
~.
7CV1n-Vtn)2 = j[2 (V,.-Voo -V1p) cv.-Voo
-CV.-Vool21
l
... (1)

v) V,n = switching threshold

Putting Vin = V1L = 0.769 v. - 1.169, we have
saturation
(a) Both nMOS and pMOS transist ors are in 1.6 (0.769 v. -1.169- 0.6)2 = [2 (0.769 v. -:.169-
3.3
region of operatio n. (V0 - 3.3)
Vo + 0.7)
following
Ex. 3.7 .11 : Consider a CMOS inverter with the
Vss= - SV
-(V0 -3.3)2]
Fig. P. 3.7.9 parameters : 2
1.6 (0.769 v.-1.76 9) = [2 (0.769 v. - 3.769 l
n region, nMOS Vro,n = 0.6 V
Soln. : Vo = 1V means operation in the saturatio (V0 - 3.3) - (V0 - 3.3)2]
lo to pMOS Vro,p = - 0.7 V
we use the saturation region expression of 1.6[0.6 v! - 2.n v. + 3.13] = [2(0.769 v! - 2.5
v.
determine the required value ofVGs· µ,, c0 , = 60 µA/ v2 and(~ )~= 8 - 3.769 v. + 12.4)
w
10 = - -
2
µ,,C•• L
- [VGs -Vr]
2 L......._ _ _ _ _ _
t p - VDD
V_o_o++..;::V...
lip C0 x = 25 µA/ v2 and -(~ t = 12 - CV!- 6.6 V + 10.8)]
O

24.8
(b) Calculate the noise m~rgins and the switching
threshold 0.96 V!- 4.35 V0 + 5 = 1.538V! - 12.538 V0 +
2
0.4 = ½x 20 x 10· 3 x ~OOO CVGs - 2) (VTH) of this circuit. The ~wer supply voltage
is V00 = 3.3 V.
Fig. P. 3.7.10 -v! + 6.6 v. -10.8
MU - May 15 May 19 5 Marks
This equation yields two values for VGs, lV and
3V. For nMOS:
VGsn Vin o.96 ~- 4.35 v. + 5 = 0.538 v! - 5.938 v. + 13.91
since is Soln.:
The first value does not make physical sense Vosn Vo 0.422 ~ + 1.588 v. - 8.91 = 0
It is OV
lower than V1. Thus VGs = 3V. From the Fig. P.3.7.9 VoL
one
the source For pMOS : VGSp Vin - Yoo Solving the above quadratic equation, we get
dear that gate is at ground potential, thus VoH 3.3V
value of Rs can be positive root,
must be at - 3, and the required Vosp Vo-Voo
determined from. transistor
11nCox(¥l V0 = 3V
(i) V1n < Vtn: When V1n is less than V1n, nMOS
is in cutoff mode and pMOS transist or is in
saturation ~Cox(¥)P Substituting the value ofV0 in Equation (1) gives,
mode as Vosp < VGsp - V1p.
VIL = - 1.169 + 0.769 v.
±1:. 2 1
0.4
~ VIL = - 1.169 + 0.769 X 3
= 5 kQ FornMO S: p<I X l_P"6 X 8 _!!_
VG,n Vin> Voo + Vtp
~ x l,P"6 x ~ -5 VIL = 1.13 V
must
To establish de voltage of+ 1V at the drain, we S 1
select Rn as follows : V00 + V,p +t-(2 V0 + Vm)
Vosn < VGsn
Ro = V 00 }'.11. - Ll 1.6
1 +.fh_
lo - 0.4
:. nMOS transist or is in non-sat uration region. ~p

Ro = 20kQ 3.3 - 0.7 + 1.6 (2 v. + 0.6)

ForpMOS :
1 + 1.6
region of
Ex. 3.7.1 0 : For a CMOS inverter find the 2.6 + 3.2 V 0 + 0.96
operation :
2.6
(i) Vin< V"' (ii) Vin > Voo + V1p Vin > Voo + V,p
Substitu ting the values, we get, 3.2 v. + 3.56
(iii) Vin = V1L (iv) Vm = ViH - 3.3 + (- 0.7) + 2 v. + (1.6) 0.6 V1H: - -2-.6--
VGSn > v,p
(v) Vin = switching threshold VIL = 1 + 1.6
Hence, PM Os transist or is in cutoff region.

--- ---- --::. .\·!~,~

 3-31 Combinational CMOS Logic Circuit 11 Digital VLSI (MU) 3-32

j
Combinational CMOS
Digital VLSI (MU)
VrH = 1.23 V0 + 1.37
- Yoo + V,p + 2 Vo + (t) Vtn
1.114 V
Soln. : Inverter threshold
where the voltage tr
. Logic Oro:i!
VTH is defined by the .
1+~ - Yoo+ Vtp +t-(2 Vo + Vtn ) . ansfer curve . JlOint
Substitu ting this v,. = V,Hin Equation (3.3.16) pp gam. It is located in the region C :~tersects the llllity

"' " l~~. ·~-~ ~ ~.

l+h figure. At this point, both the tran'. own in the above
~ [ (V- - Vm m
) Vo - v2o ] = .!?a.,2 fVrn- VDD - Vtp J2 - 3.3 + (- 0.7) + 2 V0 + 2.5 x O
1 + 2.5 .___:§_
pp mode.' Equating the current llo~~stor at in saturation
2

t[ (1.23 Vo+ 1.37 - 0.6) Vo - v:] - 4 + 2 V0 + 1.5

3.5
3.3 - 0.7 + 2.5 (2 V0 + 0.6)
1 + 2.5
2.6 + 5 V9 + 1.5
= [1 .23 V0 + 1.37 - 3.3 + 0.7]2 - 2.5 + 2 V0 3.5
3.5 = - 0.71 + 0.57 Vo
1.6 (1. 23 v!+ 0.77 Vo- v:] (1.23 Vo - 1.23)
2
5V9 +4.1
Substituting this in Equation (3 .3.7) gives, 3.5
0.368 V~ + 1.232 V0 1.SV! - 3 V0 + 1.5
p pp Vrn l.43V0 +1.17
1.132 v:- 4.232 V0 + 1.5
~ [ (V,. - Vtn )2 z [2(V,. - Yoo - Vtp)

CVo- Yoo) - (Vo - YooJ2]

Substituting this v ,. = VJH in Equation (3 .3.16) gives, VTH V;,

Solving above quadratic Equations yields, 2 pp Fig. P. 3.7.13

v ,. = v,L = - 0 .71 + 0.57 Vo ... (1) zl (Vr.-V,.) VO-Vo ]
~.
= z[V,. -Voo-V,p]2
~
V0 = 0.39V
20 2~n (V,.-Vu,) l i CV1n-Yoo-Y,-p)2
0 .6) 2]
~ µA [(- 0.71 + 0.57 V0 -
~ [ (1.43 V + 1.17 - 0.6) VO- V
2
]
Putting value ofV0 in Vrn Equation, we get, 1-'p
O
0 '✓13n(V,. - V,J = -~(V,. - Yoo- Y,p)
1.23 V0 + 1.37 ¥ [2(- 0.71 + 0.57 V0 - 3 .3 + 0 .7) (V0 - 3.3) [1.43 V0 + 1.17 - 3.3 + 0.7]2
v,.({13,+~) = ~CVoo •Y,p)+{i3,v'"
1.23 X 0.39 + 1.37 -(V0 -3.3)2] 2.5 [0.43 v ! + 0.57 V0 ] (1.43 V0 - 1.43) 2
Dividing equation by~ we get,
2.5 (-1.31 + 0.57 V0 )2 [(- 3.31 + 0 .5 7 VO) X 2
1.84V 1.075 v: + 1.425 V0 2.04 v : - 4.08 v u + 2.04
2
X (V0 - 3 .3) - (V0 - 3.3) ] V1.(1+J) = V00 +Y,p +J·Ym
1.13 - 0 V! - 5.5 V0 + 2.04
[(1.14 V0 6.62) (V0 3.3)
(0 .32 V! - 1.49 V0 + 1.7) - -

V00 + V,p +
tp .y
- (V0 - 3.3) 2 ] Solving the above quadratic equation gives tn
1.13V

3.3 -1.84 2.5 (0.32 V! -1.49 V0 + 1.7) = {(1.14 v ! -10.382 V0 + 21.846)

V0 = 0.4V
1+· ~
'\Ji\
Putting value of VO in Vrn equation, we get,
- (V! - 6.6 V0 + 10.89)}
1.46 V V1H 1.43 V0 + 1.17 Now, it is given that
2.5 (0.32 V! - 1.49 V0 + 1.7) = [0.14 v ! - 3 .782 V0 1.43 X 0.4 + 1.17 YrH 1.SV,
Ex. 3.7.12 : A CMOS inverter has following parameters :
1.742V Y00 = 3V
Yoo = 3.3 V + 10.956] VIH
V., = 0.6 Y,
v lO,n = 0.6 V 2.5 (0.32 V! -1.49 V0 + 1.7) = 0.14 V! - 3.782 V0 NML V1L-VOL
V,o,p = - 0.7 V Y,p = -0.8V
+ 10.956] 1.114- 0 = 1.114
2
K,, = 200 µA/V µ,, c0 , = 60µ A/V
56 NMH Yott-VrH
0.18 V! - 3.725 V0 + 4.25 0 .14 v!- 3 .782 V0 + 10.9 2
~ =80 µA/V µp Co, = 20µ A/ V
3.3 - 1.742 = 1.56 and
Calculate the noise margin of the circuit. Is the inverter 0.66 V!- 0.057 V0 - 6 .7 C,xr-t). rt).
µ,, 60
symmetric?
Soln.: Solving the above quadratic equation gives,
V0 3 .2 V
Ex. 3.7.13: Derive an expression for the inverter threshold
voltage (switching voltage) of a CMOS inverter. Calculate
t- = µ,c,xr-t)P = zor-t\

-3r-tlrn
VaL = OV th e IYV/L) ratios of the nMOS and pMOS transistor in the
and V0 = - 3.14 CMOS Inverter circuit with the following parameters :
VaH = 3.3V
nMos V1n =0 .6V, µ,,c 0 , =6011A// ,
_;_
V0 = 3.2 V pp
;_ 200 5 2
~p =8Cl= 2 =z .s PMOS V1p=-0.8V, µ,,c 0 , =2011A/v
Substituting the value ofV0 in Equation (1), we get,
V00 = 3 V, and VrH = 1.5 V
Since~. * ~P : . Inve rter is not symmetric. 0 .57 V0 - 0 .71

0.57 X 3.2 - 0.71 ~

'if!~,,, ,, ,••'
~ combinational CMOS Logic Circuit f/ Digital VLSI (MU) A
3-33 ---.. substituting value ofV0 in Equation (l)
3-34
Combinational CMOS Logic Circuit
,!_Digita!VLS l (MU) - - - . - : -.... /& Substituting values,

~
- 3 + (- 0.7) + 2V9 + 2(0.~ 13p = ~cox(n
VIL 0.67 Y0 - 0.83 (
Y1L 1+2
15 = -fiii - 3.7 + 2 V9 + 1.2
0.67 X 2.83 - 0.83 µ,, = 2~
1+'\jlf., 3 1.896 - 0.83 = 1.06 y
(
1 s + 1 s-J; = 2.2 + o.6-J;
-2.5 + 2~
3
- 0.83 + 0.67 v.
Y1H
Yoo+ V,p +t +
1+~
13p
(2V0 V,,J
'•-C~·~
0.9 - J ; = 0.7 v ,. v,L= o.67Y O - o.83 ... (lJ Fig. P. 3.7.15
3 + (- 0.7] + 2 (2V + 0.6]
2 For equal line and full line pA= l3A
1+2
~(V,. -Y,,J 2
2.3+4V0 +1.2
= 1f[2(V 1
, - Y00 - Y,p) CVo - Yoo)-½ (V0 - Y00Jl]
Vrn 3
:. µ,,cox ( ~1 = ~cox ( f \

3.5 + 4V9
2
3 = 1.16 + 1.33V0 ... (2) (J))p ~=2
tcY,.- Ycnl (T,
. (n
substituting v,. = v,H in following equation,
= t[ 2(V10 -Y 00 - Y"') (V. - Vool -½ (V0 -Y 00J2]
~[2(V10 -Vcn)V.-V!] = t[V,.-V 00 -V"']2
2 (H
Ex. 3.7.14: Consider a CMOS inverter circuits with
t (0.6 7YO - 0.83 - 0.6)
2
t [2 (1.16 + l.33V0 - 0.6) V0 - v!J Or(½). = z(~1
Ex. 3.7.16: Design the circuit for the function
following parameters = [2co.67Y0 -0.83-3 + o.7) cv.-3)-½(V.-3 )2] = [1.16 + 1.33V0 - 3 + 0.7]2
Y= (A+ B + C) · (D.E.F) using CMOS logic. Also find
v00 = 3.3V, VT""= 0.6V, VTOfJ = - 0.7 V.
z[2(0.56+1.33 V.)V.-V!] = [1.33V.-1.14]2 equivalent CMOS inverts circuit for simultaneous switching
2(0.67V0 -1.43)2
µ,,Cox=60µAtv2 , {~)n=a of all input Assume (~) P = 2, (~)

µ,, C , =20 µAl't/, {~} P =12. Calculate the noise margin.

=[ 2(0.67V 0
- 3.13) (V0 - 3) -½(V!- 6V0 +9)] 2[1.12v0 +2.66V!-v!] = [1.76V! -3.03V0 +u]
nMOS transistors in the circuit.
0
= 1 for all p and

0 3.32 v! + 2.24 v . - 1.76 v! + 3.03V0 -1.3 = o

IMl 1 it1MIMMWf♦i111fftid 2(0.449Y!- 1.91 V0 + 2.04)
1.56 V~ + 5.27V0 -1.3 = 0
Soln.:

(A+ B + C) • (D.E.F)
Soln . :
Yoo = 3Y Yron = 0.6Y Yrop = - 0.7Y,
= [ 2co.61Y! - 2.01v0 - 3.13v.... 9.39) -½ cv!- 6Y. + 9J] Solving above Equations we get Voo

µ,, C0 , = 60 µA(V 2, (~, = 8

2(0.449Y! -1.91 Y0 + 2.04) V0 = 0.23V (rl,• .----.--'-.......,...--.. . . .
= [2(0.67V! - 5.14V0 + 9 .39) -0.5 V! + 3Y 0 -4,5] Substituting V0 in Equation (2), 0-4 (r),=2
~C 0 , = 20µA/V2, (~P =12 o.89 Y~ - 3.82 v 0 + 4.08
Vrn 1.16 + 1.33V0
1.16 + 1.33 (0.23)
13, = µ,,c.,(~ . =60x8=480µ = [ 1.34V!- 10.28V0 + 18.78 - 0.5 V! + 3Y0 - 4.5]
VIH 1.46
Noise Margin, NML v,L - YoH = 1.06- 0 = 1.06Y
13P : ~c.,(f \ =20 X 12: 240 µ o.89 Y! - 3.82 Y0 + 4.08 [ 0.84V!- 7.28V0 + 14.28]
NMH V0 H-Vrn= 3-1.46= 1.54Y
~ 480
o.o5 Y! + 3.46 Y0 10.2 0
13P : 240 = 2 -
Ex. 3.7.15: For equal rise and tall delay five assume
µ., = 2 ~ draw an inverter equivalent circuit of 3 input NANO
-Yoo + Y,p + 2Y0 + (t) yen Y. 2.83 or - 72.03
and 2 Input XOR. e1•■&e~•iMDD
Only one root is with VO > o Soln.:

- - - - - - - -- - - -- - - - - ~
1+(t) :. V0 = 2.83 V
----=--==~~-_1---~-~.~!~.~~~..:
!3
0
~ cox (~)
0
Fig. P. 3.7.16(a)
 r
Combinati onal CMOS Logic C'
3-3 5 1f Digita l VLSI (MU)
en ~
3-36
• Digital VLSI (MU)

.
30.C[ )n=lO ,,,- I Review Questions J Combinational CMOS Logic Circwt
4- Compare different MOS inverters.
For Driver network :
. ON total ON resistance
When all the transistors are ' For pull up transistor passes '0' voltage perfectly and not 5. Explain operation of CMOS inverter with the help of its
1_ WhY nMOS
S ·r~ of each drive transistor is 1 then Voo '1' voltage level? transfer characteristics.
becomes 4 f<.JN · 0 1 L
L L L .1. .1. _l 6. Write a short note on : Static CMOS Design.
good passer of high voltage
w+w+w+w+w-4 2_ Why pMOS switch is called a
and poor passer of low voltage? 7. Explain briefly FET Sizing.

~L~ri••r< =t 3. Write a short note on : Noise

margin.

For Load network :

Total ON resistance is 3 RoN
DOD

(iL,.. = (i )p (i)p (i \
d + +
1 1 1 3
=z+z +z =z
m rotalload mlnv•load =¾
Fig. P. 3.7.17(b)

~:)_.,
C~·-·: Req 3
1 1
L)p=2%._ X~=zo
(w
"
F"ig. 3.7.16(b) 10

Ex. 3.7.17 : Design the circuit and draw layout for the 20
function Y = (D + E + F) (B + C + A) using CMOS logic. Also
find equivalent CMOS inverter circuit for simultaneous For pull down
switching of all inputs assuming that (W/1.)p = 30 for all
PMOS transistors and (W/1.Jn = 10 for all NMOS transistors.
(10 Marks)

Ans. : y
(D + E + F) (8 + C + A)
(¼)n (¼)n t (¼)
T = (¼lq= -H½lq
~ B

~ c (¼)n (¼ln t(¼)

~ A

Fig. P. 3.7.17(c)
D~

B~