SIMATIC TIA Portal Service 3

Contents 7
7. Introduction to STL ................................................................................................ 7-2
7.1. Goal of this Chapter: Displaying the Running Light when the Operation is Switched Off .... 7-3
7.2. What is STL?......................................................................................................................... 7-4
7.3. First Steps with STL .............................................................................................................. 7-5
7.3.1. Creating an STL Block .......................................................................................................... 7-5
7.3.2. STL Network in a LAD/FBD Block ........................................................................................ 7-6
7.3.3. Structure of an STL Block and Editing It ............................................................................... 7-7
7.3.4. Execution of Logic Strings (Instructions for Binary Logic Operations).................................. 7-8
7.3.5. Execution of Instructions with 1 or 2 Operands (Math Functions, Compare...) .................... 7-9
7.3.6. Compiling the Block and Downloading It ............................................................................ 7-10
7.3.7. Calling an STL Block ........................................................................................................... 7-11
7.4. Testing / Monitoring an STL Block ...................................................................................... 7-12
7.5. Frequently Used Instructions .............................................................................................. 7-13
7.5.1. Overview ............................................................................................................................. 7-13
7.5.2. L, T, TAK, POP Instructions ................................................................................................ 7-14
7.5.3. Math Function Instructions .................................................................................................. 7-15
7.5.4. Word Logic Operations ....................................................................................................... 7-16
7.5.5. Shift / Rotate Instructions .................................................................................................... 7-17
7.7. Processing 64-Bit Variables ................................................................................................ 7-18
7.8. Exercise 1 (Theory): First Check, Signal State, Result of Check and Result of Logic
Operation ............................................................................................................................ 7-19
7.9. Exercise 2: Commissioning the Running Light when the Operation is Switched Off ......... 7-20

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7. Introduction to STL

In this chapter, an introduction to the programming language STL is given and the commissioning
of an STL block is practiced.
The participant becomes familiar with STL. He gets an overview of the structure and handling of
STL blocks.
Objectives:
The participant can then commission a simple STL block.

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7.1. Goal of this Chapter:

Displaying the Running Light when the Operation is Switched
Off

Task Description
As long as the operation is not switched on ("P_operation" Q0.1 =0), the output byte
"byteRunningLight“ (QB3) of the central DO module of the S7-1500 is to show a running light
which is pulsed with a 2 Hz "Clock_2Hz" (M10.3).

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7.2. What is STL?

STL (STatementList) is a machine-oriented, text-based programming language complying with

the IEC61131-3 standard.
In the past, this was the only programming language for the efficient programming of
mathematical algorithms and complex data processing tasks in control engineering.
Today, this programming language is still available in the S7-1500 for compatibility reasons.
However, today SCL is available for all controllers as an efficient programming language
for the programming of mathematical algorithms and complex data processing tasks.

PLCopen Reusability Level

STL does not fulfill the Base Level and the Reusability Level according to the PLCopen Standard
since this language is not available in all CPUs and the scope of the instructions also differs
somewhat amongst the CPUs.

Restrictions with Regard to Performance

In general, the STL-Compiler is also an efficient compiler for compiling into optimized machine
code.
The performance is lower when register commands are used since the registers (accumulators,
address registers, DB registers...) do not really exist for S7-1500, rather are only emulated.
• Data storage via indirect access by means of address registers
→ high performance, indexed symbolic accesses are possible for S7-1500
• Accesses via data registers (accumulators) for example, arithmetic
etc.

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7.3. First Steps with STL

7.3.1. Creating an STL Block

Just as with all other LAD/FBD/STL blocks, STL blocks are also created and managed in the
"Program blocks" section of the opened project.
• Possible block types: FC, FB or OB
• Selected language: STL
This cannot be changed later on since a switch-over to other programming languages (for
example, LAD/FBD/SCL) generally is not possible.
Block name and block number can be chosen (as is also generally the case for other languages).

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7.3.2. STL Network in a LAD/FBD Block

Caution!
The registers (accumulators, address/DB registers...) do not really exist in S7-1500. They
are emulated and are only available within the STL networks of a block.

A data transfer between LAD/FBD networks and STL networks can only be done using PLC tags.
Even the result of logic operation (RLO) of a binary logic chain is set to undefined for network
transfers with language change (LAD/FBD ↔ STL).

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7.3.3. Structure of an STL Block and Editing It

The block structure (interface and instruction section) is identical to that of LAD/FBD/SCL blocks.
When programming instructions, the following points must be taken into consideration:
• Each instruction requires its own line.
• All identifiers (names) used in the instruction section must be defined as a global PLC tag, DB
variable or as an interface variable.

Drag & Drop

To support the programming in the instruction section, instructions (from the "Instructions"
TaskCard), tags and variables (from the Details view or the block interface) and block calls (from
the Project tree) can be inserted using drag & drop.

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7.3.4. Execution of Logic Strings (Instructions for Binary Logic Operations)

Bit logic operations use the RLO from the previous line and, with the result of check of the
operand, form a new RLO.
If the status ‘first check’ is fulfilled, there is no gating, but only the result of check of the operand is
adopted in the RLO.

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7.3.5. Execution of Instructions with 1 or 2 Operands

(Math Functions, Compare...)

ACCU1, ACCU2
Size: 4 bytes or 32 bits
These are two CPU-internal memories for storing operand values for the execution of a byte,
word or double-word instruction with 1 or 2 operands.
In the S7-300/400, these were very quick CPU-internal registers (memories). In the
S7-1500, they are emulated and so have no performance advantage vis-à-vis
LAD/FBD or SCL.

Load
Loading influences both ACCU1 and ACCU2 data registers
1. Value from ACCU1 is written in ACCU2
2. New load value is written in ACCU1

Transfer
The value from ACCU1 is always stored

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7.3.6. Compiling the Block and Downloading It

STL blocks are handled the same as LAD/FBD/SCL/GRAPH blocks.

These, as well, are compiled and downloaded.

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7.3.7. Calling an STL Block

STL blocks can be created as an FC or an FB depending on the task. These can be called by any
block. It doesn’t matter in which STEP 7 language (SCL, GRAPH, STL, LAD or FBD) these
blocks were created.
In accordance with the principle of structured programming, other blocks (FB, FC) can also be
called by an STL block. These blocks could have been created in STL or in another STEP 7
language (SCL, LAD, etc.).

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7.4. Testing / Monitoring an STL Block

Correctly compiled STL blocks which have been downloaded into the controller can be tested
using the monitoring function “Monitor”.

Address
Global operands → Operand address
Constants as operand → Value of the constant

RLO
The entry of the current RLO is additionally highlighted in color depending on the status.
• RLO = 1 → Table entry Column "RLO" highlighted in green
• RLO = 0 → Table entry Column "RLO" highlighted in blue

Extra
This column is used for further information depending on the need. For example,
- for mathematical instructions → relevant status bits
- for timer and counter instructions → time or count values
- for indirect addressing → memory address
- for ACCU manipulation → ACCU2

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7.5. Frequently Used Instructions

7.5.1. Overview

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7.5.2. L, T, TAK, POP Instructions

The load or transfer instruction depends of the type/size of the operand.

• Load
→ value entry in ACCU1 is right-justified, the rest is filled with leading zeros
• Transfer
→ value removal from ACCU1 is right-justified, the rest is not taken into consideration and
remains unchanged

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7.5.3. Math Function Instructions

The data type of the selected instruction requires:

• the interpretation of the values in ACCU1 and ACCU2
• the size and coding of the result
Caution!
If an overflow/underflow occurs during the execution of a math function instruction, the
incorrect (shortened) value is made available in ACCU1. No programming error is
generated.
e.g. Division by 0
e.g. Multiplication of two INT values with the result > 32767 or the result < -32768
The status “Result invalid” can be queried via the status-bit OV (Overflow).

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7.5.4. Word Logic Operations

Word logic operations gate the operands ACCU1 with ACCU2 bit-by-bit and make the result
available in ACCU1.

AND Word Logic Operation

This is used, for example, to extract certain word ranges of a variable.
Example mentioned above
xxxx_xxxx_xxxx_xxxx_ 0000_0000_1111_1111 extracts the right byte of the value from ACCU2
xxxx_xxxx_xxxx_xxxx_ 1010_1111_0001_0011 16#AF13
AW
0000_0000_0000_0000_0000_0000_0001_0011 16#00000013

This is used, for example, to check whether a certain bit of a variable is set.
0000_0000_0000_0000_0000_0000_0001_0000 checks bit 4 of the value from ACCU2
0000_0001_0000_0400_1010_1111_0001_0011 16#0104AF13
AD
0000_0000_0000_0000_0000_0000_0001_0000 ACCU1<>0, when bit is set
ACCU1 = 0, when bit is not set

OR Word Logic Operation

This is used, for example, to set a certain bit of a variable.
Example mentioned above
0000_0000_0000_0000_0000_0000_0010_0000 sets bit 5 of the value from ACCU2
0000_0001_0000_0400_1010_1111_0001_0011 16#0104AF13
OD
0000_0001_0000_0400_1010_1111_0011_0011 16#0104AF33

LAD/FBD and SCL

Instructions for word logic operations are also available in these programming languages.

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7.5.5. Shift / Rotate Instructions

Shift operations in ACCU1 are available for word and double-word.

Rotate always affects the entire ACCU1.

Status Bit CC1

If a shift or rotate instruction is used which uses this status, the status can be queried with a
binary logic operation.
e.g. A CC1 after SLW, SLD, SRW, SRD
CC1 delivers 1 as the signal status when, for a shift instruction, the last shifted (out) bit was a 1.
CC1 delivers 0 as the signal status when, for a shift instruction, the last shifted (out) bit was a 0.

LAD/FBD and SCL

Shift and rotate instructions are also available in these programming languages.

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7.7. Processing 64-Bit Variables

Since math function instructions and comparators expect the values in ACCU1/2 and these only
have a size of 32 bits, 64-bit variables cannot be processed by these.
STEP 7 supplies the required global library.

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7.8. Exercise 1 (Theory):

First Check, Signal State, Result of Check and Result of Logic
Operation

Task
An instruction sequence with 3 different signal statuses of the checked (queried) binary signals is
given.
Analyze the logic string with regards to the result of check and result of logic operation and enter
your results in the table.

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7.9. Exercise 2: Commissioning the Running Light when the

Operation is Switched Off

Task
As long as the operation is not switched on ("P_operation" Q0.1 =0), the output byte
"byteRunningLight" (QB3) of the central DO module of the S7-1500 is to show a running light
which is pulsed with a 2 Hz "Clock_2Hz" (M10.3).
The running light is to fulfill the following conditions:
• Switch on “P_operation”
(Input parameter #StatusOperation = ′0′ →'1'), the running light always starts from Bit No.0
(Q3.0).
• Switch off “P_operation”
(Input parameter #StatusOperation = '0') all bits are set to 0.
For this, an STL block is prepared in the course library.
Copy the FB from the course library, integrate the call in your FB "Signal", download the program
expansion and test the running light display at QB3.

What to Do

1. Copy the program blocks

In the course library, open the "07" section and copy the FB into your own project (in the
"Program blocks" folder).

2. Integrate the running light display in the program → FB call in FB "Signal"

Open FB "Signal" and add a network which calls the FB "RunningLight".
Create the relevant PLC tag for the output byte.

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3. Compile the program and download it

Check the result in the Inspector window, "Info" + "Compile/General" tabs.

4. Test the running light display at QB3

Switch the operation on (no running light) or off (running light).

Open FB20 and monitor the program sequence.

In the FB, the ENO-Status of the block is formed.
ENO = 0 → running light is set to 0 (switched off)
ENO = 1 → running light is switched on
In the next chapter there is a detailed explanation for this.

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